[net-next-2.6.git] / virt / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			ASSERT(redir_index < IOAPIC_NUM_PINS);

			redir_content = ioapic->redirtbl[redir_index].bits;
			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
{
	union kvm_ioapic_redirect_entry *pent;
	int injected = -1;

	pent = &ioapic->redirtbl[idx];

	if (!pent->fields.mask) {
		injected = ioapic_deliver(ioapic, idx);
		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
			pent->fields.remote_irr = 1;
	}
	if (!pent->fields.trig_mode)
		ioapic->irr &= ~(1 << idx);

	return injected;
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		mask_before = ioapic->redirtbl[index].fields.mask;
		if (ioapic->ioregsel & 1) {
			ioapic->redirtbl[index].bits &= 0xffffffff;
			ioapic->redirtbl[index].bits |= (u64) val << 32;
		} else {
			ioapic->redirtbl[index].bits &= ~0xffffffffULL;
			ioapic->redirtbl[index].bits |= (u32) val;
			ioapic->redirtbl[index].fields.remote_irr = 0;
		}
		mask_after = ioapic->redirtbl[index].fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
		if (ioapic->irr & (1 << index))
			ioapic_service(ioapic, index);
		break;
	}
}

static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
{
	union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
	DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
	struct kvm_vcpu *vcpu;
	int vcpu_id, r = -1;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     entry.fields.dest, entry.fields.dest_mode,
		     entry.fields.delivery_mode, entry.fields.vector,
		     entry.fields.trig_mode);

	/* Always delivery PIT interrupt to vcpu 0 */
#ifdef CONFIG_X86
	if (irq == 0) {
                bitmap_zero(deliver_bitmask, KVM_MAX_VCPUS);
		__set_bit(0, deliver_bitmask);
        } else
#endif
		kvm_get_intr_delivery_bitmask(ioapic, &entry, deliver_bitmask);

	if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
		ioapic_debug("no target on destination\n");
		return 0;
	}

	while ((vcpu_id = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
			< KVM_MAX_VCPUS) {
		__clear_bit(vcpu_id, deliver_bitmask);
		vcpu = ioapic->kvm->vcpus[vcpu_id];
		if (vcpu) {
			if (r < 0)
				r = 0;
			r += kvm_apic_set_irq(vcpu,
					entry.fields.vector,
					entry.fields.trig_mode,
					entry.fields.delivery_mode);
		} else
			ioapic_debug("null destination vcpu: "
				     "mask=%x vector=%x delivery_mode=%x\n",
				     entry.fields.deliver_bitmask,
				     entry.fields.vector,
				     entry.fields.delivery_mode);
	}
	return r;
}

int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
{
	u32 old_irr = ioapic->irr;
	u32 mask = 1 << irq;
	union kvm_ioapic_redirect_entry entry;
	int ret = 1;

	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
		entry = ioapic->redirtbl[irq];
		level ^= entry.fields.polarity;
		if (!level)
			ioapic->irr &= ~mask;
		else {
			ioapic->irr |= mask;
			if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
			    || !entry.fields.remote_irr)
				ret = ioapic_service(ioapic, irq);
		}
	}
	return ret;
}

static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
				    int trigger_mode)
{
	union kvm_ioapic_redirect_entry *ent;

	ent = &ioapic->redirtbl[pin];

	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);

	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
			ioapic_service(ioapic, pin);
	}
}

void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		if (ioapic->redirtbl[i].fields.vector == vector)
			__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
}

static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
			   int len, int is_write)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;

	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
			     void *val)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
	u32 result;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
}

static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
			      const void *val)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
	u32 data;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */
	if (len == 4 || len == 8)
		data = *(u32 *) val;
	else {
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		return;
	}

	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data;
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;
#ifdef	CONFIG_IA64
	case IOAPIC_REG_EOI:
		kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
		break;
#endif

	default:
		break;
	}
}

void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->id = 0;
}

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	ioapic->dev.read = ioapic_mmio_read;
	ioapic->dev.write = ioapic_mmio_write;
	ioapic->dev.in_range = ioapic_in_range;
	ioapic->dev.private = ioapic;
	ioapic->kvm = kvm;
	kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
	return 0;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
	2	* Copyright (C) 2001 MandrakeSoft S.A.
	3	*
	4	* MandrakeSoft S.A.
	5	* 43, rue d'Aboukir
	6	* 75002 Paris - France
	7	* http://www.linux-mandrake.com/
	8	* http://www.mandrakesoft.com/
	9	*
	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2 of the License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* Yunhong Jiang <yunhong.jiang@intel.com>
	25	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	26	* Based on Xen 3.1 code.
	27	*/
	28
edf88417	29	#include <linux/kvm_host.h>
1fd4f2a5 ED	30	#include <linux/kvm.h>
	31	#include <linux/mm.h>
	32	#include <linux/highmem.h>
	33	#include <linux/smp.h>
	34	#include <linux/hrtimer.h>
	35	#include <linux/io.h>
	36	#include <asm/processor.h>
1fd4f2a5 ED	37	#include <asm/page.h>
1fd4f2a5 ED	38	#include <asm/current.h>
82470196 ZX	39
	40	#include "ioapic.h"
	41	#include "lapic.h"
f5244726	42	#include "irq.h"
82470196	43
e25e3ed5 LV	44	#if 0
	45	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	46	#else
1fd4f2a5	47	#define ioapic_debug(fmt, arg...)
e25e3ed5	48	#endif
ff4b9df8	49	static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
1fd4f2a5 ED	50
	51	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	52	unsigned long addr,
	53	unsigned long length)
	54	{
	55	unsigned long result = 0;
	56
	57	switch (ioapic->ioregsel) {
	58	case IOAPIC_REG_VERSION:
	59	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	60	\| (IOAPIC_VERSION_ID & 0xff));
	61	break;
	62
	63	case IOAPIC_REG_APIC_ID:
	64	case IOAPIC_REG_ARB_ID:
	65	result = ((ioapic->id & 0xf) << 24);
	66	break;
	67
	68	default:
	69	{
	70	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	71	u64 redir_content;
	72
	73	ASSERT(redir_index < IOAPIC_NUM_PINS);
	74
	75	redir_content = ioapic->redirtbl[redir_index].bits;
	76	result = (ioapic->ioregsel & 0x1) ?
	77	(redir_content >> 32) & 0xffffffff :
	78	redir_content & 0xffffffff;
	79	break;
	80	}
	81	}
	82
	83	return result;
	84	}
	85
4925663a	86	static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
1fd4f2a5	87	{
cf9e4e15	88	union kvm_ioapic_redirect_entry *pent;
4925663a	89	int injected = -1;
1fd4f2a5 ED	90
	91	pent = &ioapic->redirtbl[idx];
	92
	93	if (!pent->fields.mask) {
4925663a	94	injected = ioapic_deliver(ioapic, idx);
ff4b9df8	95	if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
1fd4f2a5 ED	96	pent->fields.remote_irr = 1;
	97	}
	98	if (!pent->fields.trig_mode)
	99	ioapic->irr &= ~(1 << idx);
4925663a GN	100
4925663a GN	101	return injected;
1fd4f2a5 ED	102	}
	103
	104	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	105	{
	106	unsigned index;
75858a84	107	bool mask_before, mask_after;
1fd4f2a5 ED	108
	109	switch (ioapic->ioregsel) {
	110	case IOAPIC_REG_VERSION:
	111	/* Writes are ignored. */
	112	break;
	113
	114	case IOAPIC_REG_APIC_ID:
	115	ioapic->id = (val >> 24) & 0xf;
	116	break;
	117
	118	case IOAPIC_REG_ARB_ID:
	119	break;
	120
	121	default:
	122	index = (ioapic->ioregsel - 0x10) >> 1;
	123
e25e3ed5	124	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	125	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	126	return;
75858a84	127	mask_before = ioapic->redirtbl[index].fields.mask;
1fd4f2a5 ED	128	if (ioapic->ioregsel & 1) {
	129	ioapic->redirtbl[index].bits &= 0xffffffff;
	130	ioapic->redirtbl[index].bits \|= (u64) val << 32;
	131	} else {
	132	ioapic->redirtbl[index].bits &= ~0xffffffffULL;
	133	ioapic->redirtbl[index].bits \|= (u32) val;
	134	ioapic->redirtbl[index].fields.remote_irr = 0;
	135	}
75858a84 AK	136	mask_after = ioapic->redirtbl[index].fields.mask;
	137	if (mask_before != mask_after)
	138	kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
1fd4f2a5 ED	139	if (ioapic->irr & (1 << index))
	140	ioapic_service(ioapic, index);
	141	break;
	142	}
	143	}
	144
ff4b9df8	145	static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
1fd4f2a5	146	{
116191b6	147	union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
bfd349d0	148	DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
1fd4f2a5	149	struct kvm_vcpu *vcpu;
4925663a	150	int vcpu_id, r = -1;
1fd4f2a5 ED	151
1fd4f2a5 ED	152	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
e25e3ed5	153	"vector=%x trig_mode=%x\n",
116191b6 SY	154	entry.fields.dest, entry.fields.dest_mode,
	155	entry.fields.delivery_mode, entry.fields.vector,
	156	entry.fields.trig_mode);
1fd4f2a5	157
116191b6	158	/* Always delivery PIT interrupt to vcpu 0 */
8c35f237	159	#ifdef CONFIG_X86
74a3a8f1 SY	160	if (irq == 0) {
74a3a8f1 SY	161	bitmap_zero(deliver_bitmask, KVM_MAX_VCPUS);
bfd349d0	162	__set_bit(0, deliver_bitmask);
74a3a8f1	163	} else
8c35f237	164	#endif
bfd349d0 SY	165	kvm_get_intr_delivery_bitmask(ioapic, &entry, deliver_bitmask);
	166
	167	if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
	168	ioapic_debug("no target on destination\n");
	169	return 0;
	170	}
116191b6	171
bfd349d0 SY	172	while ((vcpu_id = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
	173	< KVM_MAX_VCPUS) {
	174	__clear_bit(vcpu_id, deliver_bitmask);
116191b6 SY	175	vcpu = ioapic->kvm->vcpus[vcpu_id];
116191b6 SY	176	if (vcpu) {
6da7e3f6 GN	177	if (r < 0)
	178	r = 0;
	179	r += kvm_apic_set_irq(vcpu,
	180	entry.fields.vector,
	181	entry.fields.trig_mode,
	182	entry.fields.delivery_mode);
116191b6 SY	183	} else
	184	ioapic_debug("null destination vcpu: "
	185	"mask=%x vector=%x delivery_mode=%x\n",
	186	entry.fields.deliver_bitmask,
	187	entry.fields.vector,
	188	entry.fields.delivery_mode);
1fd4f2a5	189	}
ff4b9df8	190	return r;
1fd4f2a5 ED	191	}
1fd4f2a5 ED	192
4925663a	193	int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
1fd4f2a5 ED	194	{
	195	u32 old_irr = ioapic->irr;
	196	u32 mask = 1 << irq;
cf9e4e15	197	union kvm_ioapic_redirect_entry entry;
4925663a	198	int ret = 1;
1fd4f2a5 ED	199
	200	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
	201	entry = ioapic->redirtbl[irq];
	202	level ^= entry.fields.polarity;
	203	if (!level)
	204	ioapic->irr &= ~mask;
	205	else {
	206	ioapic->irr \|= mask;
	207	if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
	208	\|\| !entry.fields.remote_irr)
4925663a	209	ret = ioapic_service(ioapic, irq);
1fd4f2a5 ED	210	}
1fd4f2a5 ED	211	}
4925663a	212	return ret;
1fd4f2a5 ED	213	}
1fd4f2a5 ED	214
44882eed	215	static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
f5244726	216	int trigger_mode)
1fd4f2a5	217	{
cf9e4e15	218	union kvm_ioapic_redirect_entry *ent;
1fd4f2a5	219
44882eed	220	ent = &ioapic->redirtbl[pin];
1fd4f2a5	221
44882eed	222	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
f5244726 MT	223
	224	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
	225	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
	226	ent->fields.remote_irr = 0;
44882eed MT	227	if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
44882eed MT	228	ioapic_service(ioapic, pin);
f5244726	229	}
1fd4f2a5 ED	230	}
1fd4f2a5 ED	231
f5244726	232	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
4fa6b9c5 AK	233	{
	234	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	235	int i;
	236
	237	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	238	if (ioapic->redirtbl[i].fields.vector == vector)
f5244726	239	__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
4fa6b9c5 AK	240	}
4fa6b9c5 AK	241
92760499 LV	242	static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	243	int len, int is_write)
1fd4f2a5 ED	244	{
	245	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	246
	247	return ((addr >= ioapic->base_address &&
	248	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	249	}
	250
	251	static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
	252	void *val)
	253	{
	254	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	255	u32 result;
	256
e25e3ed5	257	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	258	ASSERT(!(addr & 0xf)); /* check alignment */
	259
	260	addr &= 0xff;
	261	switch (addr) {
	262	case IOAPIC_REG_SELECT:
	263	result = ioapic->ioregsel;
	264	break;
	265
	266	case IOAPIC_REG_WINDOW:
	267	result = ioapic_read_indirect(ioapic, addr, len);
	268	break;
	269
	270	default:
	271	result = 0;
	272	break;
	273	}
	274	switch (len) {
	275	case 8:
	276	(u64 ) val = result;
	277	break;
	278	case 1:
	279	case 2:
	280	case 4:
	281	memcpy(val, (char *)&result, len);
	282	break;
	283	default:
	284	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	285	}
	286	}
	287
	288	static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
	289	const void *val)
	290	{
	291	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	292	u32 data;
	293
e25e3ed5 LV	294	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	295	(void*)addr, len, val);
1fd4f2a5 ED	296	ASSERT(!(addr & 0xf)); /* check alignment */
	297	if (len == 4 \|\| len == 8)
	298	data = (u32 ) val;
	299	else {
	300	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
	301	return;
	302	}
	303
	304	addr &= 0xff;
	305	switch (addr) {
	306	case IOAPIC_REG_SELECT:
	307	ioapic->ioregsel = data;
	308	break;
	309
	310	case IOAPIC_REG_WINDOW:
	311	ioapic_write_indirect(ioapic, data);
	312	break;
b1fd3d30 ZX	313	#ifdef CONFIG_IA64
b1fd3d30 ZX	314	case IOAPIC_REG_EOI:
26815a64	315	kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
b1fd3d30 ZX	316	break;
b1fd3d30 ZX	317	#endif
1fd4f2a5 ED	318
	319	default:
	320	break;
	321	}
	322	}
	323
8c392696 ED	324	void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
	325	{
	326	int i;
	327
	328	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	329	ioapic->redirtbl[i].fields.mask = 1;
	330	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	331	ioapic->ioregsel = 0;
	332	ioapic->irr = 0;
	333	ioapic->id = 0;
	334	}
	335
1fd4f2a5 ED	336	int kvm_ioapic_init(struct kvm *kvm)
	337	{
	338	struct kvm_ioapic *ioapic;
1fd4f2a5 ED	339
	340	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	341	if (!ioapic)
	342	return -ENOMEM;
d7deeeb0	343	kvm->arch.vioapic = ioapic;
8c392696	344	kvm_ioapic_reset(ioapic);
1fd4f2a5 ED	345	ioapic->dev.read = ioapic_mmio_read;
	346	ioapic->dev.write = ioapic_mmio_write;
	347	ioapic->dev.in_range = ioapic_in_range;
	348	ioapic->dev.private = ioapic;
	349	ioapic->kvm = kvm;
	350	kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
	351	return 0;
	352	}
75858a84	353