[net-next-2.6.git] / sound / soc / soc-cache.c

/*
 * soc-cache.c  --  ASoC register cache helpers
 *
 * Copyright 2009 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>

static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[2];
	int ret;

	BUG_ON(codec->volatile_register);

	data[0] = (reg << 1) | ((value >> 8) & 0x0001);
	data[1] = value & 0x00ff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;
	ret = codec->hw_write(codec->control_data, data, 2);
	if (ret == 2)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_7_9_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_7_9_spi_write NULL
#endif

static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u8 *cache = codec->reg_cache;
	u8 data[2];

	BUG_ON(codec->volatile_register);

	data[0] = reg & 0xff;
	data[1] = value & 0xff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;

	if (codec->hw_write(codec->control_data, data, 2) == 2)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u8 *cache = codec->reg_cache;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
			      unsigned int value)
{
	u16 *reg_cache = codec->reg_cache;
	u8 data[3];

	data[0] = reg;
	data[1] = (value >> 8) & 0xff;
	data[2] = value & 0xff;

	if (!snd_soc_codec_volatile_register(codec, reg))
		reg_cache[reg] = value;

	if (codec->hw_write(codec->control_data, data, 3) == 3)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
				      unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->reg_cache_size ||
	    snd_soc_codec_volatile_register(codec, reg))
		return codec->hw_read(codec, reg);
	else
		return cache[reg];
}

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u8 reg = r;
	u16 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 1;
	xfer[0].buf = &reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 2;
	xfer[1].buf = (u8 *)&data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return (data >> 8) | ((data & 0xff) << 8);
}
#else
#define snd_soc_8_16_read_i2c NULL
#endif

static struct {
	int addr_bits;
	int data_bits;
	int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
	int (*spi_write)(void *, const char *, int);
	unsigned int (*read)(struct snd_soc_codec *, unsigned int);
	unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
} io_types[] = {
	{ 7, 9, snd_soc_7_9_write, snd_soc_7_9_spi_write, snd_soc_7_9_read },
	{ 8, 8, snd_soc_8_8_write, NULL, snd_soc_8_8_read, NULL },
	{ 8, 16, snd_soc_8_16_write, NULL, snd_soc_8_16_read,
	  snd_soc_8_16_read_i2c },
};

/**
 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
 *
 * @codec: CODEC to configure.
 * @type: Type of cache.
 * @addr_bits: Number of bits of register address data.
 * @data_bits: Number of bits of data per register.
 * @control: Control bus used.
 *
 * Register formats are frequently shared between many I2C and SPI
 * devices.  In order to promote code reuse the ASoC core provides
 * some standard implementations of CODEC read and write operations
 * which can be set up using this function.
 *
 * The caller is responsible for allocating and initialising the
 * actual cache.
 *
 * Note that at present this code cannot be used by CODECs with
 * volatile registers.
 */
int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
			       int addr_bits, int data_bits,
			       enum snd_soc_control_type control)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(io_types); i++)
		if (io_types[i].addr_bits == addr_bits &&
		    io_types[i].data_bits == data_bits)
			break;
	if (i == ARRAY_SIZE(io_types)) {
		printk(KERN_ERR
		       "No I/O functions for %d bit address %d bit data\n",
		       addr_bits, data_bits);
		return -EINVAL;
	}

	codec->write = io_types[i].write;
	codec->read = io_types[i].read;

	switch (control) {
	case SND_SOC_CUSTOM:
		break;

	case SND_SOC_I2C:
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
		codec->hw_write = (hw_write_t)i2c_master_send;
#endif
		if (io_types[i].i2c_read)
			codec->hw_read = io_types[i].i2c_read;
		break;

	case SND_SOC_SPI:
		if (io_types[i].spi_write)
			codec->hw_write = io_types[i].spi_write;
		break;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
Commit	Line	Data
17a52fd6 MB	1	/*
	2	* soc-cache.c -- ASoC register cache helpers
	3	*
	4	* Copyright 2009 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
7084a42b	14	#include <linux/i2c.h>
27ded041	15	#include <linux/spi/spi.h>
17a52fd6 MB	16	#include <sound/soc.h>
	17
	18	static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
	19	unsigned int reg)
	20	{
	21	u16 *cache = codec->reg_cache;
	22	if (reg >= codec->reg_cache_size)
	23	return -1;
	24	return cache[reg];
	25	}
	26
	27	static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
	28	unsigned int value)
	29	{
	30	u16 *cache = codec->reg_cache;
	31	u8 data[2];
	32	int ret;
	33
	34	BUG_ON(codec->volatile_register);
	35
	36	data[0] = (reg << 1) \| ((value >> 8) & 0x0001);
	37	data[1] = value & 0x00ff;
	38
	39	if (reg < codec->reg_cache_size)
	40	cache[reg] = value;
	41	ret = codec->hw_write(codec->control_data, data, 2);
	42	if (ret == 2)
	43	return 0;
	44	if (ret < 0)
	45	return ret;
	46	else
	47	return -EIO;
	48	}
	49
27ded041 MB	50	#if defined(CONFIG_SPI_MASTER)
	51	static int snd_soc_7_9_spi_write(void control_data, const char data,
	52	int len)
	53	{
	54	struct spi_device *spi = control_data;
	55	struct spi_transfer t;
	56	struct spi_message m;
	57	u8 msg[2];
	58
	59	if (len <= 0)
	60	return 0;
	61
	62	msg[0] = data[0];
	63	msg[1] = data[1];
	64
	65	spi_message_init(&m);
	66	memset(&t, 0, (sizeof t));
	67
	68	t.tx_buf = &msg[0];
	69	t.len = len;
	70
	71	spi_message_add_tail(&t, &m);
	72	spi_sync(spi, &m);
	73
	74	return len;
	75	}
	76	#else
	77	#define snd_soc_7_9_spi_write NULL
	78	#endif
	79
341c9b84 JS	80	static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
	81	unsigned int value)
	82	{
	83	u8 *cache = codec->reg_cache;
	84	u8 data[2];
	85
	86	BUG_ON(codec->volatile_register);
	87
	88	data[0] = reg & 0xff;
	89	data[1] = value & 0xff;
	90
	91	if (reg < codec->reg_cache_size)
	92	cache[reg] = value;
	93
	94	if (codec->hw_write(codec->control_data, data, 2) == 2)
	95	return 0;
	96	else
	97	return -EIO;
	98	}
	99
	100	static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
	101	unsigned int reg)
	102	{
	103	u8 *cache = codec->reg_cache;
	104	if (reg >= codec->reg_cache_size)
	105	return -1;
	106	return cache[reg];
	107	}
	108
afa2f106 MB	109	static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
	110	unsigned int value)
	111	{
	112	u16 *reg_cache = codec->reg_cache;
	113	u8 data[3];
	114
	115	data[0] = reg;
	116	data[1] = (value >> 8) & 0xff;
	117	data[2] = value & 0xff;
	118
	119	if (!snd_soc_codec_volatile_register(codec, reg))
	120	reg_cache[reg] = value;
	121
	122	if (codec->hw_write(codec->control_data, data, 3) == 3)
	123	return 0;
	124	else
	125	return -EIO;
	126	}
	127
	128	static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
	129	unsigned int reg)
	130	{
	131	u16 *cache = codec->reg_cache;
	132
	133	if (reg >= codec->reg_cache_size \|\|
	134	snd_soc_codec_volatile_register(codec, reg))
	135	return codec->hw_read(codec, reg);
	136	else
	137	return cache[reg];
	138	}
	139
17244c24	140	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
afa2f106 MB	141	static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
	142	unsigned int r)
	143	{
	144	struct i2c_msg xfer[2];
	145	u8 reg = r;
	146	u16 data;
	147	int ret;
	148	struct i2c_client *client = codec->control_data;
	149
	150	/* Write register */
	151	xfer[0].addr = client->addr;
	152	xfer[0].flags = 0;
	153	xfer[0].len = 1;
	154	xfer[0].buf = ®
	155
	156	/* Read data */
	157	xfer[1].addr = client->addr;
	158	xfer[1].flags = I2C_M_RD;
	159	xfer[1].len = 2;
	160	xfer[1].buf = (u8 *)&data;
	161
	162	ret = i2c_transfer(client->adapter, xfer, 2);
	163	if (ret != 2) {
	164	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	165	return 0;
	166	}
	167
	168	return (data >> 8) \| ((data & 0xff) << 8);
	169	}
	170	#else
	171	#define snd_soc_8_16_read_i2c NULL
	172	#endif
17a52fd6 MB	173
	174	static struct {
	175	int addr_bits;
	176	int data_bits;
afa2f106	177	int (write)(struct snd_soc_codec codec, unsigned int, unsigned int);
27ded041	178	int (spi_write)(void , const char *, int);
17a52fd6	179	unsigned int (read)(struct snd_soc_codec , unsigned int);
afa2f106	180	unsigned int (i2c_read)(struct snd_soc_codec , unsigned int);
17a52fd6	181	} io_types[] = {
27ded041	182	{ 7, 9, snd_soc_7_9_write, snd_soc_7_9_spi_write, snd_soc_7_9_read },
341c9b84	183	{ 8, 8, snd_soc_8_8_write, NULL, snd_soc_8_8_read, NULL },
27ded041	184	{ 8, 16, snd_soc_8_16_write, NULL, snd_soc_8_16_read,
afa2f106	185	snd_soc_8_16_read_i2c },
17a52fd6 MB	186	};
	187
	188	/**
	189	* snd_soc_codec_set_cache_io: Set up standard I/O functions.
	190	*
	191	* @codec: CODEC to configure.
	192	* @type: Type of cache.
	193	* @addr_bits: Number of bits of register address data.
	194	* @data_bits: Number of bits of data per register.
7084a42b	195	* @control: Control bus used.
17a52fd6 MB	196	*
	197	* Register formats are frequently shared between many I2C and SPI
	198	* devices. In order to promote code reuse the ASoC core provides
	199	* some standard implementations of CODEC read and write operations
	200	* which can be set up using this function.
	201	*
	202	* The caller is responsible for allocating and initialising the
	203	* actual cache.
	204	*
	205	* Note that at present this code cannot be used by CODECs with
	206	* volatile registers.
	207	*/
	208	int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
7084a42b MB	209	int addr_bits, int data_bits,
7084a42b MB	210	enum snd_soc_control_type control)
17a52fd6 MB	211	{
	212	int i;
	213
17a52fd6 MB	214	for (i = 0; i < ARRAY_SIZE(io_types); i++)
	215	if (io_types[i].addr_bits == addr_bits &&
	216	io_types[i].data_bits == data_bits)
	217	break;
	218	if (i == ARRAY_SIZE(io_types)) {
	219	printk(KERN_ERR
	220	"No I/O functions for %d bit address %d bit data\n",
	221	addr_bits, data_bits);
	222	return -EINVAL;
	223	}
	224
	225	codec->write = io_types[i].write;
	226	codec->read = io_types[i].read;
	227
7084a42b MB	228	switch (control) {
	229	case SND_SOC_CUSTOM:
	230	break;
	231
	232	case SND_SOC_I2C:
17244c24	233	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
7084a42b MB	234	codec->hw_write = (hw_write_t)i2c_master_send;
7084a42b MB	235	#endif
afa2f106 MB	236	if (io_types[i].i2c_read)
afa2f106 MB	237	codec->hw_read = io_types[i].i2c_read;
7084a42b MB	238	break;
	239
	240	case SND_SOC_SPI:
27ded041 MB	241	if (io_types[i].spi_write)
27ded041 MB	242	codec->hw_write = io_types[i].spi_write;
7084a42b MB	243	break;
	244	}
	245
17a52fd6 MB	246	return 0;
	247	}
	248	EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);