[net-next-2.6.git] / sound / soc / soc-cache.c

/*
 * soc-cache.c  --  ASoC register cache helpers
 *
 * Copyright 2009 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>

static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[2];
	int ret;

	BUG_ON(codec->volatile_register);

	data[0] = (reg << 4) | ((value >> 8) & 0x000f);
	data[1] = value & 0x00ff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;
	ret = codec->hw_write(codec->control_data, data, 2);
	if (ret == 2)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_4_12_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[1];
	msg[1] = data[0];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_4_12_spi_write NULL
#endif

static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[2];
	int ret;

	BUG_ON(codec->volatile_register);

	data[0] = (reg << 1) | ((value >> 8) & 0x0001);
	data[1] = value & 0x00ff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;
	ret = codec->hw_write(codec->control_data, data, 2);
	if (ret == 2)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_7_9_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_7_9_spi_write NULL
#endif

static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u8 *cache = codec->reg_cache;
	u8 data[2];

	BUG_ON(codec->volatile_register);

	data[0] = reg & 0xff;
	data[1] = value & 0xff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;

	if (codec->hw_write(codec->control_data, data, 2) == 2)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u8 *cache = codec->reg_cache;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
			      unsigned int value)
{
	u16 *reg_cache = codec->reg_cache;
	u8 data[3];

	data[0] = reg;
	data[1] = (value >> 8) & 0xff;
	data[2] = value & 0xff;

	if (!snd_soc_codec_volatile_register(codec, reg))
		reg_cache[reg] = value;

	if (codec->hw_write(codec->control_data, data, 3) == 3)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
				      unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->reg_cache_size ||
	    snd_soc_codec_volatile_register(codec, reg))
		return codec->hw_read(codec, reg);
	else
		return cache[reg];
}

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u8 reg = r;
	u16 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 1;
	xfer[0].buf = &reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 2;
	xfer[1].buf = (u8 *)&data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return (data >> 8) | ((data & 0xff) << 8);
}
#else
#define snd_soc_8_16_read_i2c NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u16 reg = r;
	u8 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 2;
	xfer[0].buf = (u8 *)&reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 1;
	xfer[1].buf = &data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return data;
}
#else
#define snd_soc_16_8_read_i2c NULL
#endif

static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	reg &= 0xff;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[3];
	int ret;

	BUG_ON(codec->volatile_register);

	data[0] = (reg >> 8) & 0xff;
	data[1] = reg & 0xff;
	data[2] = value;

	reg &= 0xff;
	if (reg < codec->reg_cache_size)
		cache[reg] = value;
	ret = codec->hw_write(codec->control_data, data, 3);
	if (ret == 3)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_16_8_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[3];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];
	msg[2] = data[2];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_16_8_spi_write NULL
#endif


static struct {
	int addr_bits;
	int data_bits;
	int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
	int (*spi_write)(void *, const char *, int);
	unsigned int (*read)(struct snd_soc_codec *, unsigned int);
	unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
} io_types[] = {
	{
		.addr_bits = 4, .data_bits = 12,
		.write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
		.spi_write = snd_soc_4_12_spi_write,
	},
	{
		.addr_bits = 7, .data_bits = 9,
		.write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
		.spi_write = snd_soc_7_9_spi_write,
	},
	{
		.addr_bits = 8, .data_bits = 8,
		.write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
	},
	{
		.addr_bits = 8, .data_bits = 16,
		.write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
		.i2c_read = snd_soc_8_16_read_i2c,
	},
	{
		.addr_bits = 16, .data_bits = 8,
		.write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
		.i2c_read = snd_soc_16_8_read_i2c,
		.spi_write = snd_soc_16_8_spi_write,
	},
};

/**
 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
 *
 * @codec: CODEC to configure.
 * @type: Type of cache.
 * @addr_bits: Number of bits of register address data.
 * @data_bits: Number of bits of data per register.
 * @control: Control bus used.
 *
 * Register formats are frequently shared between many I2C and SPI
 * devices.  In order to promote code reuse the ASoC core provides
 * some standard implementations of CODEC read and write operations
 * which can be set up using this function.
 *
 * The caller is responsible for allocating and initialising the
 * actual cache.
 *
 * Note that at present this code cannot be used by CODECs with
 * volatile registers.
 */
int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
			       int addr_bits, int data_bits,
			       enum snd_soc_control_type control)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(io_types); i++)
		if (io_types[i].addr_bits == addr_bits &&
		    io_types[i].data_bits == data_bits)
			break;
	if (i == ARRAY_SIZE(io_types)) {
		printk(KERN_ERR
		       "No I/O functions for %d bit address %d bit data\n",
		       addr_bits, data_bits);
		return -EINVAL;
	}

	codec->write = io_types[i].write;
	codec->read = io_types[i].read;

	switch (control) {
	case SND_SOC_CUSTOM:
		break;

	case SND_SOC_I2C:
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
		codec->hw_write = (hw_write_t)i2c_master_send;
#endif
		if (io_types[i].i2c_read)
			codec->hw_read = io_types[i].i2c_read;
		break;

	case SND_SOC_SPI:
		if (io_types[i].spi_write)
			codec->hw_write = io_types[i].spi_write;
		break;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
Commit	Line	Data
17a52fd6 MB	1	/*
	2	* soc-cache.c -- ASoC register cache helpers
	3	*
	4	* Copyright 2009 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
7084a42b	14	#include <linux/i2c.h>
27ded041	15	#include <linux/spi/spi.h>
17a52fd6 MB	16	#include <sound/soc.h>
17a52fd6 MB	17
63b62ab0 BS	18	static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
	19	unsigned int reg)
	20	{
	21	u16 *cache = codec->reg_cache;
	22	if (reg >= codec->reg_cache_size)
	23	return -1;
	24	return cache[reg];
	25	}
	26
	27	static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
	28	unsigned int value)
	29	{
	30	u16 *cache = codec->reg_cache;
	31	u8 data[2];
	32	int ret;
	33
	34	BUG_ON(codec->volatile_register);
	35
	36	data[0] = (reg << 4) \| ((value >> 8) & 0x000f);
	37	data[1] = value & 0x00ff;
	38
	39	if (reg < codec->reg_cache_size)
	40	cache[reg] = value;
	41	ret = codec->hw_write(codec->control_data, data, 2);
	42	if (ret == 2)
	43	return 0;
	44	if (ret < 0)
	45	return ret;
	46	else
	47	return -EIO;
	48	}
	49
	50	#if defined(CONFIG_SPI_MASTER)
	51	static int snd_soc_4_12_spi_write(void control_data, const char data,
	52	int len)
	53	{
	54	struct spi_device *spi = control_data;
	55	struct spi_transfer t;
	56	struct spi_message m;
	57	u8 msg[2];
	58
	59	if (len <= 0)
	60	return 0;
	61
	62	msg[0] = data[1];
	63	msg[1] = data[0];
	64
	65	spi_message_init(&m);
	66	memset(&t, 0, (sizeof t));
	67
	68	t.tx_buf = &msg[0];
	69	t.len = len;
	70
	71	spi_message_add_tail(&t, &m);
	72	spi_sync(spi, &m);
	73
	74	return len;
	75	}
	76	#else
	77	#define snd_soc_4_12_spi_write NULL
	78	#endif
	79
17a52fd6 MB	80	static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
	81	unsigned int reg)
	82	{
	83	u16 *cache = codec->reg_cache;
	84	if (reg >= codec->reg_cache_size)
	85	return -1;
	86	return cache[reg];
	87	}
	88
	89	static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
	90	unsigned int value)
	91	{
	92	u16 *cache = codec->reg_cache;
	93	u8 data[2];
	94	int ret;
	95
	96	BUG_ON(codec->volatile_register);
	97
	98	data[0] = (reg << 1) \| ((value >> 8) & 0x0001);
	99	data[1] = value & 0x00ff;
	100
	101	if (reg < codec->reg_cache_size)
	102	cache[reg] = value;
	103	ret = codec->hw_write(codec->control_data, data, 2);
	104	if (ret == 2)
	105	return 0;
	106	if (ret < 0)
	107	return ret;
	108	else
	109	return -EIO;
	110	}
	111
27ded041 MB	112	#if defined(CONFIG_SPI_MASTER)
	113	static int snd_soc_7_9_spi_write(void control_data, const char data,
	114	int len)
	115	{
	116	struct spi_device *spi = control_data;
	117	struct spi_transfer t;
	118	struct spi_message m;
	119	u8 msg[2];
	120
	121	if (len <= 0)
	122	return 0;
	123
	124	msg[0] = data[0];
	125	msg[1] = data[1];
	126
	127	spi_message_init(&m);
	128	memset(&t, 0, (sizeof t));
	129
	130	t.tx_buf = &msg[0];
	131	t.len = len;
	132
	133	spi_message_add_tail(&t, &m);
	134	spi_sync(spi, &m);
	135
	136	return len;
	137	}
	138	#else
	139	#define snd_soc_7_9_spi_write NULL
	140	#endif
	141
341c9b84 JS	142	static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
	143	unsigned int value)
	144	{
	145	u8 *cache = codec->reg_cache;
	146	u8 data[2];
	147
	148	BUG_ON(codec->volatile_register);
	149
	150	data[0] = reg & 0xff;
	151	data[1] = value & 0xff;
	152
	153	if (reg < codec->reg_cache_size)
	154	cache[reg] = value;
	155
	156	if (codec->hw_write(codec->control_data, data, 2) == 2)
	157	return 0;
	158	else
	159	return -EIO;
	160	}
	161
	162	static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
	163	unsigned int reg)
	164	{
	165	u8 *cache = codec->reg_cache;
	166	if (reg >= codec->reg_cache_size)
	167	return -1;
	168	return cache[reg];
	169	}
	170
afa2f106 MB	171	static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
	172	unsigned int value)
	173	{
	174	u16 *reg_cache = codec->reg_cache;
	175	u8 data[3];
	176
	177	data[0] = reg;
	178	data[1] = (value >> 8) & 0xff;
	179	data[2] = value & 0xff;
	180
	181	if (!snd_soc_codec_volatile_register(codec, reg))
	182	reg_cache[reg] = value;
	183
	184	if (codec->hw_write(codec->control_data, data, 3) == 3)
	185	return 0;
	186	else
	187	return -EIO;
	188	}
	189
	190	static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
	191	unsigned int reg)
	192	{
	193	u16 *cache = codec->reg_cache;
	194
	195	if (reg >= codec->reg_cache_size \|\|
	196	snd_soc_codec_volatile_register(codec, reg))
	197	return codec->hw_read(codec, reg);
	198	else
	199	return cache[reg];
	200	}
	201
17244c24	202	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
afa2f106 MB	203	static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
	204	unsigned int r)
	205	{
	206	struct i2c_msg xfer[2];
	207	u8 reg = r;
	208	u16 data;
	209	int ret;
	210	struct i2c_client *client = codec->control_data;
	211
	212	/* Write register */
	213	xfer[0].addr = client->addr;
	214	xfer[0].flags = 0;
	215	xfer[0].len = 1;
	216	xfer[0].buf = ®
	217
	218	/* Read data */
	219	xfer[1].addr = client->addr;
	220	xfer[1].flags = I2C_M_RD;
	221	xfer[1].len = 2;
	222	xfer[1].buf = (u8 *)&data;
	223
	224	ret = i2c_transfer(client->adapter, xfer, 2);
	225	if (ret != 2) {
	226	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	227	return 0;
	228	}
	229
	230	return (data >> 8) \| ((data & 0xff) << 8);
	231	}
	232	#else
	233	#define snd_soc_8_16_read_i2c NULL
	234	#endif
17a52fd6	235
994dc424 BS	236	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	237	static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
	238	unsigned int r)
	239	{
	240	struct i2c_msg xfer[2];
	241	u16 reg = r;
	242	u8 data;
	243	int ret;
	244	struct i2c_client *client = codec->control_data;
	245
	246	/* Write register */
	247	xfer[0].addr = client->addr;
	248	xfer[0].flags = 0;
	249	xfer[0].len = 2;
	250	xfer[0].buf = (u8 *)®
	251
	252	/* Read data */
	253	xfer[1].addr = client->addr;
	254	xfer[1].flags = I2C_M_RD;
	255	xfer[1].len = 1;
	256	xfer[1].buf = &data;
	257
	258	ret = i2c_transfer(client->adapter, xfer, 2);
	259	if (ret != 2) {
	260	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	261	return 0;
	262	}
	263
	264	return data;
	265	}
	266	#else
	267	#define snd_soc_16_8_read_i2c NULL
	268	#endif
	269
	270	static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
	271	unsigned int reg)
	272	{
	273	u16 *cache = codec->reg_cache;
	274
	275	reg &= 0xff;
	276	if (reg >= codec->reg_cache_size)
	277	return -1;
	278	return cache[reg];
	279	}
	280
	281	static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
	282	unsigned int value)
	283	{
	284	u16 *cache = codec->reg_cache;
	285	u8 data[3];
	286	int ret;
	287
	288	BUG_ON(codec->volatile_register);
	289
	290	data[0] = (reg >> 8) & 0xff;
	291	data[1] = reg & 0xff;
	292	data[2] = value;
	293
	294	reg &= 0xff;
	295	if (reg < codec->reg_cache_size)
	296	cache[reg] = value;
	297	ret = codec->hw_write(codec->control_data, data, 3);
	298	if (ret == 3)
	299	return 0;
300	if (ret < 0)
301	return ret;
302	else
303	return -EIO;
304	}
305
306	#if defined(CONFIG_SPI_MASTER)
307	static int snd_soc_16_8_spi_write(void control_data, const char data,
308	int len)
309	{
310	struct spi_device *spi = control_data;
311	struct spi_transfer t;
312	struct spi_message m;
313	u8 msg[3];
314
315	if (len <= 0)
316	return 0;
317
318	msg[0] = data[0];
319	msg[1] = data[1];
320	msg[2] = data[2];
321
322	spi_message_init(&m);
323	memset(&t, 0, (sizeof t));
324
325	t.tx_buf = &msg[0];
326	t.len = len;
327
328	spi_message_add_tail(&t, &m);
329	spi_sync(spi, &m);
330
331	return len;
332	}
333	#else
334	#define snd_soc_16_8_spi_write NULL
335	#endif
336
337
17a52fd6 MB	338	static struct {
	339	int addr_bits;
	340	int data_bits;
afa2f106	341	int (write)(struct snd_soc_codec codec, unsigned int, unsigned int);
27ded041	342	int (spi_write)(void , const char *, int);
17a52fd6	343	unsigned int (read)(struct snd_soc_codec , unsigned int);
afa2f106	344	unsigned int (i2c_read)(struct snd_soc_codec , unsigned int);
17a52fd6	345	} io_types[] = {
63b62ab0 BS	346	{
	347	.addr_bits = 4, .data_bits = 12,
	348	.write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
	349	.spi_write = snd_soc_4_12_spi_write,
	350	},
d62ab358 MB	351	{
	352	.addr_bits = 7, .data_bits = 9,
	353	.write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
8998c899	354	.spi_write = snd_soc_7_9_spi_write,
d62ab358 MB	355	},
	356	{
	357	.addr_bits = 8, .data_bits = 8,
	358	.write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
	359	},
	360	{
	361	.addr_bits = 8, .data_bits = 16,
	362	.write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
	363	.i2c_read = snd_soc_8_16_read_i2c,
	364	},
994dc424 BS	365	{
	366	.addr_bits = 16, .data_bits = 8,
	367	.write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
	368	.i2c_read = snd_soc_16_8_read_i2c,
	369	.spi_write = snd_soc_16_8_spi_write,
	370	},
17a52fd6 MB	371	};
	372
	373	/**
	374	* snd_soc_codec_set_cache_io: Set up standard I/O functions.
	375	*
	376	* @codec: CODEC to configure.
	377	* @type: Type of cache.
	378	* @addr_bits: Number of bits of register address data.
	379	* @data_bits: Number of bits of data per register.
7084a42b	380	* @control: Control bus used.
17a52fd6 MB	381	*
	382	* Register formats are frequently shared between many I2C and SPI
	383	* devices. In order to promote code reuse the ASoC core provides
	384	* some standard implementations of CODEC read and write operations
	385	* which can be set up using this function.
	386	*
	387	* The caller is responsible for allocating and initialising the
	388	* actual cache.
	389	*
	390	* Note that at present this code cannot be used by CODECs with
	391	* volatile registers.
	392	*/
	393	int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
7084a42b MB	394	int addr_bits, int data_bits,
7084a42b MB	395	enum snd_soc_control_type control)
17a52fd6 MB	396	{
	397	int i;
	398
17a52fd6 MB	399	for (i = 0; i < ARRAY_SIZE(io_types); i++)
	400	if (io_types[i].addr_bits == addr_bits &&
	401	io_types[i].data_bits == data_bits)
	402	break;
	403	if (i == ARRAY_SIZE(io_types)) {
	404	printk(KERN_ERR
	405	"No I/O functions for %d bit address %d bit data\n",
	406	addr_bits, data_bits);
	407	return -EINVAL;
	408	}
	409
	410	codec->write = io_types[i].write;
	411	codec->read = io_types[i].read;
	412
7084a42b MB	413	switch (control) {
	414	case SND_SOC_CUSTOM:
	415	break;
	416
	417	case SND_SOC_I2C:
17244c24	418	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
7084a42b MB	419	codec->hw_write = (hw_write_t)i2c_master_send;
7084a42b MB	420	#endif
afa2f106 MB	421	if (io_types[i].i2c_read)
afa2f106 MB	422	codec->hw_read = io_types[i].i2c_read;
7084a42b MB	423	break;
	424
	425	case SND_SOC_SPI:
27ded041 MB	426	if (io_types[i].spi_write)
27ded041 MB	427	codec->hw_write = io_types[i].spi_write;
7084a42b MB	428	break;
	429	}
	430
17a52fd6 MB	431	return 0;
	432	}
	433	EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);