[net-next-2.6.git] / sound / soc / imx / imx-ssi.c

/*
 * imx-ssi.c  --  ALSA Soc Audio Layer
 *
 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
 *
 * This code is based on code copyrighted by Freescale,
 * Liam Girdwood, Javier Martin and probably others.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *
 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 * one FIFO which combines all valid receive slots. We cannot even select
 * which slots we want to receive. The WM9712 with which this driver
 * was developped with always sends GPIO status data in slot 12 which
 * we receive in our (PCM-) data stream. The only chance we have is to
 * manually skip this data in the FIQ handler. With sampling rates different
 * from 48000Hz not every frame has valid receive data, so the ratio
 * between pcm data and GPIO status data changes. Our FIQ handler is not
 * able to handle this, hence this driver only works with 48000Hz sampling
 * rate.
 * Reading and writing AC97 registers is another challenge. The core
 * provides us status bits when the read register is updated with *another*
 * value. When we read the same register two times (and the register still
 * contains the same value) these status bits are not set. We work
 * around this by not polling these bits but only wait a fixed delay.
 * 
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <mach/ssi.h>
#include <mach/hardware.h>

#include "imx-ssi.h"

#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)

/*
 * SSI Network Mode or TDM slots configuration.
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 */
static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
	struct imx_ssi *ssi = cpu_dai->private_data;
	u32 sccr;

	sccr = readl(ssi->base + SSI_STCCR);
	sccr &= ~SSI_STCCR_DC_MASK;
	sccr |= SSI_STCCR_DC(slots - 1);
	writel(sccr, ssi->base + SSI_STCCR);

	sccr = readl(ssi->base + SSI_SRCCR);
	sccr &= ~SSI_STCCR_DC_MASK;
	sccr |= SSI_STCCR_DC(slots - 1);
	writel(sccr, ssi->base + SSI_SRCCR);

	writel(tx_mask, ssi->base + SSI_STMSK);
	writel(rx_mask, ssi->base + SSI_SRMSK);

	return 0;
}

/*
 * SSI DAI format configuration.
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 * Note: We don't use the I2S modes but instead manually configure the
 * SSI for I2S because the I2S mode is only a register preset.
 */
static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
	struct imx_ssi *ssi = cpu_dai->private_data;
	u32 strcr = 0, scr;

	scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);

	/* DAI mode */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* data on rising edge of bclk, frame low 1clk before data */
		strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
		scr |= SSI_SCR_NET;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		/* data on rising edge of bclk, frame high with data */
		strcr |= SSI_STCR_TXBIT0;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/* data on rising edge of bclk, frame high with data */
		strcr |= SSI_STCR_TFSL;
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/* data on rising edge of bclk, frame high 1clk before data */
		strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
		break;
	}

	/* DAI clock inversion */
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_IF:
		strcr |= SSI_STCR_TFSI;
		strcr &= ~SSI_STCR_TSCKP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
		break;
	case SND_SOC_DAIFMT_NB_NF:
		strcr &= ~SSI_STCR_TFSI;
		strcr |= SSI_STCR_TSCKP;
		break;
	}

	/* DAI clock master masks */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		/* Master mode not implemented, needs handling of clocks. */
		return -EINVAL;
	}

	strcr |= SSI_STCR_TFEN0;

	writel(strcr, ssi->base + SSI_STCR);
	writel(strcr, ssi->base + SSI_SRCR);
	writel(scr, ssi->base + SSI_SCR);

	return 0;
}

/*
 * SSI system clock configuration.
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 */
static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct imx_ssi *ssi = cpu_dai->private_data;
	u32 scr;

	scr = readl(ssi->base + SSI_SCR);

	switch (clk_id) {
	case IMX_SSP_SYS_CLK:
		if (dir == SND_SOC_CLOCK_OUT)
			scr |= SSI_SCR_SYS_CLK_EN;
		else
			scr &= ~SSI_SCR_SYS_CLK_EN;
		break;
	default:
		return -EINVAL;
	}

	writel(scr, ssi->base + SSI_SCR);

	return 0;
}

/*
 * SSI Clock dividers
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 */
static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
				  int div_id, int div)
{
	struct imx_ssi *ssi = cpu_dai->private_data;
	u32 stccr, srccr;

	stccr = readl(ssi->base + SSI_STCCR);
	srccr = readl(ssi->base + SSI_SRCCR);

	switch (div_id) {
	case IMX_SSI_TX_DIV_2:
		stccr &= ~SSI_STCCR_DIV2;
		stccr |= div;
		break;
	case IMX_SSI_TX_DIV_PSR:
		stccr &= ~SSI_STCCR_PSR;
		stccr |= div;
		break;
	case IMX_SSI_TX_DIV_PM:
		stccr &= ~0xff;
		stccr |= SSI_STCCR_PM(div);
		break;
	case IMX_SSI_RX_DIV_2:
		stccr &= ~SSI_STCCR_DIV2;
		stccr |= div;
		break;
	case IMX_SSI_RX_DIV_PSR:
		stccr &= ~SSI_STCCR_PSR;
		stccr |= div;
		break;
	case IMX_SSI_RX_DIV_PM:
		stccr &= ~0xff;
		stccr |= SSI_STCCR_PM(div);
		break;
	default:
		return -EINVAL;
	}

	writel(stccr, ssi->base + SSI_STCCR);
	writel(srccr, ssi->base + SSI_SRCCR);

	return 0;
}

/*
 * Should only be called when port is inactive (i.e. SSIEN = 0),
 * although can be called multiple times by upper layers.
 */
static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *params,
			     struct snd_soc_dai *cpu_dai)
{
	struct imx_ssi *ssi = cpu_dai->private_data;
	struct imx_pcm_dma_params *dma_data;
	u32 reg, sccr;

	/* Tx/Rx config */
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		reg = SSI_STCCR;
		dma_data = &ssi->dma_params_tx;
	} else {
		reg = SSI_SRCCR;
		dma_data = &ssi->dma_params_rx;
	}

	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);

	sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;

	/* DAI data (word) size */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		sccr |= SSI_SRCCR_WL(16);
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		sccr |= SSI_SRCCR_WL(20);
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		sccr |= SSI_SRCCR_WL(24);
		break;
	}

	writel(sccr, ssi->base + reg);

	return 0;
}

static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
		struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct imx_ssi *ssi = cpu_dai->private_data;
	unsigned int sier_bits, sier;
	unsigned int scr;

	scr = readl(ssi->base + SSI_SCR);
	sier = readl(ssi->base + SSI_SIER);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		if (ssi->flags & IMX_SSI_DMA)
			sier_bits = SSI_SIER_TDMAE;
		else
			sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
	} else {
		if (ssi->flags & IMX_SSI_DMA)
			sier_bits = SSI_SIER_RDMAE;
		else
			sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
	}

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			scr |= SSI_SCR_TE;
		else
			scr |= SSI_SCR_RE;
		sier |= sier_bits;

		if (++ssi->enabled == 1)
			scr |= SSI_SCR_SSIEN;

		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			scr &= ~SSI_SCR_TE;
		else
			scr &= ~SSI_SCR_RE;
		sier &= ~sier_bits;

		if (--ssi->enabled == 0)
			scr &= ~SSI_SCR_SSIEN;

		break;
	default:
		return -EINVAL;
	}

	if (!(ssi->flags & IMX_SSI_USE_AC97))
		/* rx/tx are always enabled to access ac97 registers */
		writel(scr, ssi->base + SSI_SCR);

	writel(sier, ssi->base + SSI_SIER);

	return 0;
}

static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
	.hw_params	= imx_ssi_hw_params,
	.set_fmt	= imx_ssi_set_dai_fmt,
	.set_clkdiv	= imx_ssi_set_dai_clkdiv,
	.set_sysclk	= imx_ssi_set_dai_sysclk,
	.set_tdm_slot	= imx_ssi_set_dai_tdm_slot,
	.trigger	= imx_ssi_trigger,
};

static struct snd_soc_dai imx_ssi_dai = {
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &imx_ssi_pcm_dai_ops,
};

int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
		struct vm_area_struct *vma)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	int ret;

	ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
			runtime->dma_addr, runtime->dma_bytes);

	pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
			runtime->dma_area,
			runtime->dma_addr,
			runtime->dma_bytes);
	return ret;
}

static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
{
	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
	struct snd_dma_buffer *buf = &substream->dma_buffer;
	size_t size = IMX_SSI_DMABUF_SIZE;

	buf->dev.type = SNDRV_DMA_TYPE_DEV;
	buf->dev.dev = pcm->card->dev;
	buf->private_data = NULL;
	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
					   &buf->addr, GFP_KERNEL);
	if (!buf->area)
		return -ENOMEM;
	buf->bytes = size;

	return 0;
}

static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);

int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
	struct snd_pcm *pcm)
{

	int ret = 0;

	if (!card->dev->dma_mask)
		card->dev->dma_mask = &imx_pcm_dmamask;
	if (!card->dev->coherent_dma_mask)
		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
	if (dai->playback.channels_min) {
		ret = imx_pcm_preallocate_dma_buffer(pcm,
			SNDRV_PCM_STREAM_PLAYBACK);
		if (ret)
			goto out;
	}

	if (dai->capture.channels_min) {
		ret = imx_pcm_preallocate_dma_buffer(pcm,
			SNDRV_PCM_STREAM_CAPTURE);
		if (ret)
			goto out;
	}

out:
	return ret;
}

void imx_pcm_free(struct snd_pcm *pcm)
{
	struct snd_pcm_substream *substream;
	struct snd_dma_buffer *buf;
	int stream;

	for (stream = 0; stream < 2; stream++) {
		substream = pcm->streams[stream].substream;
		if (!substream)
			continue;

		buf = &substream->dma_buffer;
		if (!buf->area)
			continue;

		dma_free_writecombine(pcm->card->dev, buf->bytes,
				      buf->area, buf->addr);
		buf->area = NULL;
	}
}

struct snd_soc_platform imx_soc_platform = {
	.name		= "imx-audio",
};
EXPORT_SYMBOL_GPL(imx_soc_platform);

static struct snd_soc_dai imx_ac97_dai = {
	.name = "AC97",
	.ac97_control = 1,
	.playback = {
		.stream_name = "AC97 Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.stream_name = "AC97 Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &imx_ssi_pcm_dai_ops,
};

static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
{
	void __iomem *base = imx_ssi->base;

	writel(0x0, base + SSI_SCR);
	writel(0x0, base + SSI_STCR);
	writel(0x0, base + SSI_SRCR);

	writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);

	writel(SSI_SFCSR_RFWM0(8) |
		SSI_SFCSR_TFWM0(8) |
		SSI_SFCSR_RFWM1(8) |
		SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);

	writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
	writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);

	writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
	writel(SSI_SOR_WAIT(3), base + SSI_SOR);

	writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
			SSI_SCR_TE | SSI_SCR_RE,
			base + SSI_SCR);

	writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
	writel(0xff, base + SSI_SACCDIS);
	writel(0x300, base + SSI_SACCEN);
}

static struct imx_ssi *ac97_ssi;

static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
		unsigned short val)
{
	struct imx_ssi *imx_ssi = ac97_ssi;
	void __iomem *base = imx_ssi->base;
	unsigned int lreg;
	unsigned int lval;

	if (reg > 0x7f)
		return;

	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);

	lreg = reg <<  12;
	writel(lreg, base + SSI_SACADD);

	lval = val << 4;
	writel(lval , base + SSI_SACDAT);

	writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
	udelay(100);
}

static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
		unsigned short reg)
{
	struct imx_ssi *imx_ssi = ac97_ssi;
	void __iomem *base = imx_ssi->base;

	unsigned short val = -1;
	unsigned int lreg;

	lreg = (reg & 0x7f) <<  12 ;
	writel(lreg, base + SSI_SACADD);
	writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);

	udelay(100);

	val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;

	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);

	return val;
}

static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
{
	struct imx_ssi *imx_ssi = ac97_ssi;

	if (imx_ssi->ac97_reset)
		imx_ssi->ac97_reset(ac97);
}

static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct imx_ssi *imx_ssi = ac97_ssi;

	if (imx_ssi->ac97_warm_reset)
		imx_ssi->ac97_warm_reset(ac97);
}

struct snd_ac97_bus_ops soc_ac97_ops = {
	.read		= imx_ssi_ac97_read,
	.write		= imx_ssi_ac97_write,
	.reset		= imx_ssi_ac97_reset,
	.warm_reset	= imx_ssi_ac97_warm_reset
};
EXPORT_SYMBOL_GPL(soc_ac97_ops);

struct snd_soc_dai imx_ssi_pcm_dai[2];
EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);

static int imx_ssi_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct imx_ssi *ssi;
	struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
	struct snd_soc_platform *platform;
	int ret = 0;
	unsigned int val;
	struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];

	if (dai->id >= ARRAY_SIZE(imx_ssi_pcm_dai))
		return -EINVAL;

	ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
	if (!ssi)
		return -ENOMEM;

	if (pdata) {
		ssi->ac97_reset = pdata->ac97_reset;
		ssi->ac97_warm_reset = pdata->ac97_warm_reset;
		ssi->flags = pdata->flags;
	}

	ssi->irq = platform_get_irq(pdev, 0);

	ssi->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(ssi->clk)) {
		ret = PTR_ERR(ssi->clk);
		dev_err(&pdev->dev, "Cannot get the clock: %d\n",
			ret);
		goto failed_clk;
	}
	clk_enable(ssi->clk);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENODEV;
		goto failed_get_resource;
	}

	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
		dev_err(&pdev->dev, "request_mem_region failed\n");
		ret = -EBUSY;
		goto failed_get_resource;
	}

	ssi->base = ioremap(res->start, resource_size(res));
	if (!ssi->base) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENODEV;
		goto failed_ioremap;
	}

	if (ssi->flags & IMX_SSI_USE_AC97) {
		if (ac97_ssi) {
			ret = -EBUSY;
			goto failed_ac97;
		}
		ac97_ssi = ssi;
		setup_channel_to_ac97(ssi);
		memcpy(dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
	} else
		memcpy(dai, &imx_ssi_dai, sizeof(imx_ssi_dai));

	writel(0x0, ssi->base + SSI_SIER);

	ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
	ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
	if (res)
		ssi->dma_params_tx.dma = res->start;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
	if (res)
		ssi->dma_params_rx.dma = res->start;

	dai->id = pdev->id;
	dai->dev = &pdev->dev;
	dai->name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
	dai->private_data = ssi;

	if ((cpu_is_mx27() || cpu_is_mx21()) &&
			!(ssi->flags & IMX_SSI_USE_AC97) &&
			(ssi->flags & IMX_SSI_DMA)) {
		ssi->flags |= IMX_SSI_DMA;
		platform = imx_ssi_dma_mx2_init(pdev, ssi);
	} else
		platform = imx_ssi_fiq_init(pdev, ssi);

	imx_soc_platform.pcm_ops = platform->pcm_ops;
	imx_soc_platform.pcm_new = platform->pcm_new;
	imx_soc_platform.pcm_free = platform->pcm_free;

	val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
		SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
	writel(val, ssi->base + SSI_SFCSR);

	ret = snd_soc_register_dai(dai);
	if (ret) {
		dev_err(&pdev->dev, "register DAI failed\n");
		goto failed_register;
	}

	platform_set_drvdata(pdev, ssi);

	return 0;

failed_register:
failed_ac97:
	iounmap(ssi->base);
failed_ioremap:
	release_mem_region(res->start, resource_size(res));
failed_get_resource:
	clk_disable(ssi->clk);
	clk_put(ssi->clk);
failed_clk:
	kfree(ssi);

	return ret;
}

static int __devexit imx_ssi_remove(struct platform_device *pdev)
{
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct imx_ssi *ssi = platform_get_drvdata(pdev);
	struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];

	snd_soc_unregister_dai(dai);

	if (ssi->flags & IMX_SSI_USE_AC97)
		ac97_ssi = NULL;

	if (!(ssi->flags & IMX_SSI_DMA))
		imx_ssi_fiq_exit(pdev, ssi);

	iounmap(ssi->base);
	release_mem_region(res->start, resource_size(res));
	clk_disable(ssi->clk);
	clk_put(ssi->clk);
	kfree(ssi);

	return 0;
}

static struct platform_driver imx_ssi_driver = {
	.probe = imx_ssi_probe,
	.remove = __devexit_p(imx_ssi_remove),

	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
	},
};

static int __init imx_ssi_init(void)
{
	int ret;

	ret = snd_soc_register_platform(&imx_soc_platform);
	if (ret) {
		pr_err("failed to register soc platform: %d\n", ret);
		return ret;
	}

	ret = platform_driver_register(&imx_ssi_driver);
	if (ret) {
		snd_soc_unregister_platform(&imx_soc_platform);
		return ret;
	}

	return 0;
}

static void __exit imx_ssi_exit(void)
{
	platform_driver_unregister(&imx_ssi_driver);
	snd_soc_unregister_platform(&imx_soc_platform);
}

module_init(imx_ssi_init);
module_exit(imx_ssi_exit);

/* Module information */
MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
8380222e SH	1	/*
	2	* imx-ssi.c -- ALSA Soc Audio Layer
	3	*
	4	* Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
	5	*
	6	* This code is based on code copyrighted by Freescale,
	7	* Liam Girdwood, Javier Martin and probably others.
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*
	14	*
	15	* The i.MX SSI core has some nasty limitations in AC97 mode. While most
	16	* sane processor vendors have a FIFO per AC97 slot, the i.MX has only
	17	* one FIFO which combines all valid receive slots. We cannot even select
	18	* which slots we want to receive. The WM9712 with which this driver
	19	* was developped with always sends GPIO status data in slot 12 which
	20	* we receive in our (PCM-) data stream. The only chance we have is to
	21	* manually skip this data in the FIQ handler. With sampling rates different
	22	* from 48000Hz not every frame has valid receive data, so the ratio
	23	* between pcm data and GPIO status data changes. Our FIQ handler is not
	24	* able to handle this, hence this driver only works with 48000Hz sampling
	25	* rate.
25d1fbfd	26	* Reading and writing AC97 registers is another challenge. The core
8380222e SH	27	* provides us status bits when the read register is updated with another
	28	* value. When we read the same register two times (and the register still
	29	* contains the same value) these status bits are not set. We work
	30	* around this by not polling these bits but only wait a fixed delay.
	31	*
	32	*/
	33
	34	#include <linux/clk.h>
	35	#include <linux/delay.h>
	36	#include <linux/device.h>
	37	#include <linux/dma-mapping.h>
	38	#include <linux/init.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/module.h>
	41	#include <linux/platform_device.h>
5a0e3ad6	42	#include <linux/slab.h>
8380222e SH	43
	44	#include <sound/core.h>
	45	#include <sound/initval.h>
	46	#include <sound/pcm.h>
	47	#include <sound/pcm_params.h>
	48	#include <sound/soc.h>
	49
	50	#include <mach/ssi.h>
	51	#include <mach/hardware.h>
	52
	53	#include "imx-ssi.h"
	54
	55	#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN \| SSI_SACNT_FV)
	56
	57	/*
	58	* SSI Network Mode or TDM slots configuration.
	59	* Should only be called when port is inactive (i.e. SSIEN = 0).
	60	*/
	61	static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
	62	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
	63	{
48dbc419	64	struct imx_ssi *ssi = cpu_dai->private_data;
8380222e SH	65	u32 sccr;
	66
	67	sccr = readl(ssi->base + SSI_STCCR);
	68	sccr &= ~SSI_STCCR_DC_MASK;
	69	sccr \|= SSI_STCCR_DC(slots - 1);
	70	writel(sccr, ssi->base + SSI_STCCR);
	71
	72	sccr = readl(ssi->base + SSI_SRCCR);
	73	sccr &= ~SSI_STCCR_DC_MASK;
	74	sccr \|= SSI_STCCR_DC(slots - 1);
	75	writel(sccr, ssi->base + SSI_SRCCR);
	76
	77	writel(tx_mask, ssi->base + SSI_STMSK);
	78	writel(rx_mask, ssi->base + SSI_SRMSK);
	79
	80	return 0;
	81	}
	82
	83	/*
	84	* SSI DAI format configuration.
	85	* Should only be called when port is inactive (i.e. SSIEN = 0).
	86	* Note: We don't use the I2S modes but instead manually configure the
	87	* SSI for I2S because the I2S mode is only a register preset.
	88	*/
	89	static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
	90	{
48dbc419	91	struct imx_ssi *ssi = cpu_dai->private_data;
8380222e SH	92	u32 strcr = 0, scr;
	93
	94	scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN \| SSI_SCR_NET);
	95
	96	/* DAI mode */
	97	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	98	case SND_SOC_DAIFMT_I2S:
	99	/* data on rising edge of bclk, frame low 1clk before data */
	100	strcr \|= SSI_STCR_TFSI \| SSI_STCR_TEFS \| SSI_STCR_TXBIT0;
	101	scr \|= SSI_SCR_NET;
	102	break;
	103	case SND_SOC_DAIFMT_LEFT_J:
	104	/* data on rising edge of bclk, frame high with data */
	105	strcr \|= SSI_STCR_TXBIT0;
	106	break;
	107	case SND_SOC_DAIFMT_DSP_B:
	108	/* data on rising edge of bclk, frame high with data */
	109	strcr \|= SSI_STCR_TFSL;
	110	break;
	111	case SND_SOC_DAIFMT_DSP_A:
	112	/* data on rising edge of bclk, frame high 1clk before data */
	113	strcr \|= SSI_STCR_TFSL \| SSI_STCR_TEFS;
	114	break;
	115	}
	116
	117	/* DAI clock inversion */
	118	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	119	case SND_SOC_DAIFMT_IB_IF:
	120	strcr \|= SSI_STCR_TFSI;
	121	strcr &= ~SSI_STCR_TSCKP;
	122	break;
	123	case SND_SOC_DAIFMT_IB_NF:
	124	strcr &= ~(SSI_STCR_TSCKP \| SSI_STCR_TFSI);
	125	break;
	126	case SND_SOC_DAIFMT_NB_IF:
	127	strcr \|= SSI_STCR_TFSI \| SSI_STCR_TSCKP;
	128	break;
	129	case SND_SOC_DAIFMT_NB_NF:
	130	strcr &= ~SSI_STCR_TFSI;
	131	strcr \|= SSI_STCR_TSCKP;
	132	break;
	133	}
	134
	135	/* DAI clock master masks */
	136	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
d08a68bf	137	case SND_SOC_DAIFMT_CBM_CFM:
8380222e	138	break;
d08a68bf MB	139	default:
	140	/* Master mode not implemented, needs handling of clocks. */
	141	return -EINVAL;
8380222e SH	142	}
	143
	144	strcr \|= SSI_STCR_TFEN0;
	145
	146	writel(strcr, ssi->base + SSI_STCR);
	147	writel(strcr, ssi->base + SSI_SRCR);
	148	writel(scr, ssi->base + SSI_SCR);
	149
	150	return 0;
	151	}
	152
	153	/*
	154	* SSI system clock configuration.
	155	* Should only be called when port is inactive (i.e. SSIEN = 0).
	156	*/
	157	static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
	158	int clk_id, unsigned int freq, int dir)
	159	{
48dbc419	160	struct imx_ssi *ssi = cpu_dai->private_data;
8380222e SH	161	u32 scr;
	162
	163	scr = readl(ssi->base + SSI_SCR);
	164
	165	switch (clk_id) {
	166	case IMX_SSP_SYS_CLK:
	167	if (dir == SND_SOC_CLOCK_OUT)
	168	scr \|= SSI_SCR_SYS_CLK_EN;
	169	else
	170	scr &= ~SSI_SCR_SYS_CLK_EN;
	171	break;
	172	default:
	173	return -EINVAL;
	174	}
	175
	176	writel(scr, ssi->base + SSI_SCR);
	177
	178	return 0;
	179	}
	180
	181	/*
	182	* SSI Clock dividers
	183	* Should only be called when port is inactive (i.e. SSIEN = 0).
	184	*/
	185	static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
	186	int div_id, int div)
	187	{
48dbc419	188	struct imx_ssi *ssi = cpu_dai->private_data;
8380222e SH	189	u32 stccr, srccr;
	190
	191	stccr = readl(ssi->base + SSI_STCCR);
	192	srccr = readl(ssi->base + SSI_SRCCR);
	193
	194	switch (div_id) {
	195	case IMX_SSI_TX_DIV_2:
	196	stccr &= ~SSI_STCCR_DIV2;
	197	stccr \|= div;
	198	break;
	199	case IMX_SSI_TX_DIV_PSR:
	200	stccr &= ~SSI_STCCR_PSR;
	201	stccr \|= div;
	202	break;
	203	case IMX_SSI_TX_DIV_PM:
	204	stccr &= ~0xff;
	205	stccr \|= SSI_STCCR_PM(div);
	206	break;
	207	case IMX_SSI_RX_DIV_2:
	208	stccr &= ~SSI_STCCR_DIV2;
	209	stccr \|= div;
	210	break;
	211	case IMX_SSI_RX_DIV_PSR:
	212	stccr &= ~SSI_STCCR_PSR;
	213	stccr \|= div;
	214	break;
	215	case IMX_SSI_RX_DIV_PM:
	216	stccr &= ~0xff;
	217	stccr \|= SSI_STCCR_PM(div);
	218	break;
	219	default:
	220	return -EINVAL;
	221	}
	222
	223	writel(stccr, ssi->base + SSI_STCCR);
	224	writel(srccr, ssi->base + SSI_SRCCR);
	225
	226	return 0;
	227	}
	228
	229	/*
	230	* Should only be called when port is inactive (i.e. SSIEN = 0),
	231	* although can be called multiple times by upper layers.
	232	*/
	233	static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
	234	struct snd_pcm_hw_params *params,
	235	struct snd_soc_dai *cpu_dai)
	236	{
48dbc419	237	struct imx_ssi *ssi = cpu_dai->private_data;
5f712b2b	238	struct imx_pcm_dma_params *dma_data;
8380222e SH	239	u32 reg, sccr;
	240
	241	/* Tx/Rx config */
	242	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	243	reg = SSI_STCCR;
5f712b2b	244	dma_data = &ssi->dma_params_tx;
8380222e SH	245	} else {
8380222e SH	246	reg = SSI_SRCCR;
5f712b2b	247	dma_data = &ssi->dma_params_rx;
8380222e SH	248	}
8380222e SH	249
5f712b2b DM	250	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
5f712b2b DM	251
8380222e SH	252	sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
	253
	254	/* DAI data (word) size */
	255	switch (params_format(params)) {
	256	case SNDRV_PCM_FORMAT_S16_LE:
	257	sccr \|= SSI_SRCCR_WL(16);
	258	break;
	259	case SNDRV_PCM_FORMAT_S20_3LE:
	260	sccr \|= SSI_SRCCR_WL(20);
	261	break;
	262	case SNDRV_PCM_FORMAT_S24_LE:
	263	sccr \|= SSI_SRCCR_WL(24);
	264	break;
	265	}
	266
	267	writel(sccr, ssi->base + reg);
	268
	269	return 0;
	270	}
	271
	272	static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
	273	struct snd_soc_dai *dai)
	274	{
	275	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	276	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
48dbc419	277	struct imx_ssi *ssi = cpu_dai->private_data;
8380222e SH	278	unsigned int sier_bits, sier;
	279	unsigned int scr;
	280
	281	scr = readl(ssi->base + SSI_SCR);
	282	sier = readl(ssi->base + SSI_SIER);
	283
	284	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	285	if (ssi->flags & IMX_SSI_DMA)
	286	sier_bits = SSI_SIER_TDMAE;
	287	else
	288	sier_bits = SSI_SIER_TIE \| SSI_SIER_TFE0_EN;
	289	} else {
	290	if (ssi->flags & IMX_SSI_DMA)
	291	sier_bits = SSI_SIER_RDMAE;
	292	else
	293	sier_bits = SSI_SIER_RIE \| SSI_SIER_RFF0_EN;
	294	}
	295
	296	switch (cmd) {
	297	case SNDRV_PCM_TRIGGER_START:
	298	case SNDRV_PCM_TRIGGER_RESUME:
	299	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	300	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	301	scr \|= SSI_SCR_TE;
	302	else
	303	scr \|= SSI_SCR_RE;
	304	sier \|= sier_bits;
	305
	306	if (++ssi->enabled == 1)
	307	scr \|= SSI_SCR_SSIEN;
	308
	309	break;
	310
	311	case SNDRV_PCM_TRIGGER_STOP:
	312	case SNDRV_PCM_TRIGGER_SUSPEND:
	313	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	314	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	315	scr &= ~SSI_SCR_TE;
	316	else
	317	scr &= ~SSI_SCR_RE;
	318	sier &= ~sier_bits;
	319
	320	if (--ssi->enabled == 0)
	321	scr &= ~SSI_SCR_SSIEN;
	322
	323	break;
	324	default:
	325	return -EINVAL;
	326	}
	327
	328	if (!(ssi->flags & IMX_SSI_USE_AC97))
	329	/* rx/tx are always enabled to access ac97 registers */
	330	writel(scr, ssi->base + SSI_SCR);
	331
	332	writel(sier, ssi->base + SSI_SIER);
	333
	334	return 0;
	335	}
	336
	337	static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
	338	.hw_params = imx_ssi_hw_params,
	339	.set_fmt = imx_ssi_set_dai_fmt,
	340	.set_clkdiv = imx_ssi_set_dai_clkdiv,
	341	.set_sysclk = imx_ssi_set_dai_sysclk,
342	.set_tdm_slot = imx_ssi_set_dai_tdm_slot,
343	.trigger = imx_ssi_trigger,
344	};
345
346	static struct snd_soc_dai imx_ssi_dai = {
347	.playback = {
348	.channels_min = 2,
349	.channels_max = 2,
350	.rates = SNDRV_PCM_RATE_8000_96000,
351	.formats = SNDRV_PCM_FMTBIT_S16_LE,
352	},
353	.capture = {
354	.channels_min = 2,
355	.channels_max = 2,
356	.rates = SNDRV_PCM_RATE_8000_96000,
357	.formats = SNDRV_PCM_FMTBIT_S16_LE,
358	},
359	.ops = &imx_ssi_pcm_dai_ops,
360	};
361
362	int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
363	struct vm_area_struct *vma)
364	{
365	struct snd_pcm_runtime *runtime = substream->runtime;
366	int ret;
367
368	ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
369	runtime->dma_addr, runtime->dma_bytes);
370
371	pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
372	runtime->dma_area,
373	runtime->dma_addr,
374	runtime->dma_bytes);
375	return ret;
376	}
377
378	static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
379	{
380	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
381	struct snd_dma_buffer *buf = &substream->dma_buffer;
382	size_t size = IMX_SSI_DMABUF_SIZE;
383
384	buf->dev.type = SNDRV_DMA_TYPE_DEV;
385	buf->dev.dev = pcm->card->dev;
386	buf->private_data = NULL;
387	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
388	&buf->addr, GFP_KERNEL);
389	if (!buf->area)
390	return -ENOMEM;
391	buf->bytes = size;
392
393	return 0;
394	}
395
396	static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
397
398	int imx_pcm_new(struct snd_card card, struct snd_soc_dai dai,
399	struct snd_pcm *pcm)
400	{
401
402	int ret = 0;
403
404	if (!card->dev->dma_mask)
405	card->dev->dma_mask = &imx_pcm_dmamask;
406	if (!card->dev->coherent_dma_mask)
407	card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
408	if (dai->playback.channels_min) {
409	ret = imx_pcm_preallocate_dma_buffer(pcm,
410	SNDRV_PCM_STREAM_PLAYBACK);
411	if (ret)
412	goto out;
413	}
414
415	if (dai->capture.channels_min) {
416	ret = imx_pcm_preallocate_dma_buffer(pcm,
417	SNDRV_PCM_STREAM_CAPTURE);
418	if (ret)
419	goto out;
420	}
421
422	out:
423	return ret;
424	}
425
426	void imx_pcm_free(struct snd_pcm *pcm)
427	{
428	struct snd_pcm_substream *substream;
429	struct snd_dma_buffer *buf;
430	int stream;
431
432	for (stream = 0; stream < 2; stream++) {
433	substream = pcm->streams[stream].substream;
434	if (!substream)
435	continue;
436
437	buf = &substream->dma_buffer;
438	if (!buf->area)
439	continue;
440
441	dma_free_writecombine(pcm->card->dev, buf->bytes,
442	buf->area, buf->addr);
443	buf->area = NULL;
444	}
445	}
446
447	struct snd_soc_platform imx_soc_platform = {
448	.name = "imx-audio",
449	};
450	EXPORT_SYMBOL_GPL(imx_soc_platform);
451
452	static struct snd_soc_dai imx_ac97_dai = {
453	.name = "AC97",
454	.ac97_control = 1,
455	.playback = {
456	.stream_name = "AC97 Playback",
457	.channels_min = 2,
458	.channels_max = 2,
459	.rates = SNDRV_PCM_RATE_48000,
460	.formats = SNDRV_PCM_FMTBIT_S16_LE,
461	},
462	.capture = {
463	.stream_name = "AC97 Capture",
464	.channels_min = 2,
465	.channels_max = 2,
466	.rates = SNDRV_PCM_RATE_48000,
467	.formats = SNDRV_PCM_FMTBIT_S16_LE,
468	},
469	.ops = &imx_ssi_pcm_dai_ops,
470	};
471
472	static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
473	{
474	void __iomem *base = imx_ssi->base;
475
476	writel(0x0, base + SSI_SCR);
477	writel(0x0, base + SSI_STCR);
478	writel(0x0, base + SSI_SRCR);
479
480	writel(SSI_SCR_SYN \| SSI_SCR_NET, base + SSI_SCR);
481
482	writel(SSI_SFCSR_RFWM0(8) \|
483	SSI_SFCSR_TFWM0(8) \|
484	SSI_SFCSR_RFWM1(8) \|
485	SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
486
487	writel(SSI_STCCR_WL(16) \| SSI_STCCR_DC(12), base + SSI_STCCR);
488	writel(SSI_STCCR_WL(16) \| SSI_STCCR_DC(12), base + SSI_SRCCR);
489
490	writel(SSI_SCR_SYN \| SSI_SCR_NET \| SSI_SCR_SSIEN, base + SSI_SCR);
491	writel(SSI_SOR_WAIT(3), base + SSI_SOR);
492
493	writel(SSI_SCR_SYN \| SSI_SCR_NET \| SSI_SCR_SSIEN \|
494	SSI_SCR_TE \| SSI_SCR_RE,
495	base + SSI_SCR);
496
497	writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
498	writel(0xff, base + SSI_SACCDIS);
499	writel(0x300, base + SSI_SACCEN);
500	}
501
502	static struct imx_ssi *ac97_ssi;
503
504	static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
505	unsigned short val)
506	{
507	struct imx_ssi *imx_ssi = ac97_ssi;
508	void __iomem *base = imx_ssi->base;
509	unsigned int lreg;
510	unsigned int lval;
511
512	if (reg > 0x7f)
513	return;
514
515	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
516
517	lreg = reg << 12;
518	writel(lreg, base + SSI_SACADD);
519
520	lval = val << 4;
521	writel(lval , base + SSI_SACDAT);
522
523	writel(SSI_SACNT_DEFAULT \| SSI_SACNT_WR, base + SSI_SACNT);
524	udelay(100);
525	}
526
527	static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
528	unsigned short reg)
529	{
530	struct imx_ssi *imx_ssi = ac97_ssi;
531	void __iomem *base = imx_ssi->base;
532
533	unsigned short val = -1;
534	unsigned int lreg;
535
536	lreg = (reg & 0x7f) << 12 ;
537	writel(lreg, base + SSI_SACADD);
538	writel(SSI_SACNT_DEFAULT \| SSI_SACNT_RD, base + SSI_SACNT);
539
540	udelay(100);
541
542	val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
543
544	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
545
546	return val;
547	}
548
549	static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
550	{
551	struct imx_ssi *imx_ssi = ac97_ssi;
552
553	if (imx_ssi->ac97_reset)
554	imx_ssi->ac97_reset(ac97);
555	}
556
557	static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
558	{
559	struct imx_ssi *imx_ssi = ac97_ssi;
560
561	if (imx_ssi->ac97_warm_reset)
562	imx_ssi->ac97_warm_reset(ac97);
563	}
564
565	struct snd_ac97_bus_ops soc_ac97_ops = {
566	.read = imx_ssi_ac97_read,
567	.write = imx_ssi_ac97_write,
568	.reset = imx_ssi_ac97_reset,
569	.warm_reset = imx_ssi_ac97_warm_reset
570	};
571	EXPORT_SYMBOL_GPL(soc_ac97_ops);
572
48dbc419	573	struct snd_soc_dai imx_ssi_pcm_dai[2];
8380222e SH	574	EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
	575
	576	static int imx_ssi_probe(struct platform_device *pdev)
	577	{
	578	struct resource *res;
	579	struct imx_ssi *ssi;
	580	struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
	581	struct snd_soc_platform *platform;
	582	int ret = 0;
	583	unsigned int val;
48dbc419 MB	584	struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
	585
	586	if (dai->id >= ARRAY_SIZE(imx_ssi_pcm_dai))
	587	return -EINVAL;
8380222e SH	588
	589	ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
	590	if (!ssi)
	591	return -ENOMEM;
	592
	593	if (pdata) {
	594	ssi->ac97_reset = pdata->ac97_reset;
	595	ssi->ac97_warm_reset = pdata->ac97_warm_reset;
	596	ssi->flags = pdata->flags;
	597	}
	598
8380222e SH	599	ssi->irq = platform_get_irq(pdev, 0);
	600
	601	ssi->clk = clk_get(&pdev->dev, NULL);
	602	if (IS_ERR(ssi->clk)) {
	603	ret = PTR_ERR(ssi->clk);
	604	dev_err(&pdev->dev, "Cannot get the clock: %d\n",
	605	ret);
	606	goto failed_clk;
	607	}
	608	clk_enable(ssi->clk);
	609
	610	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	611	if (!res) {
	612	ret = -ENODEV;
	613	goto failed_get_resource;
	614	}
	615
	616	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
	617	dev_err(&pdev->dev, "request_mem_region failed\n");
	618	ret = -EBUSY;
	619	goto failed_get_resource;
	620	}
	621
	622	ssi->base = ioremap(res->start, resource_size(res));
	623	if (!ssi->base) {
	624	dev_err(&pdev->dev, "ioremap failed\n");
	625	ret = -ENODEV;
	626	goto failed_ioremap;
	627	}
	628
	629	if (ssi->flags & IMX_SSI_USE_AC97) {
	630	if (ac97_ssi) {
	631	ret = -EBUSY;
	632	goto failed_ac97;
	633	}
	634	ac97_ssi = ssi;
	635	setup_channel_to_ac97(ssi);
48dbc419	636	memcpy(dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
8380222e	637	} else
48dbc419	638	memcpy(dai, &imx_ssi_dai, sizeof(imx_ssi_dai));
8380222e SH	639
	640	writel(0x0, ssi->base + SSI_SIER);
	641
	642	ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
	643	ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
	644
	645	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
	646	if (res)
	647	ssi->dma_params_tx.dma = res->start;
	648
	649	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
	650	if (res)
	651	ssi->dma_params_rx.dma = res->start;
	652
48dbc419 MB	653	dai->id = pdev->id;
	654	dai->dev = &pdev->dev;
	655	dai->name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
	656	dai->private_data = ssi;
8380222e SH	657
8380222e SH	658	if ((cpu_is_mx27() \|\| cpu_is_mx21()) &&
206b60e1 SH	659	!(ssi->flags & IMX_SSI_USE_AC97) &&
206b60e1 SH	660	(ssi->flags & IMX_SSI_DMA)) {
8380222e SH	661	ssi->flags \|= IMX_SSI_DMA;
	662	platform = imx_ssi_dma_mx2_init(pdev, ssi);
	663	} else
	664	platform = imx_ssi_fiq_init(pdev, ssi);
	665
	666	imx_soc_platform.pcm_ops = platform->pcm_ops;
	667	imx_soc_platform.pcm_new = platform->pcm_new;
	668	imx_soc_platform.pcm_free = platform->pcm_free;
	669
	670	val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) \|
	671	SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
	672	writel(val, ssi->base + SSI_SFCSR);
	673
48dbc419	674	ret = snd_soc_register_dai(dai);
8380222e SH	675	if (ret) {
	676	dev_err(&pdev->dev, "register DAI failed\n");
	677	goto failed_register;
	678	}
	679
	680	platform_set_drvdata(pdev, ssi);
	681
	682	return 0;
	683
	684	failed_register:
	685	failed_ac97:
	686	iounmap(ssi->base);
	687	failed_ioremap:
	688	release_mem_region(res->start, resource_size(res));
	689	failed_get_resource:
	690	clk_disable(ssi->clk);
	691	clk_put(ssi->clk);
	692	failed_clk:
	693	kfree(ssi);
	694
	695	return ret;
	696	}
	697
	698	static int __devexit imx_ssi_remove(struct platform_device *pdev)
	699	{
	700	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	701	struct imx_ssi *ssi = platform_get_drvdata(pdev);
48dbc419	702	struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
8380222e	703
48dbc419	704	snd_soc_unregister_dai(dai);
8380222e SH	705
	706	if (ssi->flags & IMX_SSI_USE_AC97)
	707	ac97_ssi = NULL;
	708
	709	if (!(ssi->flags & IMX_SSI_DMA))
	710	imx_ssi_fiq_exit(pdev, ssi);
	711
	712	iounmap(ssi->base);
	713	release_mem_region(res->start, resource_size(res));
	714	clk_disable(ssi->clk);
	715	clk_put(ssi->clk);
	716	kfree(ssi);
	717
	718	return 0;
	719	}
	720
	721	static struct platform_driver imx_ssi_driver = {
	722	.probe = imx_ssi_probe,
	723	.remove = __devexit_p(imx_ssi_remove),
	724
	725	.driver = {
	726	.name = DRV_NAME,
	727	.owner = THIS_MODULE,
	728	},
	729	};
	730
	731	static int __init imx_ssi_init(void)
	732	{
	733	int ret;
	734
	735	ret = snd_soc_register_platform(&imx_soc_platform);
	736	if (ret) {
	737	pr_err("failed to register soc platform: %d\n", ret);
	738	return ret;
	739	}
	740
	741	ret = platform_driver_register(&imx_ssi_driver);
	742	if (ret) {
	743	snd_soc_unregister_platform(&imx_soc_platform);
	744	return ret;
	745	}
	746
	747	return 0;
	748	}
	749
	750	static void __exit imx_ssi_exit(void)
	751	{
	752	platform_driver_unregister(&imx_ssi_driver);
	753	snd_soc_unregister_platform(&imx_soc_platform);
	754	}
	755
	756	module_init(imx_ssi_init);
	757	module_exit(imx_ssi_exit);
	758
	759	/* Module information */
	760	MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
	761	MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
	762	MODULE_LICENSE("GPL");
	763