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ASoC: davinci-mcasp.c: Return error code in failure
[net-next-2.6.git] / sound / soc / davinci / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/initval.h>
30#include <sound/soc.h>
31
32#include "davinci-pcm.h"
33#include "davinci-mcasp.h"
34
35/*
36 * McASP register definitions
37 */
38#define DAVINCI_MCASP_PID_REG 0x00
39#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
40
41#define DAVINCI_MCASP_PFUNC_REG 0x10
42#define DAVINCI_MCASP_PDIR_REG 0x14
43#define DAVINCI_MCASP_PDOUT_REG 0x18
44#define DAVINCI_MCASP_PDSET_REG 0x1c
45
46#define DAVINCI_MCASP_PDCLR_REG 0x20
47
48#define DAVINCI_MCASP_TLGC_REG 0x30
49#define DAVINCI_MCASP_TLMR_REG 0x34
50
51#define DAVINCI_MCASP_GBLCTL_REG 0x44
52#define DAVINCI_MCASP_AMUTE_REG 0x48
53#define DAVINCI_MCASP_LBCTL_REG 0x4c
54
55#define DAVINCI_MCASP_TXDITCTL_REG 0x50
56
57#define DAVINCI_MCASP_GBLCTLR_REG 0x60
58#define DAVINCI_MCASP_RXMASK_REG 0x64
59#define DAVINCI_MCASP_RXFMT_REG 0x68
60#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
61
62#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
63#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
64#define DAVINCI_MCASP_RXTDM_REG 0x78
65#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
66
67#define DAVINCI_MCASP_RXSTAT_REG 0x80
68#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
69#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
70#define DAVINCI_MCASP_REVTCTL_REG 0x8c
71
72#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
73#define DAVINCI_MCASP_TXMASK_REG 0xa4
74#define DAVINCI_MCASP_TXFMT_REG 0xa8
75#define DAVINCI_MCASP_TXFMCTL_REG 0xac
76
77#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
78#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
79#define DAVINCI_MCASP_TXTDM_REG 0xb8
80#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
81
82#define DAVINCI_MCASP_TXSTAT_REG 0xc0
83#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
84#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
85#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
86
87/* Left(even TDM Slot) Channel Status Register File */
88#define DAVINCI_MCASP_DITCSRA_REG 0x100
89/* Right(odd TDM slot) Channel Status Register File */
90#define DAVINCI_MCASP_DITCSRB_REG 0x118
91/* Left(even TDM slot) User Data Register File */
92#define DAVINCI_MCASP_DITUDRA_REG 0x130
93/* Right(odd TDM Slot) User Data Register File */
94#define DAVINCI_MCASP_DITUDRB_REG 0x148
95
96/* Serializer n Control Register */
97#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
98#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
99 (n << 2))
100
101/* Transmit Buffer for Serializer n */
102#define DAVINCI_MCASP_TXBUF_REG 0x200
103/* Receive Buffer for Serializer n */
104#define DAVINCI_MCASP_RXBUF_REG 0x280
105
6a99fb5f
C		 106/* McASP FIFO Registers */
107#define DAVINCI_MCASP_WFIFOCTL (0x1010)
108#define DAVINCI_MCASP_WFIFOSTS (0x1014)
109#define DAVINCI_MCASP_RFIFOCTL (0x1018)
110#define DAVINCI_MCASP_RFIFOSTS (0x101C)
b67f4487
C		 111
112/*
113 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
114 * Register Bits
115 */
116#define MCASP_FREE BIT(0)
117#define MCASP_SOFT BIT(1)
118
119/*
120 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
121 */
122#define AXR(n) (1<<n)
123#define PFUNC_AMUTE BIT(25)
124#define ACLKX BIT(26)
125#define AHCLKX BIT(27)
126#define AFSX BIT(28)
127#define ACLKR BIT(29)
128#define AHCLKR BIT(30)
129#define AFSR BIT(31)
130
131/*
132 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
133 */
134#define AXR(n) (1<<n)
135#define PDIR_AMUTE BIT(25)
136#define ACLKX BIT(26)
137#define AHCLKX BIT(27)
138#define AFSX BIT(28)
139#define ACLKR BIT(29)
140#define AHCLKR BIT(30)
141#define AFSR BIT(31)
142
143/*
144 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
145 */
146#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
147#define VA BIT(2)
148#define VB BIT(3)
149
150/*
151 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
152 */
153#define TXROT(val) (val)
154#define TXSEL BIT(3)
155#define TXSSZ(val) (val<<4)
156#define TXPBIT(val) (val<<8)
157#define TXPAD(val) (val<<13)
158#define TXORD BIT(15)
159#define FSXDLY(val) (val<<16)
160
161/*
162 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
163 */
164#define RXROT(val) (val)
165#define RXSEL BIT(3)
166#define RXSSZ(val) (val<<4)
167#define RXPBIT(val) (val<<8)
168#define RXPAD(val) (val<<13)
169#define RXORD BIT(15)
170#define FSRDLY(val) (val<<16)
171
172/*
173 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
174 */
175#define FSXPOL BIT(0)
176#define AFSXE BIT(1)
177#define FSXDUR BIT(4)
178#define FSXMOD(val) (val<<7)
179
180/*
181 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
182 */
183#define FSRPOL BIT(0)
184#define AFSRE BIT(1)
185#define FSRDUR BIT(4)
186#define FSRMOD(val) (val<<7)
187
188/*
189 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
190 */
191#define ACLKXDIV(val) (val)
192#define ACLKXE BIT(5)
193#define TX_ASYNC BIT(6)
194#define ACLKXPOL BIT(7)
195
196/*
197 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
198 */
199#define ACLKRDIV(val) (val)
200#define ACLKRE BIT(5)
201#define RX_ASYNC BIT(6)
202#define ACLKRPOL BIT(7)
203
204/*
205 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
206 * Register Bits
207 */
208#define AHCLKXDIV(val) (val)
209#define AHCLKXPOL BIT(14)
210#define AHCLKXE BIT(15)
211
212/*
213 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
214 * Register Bits
215 */
216#define AHCLKRDIV(val) (val)
217#define AHCLKRPOL BIT(14)
218#define AHCLKRE BIT(15)
219
220/*
221 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
222 */
223#define MODE(val) (val)
224#define DISMOD (val)(val<<2)
225#define TXSTATE BIT(4)
226#define RXSTATE BIT(5)
227
228/*
229 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
230 */
231#define LBEN BIT(0)
232#define LBORD BIT(1)
233#define LBGENMODE(val) (val<<2)
234
235/*
236 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
237 */
238#define TXTDMS(n) (1<<n)
239
240/*
241 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
242 */
243#define RXTDMS(n) (1<<n)
244
245/*
246 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
247 */
248#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
249#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
250#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
251#define RXSMRST BIT(3) /* Receiver State Machine Reset */
252#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
253#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
254#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
255#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
256#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
257#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
258
259/*
260 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
261 */
262#define MUTENA(val) (val)
263#define MUTEINPOL BIT(2)
264#define MUTEINENA BIT(3)
265#define MUTEIN BIT(4)
266#define MUTER BIT(5)
267#define MUTEX BIT(6)
268#define MUTEFSR BIT(7)
269#define MUTEFSX BIT(8)
270#define MUTEBADCLKR BIT(9)
271#define MUTEBADCLKX BIT(10)
272#define MUTERXDMAERR BIT(11)
273#define MUTETXDMAERR BIT(12)
274
275/*
276 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
277 */
278#define RXDATADMADIS BIT(0)
279
280/*
281 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
282 */
283#define TXDATADMADIS BIT(0)
284
6a99fb5f
C		 285/*
286 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
287 */
288#define FIFO_ENABLE BIT(16)
289#define NUMEVT_MASK (0xFF << 8)
290#define NUMDMA_MASK (0xFF)
291
b67f4487
C		 292#define DAVINCI_MCASP_NUM_SERIALIZER 16
293
294static inline void mcasp_set_bits(void __iomem *reg, u32 val)
295{
296 __raw_writel(__raw_readl(reg) | val, reg);
297}
298
299static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
300{
301 __raw_writel((__raw_readl(reg) & ~(val)), reg);
302}
303
304static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
305{
306 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
307}
308
309static inline void mcasp_set_reg(void __iomem *reg, u32 val)
310{
311 __raw_writel(val, reg);
312}
313
314static inline u32 mcasp_get_reg(void __iomem *reg)
315{
316 return (unsigned int)__raw_readl(reg);
317}
318
319static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
320{
321 int i = 0;
322
323 mcasp_set_bits(regs, val);
324
325 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
326 /* loop count is to avoid the lock-up */
327 for (i = 0; i < 1000; i++) {
328 if ((mcasp_get_reg(regs) & val) == val)
329 break;
330 }
331
332 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
333 printk(KERN_ERR "GBLCTL write error\n");
334}
335
b67f4487
C		 336static void mcasp_start_rx(struct davinci_audio_dev *dev)
337{
338 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
339 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
340 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
341 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
342
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
344 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
345 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
346
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
348 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
349}
350
351static void mcasp_start_tx(struct davinci_audio_dev *dev)
352{
6a99fb5f
C		 353 u8 offset = 0, i;
354 u32 cnt;
355
b67f4487
C		 356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
358 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
359 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
360
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
362 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
363 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
6a99fb5f
C		 364 for (i = 0; i < dev->num_serializer; i++) {
365 if (dev->serial_dir[i] == TX_MODE) {
366 offset = i;
367 break;
368 }
369 }
370
371 /* wait for TX ready */
372 cnt = 0;
373 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
374 TXSTATE) && (cnt < 100000))
375 cnt++;
376
b67f4487
C		 377 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
378}
379
380static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
381{
539d3d8c
C		 382 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
383 if (dev->txnumevt) /* enable FIFO */
384 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
385 FIFO_ENABLE);
b67f4487 386 mcasp_start_tx(dev);
539d3d8c
C		 387 } else {
388 if (dev->rxnumevt) /* enable FIFO */
389 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
390 FIFO_ENABLE);
b67f4487 391 mcasp_start_rx(dev);
539d3d8c 392 }
b67f4487
C		 393}
394
395static void mcasp_stop_rx(struct davinci_audio_dev *dev)
396{
397 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
398 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
399}
400
401static void mcasp_stop_tx(struct davinci_audio_dev *dev)
402{
403 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
404 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
405}
406
407static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
408{
539d3d8c
C		 409 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
410 if (dev->txnumevt) /* disable FIFO */
411 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
412 FIFO_ENABLE);
b67f4487 413 mcasp_stop_tx(dev);
539d3d8c
C		 414 } else {
415 if (dev->rxnumevt) /* disable FIFO */
416 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
417 FIFO_ENABLE);
b67f4487 418 mcasp_stop_rx(dev);
539d3d8c 419 }
b67f4487
C		 420}
421
422static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
423 unsigned int fmt)
424{
f0fba2ad 425 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 426 void __iomem *base = dev->base;
427
428 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
429 case SND_SOC_DAIFMT_CBS_CFS:
430 /* codec is clock and frame slave */
431 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
432 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
433
434 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
435 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
436
437 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
438 break;
517ee6cf
C		 439 case SND_SOC_DAIFMT_CBM_CFS:
440 /* codec is clock master and frame slave */
441 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
442 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
443
444 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
445 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
446
447 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));
448 break;
b67f4487
C		 449 case SND_SOC_DAIFMT_CBM_CFM:
450 /* codec is clock and frame master */
451 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
452 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
453
454 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
455 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
456
457 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
458 break;
459
460 default:
461 return -EINVAL;
462 }
463
464 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
465 case SND_SOC_DAIFMT_IB_NF:
466 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
467 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
468
469 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
470 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
471 break;
472
473 case SND_SOC_DAIFMT_NB_IF:
474 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
475 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
476
477 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
478 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
479 break;
480
481 case SND_SOC_DAIFMT_IB_IF:
482 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
483 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
484
485 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
486 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
487 break;
488
489 case SND_SOC_DAIFMT_NB_NF:
490 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
491 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
492
493 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
494 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
495 break;
496
497 default:
498 return -EINVAL;
499 }
500
501 return 0;
502}
503
504static int davinci_config_channel_size(struct davinci_audio_dev *dev,
505 int channel_size)
506{
507 u32 fmt = 0;
0c31cf3e 508 u32 mask, rotate;
b67f4487
C		 509
510 switch (channel_size) {
511 case DAVINCI_AUDIO_WORD_8:
512 fmt = 0x03;
0c31cf3e
C		 513 rotate = 6;
514 mask = 0x000000ff;
b67f4487
C		 515 break;
516
517 case DAVINCI_AUDIO_WORD_12:
518 fmt = 0x05;
0c31cf3e
C		 519 rotate = 5;
520 mask = 0x00000fff;
b67f4487
C		 521 break;
522
523 case DAVINCI_AUDIO_WORD_16:
524 fmt = 0x07;
0c31cf3e
C		 525 rotate = 4;
526 mask = 0x0000ffff;
b67f4487
C		 527 break;
528
529 case DAVINCI_AUDIO_WORD_20:
530 fmt = 0x09;
0c31cf3e
C		 531 rotate = 3;
532 mask = 0x000fffff;
b67f4487
C		 533 break;
534
535 case DAVINCI_AUDIO_WORD_24:
536 fmt = 0x0B;
0c31cf3e
C		 537 rotate = 2;
538 mask = 0x00ffffff;
b67f4487
C		 539 break;
540
541 case DAVINCI_AUDIO_WORD_28:
542 fmt = 0x0D;
0c31cf3e
C		 543 rotate = 1;
544 mask = 0x0fffffff;
b67f4487
C		 545 break;
546
547 case DAVINCI_AUDIO_WORD_32:
548 fmt = 0x0F;
0c31cf3e
C		 549 rotate = 0;
550 mask = 0xffffffff;
b67f4487
C		 551 break;
552
553 default:
554 return -EINVAL;
555 }
556
557 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
558 RXSSZ(fmt), RXSSZ(0x0F));
559 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
560 TXSSZ(fmt), TXSSZ(0x0F));
0c31cf3e
C		 561 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
562 TXROT(7));
563 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
564 RXROT(7));
565 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
566 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
567
b67f4487
C		 568 return 0;
569}
570
571static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
572{
573 int i;
6a99fb5f
C		 574 u8 tx_ser = 0;
575 u8 rx_ser = 0;
b67f4487
C		 576
577 /* Default configuration */
578 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
579
580 /* All PINS as McASP */
581 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
582
583 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
584 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
585 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
586 TXDATADMADIS);
587 } else {
588 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
589 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
590 RXDATADMADIS);
591 }
592
593 for (i = 0; i < dev->num_serializer; i++) {
594 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
595 dev->serial_dir[i]);
6a99fb5f 596 if (dev->serial_dir[i] == TX_MODE) {
b67f4487
C		 597 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
598 AXR(i));
6a99fb5f
C		 599 tx_ser++;
600 } else if (dev->serial_dir[i] == RX_MODE) {
b67f4487
C		 601 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
602 AXR(i));
6a99fb5f
C		 603 rx_ser++;
604 }
605 }
606
607 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
608 if (dev->txnumevt * tx_ser > 64)
609 dev->txnumevt = 1;
610
611 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
612 NUMDMA_MASK);
613 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
614 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
6a99fb5f
C		 615 }
616
617 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
618 if (dev->rxnumevt * rx_ser > 64)
619 dev->rxnumevt = 1;
620
621 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
622 NUMDMA_MASK);
623 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
624 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
b67f4487
C		 625 }
626}
627
628static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
629{
630 int i, active_slots;
631 u32 mask = 0;
632
633 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
634 for (i = 0; i < active_slots; i++)
635 mask |= (1 << i);
636
6a99fb5f
C		 637 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
638
b67f4487
C		 639 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
640 /* bit stream is MSB first with no delay */
641 /* DSP_B mode */
642 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
643 AHCLKXE);
644 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
645 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
646
647 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
648 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
649 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
650 else
651 printk(KERN_ERR "playback tdm slot %d not supported\n",
652 dev->tdm_slots);
653
b67f4487
C		 654 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
655 } else {
656 /* bit stream is MSB first with no delay */
657 /* DSP_B mode */
658 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
659 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
660 AHCLKRE);
661 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
662
663 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
664 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
665 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
666 else
667 printk(KERN_ERR "capture tdm slot %d not supported\n",
668 dev->tdm_slots);
669
b67f4487
C		 670 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
671 }
672}
673
674/* S/PDIF */
675static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
676{
677 /* Set the PDIR for Serialiser as output */
678 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
679
680 /* TXMASK for 24 bits */
681 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
682
683 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
684 and LSB first */
685 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
686 TXROT(6) | TXSSZ(15));
687
688 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
689 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
690 AFSXE | FSXMOD(0x180));
691
692 /* Set the TX tdm : for all the slots */
693 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
694
695 /* Set the TX clock controls : div = 1 and internal */
696 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
697 ACLKXE | TX_ASYNC);
698
699 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
700
701 /* Only 44100 and 48000 are valid, both have the same setting */
702 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
703
704 /* Enable the DIT */
705 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
706}
707
708static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
709 struct snd_pcm_hw_params *params,
710 struct snd_soc_dai *cpu_dai)
711{
f0fba2ad 712 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 713 struct davinci_pcm_dma_params *dma_params =
92e2a6f6 714 &dev->dma_params[substream->stream];
b67f4487 715 int word_length;
4fa9c1a5 716 u8 fifo_level;
b67f4487 717
f0fba2ad
LG		 718 cpu_dai->capture_dma_data = dev->dma_params;
719 cpu_dai->playback_dma_data = dev->dma_params;
720
b67f4487 721 davinci_hw_common_param(dev, substream->stream);
6a99fb5f 722 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4fa9c1a5 723 fifo_level = dev->txnumevt;
6a99fb5f 724 else
4fa9c1a5 725 fifo_level = dev->rxnumevt;
b67f4487
C		 726
727 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
728 davinci_hw_dit_param(dev);
729 else
730 davinci_hw_param(dev, substream->stream);
731
732 switch (params_format(params)) {
733 case SNDRV_PCM_FORMAT_S8:
734 dma_params->data_type = 1;
735 word_length = DAVINCI_AUDIO_WORD_8;
736 break;
737
738 case SNDRV_PCM_FORMAT_S16_LE:
739 dma_params->data_type = 2;
740 word_length = DAVINCI_AUDIO_WORD_16;
741 break;
742
743 case SNDRV_PCM_FORMAT_S32_LE:
744 dma_params->data_type = 4;
745 word_length = DAVINCI_AUDIO_WORD_32;
746 break;
747
748 default:
749 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
750 return -EINVAL;
751 }
6a99fb5f 752
4fa9c1a5
C		 753 if (dev->version == MCASP_VERSION_2 && !fifo_level)
754 dma_params->acnt = 4;
755 else
6a99fb5f
C		 756 dma_params->acnt = dma_params->data_type;
757
4fa9c1a5 758 dma_params->fifo_level = fifo_level;
b67f4487
C		 759 davinci_config_channel_size(dev, word_length);
760
761 return 0;
762}
763
764static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
765 int cmd, struct snd_soc_dai *cpu_dai)
766{
f0fba2ad 767 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 768 int ret = 0;
769
770 switch (cmd) {
b67f4487 771 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 772 case SNDRV_PCM_TRIGGER_START:
773 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
a47979b5
C		 774 if (!dev->clk_active) {
775 clk_enable(dev->clk);
776 dev->clk_active = 1;
777 }
b67f4487
C		 778 davinci_mcasp_start(dev, substream->stream);
779 break;
780
b67f4487 781 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5
C		 782 davinci_mcasp_stop(dev, substream->stream);
783 if (dev->clk_active) {
784 clk_disable(dev->clk);
785 dev->clk_active = 0;
786 }
787
788 break;
789
790 case SNDRV_PCM_TRIGGER_STOP:
b67f4487
C		 791 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
792 davinci_mcasp_stop(dev, substream->stream);
793 break;
794
795 default:
796 ret = -EINVAL;
797 }
798
799 return ret;
800}
801
802static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
b67f4487
C		 803 .trigger = davinci_mcasp_trigger,
804 .hw_params = davinci_mcasp_hw_params,
805 .set_fmt = davinci_mcasp_set_dai_fmt,
806
807};
808
f0fba2ad 809static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 810 {
f0fba2ad 811 .name = "davinci-mcasp.0",
b67f4487
C		 812 .playback = {
813 .channels_min = 2,
814 .channels_max = 2,
815 .rates = DAVINCI_MCASP_RATES,
816 .formats = SNDRV_PCM_FMTBIT_S8 |
817 SNDRV_PCM_FMTBIT_S16_LE |
818 SNDRV_PCM_FMTBIT_S32_LE,
819 },
820 .capture = {
821 .channels_min = 2,
822 .channels_max = 2,
823 .rates = DAVINCI_MCASP_RATES,
824 .formats = SNDRV_PCM_FMTBIT_S8 |
825 SNDRV_PCM_FMTBIT_S16_LE |
826 SNDRV_PCM_FMTBIT_S32_LE,
827 },
828 .ops = &davinci_mcasp_dai_ops,
829
830 },
831 {
f0fba2ad 832 "davinci-mcasp.1",
b67f4487
C		 833 .playback = {
834 .channels_min = 1,
835 .channels_max = 384,
836 .rates = DAVINCI_MCASP_RATES,
837 .formats = SNDRV_PCM_FMTBIT_S16_LE,
838 },
839 .ops = &davinci_mcasp_dai_ops,
840 },
841
842};
b67f4487
C		 843
844static int davinci_mcasp_probe(struct platform_device *pdev)
845{
846 struct davinci_pcm_dma_params *dma_data;
847 struct resource *mem, *ioarea, *res;
848 struct snd_platform_data *pdata;
849 struct davinci_audio_dev *dev;
b67f4487
C		 850 int ret = 0;
851
852 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
853 if (!dev)
854 return -ENOMEM;
855
b67f4487
C		 856 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
857 if (!mem) {
858 dev_err(&pdev->dev, "no mem resource?\n");
859 ret = -ENODEV;
860 goto err_release_data;
861 }
862
863 ioarea = request_mem_region(mem->start,
864 (mem->end - mem->start) + 1, pdev->name);
865 if (!ioarea) {
866 dev_err(&pdev->dev, "Audio region already claimed\n");
867 ret = -EBUSY;
868 goto err_release_data;
869 }
870
871 pdata = pdev->dev.platform_data;
3e46a447 872 dev->clk = clk_get(&pdev->dev, NULL);
b67f4487
C		 873 if (IS_ERR(dev->clk)) {
874 ret = -ENODEV;
875 goto err_release_region;
876 }
877
878 clk_enable(dev->clk);
a47979b5 879 dev->clk_active = 1;
b67f4487
C		 880
881 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
882 dev->op_mode = pdata->op_mode;
883 dev->tdm_slots = pdata->tdm_slots;
884 dev->num_serializer = pdata->num_serializer;
885 dev->serial_dir = pdata->serial_dir;
886 dev->codec_fmt = pdata->codec_fmt;
6a99fb5f
C		 887 dev->version = pdata->version;
888 dev->txnumevt = pdata->txnumevt;
889 dev->rxnumevt = pdata->rxnumevt;
b67f4487 890
92e2a6f6 891 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
48519f0a
SN		 892 dma_data->asp_chan_q = pdata->asp_chan_q;
893 dma_data->ram_chan_q = pdata->ram_chan_q;
92e2a6f6 894 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
b67f4487 895 io_v2p(dev->base));
b67f4487
C		 896
897 /* first TX, then RX */
898 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
899 if (!res) {
900 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 901 ret = -ENODEV;
b67f4487
C		 902 goto err_release_region;
903 }
904
92e2a6f6
TK		 905 dma_data->channel = res->start;
906
907 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
48519f0a
SN		 908 dma_data->asp_chan_q = pdata->asp_chan_q;
909 dma_data->ram_chan_q = pdata->ram_chan_q;
92e2a6f6 910 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
b67f4487 911 io_v2p(dev->base));
b67f4487
C		 912
913 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
914 if (!res) {
915 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 916 ret = -ENODEV;
b67f4487
C		 917 goto err_release_region;
918 }
919
92e2a6f6 920 dma_data->channel = res->start;
f0fba2ad
LG		 921 dev_set_drvdata(&pdev->dev, dev);
922 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
b67f4487
C		 923
924 if (ret != 0)
925 goto err_release_region;
926 return 0;
927
928err_release_region:
929 release_mem_region(mem->start, (mem->end - mem->start) + 1);
930err_release_data:
b67f4487
C		 931 kfree(dev);
932
933 return ret;
934}
935
936static int davinci_mcasp_remove(struct platform_device *pdev)
937{
f0fba2ad 938 struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
b67f4487
C		 939 struct resource *mem;
940
f0fba2ad 941 snd_soc_unregister_dai(&pdev->dev);
b67f4487
C		 942 clk_disable(dev->clk);
943 clk_put(dev->clk);
944 dev->clk = NULL;
945
946 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
947 release_mem_region(mem->start, (mem->end - mem->start) + 1);
948
b67f4487
C		 949 kfree(dev);
950
951 return 0;
952}
953
954static struct platform_driver davinci_mcasp_driver = {
955 .probe = davinci_mcasp_probe,
956 .remove = davinci_mcasp_remove,
957 .driver = {
958 .name = "davinci-mcasp",
959 .owner = THIS_MODULE,
960 },
961};
962
963static int __init davinci_mcasp_init(void)
964{
965 return platform_driver_register(&davinci_mcasp_driver);
966}
967module_init(davinci_mcasp_init);
968
969static void __exit davinci_mcasp_exit(void)
970{
971 platform_driver_unregister(&davinci_mcasp_driver);
972}
973module_exit(davinci_mcasp_exit);
974
975MODULE_AUTHOR("Steve Chen");
976MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
977MODULE_LICENSE("GPL");
978
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