]> bbs.cooldavid.org Git - net-next-2.6.git/blame - sound/soc/codecs/wm8903.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Add WM8903 interrupt support
[net-next-2.6.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/tlv.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
8abd16a6 32#include <sound/wm8903.h>
f1c0a02f
MB		 33
34#include "wm8903.h"
35
f1c0a02f
MB		 36/* Register defaults at reset */
37static u16 wm8903_reg_defaults[] = {
38 0x8903, /* R0 - SW Reset and ID */
39 0x0000, /* R1 - Revision Number */
40 0x0000, /* R2 */
41 0x0000, /* R3 */
42 0x0018, /* R4 - Bias Control 0 */
43 0x0000, /* R5 - VMID Control 0 */
44 0x0000, /* R6 - Mic Bias Control 0 */
45 0x0000, /* R7 */
46 0x0001, /* R8 - Analogue DAC 0 */
47 0x0000, /* R9 */
48 0x0001, /* R10 - Analogue ADC 0 */
49 0x0000, /* R11 */
50 0x0000, /* R12 - Power Management 0 */
51 0x0000, /* R13 - Power Management 1 */
52 0x0000, /* R14 - Power Management 2 */
53 0x0000, /* R15 - Power Management 3 */
54 0x0000, /* R16 - Power Management 4 */
55 0x0000, /* R17 - Power Management 5 */
56 0x0000, /* R18 - Power Management 6 */
57 0x0000, /* R19 */
58 0x0400, /* R20 - Clock Rates 0 */
59 0x0D07, /* R21 - Clock Rates 1 */
60 0x0000, /* R22 - Clock Rates 2 */
61 0x0000, /* R23 */
62 0x0050, /* R24 - Audio Interface 0 */
63 0x0242, /* R25 - Audio Interface 1 */
64 0x0008, /* R26 - Audio Interface 2 */
65 0x0022, /* R27 - Audio Interface 3 */
66 0x0000, /* R28 */
67 0x0000, /* R29 */
68 0x00C0, /* R30 - DAC Digital Volume Left */
69 0x00C0, /* R31 - DAC Digital Volume Right */
70 0x0000, /* R32 - DAC Digital 0 */
71 0x0000, /* R33 - DAC Digital 1 */
72 0x0000, /* R34 */
73 0x0000, /* R35 */
74 0x00C0, /* R36 - ADC Digital Volume Left */
75 0x00C0, /* R37 - ADC Digital Volume Right */
76 0x0000, /* R38 - ADC Digital 0 */
77 0x0073, /* R39 - Digital Microphone 0 */
78 0x09BF, /* R40 - DRC 0 */
79 0x3241, /* R41 - DRC 1 */
80 0x0020, /* R42 - DRC 2 */
81 0x0000, /* R43 - DRC 3 */
82 0x0085, /* R44 - Analogue Left Input 0 */
83 0x0085, /* R45 - Analogue Right Input 0 */
84 0x0044, /* R46 - Analogue Left Input 1 */
85 0x0044, /* R47 - Analogue Right Input 1 */
86 0x0000, /* R48 */
87 0x0000, /* R49 */
88 0x0008, /* R50 - Analogue Left Mix 0 */
89 0x0004, /* R51 - Analogue Right Mix 0 */
90 0x0000, /* R52 - Analogue Spk Mix Left 0 */
91 0x0000, /* R53 - Analogue Spk Mix Left 1 */
92 0x0000, /* R54 - Analogue Spk Mix Right 0 */
93 0x0000, /* R55 - Analogue Spk Mix Right 1 */
94 0x0000, /* R56 */
95 0x002D, /* R57 - Analogue OUT1 Left */
96 0x002D, /* R58 - Analogue OUT1 Right */
97 0x0039, /* R59 - Analogue OUT2 Left */
98 0x0039, /* R60 - Analogue OUT2 Right */
99 0x0100, /* R61 */
100 0x0139, /* R62 - Analogue OUT3 Left */
101 0x0139, /* R63 - Analogue OUT3 Right */
102 0x0000, /* R64 */
103 0x0000, /* R65 - Analogue SPK Output Control 0 */
104 0x0000, /* R66 */
105 0x0010, /* R67 - DC Servo 0 */
106 0x0100, /* R68 */
107 0x00A4, /* R69 - DC Servo 2 */
108 0x0807, /* R70 */
109 0x0000, /* R71 */
110 0x0000, /* R72 */
111 0x0000, /* R73 */
112 0x0000, /* R74 */
113 0x0000, /* R75 */
114 0x0000, /* R76 */
115 0x0000, /* R77 */
116 0x0000, /* R78 */
117 0x000E, /* R79 */
118 0x0000, /* R80 */
119 0x0000, /* R81 */
120 0x0000, /* R82 */
121 0x0000, /* R83 */
122 0x0000, /* R84 */
123 0x0000, /* R85 */
124 0x0000, /* R86 */
125 0x0006, /* R87 */
126 0x0000, /* R88 */
127 0x0000, /* R89 */
128 0x0000, /* R90 - Analogue HP 0 */
129 0x0060, /* R91 */
130 0x0000, /* R92 */
131 0x0000, /* R93 */
132 0x0000, /* R94 - Analogue Lineout 0 */
133 0x0060, /* R95 */
134 0x0000, /* R96 */
135 0x0000, /* R97 */
136 0x0000, /* R98 - Charge Pump 0 */
137 0x1F25, /* R99 */
138 0x2B19, /* R100 */
139 0x01C0, /* R101 */
140 0x01EF, /* R102 */
141 0x2B00, /* R103 */
142 0x0000, /* R104 - Class W 0 */
143 0x01C0, /* R105 */
144 0x1C10, /* R106 */
145 0x0000, /* R107 */
146 0x0000, /* R108 - Write Sequencer 0 */
147 0x0000, /* R109 - Write Sequencer 1 */
148 0x0000, /* R110 - Write Sequencer 2 */
149 0x0000, /* R111 - Write Sequencer 3 */
150 0x0000, /* R112 - Write Sequencer 4 */
151 0x0000, /* R113 */
152 0x0000, /* R114 - Control Interface */
153 0x0000, /* R115 */
154 0x00A8, /* R116 - GPIO Control 1 */
155 0x00A8, /* R117 - GPIO Control 2 */
156 0x00A8, /* R118 - GPIO Control 3 */
157 0x0220, /* R119 - GPIO Control 4 */
158 0x01A0, /* R120 - GPIO Control 5 */
159 0x0000, /* R121 - Interrupt Status 1 */
160 0xFFFF, /* R122 - Interrupt Status 1 Mask */
161 0x0000, /* R123 - Interrupt Polarity 1 */
162 0x0000, /* R124 */
163 0x0003, /* R125 */
164 0x0000, /* R126 - Interrupt Control */
165 0x0000, /* R127 */
166 0x0005, /* R128 */
167 0x0000, /* R129 - Control Interface Test 1 */
168 0x0000, /* R130 */
169 0x0000, /* R131 */
170 0x0000, /* R132 */
171 0x0000, /* R133 */
172 0x0000, /* R134 */
173 0x03FF, /* R135 */
174 0x0007, /* R136 */
175 0x0040, /* R137 */
176 0x0000, /* R138 */
177 0x0000, /* R139 */
178 0x0000, /* R140 */
179 0x0000, /* R141 */
180 0x0000, /* R142 */
181 0x0000, /* R143 */
182 0x0000, /* R144 */
183 0x0000, /* R145 */
184 0x0000, /* R146 */
185 0x0000, /* R147 */
186 0x4000, /* R148 */
187 0x6810, /* R149 - Charge Pump Test 1 */
188 0x0004, /* R150 */
189 0x0000, /* R151 */
190 0x0000, /* R152 */
191 0x0000, /* R153 */
192 0x0000, /* R154 */
193 0x0000, /* R155 */
194 0x0000, /* R156 */
195 0x0000, /* R157 */
196 0x0000, /* R158 */
197 0x0000, /* R159 */
198 0x0000, /* R160 */
199 0x0000, /* R161 */
200 0x0000, /* R162 */
201 0x0000, /* R163 */
202 0x0028, /* R164 - Clock Rate Test 4 */
203 0x0004, /* R165 */
204 0x0000, /* R166 */
205 0x0060, /* R167 */
206 0x0000, /* R168 */
207 0x0000, /* R169 */
208 0x0000, /* R170 */
209 0x0000, /* R171 */
210 0x0000, /* R172 - Analogue Output Bias 0 */
211};
212
d58d5d55
MB		 213struct wm8903_priv {
214 struct snd_soc_codec codec;
215 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
216
217 int sysclk;
218
219 /* Reference counts */
d58d5d55
MB		 220 int class_w_users;
221 int playback_active;
222 int capture_active;
223
8abd16a6
MB		 224 struct completion wseq;
225
d58d5d55
MB		 226 struct snd_pcm_substream *master_substream;
227 struct snd_pcm_substream *slave_substream;
228};
229
8d50e447 230static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 231{
232 switch (reg) {
233 case WM8903_SW_RESET_AND_ID:
234 case WM8903_REVISION_NUMBER:
235 case WM8903_INTERRUPT_STATUS_1:
236 case WM8903_WRITE_SEQUENCER_4:
8d50e447 237 return 1;
f1c0a02f
MB		 238
239 default:
f1c0a02f 240 return 0;
8d50e447 241 }
f1c0a02f
MB		 242}
243
244static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
245{
246 u16 reg[5];
247 struct i2c_client *i2c = codec->control_data;
8abd16a6 248 struct wm8903_priv *wm8903 = codec->private_data;
f1c0a02f
MB		 249
250 BUG_ON(start > 48);
251
37f88e84 252 /* Enable the sequencer if it's not already on */
8d50e447 253 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 254 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
255 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f
MB		 256
257 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
258
8d50e447 259 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 260 start | WM8903_WSEQ_START);
261
262 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 263 * that will break us out of the poll early.
f1c0a02f
MB		 264 */
265 do {
8abd16a6
MB		 266 wait_for_completion_timeout(&wm8903->wseq,
267 msecs_to_jiffies(10));
f1c0a02f 268
8d50e447 269 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 270 } while (reg[4] & WM8903_WSEQ_BUSY);
271
272 dev_dbg(&i2c->dev, "Sequence complete\n");
273
37f88e84
MB		 274 /* Disable the sequencer again if we enabled it */
275 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 276
277 return 0;
278}
279
280static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
281{
282 int i;
283
284 /* There really ought to be something better we can do here :/ */
285 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 286 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 287}
288
289static void wm8903_reset(struct snd_soc_codec *codec)
290{
8d50e447 291 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 292 memcpy(codec->reg_cache, wm8903_reg_defaults,
293 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 294}
295
296#define WM8903_OUTPUT_SHORT 0x8
297#define WM8903_OUTPUT_OUT 0x4
298#define WM8903_OUTPUT_INT 0x2
299#define WM8903_OUTPUT_IN 0x1
300
42768a12
MB		 301static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
302 struct snd_kcontrol *kcontrol, int event)
303{
304 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
305 mdelay(4);
306
307 return 0;
308}
309
f1c0a02f
MB		 310/*
311 * Event for headphone and line out amplifier power changes. Special
312 * power up/down sequences are required in order to maximise pop/click
313 * performance.
314 */
315static int wm8903_output_event(struct snd_soc_dapm_widget *w,
316 struct snd_kcontrol *kcontrol, int event)
317{
318 struct snd_soc_codec *codec = w->codec;
f1c0a02f 319 u16 val;
0bc286e2 320 u16 reg;
d7d5c547
MB		 321 u16 dcs_reg;
322 u16 dcs_bit;
0bc286e2 323 int shift;
f1c0a02f
MB		 324
325 switch (w->reg) {
326 case WM8903_POWER_MANAGEMENT_2:
327 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 328 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 329 break;
330 case WM8903_POWER_MANAGEMENT_3:
331 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 332 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 333 break;
334 default:
335 BUG();
1e297a19 336 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 337 }
338
339 switch (w->shift) {
340 case 0:
341 shift = 0;
342 break;
343 case 1:
344 shift = 4;
345 break;
346 default:
347 BUG();
1e297a19 348 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 349 }
350
351 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 352 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 353
354 /* Short the output */
355 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 356 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 357 }
358
359 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 360 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 361
362 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 363 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 364
365 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 366 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 367
368 /* Turn on the output ENA_OUTP */
369 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 370 snd_soc_write(codec, reg, val);
f1c0a02f 371
d7d5c547 372 /* Enable the DC servo */
8d50e447 373 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 374 dcs_reg |= dcs_bit;
8d50e447 375 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 376
f1c0a02f
MB		 377 /* Remove the short */
378 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 379 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 380 }
381
382 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 383 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 384
385 /* Short the output */
386 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 387 snd_soc_write(codec, reg, val);
f1c0a02f 388
d7d5c547 389 /* Disable the DC servo */
8d50e447 390 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 391 dcs_reg &= ~dcs_bit;
8d50e447 392 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 393
f1c0a02f
MB		 394 /* Then disable the intermediate and output stages */
395 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
396 WM8903_OUTPUT_IN) << shift);
8d50e447 397 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 398 }
399
f1c0a02f
MB		 400 return 0;
401}
402
403/*
404 * When used with DAC outputs only the WM8903 charge pump supports
405 * operation in class W mode, providing very low power consumption
406 * when used with digital sources. Enable and disable this mode
407 * automatically depending on the mixer configuration.
408 *
409 * All the relevant controls are simple switches.
410 */
411static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
412 struct snd_ctl_elem_value *ucontrol)
413{
414 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
415 struct snd_soc_codec *codec = widget->codec;
416 struct wm8903_priv *wm8903 = codec->private_data;
417 struct i2c_client *i2c = codec->control_data;
418 u16 reg;
419 int ret;
420
8d50e447 421 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 422
423 /* Turn it off if we're about to enable bypass */
424 if (ucontrol->value.integer.value[0]) {
425 if (wm8903->class_w_users == 0) {
426 dev_dbg(&i2c->dev, "Disabling Class W\n");
8d50e447 427 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 428 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
429 }
430 wm8903->class_w_users++;
431 }
432
433 /* Implement the change */
434 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
435
436 /* If we've just disabled the last bypass path turn Class W on */
437 if (!ucontrol->value.integer.value[0]) {
438 if (wm8903->class_w_users == 1) {
439 dev_dbg(&i2c->dev, "Enabling Class W\n");
8d50e447 440 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 441 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
442 }
443 wm8903->class_w_users--;
444 }
445
446 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
447 wm8903->class_w_users);
448
449 return ret;
450}
451
452#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
453{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
454 .info = snd_soc_info_volsw, \
455 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
456 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
457
458
459/* ALSA can only do steps of .01dB */
460static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
461
291ce18c 462static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 463static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
464
465static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
466static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
467static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
468static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
469static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
470
471static const char *drc_slope_text[] = {
472 "1", "1/2", "1/4", "1/8", "1/16", "0"
473};
474
475static const struct soc_enum drc_slope_r0 =
476 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
477
478static const struct soc_enum drc_slope_r1 =
479 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
480
481static const char *drc_attack_text[] = {
482 "instantaneous",
483 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
484 "46.4ms", "92.8ms", "185.6ms"
485};
486
487static const struct soc_enum drc_attack =
488 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
489
490static const char *drc_decay_text[] = {
491 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
492 "23.87s", "47.56s"
493};
494
495static const struct soc_enum drc_decay =
496 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
497
498static const char *drc_ff_delay_text[] = {
499 "5 samples", "9 samples"
500};
501
502static const struct soc_enum drc_ff_delay =
503 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
504
505static const char *drc_qr_decay_text[] = {
506 "0.725ms", "1.45ms", "5.8ms"
507};
508
509static const struct soc_enum drc_qr_decay =
510 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
511
512static const char *drc_smoothing_text[] = {
513 "Low", "Medium", "High"
514};
515
516static const struct soc_enum drc_smoothing =
517 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
518
519static const char *soft_mute_text[] = {
520 "Fast (fs/2)", "Slow (fs/32)"
521};
522
523static const struct soc_enum soft_mute =
524 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
525
526static const char *mute_mode_text[] = {
527 "Hard", "Soft"
528};
529
530static const struct soc_enum mute_mode =
531 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
532
533static const char *dac_deemphasis_text[] = {
534 "Disabled", "32kHz", "44.1kHz", "48kHz"
535};
536
537static const struct soc_enum dac_deemphasis =
538 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
539
540static const char *companding_text[] = {
541 "ulaw", "alaw"
542};
543
544static const struct soc_enum dac_companding =
545 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
546
547static const struct soc_enum adc_companding =
548 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
549
550static const char *input_mode_text[] = {
551 "Single-Ended", "Differential Line", "Differential Mic"
552};
553
554static const struct soc_enum linput_mode_enum =
555 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
556
557static const struct soc_enum rinput_mode_enum =
558 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
559
560static const char *linput_mux_text[] = {
561 "IN1L", "IN2L", "IN3L"
562};
563
564static const struct soc_enum linput_enum =
565 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
566
567static const struct soc_enum linput_inv_enum =
568 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
569
570static const char *rinput_mux_text[] = {
571 "IN1R", "IN2R", "IN3R"
572};
573
574static const struct soc_enum rinput_enum =
575 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
576
577static const struct soc_enum rinput_inv_enum =
578 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
579
580
291ce18c
MB		 581static const char *sidetone_text[] = {
582 "None", "Left", "Right"
583};
584
585static const struct soc_enum lsidetone_enum =
586 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
587
588static const struct soc_enum rsidetone_enum =
589 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
590
f1c0a02f
MB		 591static const struct snd_kcontrol_new wm8903_snd_controls[] = {
592
593/* Input PGAs - No TLV since the scale depends on PGA mode */
594SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 595 7, 1, 1),
f1c0a02f
MB		 596SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
597 0, 31, 0),
598SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
599 6, 1, 0),
600
601SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 602 7, 1, 1),
f1c0a02f
MB		 603SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
604 0, 31, 0),
605SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
606 6, 1, 0),
607
608/* ADCs */
609SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
610SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
611SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 612SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 613 drc_tlv_thresh),
614SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
615SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
616SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
617SOC_ENUM("DRC Attack Rate", drc_attack),
618SOC_ENUM("DRC Decay Rate", drc_decay),
619SOC_ENUM("DRC FF Delay", drc_ff_delay),
620SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
621SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 622SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 623SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
624SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
625SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 626SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 627SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
628
629SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
630 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
631SOC_ENUM("ADC Companding Mode", adc_companding),
632SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
633
291ce18c
MB		 634SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
635 12, 0, digital_sidetone_tlv),
636
f1c0a02f
MB		 637/* DAC */
638SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
639 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
640SOC_ENUM("DAC Soft Mute Rate", soft_mute),
641SOC_ENUM("DAC Mute Mode", mute_mode),
642SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
643SOC_ENUM("DAC De-emphasis", dac_deemphasis),
f1c0a02f
MB		 644SOC_ENUM("DAC Companding Mode", dac_companding),
645SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
646
647/* Headphones */
648SOC_DOUBLE_R("Headphone Switch",
649 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
650 8, 1, 1),
651SOC_DOUBLE_R("Headphone ZC Switch",
652 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
653 6, 1, 0),
654SOC_DOUBLE_R_TLV("Headphone Volume",
655 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
656 0, 63, 0, out_tlv),
657
658/* Line out */
659SOC_DOUBLE_R("Line Out Switch",
660 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
661 8, 1, 1),
662SOC_DOUBLE_R("Line Out ZC Switch",
663 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
664 6, 1, 0),
665SOC_DOUBLE_R_TLV("Line Out Volume",
666 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
667 0, 63, 0, out_tlv),
668
669/* Speaker */
670SOC_DOUBLE_R("Speaker Switch",
671 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
672SOC_DOUBLE_R("Speaker ZC Switch",
673 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
674SOC_DOUBLE_R_TLV("Speaker Volume",
675 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
676 0, 63, 0, out_tlv),
677};
678
f1c0a02f
MB		 679static const struct snd_kcontrol_new linput_mode_mux =
680 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
681
682static const struct snd_kcontrol_new rinput_mode_mux =
683 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
684
685static const struct snd_kcontrol_new linput_mux =
686 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
687
688static const struct snd_kcontrol_new linput_inv_mux =
689 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
690
691static const struct snd_kcontrol_new rinput_mux =
692 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
693
694static const struct snd_kcontrol_new rinput_inv_mux =
695 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
696
291ce18c
MB		 697static const struct snd_kcontrol_new lsidetone_mux =
698 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
699
700static const struct snd_kcontrol_new rsidetone_mux =
701 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
702
f1c0a02f
MB		 703static const struct snd_kcontrol_new left_output_mixer[] = {
704SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
705SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
706SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 707SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 708};
709
710static const struct snd_kcontrol_new right_output_mixer[] = {
711SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
712SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
713SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 714SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 715};
716
717static const struct snd_kcontrol_new left_speaker_mixer[] = {
718SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
719SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
720SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
721SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 722 0, 1, 0),
f1c0a02f
MB		 723};
724
725static const struct snd_kcontrol_new right_speaker_mixer[] = {
726SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
727SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
728SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
729 1, 1, 0),
730SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 731 0, 1, 0),
f1c0a02f
MB		 732};
733
734static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
735SND_SOC_DAPM_INPUT("IN1L"),
736SND_SOC_DAPM_INPUT("IN1R"),
737SND_SOC_DAPM_INPUT("IN2L"),
738SND_SOC_DAPM_INPUT("IN2R"),
739SND_SOC_DAPM_INPUT("IN3L"),
740SND_SOC_DAPM_INPUT("IN3R"),
741
742SND_SOC_DAPM_OUTPUT("HPOUTL"),
743SND_SOC_DAPM_OUTPUT("HPOUTR"),
744SND_SOC_DAPM_OUTPUT("LINEOUTL"),
745SND_SOC_DAPM_OUTPUT("LINEOUTR"),
746SND_SOC_DAPM_OUTPUT("LOP"),
747SND_SOC_DAPM_OUTPUT("LON"),
748SND_SOC_DAPM_OUTPUT("ROP"),
749SND_SOC_DAPM_OUTPUT("RON"),
750
751SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
752
753SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
754SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
755 &linput_inv_mux),
756SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
757
758SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
759SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
760 &rinput_inv_mux),
761SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
762
763SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
764SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
765
766SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
767SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
768
291ce18c
MB		 769SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
770SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
771
f1c0a02f
MB		 772SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
773SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
774
775SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
776 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
777SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
778 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
779
780SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
781 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
782SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
783 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
784
785SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
786 1, 0, NULL, 0, wm8903_output_event,
787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 788 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 789SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
790 0, 0, NULL, 0, wm8903_output_event,
791 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 792 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 793
794SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
795 NULL, 0, wm8903_output_event,
796 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 797 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 798SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
799 NULL, 0, wm8903_output_event,
800 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 801 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 802
803SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
804 NULL, 0),
805SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
806 NULL, 0),
807
42768a12
MB		 808SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
809 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 810SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 811};
812
813static const struct snd_soc_dapm_route intercon[] = {
814
815 { "Left Input Mux", "IN1L", "IN1L" },
816 { "Left Input Mux", "IN2L", "IN2L" },
817 { "Left Input Mux", "IN3L", "IN3L" },
818
819 { "Left Input Inverting Mux", "IN1L", "IN1L" },
820 { "Left Input Inverting Mux", "IN2L", "IN2L" },
821 { "Left Input Inverting Mux", "IN3L", "IN3L" },
822
823 { "Right Input Mux", "IN1R", "IN1R" },
824 { "Right Input Mux", "IN2R", "IN2R" },
825 { "Right Input Mux", "IN3R", "IN3R" },
826
827 { "Right Input Inverting Mux", "IN1R", "IN1R" },
828 { "Right Input Inverting Mux", "IN2R", "IN2R" },
829 { "Right Input Inverting Mux", "IN3R", "IN3R" },
830
831 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
832 { "Left Input Mode Mux", "Differential Line",
833 "Left Input Mux" },
834 { "Left Input Mode Mux", "Differential Line",
835 "Left Input Inverting Mux" },
836 { "Left Input Mode Mux", "Differential Mic",
837 "Left Input Mux" },
838 { "Left Input Mode Mux", "Differential Mic",
839 "Left Input Inverting Mux" },
840
841 { "Right Input Mode Mux", "Single-Ended",
842 "Right Input Inverting Mux" },
843 { "Right Input Mode Mux", "Differential Line",
844 "Right Input Mux" },
845 { "Right Input Mode Mux", "Differential Line",
846 "Right Input Inverting Mux" },
847 { "Right Input Mode Mux", "Differential Mic",
848 "Right Input Mux" },
849 { "Right Input Mode Mux", "Differential Mic",
850 "Right Input Inverting Mux" },
851
852 { "Left Input PGA", NULL, "Left Input Mode Mux" },
853 { "Right Input PGA", NULL, "Right Input Mode Mux" },
854
855 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 856 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 857 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 858 { "ADCR", NULL, "CLK_DSP" },
859
291ce18c
MB		 860 { "DACL Sidetone", "Left", "ADCL" },
861 { "DACL Sidetone", "Right", "ADCR" },
862 { "DACR Sidetone", "Left", "ADCL" },
863 { "DACR Sidetone", "Right", "ADCR" },
864
865 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 866 { "DACL", NULL, "CLK_DSP" },
291ce18c 867 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 868 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 869
870 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
871 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
872 { "Left Output Mixer", "DACL Switch", "DACL" },
873 { "Left Output Mixer", "DACR Switch", "DACR" },
874
875 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
876 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
877 { "Right Output Mixer", "DACL Switch", "DACL" },
878 { "Right Output Mixer", "DACR Switch", "DACR" },
879
880 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
881 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
882 { "Left Speaker Mixer", "DACL Switch", "DACL" },
883 { "Left Speaker Mixer", "DACR Switch", "DACR" },
884
885 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
886 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
887 { "Right Speaker Mixer", "DACL Switch", "DACL" },
888 { "Right Speaker Mixer", "DACR Switch", "DACR" },
889
890 { "Left Line Output PGA", NULL, "Left Output Mixer" },
891 { "Right Line Output PGA", NULL, "Right Output Mixer" },
892
893 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
894 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
895
896 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
897 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
898
899 { "HPOUTL", NULL, "Left Headphone Output PGA" },
900 { "HPOUTR", NULL, "Right Headphone Output PGA" },
901
902 { "LINEOUTL", NULL, "Left Line Output PGA" },
903 { "LINEOUTR", NULL, "Right Line Output PGA" },
904
905 { "LOP", NULL, "Left Speaker PGA" },
906 { "LON", NULL, "Left Speaker PGA" },
907
908 { "ROP", NULL, "Right Speaker PGA" },
909 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 910
911 { "Left Headphone Output PGA", NULL, "Charge Pump" },
912 { "Right Headphone Output PGA", NULL, "Charge Pump" },
913 { "Left Line Output PGA", NULL, "Charge Pump" },
914 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 915};
916
917static int wm8903_add_widgets(struct snd_soc_codec *codec)
918{
919 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
920 ARRAY_SIZE(wm8903_dapm_widgets));
921
922 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
923
f1c0a02f
MB		 924 return 0;
925}
926
927static int wm8903_set_bias_level(struct snd_soc_codec *codec,
928 enum snd_soc_bias_level level)
929{
930 struct i2c_client *i2c = codec->control_data;
931 u16 reg, reg2;
932
933 switch (level) {
934 case SND_SOC_BIAS_ON:
935 case SND_SOC_BIAS_PREPARE:
8d50e447 936 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 937 reg &= ~(WM8903_VMID_RES_MASK);
938 reg |= WM8903_VMID_RES_50K;
8d50e447 939 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 940 break;
941
942 case SND_SOC_BIAS_STANDBY:
943 if (codec->bias_level == SND_SOC_BIAS_OFF) {
8d50e447 944 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 945 WM8903_CLK_SYS_ENA);
946
4dbfe809 947 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 948 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
949 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
950 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 951
f1c0a02f
MB		 952 wm8903_run_sequence(codec, 0);
953 wm8903_sync_reg_cache(codec, codec->reg_cache);
954
955 /* Enable low impedence charge pump output */
8d50e447 956 reg = snd_soc_read(codec,
f1c0a02f 957 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 958 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 959 reg | WM8903_TEST_KEY);
8d50e447
MB		 960 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
961 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 962 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 963 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 964 reg);
965
966 /* By default no bypass paths are enabled so
967 * enable Class W support.
968 */
969 dev_dbg(&i2c->dev, "Enabling Class W\n");
8d50e447 970 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 971 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
972 }
973
8d50e447 974 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 975 reg &= ~(WM8903_VMID_RES_MASK);
976 reg |= WM8903_VMID_RES_250K;
8d50e447 977 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 978 break;
979
980 case SND_SOC_BIAS_OFF:
981 wm8903_run_sequence(codec, 32);
8d50e447 982 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 983 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 984 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 985 break;
986 }
987
988 codec->bias_level = level;
989
990 return 0;
991}
992
993static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
994 int clk_id, unsigned int freq, int dir)
995{
996 struct snd_soc_codec *codec = codec_dai->codec;
997 struct wm8903_priv *wm8903 = codec->private_data;
998
999 wm8903->sysclk = freq;
1000
1001 return 0;
1002}
1003
1004static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1005 unsigned int fmt)
1006{
1007 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1008 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1009
1010 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1011 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1012
1013 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1014 case SND_SOC_DAIFMT_CBS_CFS:
1015 break;
1016 case SND_SOC_DAIFMT_CBS_CFM:
1017 aif1 |= WM8903_LRCLK_DIR;
1018 break;
1019 case SND_SOC_DAIFMT_CBM_CFM:
1020 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1021 break;
1022 case SND_SOC_DAIFMT_CBM_CFS:
1023 aif1 |= WM8903_BCLK_DIR;
1024 break;
1025 default:
1026 return -EINVAL;
1027 }
1028
1029 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1030 case SND_SOC_DAIFMT_DSP_A:
1031 aif1 |= 0x3;
1032 break;
1033 case SND_SOC_DAIFMT_DSP_B:
1034 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1035 break;
1036 case SND_SOC_DAIFMT_I2S:
1037 aif1 |= 0x2;
1038 break;
1039 case SND_SOC_DAIFMT_RIGHT_J:
1040 aif1 |= 0x1;
1041 break;
1042 case SND_SOC_DAIFMT_LEFT_J:
1043 break;
1044 default:
1045 return -EINVAL;
1046 }
1047
1048 /* Clock inversion */
1049 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1050 case SND_SOC_DAIFMT_DSP_A:
1051 case SND_SOC_DAIFMT_DSP_B:
1052 /* frame inversion not valid for DSP modes */
1053 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1054 case SND_SOC_DAIFMT_NB_NF:
1055 break;
1056 case SND_SOC_DAIFMT_IB_NF:
1057 aif1 |= WM8903_AIF_BCLK_INV;
1058 break;
1059 default:
1060 return -EINVAL;
1061 }
1062 break;
1063 case SND_SOC_DAIFMT_I2S:
1064 case SND_SOC_DAIFMT_RIGHT_J:
1065 case SND_SOC_DAIFMT_LEFT_J:
1066 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1067 case SND_SOC_DAIFMT_NB_NF:
1068 break;
1069 case SND_SOC_DAIFMT_IB_IF:
1070 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1071 break;
1072 case SND_SOC_DAIFMT_IB_NF:
1073 aif1 |= WM8903_AIF_BCLK_INV;
1074 break;
1075 case SND_SOC_DAIFMT_NB_IF:
1076 aif1 |= WM8903_AIF_LRCLK_INV;
1077 break;
1078 default:
1079 return -EINVAL;
1080 }
1081 break;
1082 default:
1083 return -EINVAL;
1084 }
1085
8d50e447 1086 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1087
1088 return 0;
1089}
1090
1091static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1092{
1093 struct snd_soc_codec *codec = codec_dai->codec;
1094 u16 reg;
1095
8d50e447 1096 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1097
1098 if (mute)
1099 reg |= WM8903_DAC_MUTE;
1100 else
1101 reg &= ~WM8903_DAC_MUTE;
1102
8d50e447 1103 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1104
1105 return 0;
1106}
1107
1108/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1109 * for optimal performance so we list the lower rates first and match
1110 * on the last match we find. */
1111static struct {
1112 int div;
1113 int rate;
1114 int mode;
1115 int mclk_div;
1116} clk_sys_ratios[] = {
1117 { 64, 0x0, 0x0, 1 },
1118 { 68, 0x0, 0x1, 1 },
1119 { 125, 0x0, 0x2, 1 },
1120 { 128, 0x1, 0x0, 1 },
1121 { 136, 0x1, 0x1, 1 },
1122 { 192, 0x2, 0x0, 1 },
1123 { 204, 0x2, 0x1, 1 },
1124
1125 { 64, 0x0, 0x0, 2 },
1126 { 68, 0x0, 0x1, 2 },
1127 { 125, 0x0, 0x2, 2 },
1128 { 128, 0x1, 0x0, 2 },
1129 { 136, 0x1, 0x1, 2 },
1130 { 192, 0x2, 0x0, 2 },
1131 { 204, 0x2, 0x1, 2 },
1132
1133 { 250, 0x2, 0x2, 1 },
1134 { 256, 0x3, 0x0, 1 },
1135 { 272, 0x3, 0x1, 1 },
1136 { 384, 0x4, 0x0, 1 },
1137 { 408, 0x4, 0x1, 1 },
1138 { 375, 0x4, 0x2, 1 },
1139 { 512, 0x5, 0x0, 1 },
1140 { 544, 0x5, 0x1, 1 },
1141 { 500, 0x5, 0x2, 1 },
1142 { 768, 0x6, 0x0, 1 },
1143 { 816, 0x6, 0x1, 1 },
1144 { 750, 0x6, 0x2, 1 },
1145 { 1024, 0x7, 0x0, 1 },
1146 { 1088, 0x7, 0x1, 1 },
1147 { 1000, 0x7, 0x2, 1 },
1148 { 1408, 0x8, 0x0, 1 },
1149 { 1496, 0x8, 0x1, 1 },
1150 { 1536, 0x9, 0x0, 1 },
1151 { 1632, 0x9, 0x1, 1 },
1152 { 1500, 0x9, 0x2, 1 },
1153
1154 { 250, 0x2, 0x2, 2 },
1155 { 256, 0x3, 0x0, 2 },
1156 { 272, 0x3, 0x1, 2 },
1157 { 384, 0x4, 0x0, 2 },
1158 { 408, 0x4, 0x1, 2 },
1159 { 375, 0x4, 0x2, 2 },
1160 { 512, 0x5, 0x0, 2 },
1161 { 544, 0x5, 0x1, 2 },
1162 { 500, 0x5, 0x2, 2 },
1163 { 768, 0x6, 0x0, 2 },
1164 { 816, 0x6, 0x1, 2 },
1165 { 750, 0x6, 0x2, 2 },
1166 { 1024, 0x7, 0x0, 2 },
1167 { 1088, 0x7, 0x1, 2 },
1168 { 1000, 0x7, 0x2, 2 },
1169 { 1408, 0x8, 0x0, 2 },
1170 { 1496, 0x8, 0x1, 2 },
1171 { 1536, 0x9, 0x0, 2 },
1172 { 1632, 0x9, 0x1, 2 },
1173 { 1500, 0x9, 0x2, 2 },
1174};
1175
1176/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1177static struct {
1178 int ratio;
1179 int div;
1180} bclk_divs[] = {
1181 { 10, 0 },
f1c0a02f
MB		 1182 { 20, 2 },
1183 { 30, 3 },
1184 { 40, 4 },
1185 { 50, 5 },
f1c0a02f
MB		 1186 { 60, 7 },
1187 { 80, 8 },
1188 { 100, 9 },
f1c0a02f
MB		 1189 { 120, 11 },
1190 { 160, 12 },
1191 { 200, 13 },
1192 { 220, 14 },
1193 { 240, 15 },
f1c0a02f
MB		 1194 { 300, 17 },
1195 { 320, 18 },
1196 { 440, 19 },
1197 { 480, 20 },
1198};
1199
1200/* Sample rates for DSP */
1201static struct {
1202 int rate;
1203 int value;
1204} sample_rates[] = {
1205 { 8000, 0 },
1206 { 11025, 1 },
1207 { 12000, 2 },
1208 { 16000, 3 },
1209 { 22050, 4 },
1210 { 24000, 5 },
1211 { 32000, 6 },
1212 { 44100, 7 },
1213 { 48000, 8 },
1214 { 88200, 9 },
1215 { 96000, 10 },
1216 { 0, 0 },
1217};
1218
dee89c4d
MB		 1219static int wm8903_startup(struct snd_pcm_substream *substream,
1220 struct snd_soc_dai *dai)
f1c0a02f
MB		 1221{
1222 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1223 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1224 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1225 struct wm8903_priv *wm8903 = codec->private_data;
1226 struct i2c_client *i2c = codec->control_data;
1227 struct snd_pcm_runtime *master_runtime;
1228
1229 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1230 wm8903->playback_active++;
1231 else
1232 wm8903->capture_active++;
1233
1234 /* The DAI has shared clocks so if we already have a playback or
1235 * capture going then constrain this substream to match it.
1236 */
1237 if (wm8903->master_substream) {
1238 master_runtime = wm8903->master_substream->runtime;
1239
727fb909
MB		 1240 dev_dbg(&i2c->dev, "Constraining to %d bits\n",
1241 master_runtime->sample_bits);
f1c0a02f
MB		 1242
1243 snd_pcm_hw_constraint_minmax(substream->runtime,
1244 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1245 master_runtime->sample_bits,
1246 master_runtime->sample_bits);
1247
1248 wm8903->slave_substream = substream;
1249 } else
1250 wm8903->master_substream = substream;
1251
1252 return 0;
1253}
1254
dee89c4d
MB		 1255static void wm8903_shutdown(struct snd_pcm_substream *substream,
1256 struct snd_soc_dai *dai)
f1c0a02f
MB		 1257{
1258 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1259 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1260 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1261 struct wm8903_priv *wm8903 = codec->private_data;
1262
1263 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1264 wm8903->playback_active--;
1265 else
1266 wm8903->capture_active--;
1267
1268 if (wm8903->master_substream == substream)
1269 wm8903->master_substream = wm8903->slave_substream;
1270
1271 wm8903->slave_substream = NULL;
1272}
1273
1274static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1275 struct snd_pcm_hw_params *params,
1276 struct snd_soc_dai *dai)
f1c0a02f
MB		 1277{
1278 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1279 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1280 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1281 struct wm8903_priv *wm8903 = codec->private_data;
1282 struct i2c_client *i2c = codec->control_data;
1283 int fs = params_rate(params);
1284 int bclk;
1285 int bclk_div;
1286 int i;
1287 int dsp_config;
1288 int clk_config;
1289 int best_val;
1290 int cur_val;
1291 int clk_sys;
1292
8d50e447
MB		 1293 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1294 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1295 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1296 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1297 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1298 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1299
1300 if (substream == wm8903->slave_substream) {
1301 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1302 return 0;
1303 }
1304
9e79261f
MB		 1305 /* Enable sloping stopband filter for low sample rates */
1306 if (fs <= 24000)
1307 dac_digital1 |= WM8903_DAC_SB_FILT;
1308 else
1309 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1310
f1c0a02f
MB		 1311 /* Configure sample rate logic for DSP - choose nearest rate */
1312 dsp_config = 0;
1313 best_val = abs(sample_rates[dsp_config].rate - fs);
1314 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1315 cur_val = abs(sample_rates[i].rate - fs);
1316 if (cur_val <= best_val) {
1317 dsp_config = i;
1318 best_val = cur_val;
1319 }
1320 }
1321
1322 /* Constraints should stop us hitting this but let's make sure */
1323 if (wm8903->capture_active)
1324 switch (sample_rates[dsp_config].rate) {
1325 case 88200:
1326 case 96000:
1327 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1328 fs);
1329 return -EINVAL;
1330
1331 default:
1332 break;
1333 }
1334
1335 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1336 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1337 clock1 |= sample_rates[dsp_config].value;
1338
1339 aif1 &= ~WM8903_AIF_WL_MASK;
1340 bclk = 2 * fs;
1341 switch (params_format(params)) {
1342 case SNDRV_PCM_FORMAT_S16_LE:
1343 bclk *= 16;
1344 break;
1345 case SNDRV_PCM_FORMAT_S20_3LE:
1346 bclk *= 20;
1347 aif1 |= 0x4;
1348 break;
1349 case SNDRV_PCM_FORMAT_S24_LE:
1350 bclk *= 24;
1351 aif1 |= 0x8;
1352 break;
1353 case SNDRV_PCM_FORMAT_S32_LE:
1354 bclk *= 32;
1355 aif1 |= 0xc;
1356 break;
1357 default:
1358 return -EINVAL;
1359 }
1360
1361 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1362 wm8903->sysclk, fs);
1363
1364 /* We may not have an MCLK which allows us to generate exactly
1365 * the clock we want, particularly with USB derived inputs, so
1366 * approximate.
1367 */
1368 clk_config = 0;
1369 best_val = abs((wm8903->sysclk /
1370 (clk_sys_ratios[0].mclk_div *
1371 clk_sys_ratios[0].div)) - fs);
1372 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1373 cur_val = abs((wm8903->sysclk /
1374 (clk_sys_ratios[i].mclk_div *
1375 clk_sys_ratios[i].div)) - fs);
1376
1377 if (cur_val <= best_val) {
1378 clk_config = i;
1379 best_val = cur_val;
1380 }
1381 }
1382
1383 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1384 clock0 |= WM8903_MCLKDIV2;
1385 clk_sys = wm8903->sysclk / 2;
1386 } else {
1387 clock0 &= ~WM8903_MCLKDIV2;
1388 clk_sys = wm8903->sysclk;
1389 }
1390
1391 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1392 WM8903_CLK_SYS_MODE_MASK);
1393 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1394 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1395
1396 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1397 clk_sys_ratios[clk_config].rate,
1398 clk_sys_ratios[clk_config].mode,
1399 clk_sys_ratios[clk_config].div);
1400
1401 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1402
1403 /* We may not get quite the right frequency if using
1404 * approximate clocks so look for the closest match that is
1405 * higher than the target (we need to ensure that there enough
1406 * BCLKs to clock out the samples).
1407 */
1408 bclk_div = 0;
1409 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1410 i = 1;
1411 while (i < ARRAY_SIZE(bclk_divs)) {
1412 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1413 if (cur_val < 0) /* BCLK table is sorted */
1414 break;
1415 bclk_div = i;
1416 best_val = cur_val;
1417 i++;
1418 }
1419
1420 aif2 &= ~WM8903_BCLK_DIV_MASK;
1421 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1422
1423 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1424 bclk_divs[bclk_div].ratio / 10, bclk,
1425 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1426
1427 aif2 |= bclk_divs[bclk_div].div;
1428 aif3 |= bclk / fs;
1429
8d50e447
MB		 1430 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1431 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1432 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1433 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1434 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1435 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1436
1437 return 0;
1438}
1439
8abd16a6
MB		 1440static irqreturn_t wm8903_irq(int irq, void *data)
1441{
1442 struct wm8903_priv *wm8903 = data;
1443 struct snd_soc_codec *codec = &wm8903->codec;
1444 int reg;
1445
1446 reg = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1);
1447
1448 if (reg & WM8903_WSEQ_BUSY_EINT) {
1449 dev_dbg(codec->dev, "Write sequencer done\n");
1450 complete(&wm8903->wseq);
1451 }
1452
1453 return IRQ_HANDLED;
1454}
1455
f1c0a02f
MB		 1456#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1457 SNDRV_PCM_RATE_11025 | \
1458 SNDRV_PCM_RATE_16000 | \
1459 SNDRV_PCM_RATE_22050 | \
1460 SNDRV_PCM_RATE_32000 | \
1461 SNDRV_PCM_RATE_44100 | \
1462 SNDRV_PCM_RATE_48000 | \
1463 SNDRV_PCM_RATE_88200 | \
1464 SNDRV_PCM_RATE_96000)
1465
1466#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1467 SNDRV_PCM_RATE_11025 | \
1468 SNDRV_PCM_RATE_16000 | \
1469 SNDRV_PCM_RATE_22050 | \
1470 SNDRV_PCM_RATE_32000 | \
1471 SNDRV_PCM_RATE_44100 | \
1472 SNDRV_PCM_RATE_48000)
1473
1474#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1475 SNDRV_PCM_FMTBIT_S20_3LE |\
1476 SNDRV_PCM_FMTBIT_S24_LE)
1477
6335d055
EM		 1478static struct snd_soc_dai_ops wm8903_dai_ops = {
1479 .startup = wm8903_startup,
1480 .shutdown = wm8903_shutdown,
1481 .hw_params = wm8903_hw_params,
1482 .digital_mute = wm8903_digital_mute,
1483 .set_fmt = wm8903_set_dai_fmt,
1484 .set_sysclk = wm8903_set_dai_sysclk,
1485};
1486
f1c0a02f
MB		 1487struct snd_soc_dai wm8903_dai = {
1488 .name = "WM8903",
1489 .playback = {
1490 .stream_name = "Playback",
1491 .channels_min = 2,
1492 .channels_max = 2,
1493 .rates = WM8903_PLAYBACK_RATES,
1494 .formats = WM8903_FORMATS,
1495 },
1496 .capture = {
1497 .stream_name = "Capture",
1498 .channels_min = 2,
1499 .channels_max = 2,
1500 .rates = WM8903_CAPTURE_RATES,
1501 .formats = WM8903_FORMATS,
1502 },
6335d055 1503 .ops = &wm8903_dai_ops,
0d960e88 1504 .symmetric_rates = 1,
f1c0a02f
MB		 1505};
1506EXPORT_SYMBOL_GPL(wm8903_dai);
1507
1508static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1509{
1510 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1511 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1512
1513 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1514
1515 return 0;
1516}
1517
1518static int wm8903_resume(struct platform_device *pdev)
1519{
1520 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1521 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1522 struct i2c_client *i2c = codec->control_data;
1523 int i;
1524 u16 *reg_cache = codec->reg_cache;
40aa7030 1525 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1526 GFP_KERNEL);
1527
1528 /* Bring the codec back up to standby first to minimise pop/clicks */
1529 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1530 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1531
1532 /* Sync back everything else */
1533 if (tmp_cache) {
1534 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1535 if (tmp_cache[i] != reg_cache[i])
8d50e447 1536 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1537 kfree(tmp_cache);
f1c0a02f
MB		 1538 } else {
1539 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1540 }
1541
1542 return 0;
1543}
1544
d58d5d55
MB		 1545static struct snd_soc_codec *wm8903_codec;
1546
c6f29811
MB		 1547static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1548 const struct i2c_device_id *id)
f1c0a02f 1549{
8abd16a6 1550 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
d58d5d55
MB		 1551 struct wm8903_priv *wm8903;
1552 struct snd_soc_codec *codec;
73b34ead 1553 int ret, i;
8abd16a6 1554 int trigger, irq_pol;
f1c0a02f
MB		 1555 u16 val;
1556
d58d5d55
MB		 1557 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1558 if (wm8903 == NULL)
1559 return -ENOMEM;
f1c0a02f 1560
d58d5d55
MB		 1561 codec = &wm8903->codec;
1562
1563 mutex_init(&codec->mutex);
1564 INIT_LIST_HEAD(&codec->dapm_widgets);
1565 INIT_LIST_HEAD(&codec->dapm_paths);
1566
1567 codec->dev = &i2c->dev;
f1c0a02f
MB		 1568 codec->name = "WM8903";
1569 codec->owner = THIS_MODULE;
f1c0a02f
MB		 1570 codec->bias_level = SND_SOC_BIAS_OFF;
1571 codec->set_bias_level = wm8903_set_bias_level;
1572 codec->dai = &wm8903_dai;
1573 codec->num_dai = 1;
d58d5d55
MB		 1574 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1575 codec->reg_cache = &wm8903->reg_cache[0];
1576 codec->private_data = wm8903;
8d50e447 1577 codec->volatile_register = wm8903_volatile_register;
8abd16a6 1578 init_completion(&wm8903->wseq);
d58d5d55
MB		 1579
1580 i2c_set_clientdata(i2c, codec);
1581 codec->control_data = i2c;
1582
8d50e447
MB		 1583 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1584 if (ret != 0) {
1585 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1586 goto err;
1587 }
1588
1589 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55
MB		 1590 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1591 dev_err(&i2c->dev,
1592 "Device with ID register %x is not a WM8903\n", val);
1593 return -ENODEV;
f1c0a02f
MB		 1594 }
1595
8d50e447 1596 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f1c0a02f
MB		 1597 dev_info(&i2c->dev, "WM8903 revision %d\n",
1598 val & WM8903_CHIP_REV_MASK);
1599
1600 wm8903_reset(codec);
1601
37f88e84 1602 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1603 if (pdata) {
1604 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1605 if (!pdata->gpio_cfg[i])
1606 continue;
1607
1608 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1609 pdata->gpio_cfg[i] & 0xffff);
1610 }
37f88e84
MB		 1611
1612 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1613 pdata->micdet_cfg);
1614
1615 /* Microphone detection needs the WSEQ clock */
1616 if (pdata->micdet_cfg)
1617 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1618 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1619
1620 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1621 }
8abd16a6
MB		 1622
1623 if (i2c->irq) {
1624 if (pdata && pdata->irq_active_low) {
1625 trigger = IRQF_TRIGGER_LOW;
1626 irq_pol = WM8903_IRQ_POL;
1627 } else {
1628 trigger = IRQF_TRIGGER_HIGH;
1629 irq_pol = 0;
1630 }
1631
1632 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1633 WM8903_IRQ_POL, irq_pol);
1634
1635 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
1636 trigger | IRQF_ONESHOT,
1637 "wm8903", wm8903);
1638 if (ret != 0) {
1639 dev_err(&i2c->dev, "Failed to request IRQ: %d\n",
1640 ret);
1641 goto err;
1642 }
1643
1644 /* Enable write sequencer interrupts */
1645 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1646 WM8903_IM_WSEQ_BUSY_EINT, 0);
1647 }
73b34ead 1648
f1c0a02f
MB		 1649 /* power on device */
1650 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1651
1652 /* Latch volume update bits */
8d50e447 1653 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1654 val |= WM8903_ADCVU;
8d50e447
MB		 1655 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1656 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1657
8d50e447 1658 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1659 val |= WM8903_DACVU;
8d50e447
MB		 1660 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1661 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1662
8d50e447 1663 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1664 val |= WM8903_HPOUTVU;
8d50e447
MB		 1665 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1666 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1667
8d50e447 1668 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1669 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1670 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1671 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1672
8d50e447 1673 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1674 val |= WM8903_SPKVU;
8d50e447
MB		 1675 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1676 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1677
1678 /* Enable DAC soft mute by default */
8d50e447 1679 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1680 val |= WM8903_DAC_MUTEMODE;
8d50e447 1681 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1682
d58d5d55
MB		 1683 wm8903_dai.dev = &i2c->dev;
1684 wm8903_codec = codec;
1685
1686 ret = snd_soc_register_codec(codec);
1687 if (ret != 0) {
1688 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
8abd16a6 1689 goto err_irq;
d58d5d55
MB		 1690 }
1691
1692 ret = snd_soc_register_dai(&wm8903_dai);
1693 if (ret != 0) {
1694 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1695 goto err_codec;
f1c0a02f
MB		 1696 }
1697
1698 return ret;
1699
d58d5d55
MB		 1700err_codec:
1701 snd_soc_unregister_codec(codec);
8abd16a6
MB		 1702err_irq:
1703 if (i2c->irq)
1704 free_irq(i2c->irq, wm8903);
d58d5d55
MB		 1705err:
1706 wm8903_codec = NULL;
1707 kfree(wm8903);
f1c0a02f
MB		 1708 return ret;
1709}
1710
c6f29811 1711static __devexit int wm8903_i2c_remove(struct i2c_client *client)
f1c0a02f 1712{
d58d5d55 1713 struct snd_soc_codec *codec = i2c_get_clientdata(client);
8abd16a6 1714 struct wm8903_priv *priv = codec->private_data;
f1c0a02f 1715
d58d5d55
MB		 1716 snd_soc_unregister_dai(&wm8903_dai);
1717 snd_soc_unregister_codec(codec);
f1c0a02f 1718
d58d5d55 1719 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f1c0a02f 1720
8abd16a6
MB		 1721 if (client->irq)
1722 free_irq(client->irq, priv);
1723
d58d5d55
MB		 1724 kfree(codec->private_data);
1725
1726 wm8903_codec = NULL;
1727 wm8903_dai.dev = NULL;
f1c0a02f 1728
f1c0a02f
MB		 1729 return 0;
1730}
1731
1732/* i2c codec control layer */
1733static const struct i2c_device_id wm8903_i2c_id[] = {
1734 { "wm8903", 0 },
1735 { }
1736};
1737MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1738
1739static struct i2c_driver wm8903_i2c_driver = {
1740 .driver = {
1741 .name = "WM8903",
1742 .owner = THIS_MODULE,
1743 },
1744 .probe = wm8903_i2c_probe,
c6f29811 1745 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1746 .id_table = wm8903_i2c_id,
1747};
1748
f1c0a02f
MB		 1749static int wm8903_probe(struct platform_device *pdev)
1750{
1751 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
f1c0a02f
MB		 1752 int ret = 0;
1753
d58d5d55
MB		 1754 if (!wm8903_codec) {
1755 dev_err(&pdev->dev, "I2C device not yet probed\n");
1756 goto err;
f1c0a02f
MB		 1757 }
1758
6627a653 1759 socdev->card->codec = wm8903_codec;
f1c0a02f 1760
d58d5d55
MB		 1761 /* register pcms */
1762 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1763 if (ret < 0) {
1764 dev_err(&pdev->dev, "failed to create pcms\n");
1765 goto err;
f1c0a02f
MB		 1766 }
1767
6627a653 1768 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
3e8e1952 1769 ARRAY_SIZE(wm8903_snd_controls));
6627a653 1770 wm8903_add_widgets(socdev->card->codec);
f1c0a02f 1771
f1c0a02f
MB		 1772 return ret;
1773
d58d5d55 1774err:
f1c0a02f
MB		 1775 return ret;
1776}
1777
1778/* power down chip */
1779static int wm8903_remove(struct platform_device *pdev)
1780{
1781 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1782 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1783
1784 if (codec->control_data)
1785 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1786
1787 snd_soc_free_pcms(socdev);
1788 snd_soc_dapm_free(socdev);
f1c0a02f
MB		 1789
1790 return 0;
1791}
1792
1793struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1794 .probe = wm8903_probe,
1795 .remove = wm8903_remove,
1796 .suspend = wm8903_suspend,
1797 .resume = wm8903_resume,
1798};
1799EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1800
c9b3a40f 1801static int __init wm8903_modinit(void)
64089b84 1802{
d58d5d55 1803 return i2c_add_driver(&wm8903_i2c_driver);
64089b84
MB		 1804}
1805module_init(wm8903_modinit);
1806
1807static void __exit wm8903_exit(void)
1808{
d58d5d55 1809 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 1810}
1811module_exit(wm8903_exit);
1812
f1c0a02f
MB		 1813MODULE_DESCRIPTION("ASoC WM8903 driver");
1814MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1815MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree