[net-next-2.6.git] / sound / pci / oxygen / oxygen.c

/*
 * C-Media CMI8788 driver for C-Media's reference design and similar models
 *
 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
 *
 *
 *  This driver is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License, version 2.
 *
 *  This driver is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this driver; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

/*
 * CMI8788:
 *
 * SPI 0 -> 1st AK4396 (front)
 * SPI 1 -> 2nd AK4396 (surround)
 * SPI 2 -> 3rd AK4396 (center/LFE)
 * SPI 3 -> WM8785
 * SPI 4 -> 4th AK4396 (back)
 *
 * GPIO 0 -> DFS0 of AK5385
 * GPIO 1 -> DFS1 of AK5385
 * GPIO 8 -> enable headphone amplifier on HT-Omega models
 *
 * CM9780:
 *
 * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input
 */

#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <sound/ac97_codec.h>
#include <sound/control.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include "oxygen.h"
#include "ak4396.h"
#include "wm8785.h"

MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_DESCRIPTION("C-Media CMI8788 driver");
MODULE_LICENSE("GPL v2");
MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8788}}");

static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;

module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "card index");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "enable card");

enum {
	MODEL_CMEDIA_REF,	/* C-Media's reference design */
	MODEL_MERIDIAN,		/* AuzenTech X-Meridian */
	MODEL_CLARO,		/* HT-Omega Claro */
	MODEL_CLARO_HALO,	/* HT-Omega Claro halo */
};

static DEFINE_PCI_DEVICE_TABLE(oxygen_ids) = {
	{ OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF },
	{ OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN },
	{ OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO },
	{ OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO },
	{ }
};
MODULE_DEVICE_TABLE(pci, oxygen_ids);


#define GPIO_AK5385_DFS_MASK	0x0003
#define GPIO_AK5385_DFS_NORMAL	0x0000
#define GPIO_AK5385_DFS_DOUBLE	0x0001
#define GPIO_AK5385_DFS_QUAD	0x0002

#define GPIO_CLARO_HP		0x0100

struct generic_data {
	u8 ak4396_regs[4][5];
	u16 wm8785_regs[3];
};

static void ak4396_write(struct oxygen *chip, unsigned int codec,
			 u8 reg, u8 value)
{
	/* maps ALSA channel pair number to SPI output */
	static const u8 codec_spi_map[4] = {
		0, 1, 2, 4
	};
	struct generic_data *data = chip->model_data;

	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
			 OXYGEN_SPI_DATA_LENGTH_2 |
			 OXYGEN_SPI_CLOCK_160 |
			 (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
			 OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
			 AK4396_WRITE | (reg << 8) | value);
	data->ak4396_regs[codec][reg] = value;
}

static void ak4396_write_cached(struct oxygen *chip, unsigned int codec,
				u8 reg, u8 value)
{
	struct generic_data *data = chip->model_data;

	if (value != data->ak4396_regs[codec][reg])
		ak4396_write(chip, codec, reg, value);
}

static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
{
	struct generic_data *data = chip->model_data;

	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
			 OXYGEN_SPI_DATA_LENGTH_2 |
			 OXYGEN_SPI_CLOCK_160 |
			 (3 << OXYGEN_SPI_CODEC_SHIFT) |
			 OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
			 (reg << 9) | value);
	if (reg < ARRAY_SIZE(data->wm8785_regs))
		data->wm8785_regs[reg] = value;
}

static void ak4396_registers_init(struct oxygen *chip)
{
	struct generic_data *data = chip->model_data;
	unsigned int i;

	for (i = 0; i < 4; ++i) {
		ak4396_write(chip, i, AK4396_CONTROL_1,
			     AK4396_DIF_24_MSB | AK4396_RSTN);
		ak4396_write(chip, i, AK4396_CONTROL_2,
			     data->ak4396_regs[0][AK4396_CONTROL_2]);
		ak4396_write(chip, i, AK4396_CONTROL_3,
			     AK4396_PCM);
		ak4396_write(chip, i, AK4396_LCH_ATT,
			     chip->dac_volume[i * 2]);
		ak4396_write(chip, i, AK4396_RCH_ATT,
			     chip->dac_volume[i * 2 + 1]);
	}
}

static void ak4396_init(struct oxygen *chip)
{
	struct generic_data *data = chip->model_data;

	data->ak4396_regs[0][AK4396_CONTROL_2] =
		AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL;
	ak4396_registers_init(chip);
	snd_component_add(chip->card, "AK4396");
}

static void ak5385_init(struct oxygen *chip)
{
	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK);
	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK);
	snd_component_add(chip->card, "AK5385");
}

static void wm8785_registers_init(struct oxygen *chip)
{
	struct generic_data *data = chip->model_data;

	wm8785_write(chip, WM8785_R7, 0);
	wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]);
	wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
}

static void wm8785_init(struct oxygen *chip)
{
	struct generic_data *data = chip->model_data;

	data->wm8785_regs[0] =
		WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST;
	data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL;
	wm8785_registers_init(chip);
	snd_component_add(chip->card, "WM8785");
}

static void generic_init(struct oxygen *chip)
{
	ak4396_init(chip);
	wm8785_init(chip);
}

static void meridian_init(struct oxygen *chip)
{
	ak4396_init(chip);
	ak5385_init(chip);
}

static void claro_enable_hp(struct oxygen *chip)
{
	msleep(300);
	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP);
	oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
}

static void claro_init(struct oxygen *chip)
{
	ak4396_init(chip);
	wm8785_init(chip);
	claro_enable_hp(chip);
}

static void claro_halo_init(struct oxygen *chip)
{
	ak4396_init(chip);
	ak5385_init(chip);
	claro_enable_hp(chip);
}

static void generic_cleanup(struct oxygen *chip)
{
}

static void claro_disable_hp(struct oxygen *chip)
{
	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
}

static void claro_cleanup(struct oxygen *chip)
{
	claro_disable_hp(chip);
}

static void claro_suspend(struct oxygen *chip)
{
	claro_disable_hp(chip);
}

static void generic_resume(struct oxygen *chip)
{
	ak4396_registers_init(chip);
	wm8785_registers_init(chip);
}

static void meridian_resume(struct oxygen *chip)
{
	ak4396_registers_init(chip);
}

static void claro_resume(struct oxygen *chip)
{
	ak4396_registers_init(chip);
	claro_enable_hp(chip);
}

static void set_ak4396_params(struct oxygen *chip,
			      struct snd_pcm_hw_params *params)
{
	struct generic_data *data = chip->model_data;
	unsigned int i;
	u8 value;

	value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK;
	if (params_rate(params) <= 54000)
		value |= AK4396_DFS_NORMAL;
	else if (params_rate(params) <= 108000)
		value |= AK4396_DFS_DOUBLE;
	else
		value |= AK4396_DFS_QUAD;

	msleep(1); /* wait for the new MCLK to become stable */

	if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) {
		for (i = 0; i < 4; ++i) {
			ak4396_write(chip, i, AK4396_CONTROL_1,
				     AK4396_DIF_24_MSB);
			ak4396_write(chip, i, AK4396_CONTROL_2, value);
			ak4396_write(chip, i, AK4396_CONTROL_1,
				     AK4396_DIF_24_MSB | AK4396_RSTN);
		}
	}
}

static void update_ak4396_volume(struct oxygen *chip)
{
	unsigned int i;

	for (i = 0; i < 4; ++i) {
		ak4396_write_cached(chip, i, AK4396_LCH_ATT,
				    chip->dac_volume[i * 2]);
		ak4396_write_cached(chip, i, AK4396_RCH_ATT,
				    chip->dac_volume[i * 2 + 1]);
	}
}

static void update_ak4396_mute(struct oxygen *chip)
{
	struct generic_data *data = chip->model_data;
	unsigned int i;
	u8 value;

	value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE;
	if (chip->dac_mute)
		value |= AK4396_SMUTE;
	for (i = 0; i < 4; ++i)
		ak4396_write_cached(chip, i, AK4396_CONTROL_2, value);
}

static void set_wm8785_params(struct oxygen *chip,
			      struct snd_pcm_hw_params *params)
{
	struct generic_data *data = chip->model_data;
	unsigned int value;

	value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST;
	if (params_rate(params) <= 48000)
		value |= WM8785_OSR_SINGLE;
	else if (params_rate(params) <= 96000)
		value |= WM8785_OSR_DOUBLE;
	else
		value |= WM8785_OSR_QUAD;
	if (value != data->wm8785_regs[0]) {
		wm8785_write(chip, WM8785_R7, 0);
		wm8785_write(chip, WM8785_R0, value);
		wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
	}
}

static void set_ak5385_params(struct oxygen *chip,
			      struct snd_pcm_hw_params *params)
{
	unsigned int value;

	if (params_rate(params) <= 54000)
		value = GPIO_AK5385_DFS_NORMAL;
	else if (params_rate(params) <= 108000)
		value = GPIO_AK5385_DFS_DOUBLE;
	else
		value = GPIO_AK5385_DFS_QUAD;
	oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
			      value, GPIO_AK5385_DFS_MASK);
}

static int rolloff_info(struct snd_kcontrol *ctl,
			struct snd_ctl_elem_info *info)
{
	static const char *const names[2] = {
		"Sharp Roll-off", "Slow Roll-off"
	};

	info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	info->count = 1;
	info->value.enumerated.items = 2;
	if (info->value.enumerated.item >= 2)
		info->value.enumerated.item = 1;
	strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
	return 0;
}

static int rolloff_get(struct snd_kcontrol *ctl,
		       struct snd_ctl_elem_value *value)
{
	struct oxygen *chip = ctl->private_data;
	struct generic_data *data = chip->model_data;

	value->value.enumerated.item[0] =
		(data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0;
	return 0;
}

static int rolloff_put(struct snd_kcontrol *ctl,
		       struct snd_ctl_elem_value *value)
{
	struct oxygen *chip = ctl->private_data;
	struct generic_data *data = chip->model_data;
	unsigned int i;
	int changed;
	u8 reg;

	mutex_lock(&chip->mutex);
	reg = data->ak4396_regs[0][AK4396_CONTROL_2];
	if (value->value.enumerated.item[0])
		reg |= AK4396_SLOW;
	else
		reg &= ~AK4396_SLOW;
	changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2];
	if (changed) {
		for (i = 0; i < 4; ++i)
			ak4396_write(chip, i, AK4396_CONTROL_2, reg);
	}
	mutex_unlock(&chip->mutex);
	return changed;
}

static const struct snd_kcontrol_new rolloff_control = {
	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
	.name = "DAC Filter Playback Enum",
	.info = rolloff_info,
	.get = rolloff_get,
	.put = rolloff_put,
};

static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
{
	static const char *const names[2] = {
		"None", "High-pass Filter"
	};

	info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	info->count = 1;
	info->value.enumerated.items = 2;
	if (info->value.enumerated.item >= 2)
		info->value.enumerated.item = 1;
	strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
	return 0;
}

static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
{
	struct oxygen *chip = ctl->private_data;
	struct generic_data *data = chip->model_data;

	value->value.enumerated.item[0] =
		(data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0;
	return 0;
}

static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
{
	struct oxygen *chip = ctl->private_data;
	struct generic_data *data = chip->model_data;
	unsigned int reg;
	int changed;

	mutex_lock(&chip->mutex);
	reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL);
	if (value->value.enumerated.item[0])
		reg |= WM8785_HPFR | WM8785_HPFL;
	changed = reg != data->wm8785_regs[WM8785_R2];
	if (changed)
		wm8785_write(chip, WM8785_R2, reg);
	mutex_unlock(&chip->mutex);
	return changed;
}

static const struct snd_kcontrol_new hpf_control = {
	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
	.name = "ADC Filter Capture Enum",
	.info = hpf_info,
	.get = hpf_get,
	.put = hpf_put,
};

static int generic_mixer_init(struct oxygen *chip)
{
	return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip));
}

static int generic_wm8785_mixer_init(struct oxygen *chip)
{
	int err;

	err = generic_mixer_init(chip);
	if (err < 0)
		return err;
	err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip));
	if (err < 0)
		return err;
	return 0;
}

static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);

static const struct oxygen_model model_generic = {
	.shortname = "C-Media CMI8788",
	.longname = "C-Media Oxygen HD Audio",
	.chip = "CMI8788",
	.init = generic_init,
	.mixer_init = generic_wm8785_mixer_init,
	.cleanup = generic_cleanup,
	.resume = generic_resume,
	.get_i2s_mclk = oxygen_default_i2s_mclk,
	.set_dac_params = set_ak4396_params,
	.set_adc_params = set_wm8785_params,
	.update_dac_volume = update_ak4396_volume,
	.update_dac_mute = update_ak4396_mute,
	.dac_tlv = ak4396_db_scale,
	.model_data_size = sizeof(struct generic_data),
	.device_config = PLAYBACK_0_TO_I2S |
			 PLAYBACK_1_TO_SPDIF |
			 PLAYBACK_2_TO_AC97_1 |
			 CAPTURE_0_FROM_I2S_1 |
			 CAPTURE_1_FROM_SPDIF |
			 CAPTURE_2_FROM_AC97_1,
	.dac_channels = 8,
	.dac_volume_min = 0,
	.dac_volume_max = 255,
	.function_flags = OXYGEN_FUNCTION_SPI |
			  OXYGEN_FUNCTION_ENABLE_SPI_4_5,
	.dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
	.adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
};

static int __devinit get_oxygen_model(struct oxygen *chip,
				      const struct pci_device_id *id)
{
	chip->model = model_generic;
	switch (id->driver_data) {
	case MODEL_MERIDIAN:
		chip->model.init = meridian_init;
		chip->model.mixer_init = generic_mixer_init;
		chip->model.resume = meridian_resume;
		chip->model.set_adc_params = set_ak5385_params;
		chip->model.device_config = PLAYBACK_0_TO_I2S |
					    PLAYBACK_1_TO_SPDIF |
					    CAPTURE_0_FROM_I2S_2 |
					    CAPTURE_1_FROM_SPDIF;
		break;
	case MODEL_CLARO:
		chip->model.init = claro_init;
		chip->model.cleanup = claro_cleanup;
		chip->model.suspend = claro_suspend;
		chip->model.resume = claro_resume;
		break;
	case MODEL_CLARO_HALO:
		chip->model.init = claro_halo_init;
		chip->model.mixer_init = generic_mixer_init;
		chip->model.cleanup = claro_cleanup;
		chip->model.suspend = claro_suspend;
		chip->model.resume = claro_resume;
		chip->model.set_adc_params = set_ak5385_params;
		chip->model.device_config = PLAYBACK_0_TO_I2S |
					    PLAYBACK_1_TO_SPDIF |
					    CAPTURE_0_FROM_I2S_2 |
					    CAPTURE_1_FROM_SPDIF;
		break;
	}
	if (id->driver_data == MODEL_MERIDIAN ||
	    id->driver_data == MODEL_CLARO_HALO) {
		chip->model.misc_flags = OXYGEN_MISC_MIDI;
		chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT;
	}
	return 0;
}

static int __devinit generic_oxygen_probe(struct pci_dev *pci,
					  const struct pci_device_id *pci_id)
{
	static int dev;
	int err;

	if (dev >= SNDRV_CARDS)
		return -ENODEV;
	if (!enable[dev]) {
		++dev;
		return -ENOENT;
	}
	err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE,
			       oxygen_ids, get_oxygen_model);
	if (err >= 0)
		++dev;
	return err;
}

static struct pci_driver oxygen_driver = {
	.name = "CMI8788",
	.id_table = oxygen_ids,
	.probe = generic_oxygen_probe,
	.remove = __devexit_p(oxygen_pci_remove),
#ifdef CONFIG_PM
	.suspend = oxygen_pci_suspend,
	.resume = oxygen_pci_resume,
#endif
};

static int __init alsa_card_oxygen_init(void)
{
	return pci_register_driver(&oxygen_driver);
}

static void __exit alsa_card_oxygen_exit(void)
{
	pci_unregister_driver(&oxygen_driver);
}

module_init(alsa_card_oxygen_init)
module_exit(alsa_card_oxygen_exit)
Commit	Line	Data
d0ce9946	1	/*
873591db	2	* C-Media CMI8788 driver for C-Media's reference design and similar models
d0ce9946 CL	3	*
	4	* Copyright (c) Clemens Ladisch <clemens@ladisch.de>
	5	*
	6	*
	7	* This driver is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License, version 2.
	9	*
	10	* This driver is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this driver; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	/*
dc0adf48 CL	21	* CMI8788:
dc0adf48 CL	22	*
d0ce9946	23	* SPI 0 -> 1st AK4396 (front)
7113e958	24	* SPI 1 -> 2nd AK4396 (surround)
d0ce9946 CL	25	* SPI 2 -> 3rd AK4396 (center/LFE)
d0ce9946 CL	26	* SPI 3 -> WM8785
7113e958	27	* SPI 4 -> 4th AK4396 (back)
d0ce9946 CL	28	*
	29	* GPIO 0 -> DFS0 of AK5385
	30	* GPIO 1 -> DFS1 of AK5385
873591db	31	* GPIO 8 -> enable headphone amplifier on HT-Omega models
dc0adf48 CL	32	*
	33	* CM9780:
	34	*
	35	* GPO 0 -> route line-in (0) or AC97 output (1) to ADC input
d0ce9946 CL	36	*/
d0ce9946 CL	37
df91bc23	38	#include <linux/delay.h>
902b05c1	39	#include <linux/mutex.h>
d0ce9946	40	#include <linux/pci.h>
902b05c1	41	#include <sound/ac97_codec.h>
ccc80fb4	42	#include <sound/control.h>
d0ce9946 CL	43	#include <sound/core.h>
	44	#include <sound/initval.h>
	45	#include <sound/pcm.h>
	46	#include <sound/pcm_params.h>
	47	#include <sound/tlv.h>
	48	#include "oxygen.h"
c626026d	49	#include "ak4396.h"
f5b2368b	50	#include "wm8785.h"
d0ce9946 CL	51
	52	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	53	MODULE_DESCRIPTION("C-Media CMI8788 driver");
d023dc0a	54	MODULE_LICENSE("GPL v2");
d0ce9946 CL	55	MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8788}}");
	56
	57	static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
	58	static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
	59	static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
	60
	61	module_param_array(index, int, NULL, 0444);
	62	MODULE_PARM_DESC(index, "card index");
	63	module_param_array(id, charp, NULL, 0444);
	64	MODULE_PARM_DESC(id, "ID string");
	65	module_param_array(enable, bool, NULL, 0444);
	66	MODULE_PARM_DESC(enable, "enable card");
	67
2f1b0ec7 CL	68	enum {
	69	MODEL_CMEDIA_REF, /* C-Media's reference design */
	70	MODEL_MERIDIAN, /* AuzenTech X-Meridian */
873591db CL	71	MODEL_CLARO, /* HT-Omega Claro */
873591db CL	72	MODEL_CLARO_HALO, /* HT-Omega Claro halo */
2f1b0ec7 CL	73	};
2f1b0ec7 CL	74
cebe41d4	75	static DEFINE_PCI_DEVICE_TABLE(oxygen_ids) = {
2f1b0ec7 CL	76	{ OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF },
	77	{ OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF },
	78	{ OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF },
	79	{ OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF },
	80	{ OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF },
	81	{ OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF },
	82	{ OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF },
	83	{ OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF },
	84	{ OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN },
873591db CL	85	{ OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO },
873591db CL	86	{ OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO },
d0ce9946 CL	87	{ }
	88	};
	89	MODULE_DEVICE_TABLE(pci, oxygen_ids);
	90
878ac3ee CL	91
	92	#define GPIO_AK5385_DFS_MASK 0x0003
	93	#define GPIO_AK5385_DFS_NORMAL 0x0000
	94	#define GPIO_AK5385_DFS_DOUBLE 0x0001
	95	#define GPIO_AK5385_DFS_QUAD 0x0002
	96
873591db CL	97	#define GPIO_CLARO_HP 0x0100
873591db CL	98
7ef37cd9	99	struct generic_data {
6f0de3ce	100	u8 ak4396_regs[4][5];
1ff04886	101	u16 wm8785_regs[3];
7ef37cd9 CL	102	};
7ef37cd9 CL	103
d0ce9946 CL	104	static void ak4396_write(struct oxygen *chip, unsigned int codec,
	105	u8 reg, u8 value)
	106	{
	107	/* maps ALSA channel pair number to SPI output */
	108	static const u8 codec_spi_map[4] = {
7113e958	109	0, 1, 2, 4
d0ce9946	110	};
6f0de3ce CL	111	struct generic_data *data = chip->model_data;
6f0de3ce CL	112
c2353a08	113	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER \|
d0ce9946	114	OXYGEN_SPI_DATA_LENGTH_2 \|
2ea85986	115	OXYGEN_SPI_CLOCK_160 \|
d0ce9946	116	(codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) \|
c2353a08	117	OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
d0ce9946	118	AK4396_WRITE \| (reg << 8) \| value);
6f0de3ce CL	119	data->ak4396_regs[codec][reg] = value;
	120	}
	121
	122	static void ak4396_write_cached(struct oxygen *chip, unsigned int codec,
	123	u8 reg, u8 value)
	124	{
	125	struct generic_data *data = chip->model_data;
	126
	127	if (value != data->ak4396_regs[codec][reg])
	128	ak4396_write(chip, codec, reg, value);
d0ce9946 CL	129	}
	130
	131	static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
	132	{
e58aee95 CL	133	struct generic_data *data = chip->model_data;
e58aee95 CL	134
c2353a08	135	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER \|
d0ce9946	136	OXYGEN_SPI_DATA_LENGTH_2 \|
2ea85986	137	OXYGEN_SPI_CLOCK_160 \|
c2353a08 CL	138	(3 << OXYGEN_SPI_CODEC_SHIFT) \|
c2353a08 CL	139	OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
d0ce9946	140	(reg << 9) \| value);
6f0de3ce CL	141	if (reg < ARRAY_SIZE(data->wm8785_regs))
6f0de3ce CL	142	data->wm8785_regs[reg] = value;
bbbfb552 CL	143	}
bbbfb552 CL	144
75146fc0	145	static void ak4396_registers_init(struct oxygen *chip)
d0ce9946	146	{
7ef37cd9	147	struct generic_data *data = chip->model_data;
d0ce9946 CL	148	unsigned int i;
d0ce9946 CL	149
d0ce9946	150	for (i = 0; i < 4; ++i) {
6f0de3ce CL	151	ak4396_write(chip, i, AK4396_CONTROL_1,
	152	AK4396_DIF_24_MSB \| AK4396_RSTN);
	153	ak4396_write(chip, i, AK4396_CONTROL_2,
	154	data->ak4396_regs[0][AK4396_CONTROL_2]);
	155	ak4396_write(chip, i, AK4396_CONTROL_3,
	156	AK4396_PCM);
	157	ak4396_write(chip, i, AK4396_LCH_ATT,
	158	chip->dac_volume[i * 2]);
	159	ak4396_write(chip, i, AK4396_RCH_ATT,
	160	chip->dac_volume[i * 2 + 1]);
d0ce9946	161	}
75146fc0 CL	162	}
	163
	164	static void ak4396_init(struct oxygen *chip)
	165	{
	166	struct generic_data *data = chip->model_data;
	167
6f0de3ce CL	168	data->ak4396_regs[0][AK4396_CONTROL_2] =
6f0de3ce CL	169	AK4396_SMUTE \| AK4396_DEM_OFF \| AK4396_DFS_NORMAL;
75146fc0	170	ak4396_registers_init(chip);
d0ce9946 CL	171	snd_component_add(chip->card, "AK4396");
	172	}
	173
	174	static void ak5385_init(struct oxygen *chip)
	175	{
878ac3ee CL	176	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK);
878ac3ee CL	177	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK);
d0ce9946 CL	178	snd_component_add(chip->card, "AK5385");
	179	}
	180
75146fc0	181	static void wm8785_registers_init(struct oxygen *chip)
d0ce9946	182	{
e58aee95 CL	183	struct generic_data *data = chip->model_data;
e58aee95 CL	184
878ac3ee	185	wm8785_write(chip, WM8785_R7, 0);
6f0de3ce	186	wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]);
1ff04886	187	wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
75146fc0	188	}
e58aee95	189
75146fc0 CL	190	static void wm8785_init(struct oxygen *chip)
	191	{
	192	struct generic_data *data = chip->model_data;
	193
6f0de3ce CL	194	data->wm8785_regs[0] =
6f0de3ce CL	195	WM8785_MCR_SLAVE \| WM8785_OSR_SINGLE \| WM8785_FORMAT_LJUST;
1ff04886	196	data->wm8785_regs[2] = WM8785_HPFR \| WM8785_HPFL;
75146fc0	197	wm8785_registers_init(chip);
d0ce9946 CL	198	snd_component_add(chip->card, "WM8785");
	199	}
	200
	201	static void generic_init(struct oxygen *chip)
	202	{
	203	ak4396_init(chip);
	204	wm8785_init(chip);
	205	}
	206
	207	static void meridian_init(struct oxygen *chip)
	208	{
	209	ak4396_init(chip);
	210	ak5385_init(chip);
	211	}
	212
873591db CL	213	static void claro_enable_hp(struct oxygen *chip)
	214	{
	215	msleep(300);
	216	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP);
	217	oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
	218	}
	219
	220	static void claro_init(struct oxygen *chip)
	221	{
	222	ak4396_init(chip);
	223	wm8785_init(chip);
	224	claro_enable_hp(chip);
	225	}
	226
	227	static void claro_halo_init(struct oxygen *chip)
d91b424d CL	228	{
	229	ak4396_init(chip);
	230	ak5385_init(chip);
873591db	231	claro_enable_hp(chip);
d91b424d CL	232	}
d91b424d CL	233
d0ce9946 CL	234	static void generic_cleanup(struct oxygen *chip)
	235	{
	236	}
	237
873591db CL	238	static void claro_disable_hp(struct oxygen *chip)
	239	{
	240	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
	241	}
	242
	243	static void claro_cleanup(struct oxygen *chip)
	244	{
	245	claro_disable_hp(chip);
	246	}
	247
	248	static void claro_suspend(struct oxygen *chip)
	249	{
	250	claro_disable_hp(chip);
	251	}
	252
4a4bc53b CL	253	static void generic_resume(struct oxygen *chip)
	254	{
	255	ak4396_registers_init(chip);
	256	wm8785_registers_init(chip);
	257	}
	258
c2bc4ff5 CL	259	static void meridian_resume(struct oxygen *chip)
	260	{
	261	ak4396_registers_init(chip);
	262	}
	263
873591db	264	static void claro_resume(struct oxygen *chip)
d91b424d CL	265	{
d91b424d CL	266	ak4396_registers_init(chip);
873591db	267	claro_enable_hp(chip);
d91b424d CL	268	}
d91b424d CL	269
d0ce9946 CL	270	static void set_ak4396_params(struct oxygen *chip,
	271	struct snd_pcm_hw_params *params)
	272	{
7ef37cd9	273	struct generic_data *data = chip->model_data;
d0ce9946 CL	274	unsigned int i;
	275	u8 value;
	276
6f0de3ce	277	value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK;
d0ce9946 CL	278	if (params_rate(params) <= 54000)
d0ce9946 CL	279	value \|= AK4396_DFS_NORMAL;
236c4920	280	else if (params_rate(params) <= 108000)
d0ce9946 CL	281	value \|= AK4396_DFS_DOUBLE;
	282	else
	283	value \|= AK4396_DFS_QUAD;
df91bc23 CL	284
	285	msleep(1); /* wait for the new MCLK to become stable */
	286
6f0de3ce CL	287	if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) {
	288	for (i = 0; i < 4; ++i) {
	289	ak4396_write(chip, i, AK4396_CONTROL_1,
	290	AK4396_DIF_24_MSB);
	291	ak4396_write(chip, i, AK4396_CONTROL_2, value);
	292	ak4396_write(chip, i, AK4396_CONTROL_1,
	293	AK4396_DIF_24_MSB \| AK4396_RSTN);
	294	}
	295	}
	296	}
	297
	298	static void update_ak4396_volume(struct oxygen *chip)
	299	{
	300	unsigned int i;
	301
d0ce9946	302	for (i = 0; i < 4; ++i) {
6f0de3ce CL	303	ak4396_write_cached(chip, i, AK4396_LCH_ATT,
	304	chip->dac_volume[i * 2]);
	305	ak4396_write_cached(chip, i, AK4396_RCH_ATT,
	306	chip->dac_volume[i * 2 + 1]);
d0ce9946 CL	307	}
	308	}
	309
d0ce9946 CL	310	static void update_ak4396_mute(struct oxygen *chip)
d0ce9946 CL	311	{
7ef37cd9	312	struct generic_data *data = chip->model_data;
d0ce9946 CL	313	unsigned int i;
	314	u8 value;
	315
6f0de3ce	316	value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE;
d0ce9946 CL	317	if (chip->dac_mute)
	318	value \|= AK4396_SMUTE;
	319	for (i = 0; i < 4; ++i)
6f0de3ce	320	ak4396_write_cached(chip, i, AK4396_CONTROL_2, value);
d0ce9946 CL	321	}
	322
	323	static void set_wm8785_params(struct oxygen *chip,
	324	struct snd_pcm_hw_params *params)
	325	{
6f0de3ce	326	struct generic_data *data = chip->model_data;
d0ce9946 CL	327	unsigned int value;
d0ce9946 CL	328
878ac3ee	329	value = WM8785_MCR_SLAVE \| WM8785_FORMAT_LJUST;
71e22a4b CL	330	if (params_rate(params) <= 48000)
	331	value \|= WM8785_OSR_SINGLE;
	332	else if (params_rate(params) <= 96000)
d0ce9946	333	value \|= WM8785_OSR_DOUBLE;
d0ce9946	334	else
71e22a4b	335	value \|= WM8785_OSR_QUAD;
6f0de3ce CL	336	if (value != data->wm8785_regs[0]) {
	337	wm8785_write(chip, WM8785_R7, 0);
	338	wm8785_write(chip, WM8785_R0, value);
1ff04886	339	wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
6f0de3ce	340	}
d0ce9946 CL	341	}
	342
	343	static void set_ak5385_params(struct oxygen *chip,
	344	struct snd_pcm_hw_params *params)
	345	{
	346	unsigned int value;
	347
	348	if (params_rate(params) <= 54000)
878ac3ee	349	value = GPIO_AK5385_DFS_NORMAL;
d0ce9946	350	else if (params_rate(params) <= 108000)
878ac3ee	351	value = GPIO_AK5385_DFS_DOUBLE;
d0ce9946	352	else
878ac3ee CL	353	value = GPIO_AK5385_DFS_QUAD;
	354	oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
	355	value, GPIO_AK5385_DFS_MASK);
d0ce9946 CL	356	}
d0ce9946 CL	357
4852ad02 CL	358	static int rolloff_info(struct snd_kcontrol *ctl,
	359	struct snd_ctl_elem_info *info)
	360	{
	361	static const char *const names[2] = {
	362	"Sharp Roll-off", "Slow Roll-off"
	363	};
	364
	365	info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	366	info->count = 1;
	367	info->value.enumerated.items = 2;
	368	if (info->value.enumerated.item >= 2)
	369	info->value.enumerated.item = 1;
	370	strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
	371	return 0;
	372	}
	373
	374	static int rolloff_get(struct snd_kcontrol *ctl,
	375	struct snd_ctl_elem_value *value)
	376	{
	377	struct oxygen *chip = ctl->private_data;
	378	struct generic_data *data = chip->model_data;
	379
	380	value->value.enumerated.item[0] =
	381	(data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0;
	382	return 0;
	383	}
	384
	385	static int rolloff_put(struct snd_kcontrol *ctl,
	386	struct snd_ctl_elem_value *value)
	387	{
	388	struct oxygen *chip = ctl->private_data;
	389	struct generic_data *data = chip->model_data;
	390	unsigned int i;
	391	int changed;
	392	u8 reg;
	393
	394	mutex_lock(&chip->mutex);
	395	reg = data->ak4396_regs[0][AK4396_CONTROL_2];
	396	if (value->value.enumerated.item[0])
	397	reg \|= AK4396_SLOW;
	398	else
	399	reg &= ~AK4396_SLOW;
	400	changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2];
	401	if (changed) {
	402	for (i = 0; i < 4; ++i)
	403	ak4396_write(chip, i, AK4396_CONTROL_2, reg);
	404	}
	405	mutex_unlock(&chip->mutex);
	406	return changed;
	407	}
	408
	409	static const struct snd_kcontrol_new rolloff_control = {
	410	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
	411	.name = "DAC Filter Playback Enum",
	412	.info = rolloff_info,
	413	.get = rolloff_get,
	414	.put = rolloff_put,
	415	};
	416
1ff04886 CL	417	static int hpf_info(struct snd_kcontrol ctl, struct snd_ctl_elem_info info)
	418	{
	419	static const char *const names[2] = {
	420	"None", "High-pass Filter"
	421	};
	422
	423	info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	424	info->count = 1;
	425	info->value.enumerated.items = 2;
	426	if (info->value.enumerated.item >= 2)
	427	info->value.enumerated.item = 1;
	428	strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
	429	return 0;
	430	}
	431
	432	static int hpf_get(struct snd_kcontrol ctl, struct snd_ctl_elem_value value)
	433	{
	434	struct oxygen *chip = ctl->private_data;
	435	struct generic_data *data = chip->model_data;
	436
	437	value->value.enumerated.item[0] =
	438	(data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0;
	439	return 0;
	440	}
	441
	442	static int hpf_put(struct snd_kcontrol ctl, struct snd_ctl_elem_value value)
	443	{
	444	struct oxygen *chip = ctl->private_data;
	445	struct generic_data *data = chip->model_data;
	446	unsigned int reg;
	447	int changed;
	448
	449	mutex_lock(&chip->mutex);
	450	reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR \| WM8785_HPFL);
	451	if (value->value.enumerated.item[0])
	452	reg \|= WM8785_HPFR \| WM8785_HPFL;
	453	changed = reg != data->wm8785_regs[WM8785_R2];
	454	if (changed)
	455	wm8785_write(chip, WM8785_R2, reg);
	456	mutex_unlock(&chip->mutex);
	457	return changed;
	458	}
	459
	460	static const struct snd_kcontrol_new hpf_control = {
	461	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
	462	.name = "ADC Filter Capture Enum",
	463	.info = hpf_info,
	464	.get = hpf_get,
	465	.put = hpf_put,
	466	};
	467
4852ad02 CL	468	static int generic_mixer_init(struct oxygen *chip)
	469	{
	470	return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip));
	471	}
	472
1ff04886 CL	473	static int generic_wm8785_mixer_init(struct oxygen *chip)
	474	{
	475	int err;
	476
	477	err = generic_mixer_init(chip);
	478	if (err < 0)
	479	return err;
	480	err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip));
	481	if (err < 0)
	482	return err;
	483	return 0;
	484	}
	485
d0ce9946 CL	486	static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
	487
	488	static const struct oxygen_model model_generic = {
	489	.shortname = "C-Media CMI8788",
	490	.longname = "C-Media Oxygen HD Audio",
	491	.chip = "CMI8788",
d0ce9946	492	.init = generic_init,
1ff04886	493	.mixer_init = generic_wm8785_mixer_init,
d0ce9946	494	.cleanup = generic_cleanup,
4a4bc53b	495	.resume = generic_resume,
76ffe1e3	496	.get_i2s_mclk = oxygen_default_i2s_mclk,
d0ce9946 CL	497	.set_dac_params = set_ak4396_params,
	498	.set_adc_params = set_wm8785_params,
	499	.update_dac_volume = update_ak4396_volume,
	500	.update_dac_mute = update_ak4396_mute,
4972a177	501	.dac_tlv = ak4396_db_scale,
7ef37cd9	502	.model_data_size = sizeof(struct generic_data),
d76596b1 CL	503	.device_config = PLAYBACK_0_TO_I2S \|
	504	PLAYBACK_1_TO_SPDIF \|
	505	PLAYBACK_2_TO_AC97_1 \|
	506	CAPTURE_0_FROM_I2S_1 \|
	507	CAPTURE_1_FROM_SPDIF \|
	508	CAPTURE_2_FROM_AC97_1,
976cd627	509	.dac_channels = 8,
193e8138 CL	510	.dac_volume_min = 0,
193e8138 CL	511	.dac_volume_max = 255,
87eedd2f CL	512	.function_flags = OXYGEN_FUNCTION_SPI \|
87eedd2f CL	513	OXYGEN_FUNCTION_ENABLE_SPI_4_5,
05855ba3 CL	514	.dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
05855ba3 CL	515	.adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
d0ce9946	516	};
d0ce9946	517
30459d7b CL	518	static int __devinit get_oxygen_model(struct oxygen *chip,
	519	const struct pci_device_id *id)
	520	{
	521	chip->model = model_generic;
	522	switch (id->driver_data) {
	523	case MODEL_MERIDIAN:
	524	chip->model.init = meridian_init;
1ff04886	525	chip->model.mixer_init = generic_mixer_init;
30459d7b CL	526	chip->model.resume = meridian_resume;
	527	chip->model.set_adc_params = set_ak5385_params;
	528	chip->model.device_config = PLAYBACK_0_TO_I2S \|
	529	PLAYBACK_1_TO_SPDIF \|
	530	CAPTURE_0_FROM_I2S_2 \|
	531	CAPTURE_1_FROM_SPDIF;
	532	break;
873591db CL	533	case MODEL_CLARO:
	534	chip->model.init = claro_init;
	535	chip->model.cleanup = claro_cleanup;
	536	chip->model.suspend = claro_suspend;
	537	chip->model.resume = claro_resume;
	538	break;
	539	case MODEL_CLARO_HALO:
	540	chip->model.init = claro_halo_init;
1ff04886	541	chip->model.mixer_init = generic_mixer_init;
873591db CL	542	chip->model.cleanup = claro_cleanup;
	543	chip->model.suspend = claro_suspend;
	544	chip->model.resume = claro_resume;
d91b424d	545	chip->model.set_adc_params = set_ak5385_params;
0873a5ae ES	546	chip->model.device_config = PLAYBACK_0_TO_I2S \|
	547	PLAYBACK_1_TO_SPDIF \|
	548	CAPTURE_0_FROM_I2S_2 \|
	549	CAPTURE_1_FROM_SPDIF;
d91b424d	550	break;
30459d7b CL	551	}
30459d7b CL	552	if (id->driver_data == MODEL_MERIDIAN \|\|
873591db	553	id->driver_data == MODEL_CLARO_HALO) {
30459d7b CL	554	chip->model.misc_flags = OXYGEN_MISC_MIDI;
	555	chip->model.device_config \|= MIDI_OUTPUT \| MIDI_INPUT;
	556	}
	557	return 0;
	558	}
	559
d0ce9946 CL	560	static int __devinit generic_oxygen_probe(struct pci_dev *pci,
	561	const struct pci_device_id *pci_id)
	562	{
	563	static int dev;
d0ce9946 CL	564	int err;
	565
	566	if (dev >= SNDRV_CARDS)
	567	return -ENODEV;
	568	if (!enable[dev]) {
	569	++dev;
	570	return -ENOENT;
	571	}
bb718588	572	err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE,
30459d7b	573	oxygen_ids, get_oxygen_model);
d0ce9946 CL	574	if (err >= 0)
	575	++dev;
	576	return err;
	577	}
	578
	579	static struct pci_driver oxygen_driver = {
	580	.name = "CMI8788",
	581	.id_table = oxygen_ids,
	582	.probe = generic_oxygen_probe,
	583	.remove = __devexit_p(oxygen_pci_remove),
4a4bc53b CL	584	#ifdef CONFIG_PM
	585	.suspend = oxygen_pci_suspend,
	586	.resume = oxygen_pci_resume,
	587	#endif
d0ce9946 CL	588	};
	589
	590	static int __init alsa_card_oxygen_init(void)
	591	{
	592	return pci_register_driver(&oxygen_driver);
	593	}
	594
	595	static void __exit alsa_card_oxygen_exit(void)
	596	{
	597	pci_unregister_driver(&oxygen_driver);
	598	}
	599
	600	module_init(alsa_card_oxygen_init)
	601	module_exit(alsa_card_oxygen_exit)