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[ALSA] pcxhr - Fix dB level information
[net-next-2.6.git] / sound / pci / hda / patch_sigmatel.c
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2f2f4251
M		 1/*
2 * Universal Interface for Intel High Definition Audio Codec
3 *
4 * HD audio interface patch for SigmaTel STAC92xx
5 *
6 * Copyright (c) 2005 Embedded Alley Solutions, Inc.
403d1944 7 * Matt Porter <mporter@embeddedalley.com>
2f2f4251
M		 8 *
9 * Based on patch_cmedia.c and patch_realtek.c
10 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
11 *
12 * This driver is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This driver is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
27#include <sound/driver.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
32#include <sound/core.h>
c7d4b2fa 33#include <sound/asoundef.h>
2f2f4251
M		 34#include "hda_codec.h"
35#include "hda_local.h"
36
4e55096e
M		 37#define NUM_CONTROL_ALLOC 32
38#define STAC_HP_EVENT 0x37
4e55096e 39
f5fcc13c
TI		 40enum {
41 STAC_REF,
dfe495d0
TI		 42 STAC_9200_DELL_D21,
43 STAC_9200_DELL_D22,
44 STAC_9200_DELL_D23,
45 STAC_9200_DELL_M21,
46 STAC_9200_DELL_M22,
47 STAC_9200_DELL_M23,
48 STAC_9200_DELL_M24,
49 STAC_9200_DELL_M25,
50 STAC_9200_DELL_M26,
51 STAC_9200_DELL_M27,
1194b5b7 52 STAC_9200_GATEWAY,
f5fcc13c
TI		 53 STAC_9200_MODELS
54};
55
56enum {
57 STAC_9205_REF,
dfe495d0 58 STAC_9205_DELL_M42,
ae0a8ed8
TD		 59 STAC_9205_DELL_M43,
60 STAC_9205_DELL_M44,
f5fcc13c
TI		 61 STAC_9205_MODELS
62};
63
8e21c34c
TD		 64enum {
65 STAC_925x_REF,
66 STAC_M2_2,
67 STAC_MA6,
2c11f955 68 STAC_PA6,
8e21c34c
TD		 69 STAC_925x_MODELS
70};
71
f5fcc13c
TI		 72enum {
73 STAC_D945_REF,
74 STAC_D945GTP3,
75 STAC_D945GTP5,
5d5d3bc3
IZ		 76 STAC_INTEL_MAC_V1,
77 STAC_INTEL_MAC_V2,
78 STAC_INTEL_MAC_V3,
79 STAC_INTEL_MAC_V4,
80 STAC_INTEL_MAC_V5,
dfe495d0 81 /* for backward compatibility */
f5fcc13c 82 STAC_MACMINI,
3fc24d85 83 STAC_MACBOOK,
6f0778d8
NB		 84 STAC_MACBOOK_PRO_V1,
85 STAC_MACBOOK_PRO_V2,
f16928fb 86 STAC_IMAC_INTEL,
0dae0f83 87 STAC_IMAC_INTEL_20,
dfe495d0
TI		 88 STAC_922X_DELL_D81,
89 STAC_922X_DELL_D82,
90 STAC_922X_DELL_M81,
91 STAC_922X_DELL_M82,
f5fcc13c
TI		 92 STAC_922X_MODELS
93};
94
95enum {
96 STAC_D965_REF,
97 STAC_D965_3ST,
98 STAC_D965_5ST,
4ff076e5 99 STAC_DELL_3ST,
f5fcc13c
TI		 100 STAC_927X_MODELS
101};
403d1944 102
2f2f4251 103struct sigmatel_spec {
c8b6bf9b 104 struct snd_kcontrol_new *mixers[4];
c7d4b2fa
M		 105 unsigned int num_mixers;
106
403d1944 107 int board_config;
c7d4b2fa 108 unsigned int surr_switch: 1;
403d1944
MP		 109 unsigned int line_switch: 1;
110 unsigned int mic_switch: 1;
3cc08dc6 111 unsigned int alt_switch: 1;
82bc955f 112 unsigned int hp_detect: 1;
62fe78e9 113 unsigned int gpio_mute: 1;
c7d4b2fa 114
8259980e
TI		 115 unsigned int gpio_mask, gpio_data;
116
2f2f4251
M		 117 /* playback */
118 struct hda_multi_out multiout;
3cc08dc6 119 hda_nid_t dac_nids[5];
2f2f4251
M		 120
121 /* capture */
122 hda_nid_t *adc_nids;
2f2f4251 123 unsigned int num_adcs;
dabbed6f
M		 124 hda_nid_t *mux_nids;
125 unsigned int num_muxes;
8b65727b
MP		 126 hda_nid_t *dmic_nids;
127 unsigned int num_dmics;
128 hda_nid_t dmux_nid;
dabbed6f 129 hda_nid_t dig_in_nid;
2f2f4251 130
2f2f4251
M		 131 /* pin widgets */
132 hda_nid_t *pin_nids;
133 unsigned int num_pins;
2f2f4251 134 unsigned int *pin_configs;
11b44bbd 135 unsigned int *bios_pin_configs;
2f2f4251
M		 136
137 /* codec specific stuff */
138 struct hda_verb *init;
c8b6bf9b 139 struct snd_kcontrol_new *mixer;
2f2f4251
M		 140
141 /* capture source */
8b65727b
MP		 142 struct hda_input_mux *dinput_mux;
143 unsigned int cur_dmux;
c7d4b2fa 144 struct hda_input_mux *input_mux;
3cc08dc6 145 unsigned int cur_mux[3];
2f2f4251 146
403d1944
MP		 147 /* i/o switches */
148 unsigned int io_switch[2];
0fb87bb4 149 unsigned int clfe_swap;
5f10c4a9 150 unsigned int aloopback;
2f2f4251 151
c7d4b2fa
M		 152 struct hda_pcm pcm_rec[2]; /* PCM information */
153
154 /* dynamic controls and input_mux */
155 struct auto_pin_cfg autocfg;
156 unsigned int num_kctl_alloc, num_kctl_used;
c8b6bf9b 157 struct snd_kcontrol_new *kctl_alloc;
8b65727b 158 struct hda_input_mux private_dimux;
c7d4b2fa 159 struct hda_input_mux private_imux;
2f2f4251
M		 160};
161
162static hda_nid_t stac9200_adc_nids[1] = {
163 0x03,
164};
165
166static hda_nid_t stac9200_mux_nids[1] = {
167 0x0c,
168};
169
170static hda_nid_t stac9200_dac_nids[1] = {
171 0x02,
172};
173
8e21c34c
TD		 174static hda_nid_t stac925x_adc_nids[1] = {
175 0x03,
176};
177
178static hda_nid_t stac925x_mux_nids[1] = {
179 0x0f,
180};
181
182static hda_nid_t stac925x_dac_nids[1] = {
183 0x02,
184};
185
2c11f955
TD		 186static hda_nid_t stac925x_dmic_nids[1] = {
187 0x15,
188};
189
2f2f4251
M		 190static hda_nid_t stac922x_adc_nids[2] = {
191 0x06, 0x07,
192};
193
194static hda_nid_t stac922x_mux_nids[2] = {
195 0x12, 0x13,
196};
197
3cc08dc6
MP		 198static hda_nid_t stac927x_adc_nids[3] = {
199 0x07, 0x08, 0x09
200};
201
202static hda_nid_t stac927x_mux_nids[3] = {
203 0x15, 0x16, 0x17
204};
205
f3302a59
MP		 206static hda_nid_t stac9205_adc_nids[2] = {
207 0x12, 0x13
208};
209
210static hda_nid_t stac9205_mux_nids[2] = {
211 0x19, 0x1a
212};
213
2549413e
TI		 214static hda_nid_t stac9205_dmic_nids[2] = {
215 0x17, 0x18,
8b65727b
MP		 216};
217
c7d4b2fa 218static hda_nid_t stac9200_pin_nids[8] = {
93ed1503
TD		 219 0x08, 0x09, 0x0d, 0x0e,
220 0x0f, 0x10, 0x11, 0x12,
2f2f4251
M		 221};
222
8e21c34c
TD		 223static hda_nid_t stac925x_pin_nids[8] = {
224 0x07, 0x08, 0x0a, 0x0b,
225 0x0c, 0x0d, 0x10, 0x11,
226};
227
2f2f4251
M		 228static hda_nid_t stac922x_pin_nids[10] = {
229 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
230 0x0f, 0x10, 0x11, 0x15, 0x1b,
231};
232
3cc08dc6
MP		 233static hda_nid_t stac927x_pin_nids[14] = {
234 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
235 0x0f, 0x10, 0x11, 0x12, 0x13,
236 0x14, 0x21, 0x22, 0x23,
237};
238
f3302a59
MP		 239static hda_nid_t stac9205_pin_nids[12] = {
240 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
241 0x0f, 0x14, 0x16, 0x17, 0x18,
242 0x21, 0x22,
f3302a59
MP		 243};
244
8b65727b
MP		 245static int stac92xx_dmux_enum_info(struct snd_kcontrol *kcontrol,
246 struct snd_ctl_elem_info *uinfo)
247{
248 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
249 struct sigmatel_spec *spec = codec->spec;
250 return snd_hda_input_mux_info(spec->dinput_mux, uinfo);
251}
252
253static int stac92xx_dmux_enum_get(struct snd_kcontrol *kcontrol,
254 struct snd_ctl_elem_value *ucontrol)
255{
256 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
257 struct sigmatel_spec *spec = codec->spec;
258
259 ucontrol->value.enumerated.item[0] = spec->cur_dmux;
260 return 0;
261}
262
263static int stac92xx_dmux_enum_put(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_value *ucontrol)
265{
266 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
267 struct sigmatel_spec *spec = codec->spec;
268
269 return snd_hda_input_mux_put(codec, spec->dinput_mux, ucontrol,
270 spec->dmux_nid, &spec->cur_dmux);
271}
272
c8b6bf9b 273static int stac92xx_mux_enum_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2f2f4251
M		 274{
275 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
276 struct sigmatel_spec *spec = codec->spec;
c7d4b2fa 277 return snd_hda_input_mux_info(spec->input_mux, uinfo);
2f2f4251
M		 278}
279
c8b6bf9b 280static int stac92xx_mux_enum_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2f2f4251
M		 281{
282 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
283 struct sigmatel_spec *spec = codec->spec;
284 unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
285
286 ucontrol->value.enumerated.item[0] = spec->cur_mux[adc_idx];
287 return 0;
288}
289
c8b6bf9b 290static int stac92xx_mux_enum_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2f2f4251
M		 291{
292 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
293 struct sigmatel_spec *spec = codec->spec;
294 unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
295
c7d4b2fa 296 return snd_hda_input_mux_put(codec, spec->input_mux, ucontrol,
2f2f4251
M		 297 spec->mux_nids[adc_idx], &spec->cur_mux[adc_idx]);
298}
299
5f10c4a9
ML		 300#define stac92xx_aloopback_info snd_ctl_boolean_mono_info
301
302static int stac92xx_aloopback_get(struct snd_kcontrol *kcontrol,
303 struct snd_ctl_elem_value *ucontrol)
304{
305 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
306 struct sigmatel_spec *spec = codec->spec;
307
308 ucontrol->value.integer.value[0] = spec->aloopback;
309 return 0;
310}
311
312static int stac92xx_aloopback_put(struct snd_kcontrol *kcontrol,
313 struct snd_ctl_elem_value *ucontrol)
314{
315 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
316 struct sigmatel_spec *spec = codec->spec;
317 unsigned int dac_mode;
318
319 if (spec->aloopback == ucontrol->value.integer.value[0])
320 return 0;
321
322 spec->aloopback = ucontrol->value.integer.value[0];
323
324
325 dac_mode = snd_hda_codec_read(codec, codec->afg, 0,
326 kcontrol->private_value & 0xFFFF, 0x0);
327
328 if (spec->aloopback) {
329 snd_hda_power_up(codec);
330 dac_mode |= 0x40;
331 } else {
332 snd_hda_power_down(codec);
333 dac_mode &= ~0x40;
334 }
335
336 snd_hda_codec_write_cache(codec, codec->afg, 0,
337 kcontrol->private_value >> 16, dac_mode);
338
339 return 1;
340}
341
6e6b88ff
ML		 342static int stac92xx_volknob_info(struct snd_kcontrol *kcontrol,
343 struct snd_ctl_elem_info *uinfo)
344{
345 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
346 uinfo->count = 1;
347 uinfo->value.integer.min = 0;
348 uinfo->value.integer.max = 127;
349 return 0;
350}
351
352static int stac92xx_volknob_get(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
354{
355 ucontrol->value.integer.value[0] = kcontrol->private_value;
356 return 0;
357}
358
359static int stac92xx_volknob_put(struct snd_kcontrol *kcontrol,
360 struct snd_ctl_elem_value *ucontrol)
361{
362 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
363
364 if (kcontrol->private_value == ucontrol->value.integer.value[0])
365 return 0;
366
367 kcontrol->private_value = ucontrol->value.integer.value[0];
368
369 snd_hda_codec_write_cache(codec, 0x24, 0,
370 AC_VERB_SET_VOLUME_KNOB_CONTROL,
371 kcontrol->private_value | 0x80);
372 return 1;
373}
374
5f10c4a9 375
c7d4b2fa 376static struct hda_verb stac9200_core_init[] = {
2f2f4251 377 /* set dac0mux for dac converter */
c7d4b2fa 378 { 0x07, AC_VERB_SET_CONNECT_SEL, 0x00},
2f2f4251
M		 379 {}
380};
381
1194b5b7
TI		 382static struct hda_verb stac9200_eapd_init[] = {
383 /* set dac0mux for dac converter */
384 {0x07, AC_VERB_SET_CONNECT_SEL, 0x00},
385 {0x08, AC_VERB_SET_EAPD_BTLENABLE, 0x02},
386 {}
387};
388
8e21c34c
TD		 389static struct hda_verb stac925x_core_init[] = {
390 /* set dac0mux for dac converter */
391 { 0x06, AC_VERB_SET_CONNECT_SEL, 0x00},
392 {}
393};
394
c7d4b2fa 395static struct hda_verb stac922x_core_init[] = {
2f2f4251 396 /* set master volume and direct control */
c7d4b2fa 397 { 0x16, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
2f2f4251
M		 398 {}
399};
400
93ed1503 401static struct hda_verb d965_core_init[] = {
19039bd0 402 /* set master volume and direct control */
93ed1503 403 { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
19039bd0
TI		 404 /* unmute node 0x1b */
405 { 0x1b, AC_VERB_SET_AMP_GAIN_MUTE, 0xb000},
406 /* select node 0x03 as DAC */
407 { 0x0b, AC_VERB_SET_CONNECT_SEL, 0x01},
408 {}
409};
410
3cc08dc6
MP		 411static struct hda_verb stac927x_core_init[] = {
412 /* set master volume and direct control */
413 { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
414 {}
415};
416
f3302a59
MP		 417static struct hda_verb stac9205_core_init[] = {
418 /* set master volume and direct control */
419 { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
420 {}
421};
422
9e05b7a3 423#define STAC_INPUT_SOURCE(cnt) \
ca7c5a8b
ML		 424 { \
425 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
426 .name = "Input Source", \
9e05b7a3 427 .count = cnt, \
ca7c5a8b
ML		 428 .info = stac92xx_mux_enum_info, \
429 .get = stac92xx_mux_enum_get, \
430 .put = stac92xx_mux_enum_put, \
431 }
432
5f10c4a9
ML		 433#define STAC_ANALOG_LOOPBACK(verb_read,verb_write) \
434 { \
435 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
436 .name = "Analog Loopback", \
437 .count = 1, \
438 .info = stac92xx_aloopback_info, \
439 .get = stac92xx_aloopback_get, \
440 .put = stac92xx_aloopback_put, \
441 .private_value = verb_read | (verb_write << 16), \
442 }
443
6e6b88ff
ML		 444#define STAC_VOLKNOB \
445 { \
446 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
447 .name = "Master Playback Volume", \
448 .count = 1, \
449 .info = stac92xx_volknob_info, \
450 .get = stac92xx_volknob_get, \
451 .put = stac92xx_volknob_put, \
452 .private_value = 127, \
453 }
454
ca7c5a8b 455
c8b6bf9b 456static struct snd_kcontrol_new stac9200_mixer[] = {
2f2f4251
M		 457 HDA_CODEC_VOLUME("Master Playback Volume", 0xb, 0, HDA_OUTPUT),
458 HDA_CODEC_MUTE("Master Playback Switch", 0xb, 0, HDA_OUTPUT),
9e05b7a3 459 STAC_INPUT_SOURCE(1),
2f2f4251
M		 460 HDA_CODEC_VOLUME("Capture Volume", 0x0a, 0, HDA_OUTPUT),
461 HDA_CODEC_MUTE("Capture Switch", 0x0a, 0, HDA_OUTPUT),
c7d4b2fa 462 HDA_CODEC_VOLUME("Capture Mux Volume", 0x0c, 0, HDA_OUTPUT),
2f2f4251
M		 463 { } /* end */
464};
465
8e21c34c 466static struct snd_kcontrol_new stac925x_mixer[] = {
9e05b7a3 467 STAC_INPUT_SOURCE(1),
8e21c34c
TD		 468 HDA_CODEC_VOLUME("Capture Volume", 0x09, 0, HDA_OUTPUT),
469 HDA_CODEC_MUTE("Capture Switch", 0x09, 0, HDA_OUTPUT),
470 HDA_CODEC_VOLUME("Capture Mux Volume", 0x0f, 0, HDA_OUTPUT),
471 { } /* end */
472};
473
9e05b7a3
ML		 474static struct snd_kcontrol_new stac9205_mixer[] = {
475 {
476 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
477 .name = "Digital Input Source",
478 .count = 1,
479 .info = stac92xx_dmux_enum_info,
480 .get = stac92xx_dmux_enum_get,
481 .put = stac92xx_dmux_enum_put,
482 },
483 STAC_INPUT_SOURCE(2),
484 STAC_ANALOG_LOOPBACK(0xFE0, 0x7E0),
6e6b88ff 485 STAC_VOLKNOB,
9e05b7a3
ML		 486
487 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x1b, 0x0, HDA_INPUT),
488 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1d, 0x0, HDA_OUTPUT),
489 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x0, 0x19, 0x0, HDA_OUTPUT),
490
491 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x1c, 0x0, HDA_INPUT),
492 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1e, 0x0, HDA_OUTPUT),
493 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x1, 0x1A, 0x0, HDA_OUTPUT),
494
2f2f4251
M		 495 { } /* end */
496};
497
19039bd0 498/* This needs to be generated dynamically based on sequence */
9e05b7a3
ML		 499static struct snd_kcontrol_new stac922x_mixer[] = {
500 STAC_INPUT_SOURCE(2),
6e6b88ff 501 STAC_VOLKNOB,
9e05b7a3
ML		 502 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x17, 0x0, HDA_INPUT),
503 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x17, 0x0, HDA_INPUT),
504 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x0, 0x12, 0x0, HDA_OUTPUT),
505
506 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x18, 0x0, HDA_INPUT),
507 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x18, 0x0, HDA_INPUT),
508 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x1, 0x13, 0x0, HDA_OUTPUT),
19039bd0
TI		 509 { } /* end */
510};
511
9e05b7a3 512
d1d985f0 513static struct snd_kcontrol_new stac927x_mixer[] = {
9e05b7a3 514 STAC_INPUT_SOURCE(3),
6e6b88ff 515 STAC_VOLKNOB,
5f10c4a9 516 STAC_ANALOG_LOOPBACK(0xFEB, 0x7EB),
3cc08dc6 517
9e05b7a3
ML		 518 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x18, 0x0, HDA_INPUT),
519 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1b, 0x0, HDA_OUTPUT),
520 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x0, 0x15, 0x0, HDA_OUTPUT),
521
522 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x19, 0x0, HDA_INPUT),
523 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1c, 0x0, HDA_OUTPUT),
524 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x1, 0x16, 0x0, HDA_OUTPUT),
525
526 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x2, 0x1A, 0x0, HDA_INPUT),
527 HDA_CODEC_MUTE_IDX("Capture Switch", 0x2, 0x1d, 0x0, HDA_OUTPUT),
528 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x2, 0x17, 0x0, HDA_OUTPUT),
f3302a59
MP		 529 { } /* end */
530};
531
2f2f4251
M		 532static int stac92xx_build_controls(struct hda_codec *codec)
533{
534 struct sigmatel_spec *spec = codec->spec;
535 int err;
c7d4b2fa 536 int i;
2f2f4251
M		 537
538 err = snd_hda_add_new_ctls(codec, spec->mixer);
539 if (err < 0)
540 return err;
c7d4b2fa
M		 541
542 for (i = 0; i < spec->num_mixers; i++) {
543 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
544 if (err < 0)
545 return err;
546 }
547
dabbed6f
M		 548 if (spec->multiout.dig_out_nid) {
549 err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid);
550 if (err < 0)
551 return err;
552 }
553 if (spec->dig_in_nid) {
554 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in_nid);
555 if (err < 0)
556 return err;
557 }
558 return 0;
2f2f4251
M		 559}
560
403d1944 561static unsigned int ref9200_pin_configs[8] = {
dabbed6f 562 0x01c47010, 0x01447010, 0x0221401f, 0x01114010,
2f2f4251
M		 563 0x02a19020, 0x01a19021, 0x90100140, 0x01813122,
564};
565
dfe495d0
TI		 566/*
567 STAC 9200 pin configs for
568 102801A8
569 102801DE
570 102801E8
571*/
572static unsigned int dell9200_d21_pin_configs[8] = {
af6c016e
TI		 573 0x400001f0, 0x400001f1, 0x02214030, 0x01014010,
574 0x02a19020, 0x01a19021, 0x90100140, 0x01813122,
dfe495d0
TI		 575};
576
577/*
578 STAC 9200 pin configs for
579 102801C0
580 102801C1
581*/
582static unsigned int dell9200_d22_pin_configs[8] = {
af6c016e
TI		 583 0x400001f0, 0x400001f1, 0x0221401f, 0x01014010,
584 0x01813020, 0x02a19021, 0x90100140, 0x400001f2,
dfe495d0
TI		 585};
586
587/*
588 STAC 9200 pin configs for
589 102801C4 (Dell Dimension E310)
590 102801C5
591 102801C7
592 102801D9
593 102801DA
594 102801E3
595*/
596static unsigned int dell9200_d23_pin_configs[8] = {
af6c016e
TI		 597 0x400001f0, 0x400001f1, 0x0221401f, 0x01014010,
598 0x01813020, 0x01a19021, 0x90100140, 0x400001f2,
dfe495d0
TI		 599};
600
601
602/*
603 STAC 9200-32 pin configs for
604 102801B5 (Dell Inspiron 630m)
605 102801D8 (Dell Inspiron 640m)
606*/
607static unsigned int dell9200_m21_pin_configs[8] = {
af6c016e
TI		 608 0x40c003fa, 0x03441340, 0x0321121f, 0x90170310,
609 0x408003fb, 0x03a11020, 0x401003fc, 0x403003fd,
dfe495d0
TI		 610};
611
612/*
613 STAC 9200-32 pin configs for
614 102801C2 (Dell Latitude D620)
615 102801C8
616 102801CC (Dell Latitude D820)
617 102801D4
618 102801D6
619*/
620static unsigned int dell9200_m22_pin_configs[8] = {
af6c016e
TI		 621 0x40c003fa, 0x0144131f, 0x0321121f, 0x90170310,
622 0x90a70321, 0x03a11020, 0x401003fb, 0x40f000fc,
dfe495d0
TI		 623};
624
625/*
626 STAC 9200-32 pin configs for
627 102801CE (Dell XPS M1710)
628 102801CF (Dell Precision M90)
629*/
630static unsigned int dell9200_m23_pin_configs[8] = {
631 0x40c003fa, 0x01441340, 0x0421421f, 0x90170310,
632 0x408003fb, 0x04a1102e, 0x90170311, 0x403003fc,
633};
634
635/*
636 STAC 9200-32 pin configs for
637 102801C9
638 102801CA
639 102801CB (Dell Latitude 120L)
640 102801D3
641*/
642static unsigned int dell9200_m24_pin_configs[8] = {
af6c016e
TI		 643 0x40c003fa, 0x404003fb, 0x0321121f, 0x90170310,
644 0x408003fc, 0x03a11020, 0x401003fd, 0x403003fe,
dfe495d0
TI		 645};
646
647/*
648 STAC 9200-32 pin configs for
649 102801BD (Dell Inspiron E1505n)
650 102801EE
651 102801EF
652*/
653static unsigned int dell9200_m25_pin_configs[8] = {
af6c016e
TI		 654 0x40c003fa, 0x01441340, 0x0421121f, 0x90170310,
655 0x408003fb, 0x04a11020, 0x401003fc, 0x403003fd,
dfe495d0
TI		 656};
657
658/*
659 STAC 9200-32 pin configs for
660 102801F5 (Dell Inspiron 1501)
661 102801F6
662*/
663static unsigned int dell9200_m26_pin_configs[8] = {
af6c016e
TI		 664 0x40c003fa, 0x404003fb, 0x0421121f, 0x90170310,
665 0x408003fc, 0x04a11020, 0x401003fd, 0x403003fe,
dfe495d0
TI		 666};
667
668/*
669 STAC 9200-32
670 102801CD (Dell Inspiron E1705/9400)
671*/
672static unsigned int dell9200_m27_pin_configs[8] = {
af6c016e
TI		 673 0x40c003fa, 0x01441340, 0x0421121f, 0x90170310,
674 0x90170310, 0x04a11020, 0x90170310, 0x40f003fc,
dfe495d0
TI		 675};
676
677
f5fcc13c
TI		 678static unsigned int *stac9200_brd_tbl[STAC_9200_MODELS] = {
679 [STAC_REF] = ref9200_pin_configs,
dfe495d0
TI		 680 [STAC_9200_DELL_D21] = dell9200_d21_pin_configs,
681 [STAC_9200_DELL_D22] = dell9200_d22_pin_configs,
682 [STAC_9200_DELL_D23] = dell9200_d23_pin_configs,
683 [STAC_9200_DELL_M21] = dell9200_m21_pin_configs,
684 [STAC_9200_DELL_M22] = dell9200_m22_pin_configs,
685 [STAC_9200_DELL_M23] = dell9200_m23_pin_configs,
686 [STAC_9200_DELL_M24] = dell9200_m24_pin_configs,
687 [STAC_9200_DELL_M25] = dell9200_m25_pin_configs,
688 [STAC_9200_DELL_M26] = dell9200_m26_pin_configs,
689 [STAC_9200_DELL_M27] = dell9200_m27_pin_configs,
403d1944
MP		 690};
691
f5fcc13c
TI		 692static const char *stac9200_models[STAC_9200_MODELS] = {
693 [STAC_REF] = "ref",
dfe495d0
TI		 694 [STAC_9200_DELL_D21] = "dell-d21",
695 [STAC_9200_DELL_D22] = "dell-d22",
696 [STAC_9200_DELL_D23] = "dell-d23",
697 [STAC_9200_DELL_M21] = "dell-m21",
698 [STAC_9200_DELL_M22] = "dell-m22",
699 [STAC_9200_DELL_M23] = "dell-m23",
700 [STAC_9200_DELL_M24] = "dell-m24",
701 [STAC_9200_DELL_M25] = "dell-m25",
702 [STAC_9200_DELL_M26] = "dell-m26",
703 [STAC_9200_DELL_M27] = "dell-m27",
1194b5b7 704 [STAC_9200_GATEWAY] = "gateway",
f5fcc13c
TI		 705};
706
707static struct snd_pci_quirk stac9200_cfg_tbl[] = {
708 /* SigmaTel reference board */
709 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
710 "DFI LanParty", STAC_REF),
e7377071 711 /* Dell laptops have BIOS problem */
dfe495d0
TI		 712 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a8,
713 "unknown Dell", STAC_9200_DELL_D21),
f5fcc13c 714 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01b5,
dfe495d0
TI		 715 "Dell Inspiron 630m", STAC_9200_DELL_M21),
716 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01bd,
717 "Dell Inspiron E1505n", STAC_9200_DELL_M25),
718 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c0,
719 "unknown Dell", STAC_9200_DELL_D22),
720 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c1,
721 "unknown Dell", STAC_9200_DELL_D22),
f5fcc13c 722 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c2,
dfe495d0
TI		 723 "Dell Latitude D620", STAC_9200_DELL_M22),
724 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c5,
725 "unknown Dell", STAC_9200_DELL_D23),
726 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c7,
727 "unknown Dell", STAC_9200_DELL_D23),
728 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c8,
729 "unknown Dell", STAC_9200_DELL_M22),
730 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c9,
731 "unknown Dell", STAC_9200_DELL_M24),
732 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ca,
733 "unknown Dell", STAC_9200_DELL_M24),
f5fcc13c 734 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cb,
dfe495d0 735 "Dell Latitude 120L", STAC_9200_DELL_M24),
877b866d 736 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cc,
dfe495d0 737 "Dell Latitude D820", STAC_9200_DELL_M22),
46f02ca3 738 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cd,
dfe495d0 739 "Dell Inspiron E1705/9400", STAC_9200_DELL_M27),
46f02ca3 740 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ce,
dfe495d0 741 "Dell XPS M1710", STAC_9200_DELL_M23),
f0f96745 742 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cf,
dfe495d0
TI		 743 "Dell Precision M90", STAC_9200_DELL_M23),
744 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d3,
745 "unknown Dell", STAC_9200_DELL_M22),
746 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d4,
747 "unknown Dell", STAC_9200_DELL_M22),
8286c53e 748 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d6,
dfe495d0 749 "unknown Dell", STAC_9200_DELL_M22),
49c605db 750 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d8,
dfe495d0
TI		 751 "Dell Inspiron 640m", STAC_9200_DELL_M21),
752 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d9,
753 "unknown Dell", STAC_9200_DELL_D23),
754 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01da,
755 "unknown Dell", STAC_9200_DELL_D23),
756 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01de,
757 "unknown Dell", STAC_9200_DELL_D21),
758 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01e3,
759 "unknown Dell", STAC_9200_DELL_D23),
760 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01e8,
761 "unknown Dell", STAC_9200_DELL_D21),
762 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ee,
763 "unknown Dell", STAC_9200_DELL_M25),
764 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ef,
765 "unknown Dell", STAC_9200_DELL_M25),
49c605db 766 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f5,
dfe495d0
TI		 767 "Dell Inspiron 1501", STAC_9200_DELL_M26),
768 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f6,
769 "unknown Dell", STAC_9200_DELL_M26),
49c605db
TD		 770 /* Panasonic */
771 SND_PCI_QUIRK(0x10f7, 0x8338, "Panasonic CF-74", STAC_REF),
1194b5b7
TI		 772 /* Gateway machines needs EAPD to be set on resume */
773 SND_PCI_QUIRK(0x107b, 0x0205, "Gateway S-7110M", STAC_9200_GATEWAY),
774 SND_PCI_QUIRK(0x107b, 0x0317, "Gateway MT3423, MX341*",
775 STAC_9200_GATEWAY),
776 SND_PCI_QUIRK(0x107b, 0x0318, "Gateway ML3019, MT3707",
777 STAC_9200_GATEWAY),
403d1944
MP		 778 {} /* terminator */
779};
780
8e21c34c
TD		 781static unsigned int ref925x_pin_configs[8] = {
782 0x40c003f0, 0x424503f2, 0x01813022, 0x02a19021,
783 0x90a70320, 0x02214210, 0x400003f1, 0x9033032e,
784};
785
786static unsigned int stac925x_MA6_pin_configs[8] = {
787 0x40c003f0, 0x424503f2, 0x01813022, 0x02a19021,
788 0x90a70320, 0x90100211, 0x400003f1, 0x9033032e,
789};
790
2c11f955
TD		 791static unsigned int stac925x_PA6_pin_configs[8] = {
792 0x40c003f0, 0x424503f2, 0x01813022, 0x02a19021,
793 0x50a103f0, 0x90100211, 0x400003f1, 0x9033032e,
794};
795
8e21c34c 796static unsigned int stac925xM2_2_pin_configs[8] = {
7353e14d
SL		 797 0x40c003f3, 0x424503f2, 0x04180011, 0x02a19020,
798 0x50a103f0, 0x90100212, 0x400003f1, 0x9033032e,
8e21c34c
TD		 799};
800
801static unsigned int *stac925x_brd_tbl[STAC_925x_MODELS] = {
802 [STAC_REF] = ref925x_pin_configs,
803 [STAC_M2_2] = stac925xM2_2_pin_configs,
804 [STAC_MA6] = stac925x_MA6_pin_configs,
2c11f955 805 [STAC_PA6] = stac925x_PA6_pin_configs,
8e21c34c
TD		 806};
807
808static const char *stac925x_models[STAC_925x_MODELS] = {
809 [STAC_REF] = "ref",
810 [STAC_M2_2] = "m2-2",
811 [STAC_MA6] = "m6",
2c11f955 812 [STAC_PA6] = "pa6",
8e21c34c
TD		 813};
814
815static struct snd_pci_quirk stac925x_cfg_tbl[] = {
816 /* SigmaTel reference board */
817 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_REF),
2c11f955 818 SND_PCI_QUIRK(0x8384, 0x7632, "Stac9202 Reference Board", STAC_REF),
8e21c34c
TD		 819 SND_PCI_QUIRK(0x107b, 0x0316, "Gateway M255", STAC_REF),
820 SND_PCI_QUIRK(0x107b, 0x0366, "Gateway MP6954", STAC_REF),
821 SND_PCI_QUIRK(0x107b, 0x0461, "Gateway NX560XL", STAC_MA6),
2c11f955 822 SND_PCI_QUIRK(0x107b, 0x0681, "Gateway NX860", STAC_PA6),
8e21c34c
TD		 823 SND_PCI_QUIRK(0x1002, 0x437b, "Gateway MX6453", STAC_M2_2),
824 {} /* terminator */
825};
826
403d1944
MP		 827static unsigned int ref922x_pin_configs[10] = {
828 0x01014010, 0x01016011, 0x01012012, 0x0221401f,
829 0x01813122, 0x01011014, 0x01441030, 0x01c41030,
2f2f4251
M		 830 0x40000100, 0x40000100,
831};
832
dfe495d0
TI		 833/*
834 STAC 922X pin configs for
835 102801A7
836 102801AB
837 102801A9
838 102801D1
839 102801D2
840*/
841static unsigned int dell_922x_d81_pin_configs[10] = {
842 0x02214030, 0x01a19021, 0x01111012, 0x01114010,
843 0x02a19020, 0x01117011, 0x400001f0, 0x400001f1,
844 0x01813122, 0x400001f2,
845};
846
847/*
848 STAC 922X pin configs for
849 102801AC
850 102801D0
851*/
852static unsigned int dell_922x_d82_pin_configs[10] = {
853 0x02214030, 0x01a19021, 0x01111012, 0x01114010,
854 0x02a19020, 0x01117011, 0x01451140, 0x400001f0,
855 0x01813122, 0x400001f1,
856};
857
858/*
859 STAC 922X pin configs for
860 102801BF
861*/
862static unsigned int dell_922x_m81_pin_configs[10] = {
863 0x0321101f, 0x01112024, 0x01111222, 0x91174220,
864 0x03a11050, 0x01116221, 0x90a70330, 0x01452340,
865 0x40C003f1, 0x405003f0,
866};
867
868/*
869 STAC 9221 A1 pin configs for
870 102801D7 (Dell XPS M1210)
871*/
872static unsigned int dell_922x_m82_pin_configs[10] = {
873 0x0221121f, 0x408103ff, 0x02111212, 0x90100310,
874 0x408003f1, 0x02111211, 0x03451340, 0x40c003f2,
875 0x508003f3, 0x405003f4,
876};
877
403d1944 878static unsigned int d945gtp3_pin_configs[10] = {
869264c4 879 0x0221401f, 0x01a19022, 0x01813021, 0x01014010,
403d1944
MP		 880 0x40000100, 0x40000100, 0x40000100, 0x40000100,
881 0x02a19120, 0x40000100,
882};
883
884static unsigned int d945gtp5_pin_configs[10] = {
869264c4
MP		 885 0x0221401f, 0x01011012, 0x01813024, 0x01014010,
886 0x01a19021, 0x01016011, 0x01452130, 0x40000100,
403d1944
MP		 887 0x02a19320, 0x40000100,
888};
889
5d5d3bc3
IZ		 890static unsigned int intel_mac_v1_pin_configs[10] = {
891 0x0121e21f, 0x400000ff, 0x9017e110, 0x400000fd,
892 0x400000fe, 0x0181e020, 0x1145e030, 0x11c5e240,
893 0x400000fc, 0x400000fb,
894};
895
896static unsigned int intel_mac_v2_pin_configs[10] = {
897 0x0121e21f, 0x90a7012e, 0x9017e110, 0x400000fd,
898 0x400000fe, 0x0181e020, 0x1145e230, 0x500000fa,
899 0x400000fc, 0x400000fb,
6f0778d8
NB		 900};
901
5d5d3bc3
IZ		 902static unsigned int intel_mac_v3_pin_configs[10] = {
903 0x0121e21f, 0x90a7012e, 0x9017e110, 0x400000fd,
904 0x400000fe, 0x0181e020, 0x1145e230, 0x11c5e240,
3fc24d85
TI		 905 0x400000fc, 0x400000fb,
906};
907
5d5d3bc3
IZ		 908static unsigned int intel_mac_v4_pin_configs[10] = {
909 0x0321e21f, 0x03a1e02e, 0x9017e110, 0x9017e11f,
910 0x400000fe, 0x0381e020, 0x1345e230, 0x13c5e240,
f16928fb
SF		 911 0x400000fc, 0x400000fb,
912};
913
5d5d3bc3
IZ		 914static unsigned int intel_mac_v5_pin_configs[10] = {
915 0x0321e21f, 0x03a1e02e, 0x9017e110, 0x9017e11f,
916 0x400000fe, 0x0381e020, 0x1345e230, 0x13c5e240,
917 0x400000fc, 0x400000fb,
0dae0f83
TI		 918};
919
76c08828 920
19039bd0 921static unsigned int *stac922x_brd_tbl[STAC_922X_MODELS] = {
f5fcc13c 922 [STAC_D945_REF] = ref922x_pin_configs,
19039bd0
TI		 923 [STAC_D945GTP3] = d945gtp3_pin_configs,
924 [STAC_D945GTP5] = d945gtp5_pin_configs,
5d5d3bc3
IZ		 925 [STAC_INTEL_MAC_V1] = intel_mac_v1_pin_configs,
926 [STAC_INTEL_MAC_V2] = intel_mac_v2_pin_configs,
927 [STAC_INTEL_MAC_V3] = intel_mac_v3_pin_configs,
928 [STAC_INTEL_MAC_V4] = intel_mac_v4_pin_configs,
929 [STAC_INTEL_MAC_V5] = intel_mac_v5_pin_configs,
dfe495d0 930 /* for backward compatibility */
5d5d3bc3
IZ		 931 [STAC_MACMINI] = intel_mac_v3_pin_configs,
932 [STAC_MACBOOK] = intel_mac_v5_pin_configs,
933 [STAC_MACBOOK_PRO_V1] = intel_mac_v3_pin_configs,
934 [STAC_MACBOOK_PRO_V2] = intel_mac_v3_pin_configs,
935 [STAC_IMAC_INTEL] = intel_mac_v2_pin_configs,
936 [STAC_IMAC_INTEL_20] = intel_mac_v3_pin_configs,
dfe495d0
TI		 937 [STAC_922X_DELL_D81] = dell_922x_d81_pin_configs,
938 [STAC_922X_DELL_D82] = dell_922x_d82_pin_configs,
939 [STAC_922X_DELL_M81] = dell_922x_m81_pin_configs,
940 [STAC_922X_DELL_M82] = dell_922x_m82_pin_configs,
403d1944
MP		 941};
942
f5fcc13c
TI		 943static const char *stac922x_models[STAC_922X_MODELS] = {
944 [STAC_D945_REF] = "ref",
945 [STAC_D945GTP5] = "5stack",
946 [STAC_D945GTP3] = "3stack",
5d5d3bc3
IZ		 947 [STAC_INTEL_MAC_V1] = "intel-mac-v1",
948 [STAC_INTEL_MAC_V2] = "intel-mac-v2",
949 [STAC_INTEL_MAC_V3] = "intel-mac-v3",
950 [STAC_INTEL_MAC_V4] = "intel-mac-v4",
951 [STAC_INTEL_MAC_V5] = "intel-mac-v5",
dfe495d0 952 /* for backward compatibility */
f5fcc13c 953 [STAC_MACMINI] = "macmini",
3fc24d85 954 [STAC_MACBOOK] = "macbook",
6f0778d8
NB		 955 [STAC_MACBOOK_PRO_V1] = "macbook-pro-v1",
956 [STAC_MACBOOK_PRO_V2] = "macbook-pro",
f16928fb 957 [STAC_IMAC_INTEL] = "imac-intel",
0dae0f83 958 [STAC_IMAC_INTEL_20] = "imac-intel-20",
dfe495d0
TI		 959 [STAC_922X_DELL_D81] = "dell-d81",
960 [STAC_922X_DELL_D82] = "dell-d82",
961 [STAC_922X_DELL_M81] = "dell-m81",
962 [STAC_922X_DELL_M82] = "dell-m82",
f5fcc13c
TI		 963};
964
965static struct snd_pci_quirk stac922x_cfg_tbl[] = {
966 /* SigmaTel reference board */
967 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
968 "DFI LanParty", STAC_D945_REF),
969 /* Intel 945G based systems */
970 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0101,
971 "Intel D945G", STAC_D945GTP3),
972 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0202,
973 "Intel D945G", STAC_D945GTP3),
974 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0606,
975 "Intel D945G", STAC_D945GTP3),
976 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0601,
977 "Intel D945G", STAC_D945GTP3),
978 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0111,
979 "Intel D945G", STAC_D945GTP3),
980 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1115,
981 "Intel D945G", STAC_D945GTP3),
982 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1116,
983 "Intel D945G", STAC_D945GTP3),
984 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1117,
985 "Intel D945G", STAC_D945GTP3),
986 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1118,
987 "Intel D945G", STAC_D945GTP3),
988 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1119,
989 "Intel D945G", STAC_D945GTP3),
990 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x8826,
991 "Intel D945G", STAC_D945GTP3),
992 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5049,
993 "Intel D945G", STAC_D945GTP3),
994 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5055,
995 "Intel D945G", STAC_D945GTP3),
996 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5048,
997 "Intel D945G", STAC_D945GTP3),
998 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0110,
999 "Intel D945G", STAC_D945GTP3),
1000 /* Intel D945G 5-stack systems */
1001 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0404,
1002 "Intel D945G", STAC_D945GTP5),
1003 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0303,
1004 "Intel D945G", STAC_D945GTP5),
1005 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0013,
1006 "Intel D945G", STAC_D945GTP5),
1007 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0417,
1008 "Intel D945G", STAC_D945GTP5),
1009 /* Intel 945P based systems */
1010 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0b0b,
1011 "Intel D945P", STAC_D945GTP3),
1012 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0112,
1013 "Intel D945P", STAC_D945GTP3),
1014 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0d0d,
1015 "Intel D945P", STAC_D945GTP3),
1016 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0909,
1017 "Intel D945P", STAC_D945GTP3),
1018 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0505,
1019 "Intel D945P", STAC_D945GTP3),
1020 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0707,
1021 "Intel D945P", STAC_D945GTP5),
1022 /* other systems */
1023 /* Apple Mac Mini (early 2006) */
1024 SND_PCI_QUIRK(0x8384, 0x7680,
5d5d3bc3 1025 "Mac Mini", STAC_INTEL_MAC_V3),
dfe495d0
TI		 1026 /* Dell systems */
1027 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a7,
1028 "unknown Dell", STAC_922X_DELL_D81),
1029 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a9,
1030 "unknown Dell", STAC_922X_DELL_D81),
1031 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ab,
1032 "unknown Dell", STAC_922X_DELL_D81),
1033 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ac,
1034 "unknown Dell", STAC_922X_DELL_D82),
1035 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01bf,
1036 "unknown Dell", STAC_922X_DELL_M81),
1037 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d0,
1038 "unknown Dell", STAC_922X_DELL_D82),
1039 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d1,
1040 "unknown Dell", STAC_922X_DELL_D81),
1041 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d2,
1042 "unknown Dell", STAC_922X_DELL_D81),
1043 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d7,
1044 "Dell XPS M1210", STAC_922X_DELL_M82),
403d1944
MP		 1045 {} /* terminator */
1046};
1047
3cc08dc6 1048static unsigned int ref927x_pin_configs[14] = {
93ed1503
TD		 1049 0x02214020, 0x02a19080, 0x0181304e, 0x01014010,
1050 0x01a19040, 0x01011012, 0x01016011, 0x0101201f,
1051 0x183301f0, 0x18a001f0, 0x18a001f0, 0x01442070,
1052 0x01c42190, 0x40000100,
3cc08dc6
MP		 1053};
1054
93ed1503 1055static unsigned int d965_3st_pin_configs[14] = {
81d3dbde
TD		 1056 0x0221401f, 0x02a19120, 0x40000100, 0x01014011,
1057 0x01a19021, 0x01813024, 0x40000100, 0x40000100,
1058 0x40000100, 0x40000100, 0x40000100, 0x40000100,
1059 0x40000100, 0x40000100
1060};
1061
93ed1503
TD		 1062static unsigned int d965_5st_pin_configs[14] = {
1063 0x02214020, 0x02a19080, 0x0181304e, 0x01014010,
1064 0x01a19040, 0x01011012, 0x01016011, 0x40000100,
1065 0x40000100, 0x40000100, 0x40000100, 0x01442070,
1066 0x40000100, 0x40000100
1067};
1068
4ff076e5
TD		 1069static unsigned int dell_3st_pin_configs[14] = {
1070 0x02211230, 0x02a11220, 0x01a19040, 0x01114210,
1071 0x01111212, 0x01116211, 0x01813050, 0x01112214,
1072 0x403003fa, 0x40000100, 0x40000100, 0x404003fb,
1073 0x40c003fc, 0x40000100
1074};
1075
93ed1503 1076static unsigned int *stac927x_brd_tbl[STAC_927X_MODELS] = {
f5fcc13c 1077 [STAC_D965_REF] = ref927x_pin_configs,
93ed1503
TD		 1078 [STAC_D965_3ST] = d965_3st_pin_configs,
1079 [STAC_D965_5ST] = d965_5st_pin_configs,
4ff076e5 1080 [STAC_DELL_3ST] = dell_3st_pin_configs,
3cc08dc6
MP		 1081};
1082
f5fcc13c
TI		 1083static const char *stac927x_models[STAC_927X_MODELS] = {
1084 [STAC_D965_REF] = "ref",
1085 [STAC_D965_3ST] = "3stack",
1086 [STAC_D965_5ST] = "5stack",
4ff076e5 1087 [STAC_DELL_3ST] = "dell-3stack",
f5fcc13c
TI		 1088};
1089
1090static struct snd_pci_quirk stac927x_cfg_tbl[] = {
1091 /* SigmaTel reference board */
1092 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1093 "DFI LanParty", STAC_D965_REF),
81d3dbde 1094 /* Intel 946 based systems */
f5fcc13c
TI		 1095 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x3d01, "Intel D946", STAC_D965_3ST),
1096 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0xa301, "Intel D946", STAC_D965_3ST),
93ed1503 1097 /* 965 based 3 stack systems */
f5fcc13c
TI		 1098 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2116, "Intel D965", STAC_D965_3ST),
1099 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2115, "Intel D965", STAC_D965_3ST),
1100 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2114, "Intel D965", STAC_D965_3ST),
1101 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2113, "Intel D965", STAC_D965_3ST),
1102 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2112, "Intel D965", STAC_D965_3ST),
1103 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2111, "Intel D965", STAC_D965_3ST),
1104 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2110, "Intel D965", STAC_D965_3ST),
1105 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2009, "Intel D965", STAC_D965_3ST),
1106 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2008, "Intel D965", STAC_D965_3ST),
1107 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2007, "Intel D965", STAC_D965_3ST),
1108 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2006, "Intel D965", STAC_D965_3ST),
1109 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2005, "Intel D965", STAC_D965_3ST),
1110 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2004, "Intel D965", STAC_D965_3ST),
1111 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2003, "Intel D965", STAC_D965_3ST),
1112 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2002, "Intel D965", STAC_D965_3ST),
1113 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2001, "Intel D965", STAC_D965_3ST),
4ff076e5 1114 /* Dell 3 stack systems */
dfe495d0 1115 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01dd, "Dell Dimension E520", STAC_DELL_3ST),
4ff076e5
TD		 1116 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ed, "Dell ", STAC_DELL_3ST),
1117 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f4, "Dell ", STAC_DELL_3ST),
93ed1503 1118 /* 965 based 5 stack systems */
f5fcc13c
TI		 1119 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2301, "Intel D965", STAC_D965_5ST),
1120 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2302, "Intel D965", STAC_D965_5ST),
1121 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2303, "Intel D965", STAC_D965_5ST),
1122 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2304, "Intel D965", STAC_D965_5ST),
1123 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2305, "Intel D965", STAC_D965_5ST),
1124 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2501, "Intel D965", STAC_D965_5ST),
1125 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2502, "Intel D965", STAC_D965_5ST),
1126 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2503, "Intel D965", STAC_D965_5ST),
1127 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2504, "Intel D965", STAC_D965_5ST),
3cc08dc6
MP		 1128 {} /* terminator */
1129};
1130
f3302a59
MP		 1131static unsigned int ref9205_pin_configs[12] = {
1132 0x40000100, 0x40000100, 0x01016011, 0x01014010,
8b65727b
MP		 1133 0x01813122, 0x01a19021, 0x40000100, 0x40000100,
1134 0x90a000f0, 0x90a000f0, 0x01441030, 0x01c41030
f3302a59
MP		 1135};
1136
dfe495d0
TI		 1137/*
1138 STAC 9205 pin configs for
1139 102801F1
1140 102801F2
1141 102801FC
1142 102801FD
1143 10280204
1144 1028021F
1145*/
1146static unsigned int dell_9205_m42_pin_configs[12] = {
1147 0x0321101F, 0x03A11020, 0x400003FA, 0x90170310,
1148 0x400003FB, 0x400003FC, 0x400003FD, 0x40F000F9,
1149 0x90A60330, 0x400003FF, 0x0144131F, 0x40C003FE,
1150};
1151
1152/*
1153 STAC 9205 pin configs for
1154 102801F9
1155 102801FA
1156 102801FE
1157 102801FF (Dell Precision M4300)
1158 10280206
1159 10280200
1160 10280201
1161*/
1162static unsigned int dell_9205_m43_pin_configs[12] = {
ae0a8ed8
TD		 1163 0x0321101f, 0x03a11020, 0x90a70330, 0x90170310,
1164 0x400000fe, 0x400000ff, 0x400000fd, 0x40f000f9,
1165 0x400000fa, 0x400000fc, 0x0144131f, 0x40c003f8,
1166};
1167
dfe495d0 1168static unsigned int dell_9205_m44_pin_configs[12] = {
ae0a8ed8
TD		 1169 0x0421101f, 0x04a11020, 0x400003fa, 0x90170310,
1170 0x400003fb, 0x400003fc, 0x400003fd, 0x400003f9,
1171 0x90a60330, 0x400003ff, 0x01441340, 0x40c003fe,
1172};
1173
f5fcc13c 1174static unsigned int *stac9205_brd_tbl[STAC_9205_MODELS] = {
ae0a8ed8 1175 [STAC_9205_REF] = ref9205_pin_configs,
dfe495d0
TI		 1176 [STAC_9205_DELL_M42] = dell_9205_m42_pin_configs,
1177 [STAC_9205_DELL_M43] = dell_9205_m43_pin_configs,
1178 [STAC_9205_DELL_M44] = dell_9205_m44_pin_configs,
f3302a59
MP		 1179};
1180
f5fcc13c
TI		 1181static const char *stac9205_models[STAC_9205_MODELS] = {
1182 [STAC_9205_REF] = "ref",
dfe495d0 1183 [STAC_9205_DELL_M42] = "dell-m42",
ae0a8ed8
TD		 1184 [STAC_9205_DELL_M43] = "dell-m43",
1185 [STAC_9205_DELL_M44] = "dell-m44",
f5fcc13c
TI		 1186};
1187
1188static struct snd_pci_quirk stac9205_cfg_tbl[] = {
1189 /* SigmaTel reference board */
1190 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1191 "DFI LanParty", STAC_9205_REF),
dfe495d0
TI		 1192 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f1,
1193 "unknown Dell", STAC_9205_DELL_M42),
1194 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f2,
1195 "unknown Dell", STAC_9205_DELL_M42),
ae0a8ed8 1196 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f8,
b44ef2f1
MR		 1197 "Dell Precision", STAC_9205_DELL_M43),
1198 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021c,
1199 "Dell Precision", STAC_9205_DELL_M43),
ae0a8ed8
TD		 1200 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f9,
1201 "Dell Precision", STAC_9205_DELL_M43),
e45e459e
MR		 1202 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021b,
1203 "Dell Precision", STAC_9205_DELL_M43),
ae0a8ed8
TD		 1204 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fa,
1205 "Dell Precision", STAC_9205_DELL_M43),
dfe495d0
TI		 1206 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fc,
1207 "unknown Dell", STAC_9205_DELL_M42),
1208 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fd,
1209 "unknown Dell", STAC_9205_DELL_M42),
ae0a8ed8
TD		 1210 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fe,
1211 "Dell Precision", STAC_9205_DELL_M43),
1212 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ff,
dfe495d0 1213 "Dell Precision M4300", STAC_9205_DELL_M43),
ae0a8ed8
TD		 1214 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0206,
1215 "Dell Precision", STAC_9205_DELL_M43),
1216 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f1,
1217 "Dell Inspiron", STAC_9205_DELL_M44),
1218 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f2,
1219 "Dell Inspiron", STAC_9205_DELL_M44),
1220 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fc,
1221 "Dell Inspiron", STAC_9205_DELL_M44),
1222 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fd,
1223 "Dell Inspiron", STAC_9205_DELL_M44),
dfe495d0
TI		 1224 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0204,
1225 "unknown Dell", STAC_9205_DELL_M42),
ae0a8ed8
TD		 1226 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021f,
1227 "Dell Inspiron", STAC_9205_DELL_M44),
f3302a59
MP		 1228 {} /* terminator */
1229};
1230
11b44bbd
RF		 1231static int stac92xx_save_bios_config_regs(struct hda_codec *codec)
1232{
1233 int i;
1234 struct sigmatel_spec *spec = codec->spec;
1235
1236 if (! spec->bios_pin_configs) {
1237 spec->bios_pin_configs = kcalloc(spec->num_pins,
1238 sizeof(*spec->bios_pin_configs), GFP_KERNEL);
1239 if (! spec->bios_pin_configs)
1240 return -ENOMEM;
1241 }
1242
1243 for (i = 0; i < spec->num_pins; i++) {
1244 hda_nid_t nid = spec->pin_nids[i];
1245 unsigned int pin_cfg;
1246
1247 pin_cfg = snd_hda_codec_read(codec, nid, 0,
1248 AC_VERB_GET_CONFIG_DEFAULT, 0x00);
1249 snd_printdd(KERN_INFO "hda_codec: pin nid %2.2x bios pin config %8.8x\n",
1250 nid, pin_cfg);
1251 spec->bios_pin_configs[i] = pin_cfg;
1252 }
1253
1254 return 0;
1255}
1256
87d48363
MR		 1257static void stac92xx_set_config_reg(struct hda_codec *codec,
1258 hda_nid_t pin_nid, unsigned int pin_config)
1259{
1260 int i;
1261 snd_hda_codec_write(codec, pin_nid, 0,
1262 AC_VERB_SET_CONFIG_DEFAULT_BYTES_0,
1263 pin_config & 0x000000ff);
1264 snd_hda_codec_write(codec, pin_nid, 0,
1265 AC_VERB_SET_CONFIG_DEFAULT_BYTES_1,
1266 (pin_config & 0x0000ff00) >> 8);
1267 snd_hda_codec_write(codec, pin_nid, 0,
1268 AC_VERB_SET_CONFIG_DEFAULT_BYTES_2,
1269 (pin_config & 0x00ff0000) >> 16);
1270 snd_hda_codec_write(codec, pin_nid, 0,
1271 AC_VERB_SET_CONFIG_DEFAULT_BYTES_3,
1272 pin_config >> 24);
1273 i = snd_hda_codec_read(codec, pin_nid, 0,
1274 AC_VERB_GET_CONFIG_DEFAULT,
1275 0x00);
1276 snd_printdd(KERN_INFO "hda_codec: pin nid %2.2x pin config %8.8x\n",
1277 pin_nid, i);
1278}
1279
2f2f4251
M		 1280static void stac92xx_set_config_regs(struct hda_codec *codec)
1281{
1282 int i;
1283 struct sigmatel_spec *spec = codec->spec;
2f2f4251 1284
87d48363
MR		 1285 if (!spec->pin_configs)
1286 return;
11b44bbd 1287
87d48363
MR		 1288 for (i = 0; i < spec->num_pins; i++)
1289 stac92xx_set_config_reg(codec, spec->pin_nids[i],
1290 spec->pin_configs[i]);
2f2f4251 1291}
2f2f4251 1292
8259980e 1293static void stac92xx_enable_gpio_mask(struct hda_codec *codec)
92a22beb 1294{
8259980e 1295 struct sigmatel_spec *spec = codec->spec;
87d48363 1296 /* Configure GPIOx as output */
82beb8fd
TI		 1297 snd_hda_codec_write_cache(codec, codec->afg, 0,
1298 AC_VERB_SET_GPIO_DIRECTION, spec->gpio_mask);
87d48363 1299 /* Configure GPIOx as CMOS */
82beb8fd 1300 snd_hda_codec_write_cache(codec, codec->afg, 0, 0x7e7, 0x00000000);
87d48363 1301 /* Assert GPIOx */
82beb8fd
TI		 1302 snd_hda_codec_write_cache(codec, codec->afg, 0,
1303 AC_VERB_SET_GPIO_DATA, spec->gpio_data);
87d48363 1304 /* Enable GPIOx */
82beb8fd
TI		 1305 snd_hda_codec_write_cache(codec, codec->afg, 0,
1306 AC_VERB_SET_GPIO_MASK, spec->gpio_mask);
92a22beb
MR		 1307}
1308
dabbed6f 1309/*
c7d4b2fa 1310 * Analog playback callbacks
dabbed6f 1311 */
c7d4b2fa
M		 1312static int stac92xx_playback_pcm_open(struct hda_pcm_stream *hinfo,
1313 struct hda_codec *codec,
c8b6bf9b 1314 struct snd_pcm_substream *substream)
2f2f4251 1315{
dabbed6f 1316 struct sigmatel_spec *spec = codec->spec;
c7d4b2fa 1317 return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream);
2f2f4251
M		 1318}
1319
2f2f4251
M		 1320static int stac92xx_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1321 struct hda_codec *codec,
1322 unsigned int stream_tag,
1323 unsigned int format,
c8b6bf9b 1324 struct snd_pcm_substream *substream)
2f2f4251
M		 1325{
1326 struct sigmatel_spec *spec = codec->spec;
403d1944 1327 return snd_hda_multi_out_analog_prepare(codec, &spec->multiout, stream_tag, format, substream);
2f2f4251
M		 1328}
1329
1330static int stac92xx_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1331 struct hda_codec *codec,
c8b6bf9b 1332 struct snd_pcm_substream *substream)
2f2f4251
M		 1333{
1334 struct sigmatel_spec *spec = codec->spec;
1335 return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout);
1336}
1337
dabbed6f
M		 1338/*
1339 * Digital playback callbacks
1340 */
1341static int stac92xx_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
1342 struct hda_codec *codec,
c8b6bf9b 1343 struct snd_pcm_substream *substream)
dabbed6f
M		 1344{
1345 struct sigmatel_spec *spec = codec->spec;
1346 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1347}
1348
1349static int stac92xx_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
1350 struct hda_codec *codec,
c8b6bf9b 1351 struct snd_pcm_substream *substream)
dabbed6f
M		 1352{
1353 struct sigmatel_spec *spec = codec->spec;
1354 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1355}
1356
6b97eb45
TI		 1357static int stac92xx_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1358 struct hda_codec *codec,
1359 unsigned int stream_tag,
1360 unsigned int format,
1361 struct snd_pcm_substream *substream)
1362{
1363 struct sigmatel_spec *spec = codec->spec;
1364 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1365 stream_tag, format, substream);
1366}
1367
dabbed6f 1368
2f2f4251
M		 1369/*
1370 * Analog capture callbacks
1371 */
1372static int stac92xx_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
1373 struct hda_codec *codec,
1374 unsigned int stream_tag,
1375 unsigned int format,
c8b6bf9b 1376 struct snd_pcm_substream *substream)
2f2f4251
M		 1377{
1378 struct sigmatel_spec *spec = codec->spec;
1379
1380 snd_hda_codec_setup_stream(codec, spec->adc_nids[substream->number],
1381 stream_tag, 0, format);
1382 return 0;
1383}
1384
1385static int stac92xx_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
1386 struct hda_codec *codec,
c8b6bf9b 1387 struct snd_pcm_substream *substream)
2f2f4251
M		 1388{
1389 struct sigmatel_spec *spec = codec->spec;
1390
1391 snd_hda_codec_setup_stream(codec, spec->adc_nids[substream->number], 0, 0, 0);
1392 return 0;
1393}
1394
dabbed6f
M		 1395static struct hda_pcm_stream stac92xx_pcm_digital_playback = {
1396 .substreams = 1,
1397 .channels_min = 2,
1398 .channels_max = 2,
1399 /* NID is set in stac92xx_build_pcms */
1400 .ops = {
1401 .open = stac92xx_dig_playback_pcm_open,
6b97eb45
TI		 1402 .close = stac92xx_dig_playback_pcm_close,
1403 .prepare = stac92xx_dig_playback_pcm_prepare
dabbed6f
M		 1404 },
1405};
1406
1407static struct hda_pcm_stream stac92xx_pcm_digital_capture = {
1408 .substreams = 1,
1409 .channels_min = 2,
1410 .channels_max = 2,
1411 /* NID is set in stac92xx_build_pcms */
1412};
1413
2f2f4251
M		 1414static struct hda_pcm_stream stac92xx_pcm_analog_playback = {
1415 .substreams = 1,
1416 .channels_min = 2,
c7d4b2fa 1417 .channels_max = 8,
2f2f4251
M		 1418 .nid = 0x02, /* NID to query formats and rates */
1419 .ops = {
1420 .open = stac92xx_playback_pcm_open,
1421 .prepare = stac92xx_playback_pcm_prepare,
1422 .cleanup = stac92xx_playback_pcm_cleanup
1423 },
1424};
1425
3cc08dc6
MP		 1426static struct hda_pcm_stream stac92xx_pcm_analog_alt_playback = {
1427 .substreams = 1,
1428 .channels_min = 2,
1429 .channels_max = 2,
1430 .nid = 0x06, /* NID to query formats and rates */
1431 .ops = {
1432 .open = stac92xx_playback_pcm_open,
1433 .prepare = stac92xx_playback_pcm_prepare,
1434 .cleanup = stac92xx_playback_pcm_cleanup
1435 },
1436};
1437
2f2f4251 1438static struct hda_pcm_stream stac92xx_pcm_analog_capture = {
2f2f4251
M		 1439 .channels_min = 2,
1440 .channels_max = 2,
9e05b7a3 1441 /* NID + .substreams is set in stac92xx_build_pcms */
2f2f4251
M		 1442 .ops = {
1443 .prepare = stac92xx_capture_pcm_prepare,
1444 .cleanup = stac92xx_capture_pcm_cleanup
1445 },
1446};
1447
1448static int stac92xx_build_pcms(struct hda_codec *codec)
1449{
1450 struct sigmatel_spec *spec = codec->spec;
1451 struct hda_pcm *info = spec->pcm_rec;
1452
1453 codec->num_pcms = 1;
1454 codec->pcm_info = info;
1455
c7d4b2fa 1456 info->name = "STAC92xx Analog";
2f2f4251 1457 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_analog_playback;
2f2f4251 1458 info->stream[SNDRV_PCM_STREAM_CAPTURE] = stac92xx_pcm_analog_capture;
3cc08dc6 1459 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adc_nids[0];
9e05b7a3 1460 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_adcs;
3cc08dc6
MP		 1461
1462 if (spec->alt_switch) {
1463 codec->num_pcms++;
1464 info++;
1465 info->name = "STAC92xx Analog Alt";
1466 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_analog_alt_playback;
1467 }
2f2f4251 1468
dabbed6f
M		 1469 if (spec->multiout.dig_out_nid || spec->dig_in_nid) {
1470 codec->num_pcms++;
1471 info++;
1472 info->name = "STAC92xx Digital";
1473 if (spec->multiout.dig_out_nid) {
1474 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_digital_playback;
1475 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->multiout.dig_out_nid;
1476 }
1477 if (spec->dig_in_nid) {
1478 info->stream[SNDRV_PCM_STREAM_CAPTURE] = stac92xx_pcm_digital_capture;
1479 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in_nid;
1480 }
1481 }
1482
2f2f4251
M		 1483 return 0;
1484}
1485
c960a03b
TI		 1486static unsigned int stac92xx_get_vref(struct hda_codec *codec, hda_nid_t nid)
1487{
1488 unsigned int pincap = snd_hda_param_read(codec, nid,
1489 AC_PAR_PIN_CAP);
1490 pincap = (pincap & AC_PINCAP_VREF) >> AC_PINCAP_VREF_SHIFT;
1491 if (pincap & AC_PINCAP_VREF_100)
1492 return AC_PINCTL_VREF_100;
1493 if (pincap & AC_PINCAP_VREF_80)
1494 return AC_PINCTL_VREF_80;
1495 if (pincap & AC_PINCAP_VREF_50)
1496 return AC_PINCTL_VREF_50;
1497 if (pincap & AC_PINCAP_VREF_GRD)
1498 return AC_PINCTL_VREF_GRD;
1499 return 0;
1500}
1501
403d1944
MP		 1502static void stac92xx_auto_set_pinctl(struct hda_codec *codec, hda_nid_t nid, int pin_type)
1503
1504{
82beb8fd
TI		 1505 snd_hda_codec_write_cache(codec, nid, 0,
1506 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_type);
403d1944
MP		 1507}
1508
a5ce8890 1509#define stac92xx_io_switch_info snd_ctl_boolean_mono_info
403d1944
MP		 1510
1511static int stac92xx_io_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1512{
1513 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
1514 struct sigmatel_spec *spec = codec->spec;
1515 int io_idx = kcontrol-> private_value & 0xff;
1516
1517 ucontrol->value.integer.value[0] = spec->io_switch[io_idx];
1518 return 0;
1519}
1520
1521static int stac92xx_io_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1522{
1523 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
1524 struct sigmatel_spec *spec = codec->spec;
1525 hda_nid_t nid = kcontrol->private_value >> 8;
1526 int io_idx = kcontrol-> private_value & 0xff;
1527 unsigned short val = ucontrol->value.integer.value[0];
1528
1529 spec->io_switch[io_idx] = val;
1530
1531 if (val)
1532 stac92xx_auto_set_pinctl(codec, nid, AC_PINCTL_OUT_EN);
c960a03b
TI		 1533 else {
1534 unsigned int pinctl = AC_PINCTL_IN_EN;
1535 if (io_idx) /* set VREF for mic */
1536 pinctl |= stac92xx_get_vref(codec, nid);
1537 stac92xx_auto_set_pinctl(codec, nid, pinctl);
1538 }
403d1944
MP		 1539 return 1;
1540}
1541
0fb87bb4
ML		 1542#define stac92xx_clfe_switch_info snd_ctl_boolean_mono_info
1543
1544static int stac92xx_clfe_switch_get(struct snd_kcontrol *kcontrol,
1545 struct snd_ctl_elem_value *ucontrol)
1546{
1547 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
1548 struct sigmatel_spec *spec = codec->spec;
1549
1550 ucontrol->value.integer.value[0] = spec->clfe_swap;
1551 return 0;
1552}
1553
1554static int stac92xx_clfe_switch_put(struct snd_kcontrol *kcontrol,
1555 struct snd_ctl_elem_value *ucontrol)
1556{
1557 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
1558 struct sigmatel_spec *spec = codec->spec;
1559 hda_nid_t nid = kcontrol->private_value & 0xff;
1560
1561 if (spec->clfe_swap == ucontrol->value.integer.value[0])
1562 return 0;
1563
1564 spec->clfe_swap = ucontrol->value.integer.value[0];
1565
1566 snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_EAPD_BTLENABLE,
1567 spec->clfe_swap ? 0x4 : 0x0);
1568
1569 return 1;
1570}
1571
403d1944
MP		 1572#define STAC_CODEC_IO_SWITCH(xname, xpval) \
1573 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1574 .name = xname, \
1575 .index = 0, \
1576 .info = stac92xx_io_switch_info, \
1577 .get = stac92xx_io_switch_get, \
1578 .put = stac92xx_io_switch_put, \
1579 .private_value = xpval, \
1580 }
1581
0fb87bb4
ML		 1582#define STAC_CODEC_CLFE_SWITCH(xname, xpval) \
1583 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1584 .name = xname, \
1585 .index = 0, \
1586 .info = stac92xx_clfe_switch_info, \
1587 .get = stac92xx_clfe_switch_get, \
1588 .put = stac92xx_clfe_switch_put, \
1589 .private_value = xpval, \
1590 }
403d1944 1591
c7d4b2fa
M		 1592enum {
1593 STAC_CTL_WIDGET_VOL,
1594 STAC_CTL_WIDGET_MUTE,
403d1944 1595 STAC_CTL_WIDGET_IO_SWITCH,
0fb87bb4 1596 STAC_CTL_WIDGET_CLFE_SWITCH
c7d4b2fa
M		 1597};
1598
c8b6bf9b 1599static struct snd_kcontrol_new stac92xx_control_templates[] = {
c7d4b2fa
M		 1600 HDA_CODEC_VOLUME(NULL, 0, 0, 0),
1601 HDA_CODEC_MUTE(NULL, 0, 0, 0),
403d1944 1602 STAC_CODEC_IO_SWITCH(NULL, 0),
0fb87bb4 1603 STAC_CODEC_CLFE_SWITCH(NULL, 0),
c7d4b2fa
M		 1604};
1605
1606/* add dynamic controls */
1607static int stac92xx_add_control(struct sigmatel_spec *spec, int type, const char *name, unsigned long val)
1608{
c8b6bf9b 1609 struct snd_kcontrol_new *knew;
c7d4b2fa
M		 1610
1611 if (spec->num_kctl_used >= spec->num_kctl_alloc) {
1612 int num = spec->num_kctl_alloc + NUM_CONTROL_ALLOC;
1613
1614 knew = kcalloc(num + 1, sizeof(*knew), GFP_KERNEL); /* array + terminator */
1615 if (! knew)
1616 return -ENOMEM;
1617 if (spec->kctl_alloc) {
1618 memcpy(knew, spec->kctl_alloc, sizeof(*knew) * spec->num_kctl_alloc);
1619 kfree(spec->kctl_alloc);
1620 }
1621 spec->kctl_alloc = knew;
1622 spec->num_kctl_alloc = num;
1623 }
1624
1625 knew = &spec->kctl_alloc[spec->num_kctl_used];
1626 *knew = stac92xx_control_templates[type];
82fe0c58 1627 knew->name = kstrdup(name, GFP_KERNEL);
c7d4b2fa
M		 1628 if (! knew->name)
1629 return -ENOMEM;
1630 knew->private_value = val;
1631 spec->num_kctl_used++;
1632 return 0;
1633}
1634
403d1944
MP		 1635/* flag inputs as additional dynamic lineouts */
1636static int stac92xx_add_dyn_out_pins(struct hda_codec *codec, struct auto_pin_cfg *cfg)
1637{
1638 struct sigmatel_spec *spec = codec->spec;
7b043899
SL		 1639 unsigned int wcaps, wtype;
1640 int i, num_dacs = 0;
1641
1642 /* use the wcaps cache to count all DACs available for line-outs */
1643 for (i = 0; i < codec->num_nodes; i++) {
1644 wcaps = codec->wcaps[i];
1645 wtype = (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT;
1646 if (wtype == AC_WID_AUD_OUT && !(wcaps & AC_WCAP_DIGITAL))
1647 num_dacs++;
1648 }
403d1944 1649
7b043899
SL		 1650 snd_printdd("%s: total dac count=%d\n", __func__, num_dacs);
1651
403d1944
MP		 1652 switch (cfg->line_outs) {
1653 case 3:
1654 /* add line-in as side */
7b043899 1655 if (cfg->input_pins[AUTO_PIN_LINE] && num_dacs > 3) {
c480f79b
TI		 1656 cfg->line_out_pins[cfg->line_outs] =
1657 cfg->input_pins[AUTO_PIN_LINE];
403d1944
MP		 1658 spec->line_switch = 1;
1659 cfg->line_outs++;
1660 }
1661 break;
1662 case 2:
1663 /* add line-in as clfe and mic as side */
7b043899 1664 if (cfg->input_pins[AUTO_PIN_LINE] && num_dacs > 2) {
c480f79b
TI		 1665 cfg->line_out_pins[cfg->line_outs] =
1666 cfg->input_pins[AUTO_PIN_LINE];
403d1944
MP		 1667 spec->line_switch = 1;
1668 cfg->line_outs++;
1669 }
7b043899 1670 if (cfg->input_pins[AUTO_PIN_MIC] && num_dacs > 3) {
c480f79b
TI		 1671 cfg->line_out_pins[cfg->line_outs] =
1672 cfg->input_pins[AUTO_PIN_MIC];
403d1944
MP		 1673 spec->mic_switch = 1;
1674 cfg->line_outs++;
1675 }
1676 break;
1677 case 1:
1678 /* add line-in as surr and mic as clfe */
7b043899 1679 if (cfg->input_pins[AUTO_PIN_LINE] && num_dacs > 1) {
c480f79b
TI		 1680 cfg->line_out_pins[cfg->line_outs] =
1681 cfg->input_pins[AUTO_PIN_LINE];
403d1944
MP		 1682 spec->line_switch = 1;
1683 cfg->line_outs++;
1684 }
7b043899 1685 if (cfg->input_pins[AUTO_PIN_MIC] && num_dacs > 2) {
c480f79b
TI		 1686 cfg->line_out_pins[cfg->line_outs] =
1687 cfg->input_pins[AUTO_PIN_MIC];
403d1944
MP		 1688 spec->mic_switch = 1;
1689 cfg->line_outs++;
1690 }
1691 break;
1692 }
1693
1694 return 0;
1695}
1696
7b043899
SL		 1697
1698static int is_in_dac_nids(struct sigmatel_spec *spec, hda_nid_t nid)
1699{
1700 int i;
1701
1702 for (i = 0; i < spec->multiout.num_dacs; i++) {
1703 if (spec->multiout.dac_nids[i] == nid)
1704 return 1;
1705 }
1706
1707 return 0;
1708}
1709
3cc08dc6 1710/*
7b043899
SL		 1711 * Fill in the dac_nids table from the parsed pin configuration
1712 * This function only works when every pin in line_out_pins[]
1713 * contains atleast one DAC in its connection list. Some 92xx
1714 * codecs are not connected directly to a DAC, such as the 9200
1715 * and 9202/925x. For those, dac_nids[] must be hard-coded.
3cc08dc6 1716 */
19039bd0 1717static int stac92xx_auto_fill_dac_nids(struct hda_codec *codec,
df802952 1718 struct auto_pin_cfg *cfg)
c7d4b2fa
M		 1719{
1720 struct sigmatel_spec *spec = codec->spec;
7b043899
SL		 1721 int i, j, conn_len = 0;
1722 hda_nid_t nid, conn[HDA_MAX_CONNECTIONS];
1723 unsigned int wcaps, wtype;
1724
c7d4b2fa
M		 1725 for (i = 0; i < cfg->line_outs; i++) {
1726 nid = cfg->line_out_pins[i];
7b043899
SL		 1727 conn_len = snd_hda_get_connections(codec, nid, conn,
1728 HDA_MAX_CONNECTIONS);
1729 for (j = 0; j < conn_len; j++) {
1730 wcaps = snd_hda_param_read(codec, conn[j],
1731 AC_PAR_AUDIO_WIDGET_CAP);
1732 wtype = (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT;
1733
1734 if (wtype != AC_WID_AUD_OUT ||
1735 (wcaps & AC_WCAP_DIGITAL))
1736 continue;
1737 /* conn[j] is a DAC routed to this line-out */
1738 if (!is_in_dac_nids(spec, conn[j]))
1739 break;
1740 }
1741
1742 if (j == conn_len) {
df802952
TI		 1743 if (spec->multiout.num_dacs > 0) {
1744 /* we have already working output pins,
1745 * so let's drop the broken ones again
1746 */
1747 cfg->line_outs = spec->multiout.num_dacs;
1748 break;
1749 }
7b043899
SL		 1750 /* error out, no available DAC found */
1751 snd_printk(KERN_ERR
1752 "%s: No available DAC for pin 0x%x\n",
1753 __func__, nid);
1754 return -ENODEV;
1755 }
1756
1757 spec->multiout.dac_nids[i] = conn[j];
1758 spec->multiout.num_dacs++;
1759 if (conn_len > 1) {
1760 /* select this DAC in the pin's input mux */
82beb8fd
TI		 1761 snd_hda_codec_write_cache(codec, nid, 0,
1762 AC_VERB_SET_CONNECT_SEL, j);
c7d4b2fa 1763
7b043899
SL		 1764 }
1765 }
c7d4b2fa 1766
7b043899
SL		 1767 snd_printd("dac_nids=%d (0x%x/0x%x/0x%x/0x%x/0x%x)\n",
1768 spec->multiout.num_dacs,
1769 spec->multiout.dac_nids[0],
1770 spec->multiout.dac_nids[1],
1771 spec->multiout.dac_nids[2],
1772 spec->multiout.dac_nids[3],
1773 spec->multiout.dac_nids[4]);
c7d4b2fa
M		 1774 return 0;
1775}
1776
eb06ed8f
TI		 1777/* create volume control/switch for the given prefx type */
1778static int create_controls(struct sigmatel_spec *spec, const char *pfx, hda_nid_t nid, int chs)
1779{
1780 char name[32];
1781 int err;
1782
1783 sprintf(name, "%s Playback Volume", pfx);
1784 err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, name,
1785 HDA_COMPOSE_AMP_VAL(nid, chs, 0, HDA_OUTPUT));
1786 if (err < 0)
1787 return err;
1788 sprintf(name, "%s Playback Switch", pfx);
1789 err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, name,
1790 HDA_COMPOSE_AMP_VAL(nid, chs, 0, HDA_OUTPUT));
1791 if (err < 0)
1792 return err;
1793 return 0;
1794}
1795
c7d4b2fa 1796/* add playback controls from the parsed DAC table */
0fb87bb4 1797static int stac92xx_auto_create_multi_out_ctls(struct hda_codec *codec,
19039bd0 1798 const struct auto_pin_cfg *cfg)
c7d4b2fa 1799{
19039bd0
TI		 1800 static const char *chname[4] = {
1801 "Front", "Surround", NULL /*CLFE*/, "Side"
1802 };
c7d4b2fa
M		 1803 hda_nid_t nid;
1804 int i, err;
1805
0fb87bb4
ML		 1806 struct sigmatel_spec *spec = codec->spec;
1807 unsigned int wid_caps;
1808
1809
c7d4b2fa 1810 for (i = 0; i < cfg->line_outs; i++) {
403d1944 1811 if (!spec->multiout.dac_nids[i])
c7d4b2fa
M		 1812 continue;
1813
1814 nid = spec->multiout.dac_nids[i];
1815
1816 if (i == 2) {
1817 /* Center/LFE */
eb06ed8f
TI		 1818 err = create_controls(spec, "Center", nid, 1);
1819 if (err < 0)
c7d4b2fa 1820 return err;
eb06ed8f
TI		 1821 err = create_controls(spec, "LFE", nid, 2);
1822 if (err < 0)
c7d4b2fa 1823 return err;
0fb87bb4
ML		 1824
1825 wid_caps = get_wcaps(codec, nid);
1826
1827 if (wid_caps & AC_WCAP_LR_SWAP) {
1828 err = stac92xx_add_control(spec,
1829 STAC_CTL_WIDGET_CLFE_SWITCH,
1830 "Swap Center/LFE Playback Switch", nid);
1831
1832 if (err < 0)
1833 return err;
1834 }
1835
c7d4b2fa 1836 } else {
eb06ed8f
TI		 1837 err = create_controls(spec, chname[i], nid, 3);
1838 if (err < 0)
c7d4b2fa
M		 1839 return err;
1840 }
1841 }
1842
403d1944
MP		 1843 if (spec->line_switch)
1844 if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_IO_SWITCH, "Line In as Output Switch", cfg->input_pins[AUTO_PIN_LINE] << 8)) < 0)
1845 return err;
1846
1847 if (spec->mic_switch)
1848 if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_IO_SWITCH, "Mic as Output Switch", (cfg->input_pins[AUTO_PIN_MIC] << 8) | 1)) < 0)
1849 return err;
1850
c7d4b2fa
M		 1851 return 0;
1852}
1853
eb06ed8f 1854static int check_in_dac_nids(struct sigmatel_spec *spec, hda_nid_t nid)
c7d4b2fa 1855{
7b043899
SL		 1856 if (is_in_dac_nids(spec, nid))
1857 return 1;
eb06ed8f
TI		 1858 if (spec->multiout.hp_nid == nid)
1859 return 1;
1860 return 0;
1861}
c7d4b2fa 1862
eb06ed8f
TI		 1863static int add_spec_dacs(struct sigmatel_spec *spec, hda_nid_t nid)
1864{
1865 if (!spec->multiout.hp_nid)
1866 spec->multiout.hp_nid = nid;
1867 else if (spec->multiout.num_dacs > 4) {
1868 printk(KERN_WARNING "stac92xx: No space for DAC 0x%x\n", nid);
1869 return 1;
1870 } else {
1871 spec->multiout.dac_nids[spec->multiout.num_dacs] = nid;
1872 spec->multiout.num_dacs++;
1873 }
1874 return 0;
1875}
4e55096e 1876
eb06ed8f
TI		 1877/* add playback controls for Speaker and HP outputs */
1878static int stac92xx_auto_create_hp_ctls(struct hda_codec *codec,
1879 struct auto_pin_cfg *cfg)
1880{
1881 struct sigmatel_spec *spec = codec->spec;
1882 hda_nid_t nid;
1883 int i, old_num_dacs, err;
1884
1885 old_num_dacs = spec->multiout.num_dacs;
1886 for (i = 0; i < cfg->hp_outs; i++) {
1887 unsigned int wid_caps = get_wcaps(codec, cfg->hp_pins[i]);
1888 if (wid_caps & AC_WCAP_UNSOL_CAP)
1889 spec->hp_detect = 1;
1890 nid = snd_hda_codec_read(codec, cfg->hp_pins[i], 0,
1891 AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
1892 if (check_in_dac_nids(spec, nid))
1893 nid = 0;
1894 if (! nid)
c7d4b2fa 1895 continue;
eb06ed8f
TI		 1896 add_spec_dacs(spec, nid);
1897 }
1898 for (i = 0; i < cfg->speaker_outs; i++) {
7b043899 1899 nid = snd_hda_codec_read(codec, cfg->speaker_pins[i], 0,
eb06ed8f
TI		 1900 AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
1901 if (check_in_dac_nids(spec, nid))
1902 nid = 0;
eb06ed8f
TI		 1903 if (! nid)
1904 continue;
1905 add_spec_dacs(spec, nid);
c7d4b2fa 1906 }
1b290a51
MR		 1907 for (i = 0; i < cfg->line_outs; i++) {
1908 nid = snd_hda_codec_read(codec, cfg->line_out_pins[i], 0,
1909 AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
1910 if (check_in_dac_nids(spec, nid))
1911 nid = 0;
1912 if (! nid)
1913 continue;
1914 add_spec_dacs(spec, nid);
1915 }
eb06ed8f
TI		 1916 for (i = old_num_dacs; i < spec->multiout.num_dacs; i++) {
1917 static const char *pfxs[] = {
1918 "Speaker", "External Speaker", "Speaker2",
1919 };
1920 err = create_controls(spec, pfxs[i - old_num_dacs],
1921 spec->multiout.dac_nids[i], 3);
1922 if (err < 0)
1923 return err;
1924 }
1925 if (spec->multiout.hp_nid) {
1926 const char *pfx;
1927 if (old_num_dacs == spec->multiout.num_dacs)
1928 pfx = "Master";
1929 else
1930 pfx = "Headphone";
1931 err = create_controls(spec, pfx, spec->multiout.hp_nid, 3);
1932 if (err < 0)
1933 return err;
1934 }
c7d4b2fa
M		 1935
1936 return 0;
1937}
1938
8b65727b 1939/* labels for dmic mux inputs */
ddc2cec4 1940static const char *stac92xx_dmic_labels[5] = {
8b65727b
MP		 1941 "Analog Inputs", "Digital Mic 1", "Digital Mic 2",
1942 "Digital Mic 3", "Digital Mic 4"
1943};
1944
1945/* create playback/capture controls for input pins on dmic capable codecs */
1946static int stac92xx_auto_create_dmic_input_ctls(struct hda_codec *codec,
1947 const struct auto_pin_cfg *cfg)
1948{
1949 struct sigmatel_spec *spec = codec->spec;
1950 struct hda_input_mux *dimux = &spec->private_dimux;
1951 hda_nid_t con_lst[HDA_MAX_NUM_INPUTS];
1952 int i, j;
1953
1954 dimux->items[dimux->num_items].label = stac92xx_dmic_labels[0];
1955 dimux->items[dimux->num_items].index = 0;
1956 dimux->num_items++;
1957
1958 for (i = 0; i < spec->num_dmics; i++) {
1959 int index;
1960 int num_cons;
1961 unsigned int def_conf;
1962
1963 def_conf = snd_hda_codec_read(codec,
1964 spec->dmic_nids[i],
1965 0,
1966 AC_VERB_GET_CONFIG_DEFAULT,
1967 0);
1968 if (get_defcfg_connect(def_conf) == AC_JACK_PORT_NONE)
1969 continue;
1970
1971 num_cons = snd_hda_get_connections(codec,
1972 spec->dmux_nid,
1973 con_lst,
1974 HDA_MAX_NUM_INPUTS);
1975 for (j = 0; j < num_cons; j++)
1976 if (con_lst[j] == spec->dmic_nids[i]) {
1977 index = j;
1978 goto found;
1979 }
1980 continue;
1981found:
1982 dimux->items[dimux->num_items].label =
1983 stac92xx_dmic_labels[dimux->num_items];
1984 dimux->items[dimux->num_items].index = index;
1985 dimux->num_items++;
1986 }
1987
1988 return 0;
1989}
1990
c7d4b2fa
M		 1991/* create playback/capture controls for input pins */
1992static int stac92xx_auto_create_analog_input_ctls(struct hda_codec *codec, const struct auto_pin_cfg *cfg)
1993{
1994 struct sigmatel_spec *spec = codec->spec;
c7d4b2fa
M		 1995 struct hda_input_mux *imux = &spec->private_imux;
1996 hda_nid_t con_lst[HDA_MAX_NUM_INPUTS];
1997 int i, j, k;
1998
1999 for (i = 0; i < AUTO_PIN_LAST; i++) {
314634bc
TI		 2000 int index;
2001
2002 if (!cfg->input_pins[i])
2003 continue;
2004 index = -1;
2005 for (j = 0; j < spec->num_muxes; j++) {
2006 int num_cons;
2007 num_cons = snd_hda_get_connections(codec,
2008 spec->mux_nids[j],
2009 con_lst,
2010 HDA_MAX_NUM_INPUTS);
2011 for (k = 0; k < num_cons; k++)
2012 if (con_lst[k] == cfg->input_pins[i]) {
2013 index = k;
2014 goto found;
2015 }
c7d4b2fa 2016 }
314634bc
TI		 2017 continue;
2018 found:
2019 imux->items[imux->num_items].label = auto_pin_cfg_labels[i];
2020 imux->items[imux->num_items].index = index;
2021 imux->num_items++;
c7d4b2fa
M		 2022 }
2023
7b043899 2024 if (imux->num_items) {
62fe78e9
SR		 2025 /*
2026 * Set the current input for the muxes.
2027 * The STAC9221 has two input muxes with identical source
2028 * NID lists. Hopefully this won't get confused.
2029 */
2030 for (i = 0; i < spec->num_muxes; i++) {
82beb8fd
TI		 2031 snd_hda_codec_write_cache(codec, spec->mux_nids[i], 0,
2032 AC_VERB_SET_CONNECT_SEL,
2033 imux->items[0].index);
62fe78e9
SR		 2034 }
2035 }
2036
c7d4b2fa
M		 2037 return 0;
2038}
2039
c7d4b2fa
M		 2040static void stac92xx_auto_init_multi_out(struct hda_codec *codec)
2041{
2042 struct sigmatel_spec *spec = codec->spec;
2043 int i;
2044
2045 for (i = 0; i < spec->autocfg.line_outs; i++) {
2046 hda_nid_t nid = spec->autocfg.line_out_pins[i];
2047 stac92xx_auto_set_pinctl(codec, nid, AC_PINCTL_OUT_EN);
2048 }
2049}
2050
2051static void stac92xx_auto_init_hp_out(struct hda_codec *codec)
2052{
2053 struct sigmatel_spec *spec = codec->spec;
eb06ed8f 2054 int i;
c7d4b2fa 2055
eb06ed8f
TI		 2056 for (i = 0; i < spec->autocfg.hp_outs; i++) {
2057 hda_nid_t pin;
2058 pin = spec->autocfg.hp_pins[i];
2059 if (pin) /* connect to front */
2060 stac92xx_auto_set_pinctl(codec, pin, AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN);
2061 }
2062 for (i = 0; i < spec->autocfg.speaker_outs; i++) {
2063 hda_nid_t pin;
2064 pin = spec->autocfg.speaker_pins[i];
2065 if (pin) /* connect to front */
2066 stac92xx_auto_set_pinctl(codec, pin, AC_PINCTL_OUT_EN);
2067 }
c7d4b2fa
M		 2068}
2069
3cc08dc6 2070static int stac92xx_parse_auto_config(struct hda_codec *codec, hda_nid_t dig_out, hda_nid_t dig_in)
c7d4b2fa
M		 2071{
2072 struct sigmatel_spec *spec = codec->spec;
2073 int err;
2074
8b65727b
MP		 2075 if ((err = snd_hda_parse_pin_def_config(codec,
2076 &spec->autocfg,
2077 spec->dmic_nids)) < 0)
c7d4b2fa 2078 return err;
82bc955f 2079 if (! spec->autocfg.line_outs)
869264c4 2080 return 0; /* can't find valid pin config */
19039bd0 2081
403d1944
MP		 2082 if ((err = stac92xx_add_dyn_out_pins(codec, &spec->autocfg)) < 0)
2083 return err;
19039bd0
TI		 2084 if (spec->multiout.num_dacs == 0)
2085 if ((err = stac92xx_auto_fill_dac_nids(codec, &spec->autocfg)) < 0)
2086 return err;
c7d4b2fa 2087
0fb87bb4
ML		 2088 err = stac92xx_auto_create_multi_out_ctls(codec, &spec->autocfg);
2089
2090 if (err < 0)
2091 return err;
2092
2093 err = stac92xx_auto_create_hp_ctls(codec, &spec->autocfg);
2094
2095 if (err < 0)
2096 return err;
2097
2098 err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg);
2099
2100 if (err < 0)
c7d4b2fa
M		 2101 return err;
2102
8b65727b
MP		 2103 if (spec->num_dmics > 0)
2104 if ((err = stac92xx_auto_create_dmic_input_ctls(codec,
2105 &spec->autocfg)) < 0)
2106 return err;
2107
c7d4b2fa 2108 spec->multiout.max_channels = spec->multiout.num_dacs * 2;
403d1944 2109 if (spec->multiout.max_channels > 2)
c7d4b2fa 2110 spec->surr_switch = 1;
c7d4b2fa 2111
82bc955f 2112 if (spec->autocfg.dig_out_pin)
3cc08dc6 2113 spec->multiout.dig_out_nid = dig_out;
82bc955f 2114 if (spec->autocfg.dig_in_pin)
3cc08dc6 2115 spec->dig_in_nid = dig_in;
c7d4b2fa
M		 2116
2117 if (spec->kctl_alloc)
2118 spec->mixers[spec->num_mixers++] = spec->kctl_alloc;
2119
2120 spec->input_mux = &spec->private_imux;
8b65727b 2121 spec->dinput_mux = &spec->private_dimux;
c7d4b2fa
M		 2122
2123 return 1;
2124}
2125
82bc955f
TI		 2126/* add playback controls for HP output */
2127static int stac9200_auto_create_hp_ctls(struct hda_codec *codec,
2128 struct auto_pin_cfg *cfg)
2129{
2130 struct sigmatel_spec *spec = codec->spec;
eb06ed8f 2131 hda_nid_t pin = cfg->hp_pins[0];
82bc955f
TI		 2132 unsigned int wid_caps;
2133
2134 if (! pin)
2135 return 0;
2136
2137 wid_caps = get_wcaps(codec, pin);
505cb341 2138 if (wid_caps & AC_WCAP_UNSOL_CAP)
82bc955f 2139 spec->hp_detect = 1;
82bc955f
TI		 2140
2141 return 0;
2142}
2143
160ea0dc
RF		 2144/* add playback controls for LFE output */
2145static int stac9200_auto_create_lfe_ctls(struct hda_codec *codec,
2146 struct auto_pin_cfg *cfg)
2147{
2148 struct sigmatel_spec *spec = codec->spec;
2149 int err;
2150 hda_nid_t lfe_pin = 0x0;
2151 int i;
2152
2153 /*
2154 * search speaker outs and line outs for a mono speaker pin
2155 * with an amp. If one is found, add LFE controls
2156 * for it.
2157 */
2158 for (i = 0; i < spec->autocfg.speaker_outs && lfe_pin == 0x0; i++) {
2159 hda_nid_t pin = spec->autocfg.speaker_pins[i];
2160 unsigned long wcaps = get_wcaps(codec, pin);
2161 wcaps &= (AC_WCAP_STEREO | AC_WCAP_OUT_AMP);
2162 if (wcaps == AC_WCAP_OUT_AMP)
2163 /* found a mono speaker with an amp, must be lfe */
2164 lfe_pin = pin;
2165 }
2166
2167 /* if speaker_outs is 0, then speakers may be in line_outs */
2168 if (lfe_pin == 0 && spec->autocfg.speaker_outs == 0) {
2169 for (i = 0; i < spec->autocfg.line_outs && lfe_pin == 0x0; i++) {
2170 hda_nid_t pin = spec->autocfg.line_out_pins[i];
2171 unsigned long cfg;
2172 cfg = snd_hda_codec_read(codec, pin, 0,
2173 AC_VERB_GET_CONFIG_DEFAULT,
2174 0x00);
2175 if (get_defcfg_device(cfg) == AC_JACK_SPEAKER) {
2176 unsigned long wcaps = get_wcaps(codec, pin);
2177 wcaps &= (AC_WCAP_STEREO | AC_WCAP_OUT_AMP);
2178 if (wcaps == AC_WCAP_OUT_AMP)
2179 /* found a mono speaker with an amp,
2180 must be lfe */
2181 lfe_pin = pin;
2182 }
2183 }
2184 }
2185
2186 if (lfe_pin) {
eb06ed8f 2187 err = create_controls(spec, "LFE", lfe_pin, 1);
160ea0dc
RF		 2188 if (err < 0)
2189 return err;
2190 }
2191
2192 return 0;
2193}
2194
c7d4b2fa
M		 2195static int stac9200_parse_auto_config(struct hda_codec *codec)
2196{
2197 struct sigmatel_spec *spec = codec->spec;
2198 int err;
2199
df694daa 2200 if ((err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL)) < 0)
c7d4b2fa
M		 2201 return err;
2202
2203 if ((err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg)) < 0)
2204 return err;
2205
82bc955f
TI		 2206 if ((err = stac9200_auto_create_hp_ctls(codec, &spec->autocfg)) < 0)
2207 return err;
2208
160ea0dc
RF		 2209 if ((err = stac9200_auto_create_lfe_ctls(codec, &spec->autocfg)) < 0)
2210 return err;
2211
82bc955f 2212 if (spec->autocfg.dig_out_pin)
c7d4b2fa 2213 spec->multiout.dig_out_nid = 0x05;
82bc955f 2214 if (spec->autocfg.dig_in_pin)
c7d4b2fa 2215 spec->dig_in_nid = 0x04;
c7d4b2fa
M		 2216
2217 if (spec->kctl_alloc)
2218 spec->mixers[spec->num_mixers++] = spec->kctl_alloc;
2219
2220 spec->input_mux = &spec->private_imux;
8b65727b 2221 spec->dinput_mux = &spec->private_dimux;
c7d4b2fa
M		 2222
2223 return 1;
2224}
2225
62fe78e9
SR		 2226/*
2227 * Early 2006 Intel Macintoshes with STAC9220X5 codecs seem to have a
2228 * funky external mute control using GPIO pins.
2229 */
2230
2231static void stac922x_gpio_mute(struct hda_codec *codec, int pin, int muted)
2232{
2233 unsigned int gpiostate, gpiomask, gpiodir;
2234
2235 gpiostate = snd_hda_codec_read(codec, codec->afg, 0,
2236 AC_VERB_GET_GPIO_DATA, 0);
2237
2238 if (!muted)
2239 gpiostate |= (1 << pin);
2240 else
2241 gpiostate &= ~(1 << pin);
2242
2243 gpiomask = snd_hda_codec_read(codec, codec->afg, 0,
2244 AC_VERB_GET_GPIO_MASK, 0);
2245 gpiomask |= (1 << pin);
2246
2247 gpiodir = snd_hda_codec_read(codec, codec->afg, 0,
2248 AC_VERB_GET_GPIO_DIRECTION, 0);
2249 gpiodir |= (1 << pin);
2250
2251 /* AppleHDA seems to do this -- WTF is this verb?? */
2252 snd_hda_codec_write(codec, codec->afg, 0, 0x7e7, 0);
2253
2254 snd_hda_codec_write(codec, codec->afg, 0,
2255 AC_VERB_SET_GPIO_MASK, gpiomask);
2256 snd_hda_codec_write(codec, codec->afg, 0,
2257 AC_VERB_SET_GPIO_DIRECTION, gpiodir);
2258
2259 msleep(1);
2260
2261 snd_hda_codec_write(codec, codec->afg, 0,
2262 AC_VERB_SET_GPIO_DATA, gpiostate);
2263}
2264
314634bc
TI		 2265static void enable_pin_detect(struct hda_codec *codec, hda_nid_t nid,
2266 unsigned int event)
2267{
2268 if (get_wcaps(codec, nid) & AC_WCAP_UNSOL_CAP)
dc81bed1
TI		 2269 snd_hda_codec_write_cache(codec, nid, 0,
2270 AC_VERB_SET_UNSOLICITED_ENABLE,
2271 (AC_USRSP_EN | event));
314634bc
TI		 2272}
2273
c7d4b2fa
M		 2274static int stac92xx_init(struct hda_codec *codec)
2275{
2276 struct sigmatel_spec *spec = codec->spec;
82bc955f
TI		 2277 struct auto_pin_cfg *cfg = &spec->autocfg;
2278 int i;
c7d4b2fa 2279
c7d4b2fa
M		 2280 snd_hda_sequence_write(codec, spec->init);
2281
82bc955f
TI		 2282 /* set up pins */
2283 if (spec->hp_detect) {
505cb341 2284 /* Enable unsolicited responses on the HP widget */
eb06ed8f 2285 for (i = 0; i < cfg->hp_outs; i++)
314634bc
TI		 2286 enable_pin_detect(codec, cfg->hp_pins[i],
2287 STAC_HP_EVENT);
0a07acaf
TI		 2288 /* force to enable the first line-out; the others are set up
2289 * in unsol_event
2290 */
2291 stac92xx_auto_set_pinctl(codec, spec->autocfg.line_out_pins[0],
2292 AC_PINCTL_OUT_EN);
eb995a8c 2293 stac92xx_auto_init_hp_out(codec);
82bc955f
TI		 2294 /* fake event to set up pins */
2295 codec->patch_ops.unsol_event(codec, STAC_HP_EVENT << 26);
2296 } else {
2297 stac92xx_auto_init_multi_out(codec);
2298 stac92xx_auto_init_hp_out(codec);
2299 }
2300 for (i = 0; i < AUTO_PIN_LAST; i++) {
c960a03b
TI		 2301 hda_nid_t nid = cfg->input_pins[i];
2302 if (nid) {
2303 unsigned int pinctl = AC_PINCTL_IN_EN;
2304 if (i == AUTO_PIN_MIC || i == AUTO_PIN_FRONT_MIC)
2305 pinctl |= stac92xx_get_vref(codec, nid);
2306 stac92xx_auto_set_pinctl(codec, nid, pinctl);
2307 }
82bc955f 2308 }
8b65727b
MP		 2309 if (spec->num_dmics > 0)
2310 for (i = 0; i < spec->num_dmics; i++)
2311 stac92xx_auto_set_pinctl(codec, spec->dmic_nids[i],
2312 AC_PINCTL_IN_EN);
2313
82bc955f
TI		 2314 if (cfg->dig_out_pin)
2315 stac92xx_auto_set_pinctl(codec, cfg->dig_out_pin,
2316 AC_PINCTL_OUT_EN);
2317 if (cfg->dig_in_pin)
2318 stac92xx_auto_set_pinctl(codec, cfg->dig_in_pin,
2319 AC_PINCTL_IN_EN);
2320
62fe78e9
SR		 2321 if (spec->gpio_mute) {
2322 stac922x_gpio_mute(codec, 0, 0);
2323 stac922x_gpio_mute(codec, 1, 0);
2324 }
2325
c7d4b2fa
M		 2326 return 0;
2327}
2328
2f2f4251
M		 2329static void stac92xx_free(struct hda_codec *codec)
2330{
c7d4b2fa
M		 2331 struct sigmatel_spec *spec = codec->spec;
2332 int i;
2333
2334 if (! spec)
2335 return;
2336
2337 if (spec->kctl_alloc) {
2338 for (i = 0; i < spec->num_kctl_used; i++)
2339 kfree(spec->kctl_alloc[i].name);
2340 kfree(spec->kctl_alloc);
2341 }
2342
11b44bbd
RF		 2343 if (spec->bios_pin_configs)
2344 kfree(spec->bios_pin_configs);
2345
c7d4b2fa 2346 kfree(spec);
2f2f4251
M		 2347}
2348
4e55096e
M		 2349static void stac92xx_set_pinctl(struct hda_codec *codec, hda_nid_t nid,
2350 unsigned int flag)
2351{
2352 unsigned int pin_ctl = snd_hda_codec_read(codec, nid,
2353 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00);
7b043899 2354
f9acba43
TI		 2355 if (pin_ctl & AC_PINCTL_IN_EN) {
2356 /*
2357 * we need to check the current set-up direction of
2358 * shared input pins since they can be switched via
2359 * "xxx as Output" mixer switch
2360 */
2361 struct sigmatel_spec *spec = codec->spec;
2362 struct auto_pin_cfg *cfg = &spec->autocfg;
2363 if ((nid == cfg->input_pins[AUTO_PIN_LINE] &&
2364 spec->line_switch) ||
2365 (nid == cfg->input_pins[AUTO_PIN_MIC] &&
2366 spec->mic_switch))
2367 return;
2368 }
2369
7b043899
SL		 2370 /* if setting pin direction bits, clear the current
2371 direction bits first */
2372 if (flag & (AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN))
2373 pin_ctl &= ~(AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN);
2374
82beb8fd 2375 snd_hda_codec_write_cache(codec, nid, 0,
4e55096e
M		 2376 AC_VERB_SET_PIN_WIDGET_CONTROL,
2377 pin_ctl | flag);
2378}
2379
2380static void stac92xx_reset_pinctl(struct hda_codec *codec, hda_nid_t nid,
2381 unsigned int flag)
2382{
2383 unsigned int pin_ctl = snd_hda_codec_read(codec, nid,
2384 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00);
82beb8fd 2385 snd_hda_codec_write_cache(codec, nid, 0,
4e55096e
M		 2386 AC_VERB_SET_PIN_WIDGET_CONTROL,
2387 pin_ctl & ~flag);
2388}
2389
314634bc
TI		 2390static int get_pin_presence(struct hda_codec *codec, hda_nid_t nid)
2391{
2392 if (!nid)
2393 return 0;
2394 if (snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PIN_SENSE, 0x00)
2395 & (1 << 31))
2396 return 1;
2397 return 0;
2398}
2399
2400static void stac92xx_hp_detect(struct hda_codec *codec, unsigned int res)
4e55096e
M		 2401{
2402 struct sigmatel_spec *spec = codec->spec;
2403 struct auto_pin_cfg *cfg = &spec->autocfg;
2404 int i, presence;
2405
eb06ed8f
TI		 2406 presence = 0;
2407 for (i = 0; i < cfg->hp_outs; i++) {
314634bc
TI		 2408 presence = get_pin_presence(codec, cfg->hp_pins[i]);
2409 if (presence)
2410 break;
eb06ed8f 2411 }
4e55096e
M		 2412
2413 if (presence) {
2414 /* disable lineouts, enable hp */
2415 for (i = 0; i < cfg->line_outs; i++)
2416 stac92xx_reset_pinctl(codec, cfg->line_out_pins[i],
2417 AC_PINCTL_OUT_EN);
eb06ed8f
TI		 2418 for (i = 0; i < cfg->speaker_outs; i++)
2419 stac92xx_reset_pinctl(codec, cfg->speaker_pins[i],
2420 AC_PINCTL_OUT_EN);
4e55096e
M		 2421 } else {
2422 /* enable lineouts, disable hp */
2423 for (i = 0; i < cfg->line_outs; i++)
2424 stac92xx_set_pinctl(codec, cfg->line_out_pins[i],
2425 AC_PINCTL_OUT_EN);
eb06ed8f
TI		 2426 for (i = 0; i < cfg->speaker_outs; i++)
2427 stac92xx_set_pinctl(codec, cfg->speaker_pins[i],
2428 AC_PINCTL_OUT_EN);
4e55096e
M		 2429 }
2430}
2431
314634bc
TI		 2432static void stac92xx_unsol_event(struct hda_codec *codec, unsigned int res)
2433{
2434 switch (res >> 26) {
2435 case STAC_HP_EVENT:
2436 stac92xx_hp_detect(codec, res);
2437 break;
2438 }
2439}
2440
cb53c626 2441#ifdef SND_HDA_NEEDS_RESUME
ff6fdc37
M		 2442static int stac92xx_resume(struct hda_codec *codec)
2443{
dc81bed1
TI		 2444 struct sigmatel_spec *spec = codec->spec;
2445
11b44bbd 2446 stac92xx_set_config_regs(codec);
dc81bed1
TI		 2447 snd_hda_sequence_write(codec, spec->init);
2448 if (spec->gpio_mute) {
2449 stac922x_gpio_mute(codec, 0, 0);
2450 stac922x_gpio_mute(codec, 1, 0);
2451 }
82beb8fd
TI		 2452 snd_hda_codec_resume_amp(codec);
2453 snd_hda_codec_resume_cache(codec);
dc81bed1
TI		 2454 /* invoke unsolicited event to reset the HP state */
2455 if (spec->hp_detect)
2456 codec->patch_ops.unsol_event(codec, STAC_HP_EVENT << 26);
ff6fdc37
M		 2457 return 0;
2458}
2459#endif
2460
2f2f4251
M		 2461static struct hda_codec_ops stac92xx_patch_ops = {
2462 .build_controls = stac92xx_build_controls,
2463 .build_pcms = stac92xx_build_pcms,
2464 .init = stac92xx_init,
2465 .free = stac92xx_free,
4e55096e 2466 .unsol_event = stac92xx_unsol_event,
cb53c626 2467#ifdef SND_HDA_NEEDS_RESUME
ff6fdc37
M		 2468 .resume = stac92xx_resume,
2469#endif
2f2f4251
M		 2470};
2471
2472static int patch_stac9200(struct hda_codec *codec)
2473{
2474 struct sigmatel_spec *spec;
c7d4b2fa 2475 int err;
2f2f4251 2476
e560d8d8 2477 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2f2f4251
M		 2478 if (spec == NULL)
2479 return -ENOMEM;
2480
2481 codec->spec = spec;
a4eed138 2482 spec->num_pins = ARRAY_SIZE(stac9200_pin_nids);
11b44bbd 2483 spec->pin_nids = stac9200_pin_nids;
f5fcc13c
TI		 2484 spec->board_config = snd_hda_check_board_config(codec, STAC_9200_MODELS,
2485 stac9200_models,
2486 stac9200_cfg_tbl);
11b44bbd
RF		 2487 if (spec->board_config < 0) {
2488 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC9200, using BIOS defaults\n");
2489 err = stac92xx_save_bios_config_regs(codec);
2490 if (err < 0) {
2491 stac92xx_free(codec);
2492 return err;
2493 }
2494 spec->pin_configs = spec->bios_pin_configs;
2495 } else {
403d1944
MP		 2496 spec->pin_configs = stac9200_brd_tbl[spec->board_config];
2497 stac92xx_set_config_regs(codec);
2498 }
2f2f4251
M		 2499
2500 spec->multiout.max_channels = 2;
2501 spec->multiout.num_dacs = 1;
2502 spec->multiout.dac_nids = stac9200_dac_nids;
2503 spec->adc_nids = stac9200_adc_nids;
2504 spec->mux_nids = stac9200_mux_nids;
dabbed6f 2505 spec->num_muxes = 1;
8b65727b 2506 spec->num_dmics = 0;
9e05b7a3 2507 spec->num_adcs = 1;
c7d4b2fa 2508
1194b5b7
TI		 2509 if (spec->board_config == STAC_9200_GATEWAY)
2510 spec->init = stac9200_eapd_init;
2511 else
2512 spec->init = stac9200_core_init;
2f2f4251 2513 spec->mixer = stac9200_mixer;
c7d4b2fa
M		 2514
2515 err = stac9200_parse_auto_config(codec);
2516 if (err < 0) {
2517 stac92xx_free(codec);
2518 return err;
2519 }
2f2f4251
M		 2520
2521 codec->patch_ops = stac92xx_patch_ops;
2522
2523 return 0;
2524}
2525
8e21c34c
TD		 2526static int patch_stac925x(struct hda_codec *codec)
2527{
2528 struct sigmatel_spec *spec;
2529 int err;
2530
2531 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2532 if (spec == NULL)
2533 return -ENOMEM;
2534
2535 codec->spec = spec;
a4eed138 2536 spec->num_pins = ARRAY_SIZE(stac925x_pin_nids);
8e21c34c
TD		 2537 spec->pin_nids = stac925x_pin_nids;
2538 spec->board_config = snd_hda_check_board_config(codec, STAC_925x_MODELS,
2539 stac925x_models,
2540 stac925x_cfg_tbl);
9e507abd 2541 again:
8e21c34c 2542 if (spec->board_config < 0) {
2c11f955
TD		 2543 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC925x,"
2544 "using BIOS defaults\n");
8e21c34c
TD		 2545 err = stac92xx_save_bios_config_regs(codec);
2546 if (err < 0) {
2547 stac92xx_free(codec);
2548 return err;
2549 }
2550 spec->pin_configs = spec->bios_pin_configs;
2551 } else if (stac925x_brd_tbl[spec->board_config] != NULL){
2552 spec->pin_configs = stac925x_brd_tbl[spec->board_config];
2553 stac92xx_set_config_regs(codec);
2554 }
2555
2556 spec->multiout.max_channels = 2;
2557 spec->multiout.num_dacs = 1;
2558 spec->multiout.dac_nids = stac925x_dac_nids;
2559 spec->adc_nids = stac925x_adc_nids;
2560 spec->mux_nids = stac925x_mux_nids;
2561 spec->num_muxes = 1;
9e05b7a3 2562 spec->num_adcs = 1;
2c11f955
TD		 2563 switch (codec->vendor_id) {
2564 case 0x83847632: /* STAC9202 */
2565 case 0x83847633: /* STAC9202D */
2566 case 0x83847636: /* STAC9251 */
2567 case 0x83847637: /* STAC9251D */
2568 spec->num_dmics = 1;
2569 spec->dmic_nids = stac925x_dmic_nids;
2570 break;
2571 default:
2572 spec->num_dmics = 0;
2573 break;
2574 }
8e21c34c
TD		 2575
2576 spec->init = stac925x_core_init;
2577 spec->mixer = stac925x_mixer;
2578
2579 err = stac92xx_parse_auto_config(codec, 0x8, 0x7);
9e507abd
TI		 2580 if (!err) {
2581 if (spec->board_config < 0) {
2582 printk(KERN_WARNING "hda_codec: No auto-config is "
2583 "available, default to model=ref\n");
2584 spec->board_config = STAC_925x_REF;
2585 goto again;
2586 }
2587 err = -EINVAL;
2588 }
8e21c34c
TD		 2589 if (err < 0) {
2590 stac92xx_free(codec);
2591 return err;
2592 }
2593
2594 codec->patch_ops = stac92xx_patch_ops;
2595
2596 return 0;
2597}
2598
2f2f4251
M		 2599static int patch_stac922x(struct hda_codec *codec)
2600{
2601 struct sigmatel_spec *spec;
c7d4b2fa 2602 int err;
2f2f4251 2603
e560d8d8 2604 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2f2f4251
M		 2605 if (spec == NULL)
2606 return -ENOMEM;
2607
2608 codec->spec = spec;
a4eed138 2609 spec->num_pins = ARRAY_SIZE(stac922x_pin_nids);
11b44bbd 2610 spec->pin_nids = stac922x_pin_nids;
f5fcc13c
TI		 2611 spec->board_config = snd_hda_check_board_config(codec, STAC_922X_MODELS,
2612 stac922x_models,
2613 stac922x_cfg_tbl);
5d5d3bc3 2614 if (spec->board_config == STAC_INTEL_MAC_V3) {
3fc24d85
TI		 2615 spec->gpio_mute = 1;
2616 /* Intel Macs have all same PCI SSID, so we need to check
2617 * codec SSID to distinguish the exact models
2618 */
6f0778d8 2619 printk(KERN_INFO "hda_codec: STAC922x, Apple subsys_id=%x\n", codec->subsystem_id);
3fc24d85 2620 switch (codec->subsystem_id) {
5d5d3bc3
IZ		 2621
2622 case 0x106b0800:
2623 spec->board_config = STAC_INTEL_MAC_V1;
c45e20eb 2624 break;
5d5d3bc3
IZ		 2625 case 0x106b0600:
2626 case 0x106b0700:
2627 spec->board_config = STAC_INTEL_MAC_V2;
6f0778d8 2628 break;
5d5d3bc3
IZ		 2629 case 0x106b0e00:
2630 case 0x106b0f00:
2631 case 0x106b1600:
2632 case 0x106b1700:
2633 case 0x106b0200:
2634 case 0x106b1e00:
2635 spec->board_config = STAC_INTEL_MAC_V3;
3fc24d85 2636 break;
5d5d3bc3
IZ		 2637 case 0x106b1a00:
2638 case 0x00000100:
2639 spec->board_config = STAC_INTEL_MAC_V4;
f16928fb 2640 break;
5d5d3bc3
IZ		 2641 case 0x106b0a00:
2642 case 0x106b2200:
2643 spec->board_config = STAC_INTEL_MAC_V5;
0dae0f83 2644 break;
3fc24d85
TI		 2645 }
2646 }
2647
9e507abd 2648 again:
11b44bbd
RF		 2649 if (spec->board_config < 0) {
2650 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC922x, "
2651 "using BIOS defaults\n");
2652 err = stac92xx_save_bios_config_regs(codec);
2653 if (err < 0) {
2654 stac92xx_free(codec);
2655 return err;
2656 }
2657 spec->pin_configs = spec->bios_pin_configs;
2658 } else if (stac922x_brd_tbl[spec->board_config] != NULL) {
403d1944
MP		 2659 spec->pin_configs = stac922x_brd_tbl[spec->board_config];
2660 stac92xx_set_config_regs(codec);
2661 }
2f2f4251 2662
c7d4b2fa
M		 2663 spec->adc_nids = stac922x_adc_nids;
2664 spec->mux_nids = stac922x_mux_nids;
2549413e 2665 spec->num_muxes = ARRAY_SIZE(stac922x_mux_nids);
9e05b7a3 2666 spec->num_adcs = ARRAY_SIZE(stac922x_adc_nids);
8b65727b 2667 spec->num_dmics = 0;
c7d4b2fa
M		 2668
2669 spec->init = stac922x_core_init;
2f2f4251 2670 spec->mixer = stac922x_mixer;
c7d4b2fa
M		 2671
2672 spec->multiout.dac_nids = spec->dac_nids;
19039bd0 2673
3cc08dc6 2674 err = stac92xx_parse_auto_config(codec, 0x08, 0x09);
9e507abd
TI		 2675 if (!err) {
2676 if (spec->board_config < 0) {
2677 printk(KERN_WARNING "hda_codec: No auto-config is "
2678 "available, default to model=ref\n");
2679 spec->board_config = STAC_D945_REF;
2680 goto again;
2681 }
2682 err = -EINVAL;
2683 }
3cc08dc6
MP		 2684 if (err < 0) {
2685 stac92xx_free(codec);
2686 return err;
2687 }
2688
2689 codec->patch_ops = stac92xx_patch_ops;
2690
807a4636
TI		 2691 /* Fix Mux capture level; max to 2 */
2692 snd_hda_override_amp_caps(codec, 0x12, HDA_OUTPUT,
2693 (0 << AC_AMPCAP_OFFSET_SHIFT) |
2694 (2 << AC_AMPCAP_NUM_STEPS_SHIFT) |
2695 (0x27 << AC_AMPCAP_STEP_SIZE_SHIFT) |
2696 (0 << AC_AMPCAP_MUTE_SHIFT));
2697
3cc08dc6
MP		 2698 return 0;
2699}
2700
2701static int patch_stac927x(struct hda_codec *codec)
2702{
2703 struct sigmatel_spec *spec;
2704 int err;
2705
2706 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2707 if (spec == NULL)
2708 return -ENOMEM;
2709
2710 codec->spec = spec;
a4eed138 2711 spec->num_pins = ARRAY_SIZE(stac927x_pin_nids);
11b44bbd 2712 spec->pin_nids = stac927x_pin_nids;
f5fcc13c
TI		 2713 spec->board_config = snd_hda_check_board_config(codec, STAC_927X_MODELS,
2714 stac927x_models,
2715 stac927x_cfg_tbl);
9e507abd 2716 again:
11b44bbd 2717 if (spec->board_config < 0) {
3cc08dc6 2718 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC927x, using BIOS defaults\n");
11b44bbd
RF		 2719 err = stac92xx_save_bios_config_regs(codec);
2720 if (err < 0) {
2721 stac92xx_free(codec);
2722 return err;
2723 }
2724 spec->pin_configs = spec->bios_pin_configs;
2725 } else if (stac927x_brd_tbl[spec->board_config] != NULL) {
3cc08dc6
MP		 2726 spec->pin_configs = stac927x_brd_tbl[spec->board_config];
2727 stac92xx_set_config_regs(codec);
2728 }
2729
81d3dbde 2730 switch (spec->board_config) {
93ed1503 2731 case STAC_D965_3ST:
81d3dbde
TD		 2732 spec->adc_nids = stac927x_adc_nids;
2733 spec->mux_nids = stac927x_mux_nids;
2549413e 2734 spec->num_muxes = ARRAY_SIZE(stac927x_mux_nids);
9e05b7a3 2735 spec->num_adcs = ARRAY_SIZE(stac927x_adc_nids);
8b65727b 2736 spec->num_dmics = 0;
93ed1503 2737 spec->init = d965_core_init;
9e05b7a3 2738 spec->mixer = stac927x_mixer;
81d3dbde 2739 break;
93ed1503
TD		 2740 case STAC_D965_5ST:
2741 spec->adc_nids = stac927x_adc_nids;
2742 spec->mux_nids = stac927x_mux_nids;
2549413e 2743 spec->num_muxes = ARRAY_SIZE(stac927x_mux_nids);
9e05b7a3 2744 spec->num_adcs = ARRAY_SIZE(stac927x_adc_nids);
8b65727b 2745 spec->num_dmics = 0;
93ed1503 2746 spec->init = d965_core_init;
9e05b7a3 2747 spec->mixer = stac927x_mixer;
81d3dbde
TD		 2748 break;
2749 default:
2750 spec->adc_nids = stac927x_adc_nids;
2751 spec->mux_nids = stac927x_mux_nids;
2549413e 2752 spec->num_muxes = ARRAY_SIZE(stac927x_mux_nids);
9e05b7a3 2753 spec->num_adcs = ARRAY_SIZE(stac927x_adc_nids);
8b65727b 2754 spec->num_dmics = 0;
81d3dbde
TD		 2755 spec->init = stac927x_core_init;
2756 spec->mixer = stac927x_mixer;
2757 }
3cc08dc6
MP		 2758
2759 spec->multiout.dac_nids = spec->dac_nids;
87d48363 2760 /* GPIO0 High = Enable EAPD */
8259980e
TI		 2761 spec->gpio_mask = spec->gpio_data = 0x00000001;
2762 stac92xx_enable_gpio_mask(codec);
92a22beb 2763
3cc08dc6 2764 err = stac92xx_parse_auto_config(codec, 0x1e, 0x20);
9e507abd
TI		 2765 if (!err) {
2766 if (spec->board_config < 0) {
2767 printk(KERN_WARNING "hda_codec: No auto-config is "
2768 "available, default to model=ref\n");
2769 spec->board_config = STAC_D965_REF;
2770 goto again;
2771 }
2772 err = -EINVAL;
2773 }
c7d4b2fa
M		 2774 if (err < 0) {
2775 stac92xx_free(codec);
2776 return err;
2777 }
2f2f4251
M		 2778
2779 codec->patch_ops = stac92xx_patch_ops;
2780
2781 return 0;
2782}
2783
f3302a59
MP		 2784static int patch_stac9205(struct hda_codec *codec)
2785{
2786 struct sigmatel_spec *spec;
8259980e 2787 int err;
f3302a59
MP		 2788
2789 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2790 if (spec == NULL)
2791 return -ENOMEM;
2792
2793 codec->spec = spec;
a4eed138 2794 spec->num_pins = ARRAY_SIZE(stac9205_pin_nids);
11b44bbd 2795 spec->pin_nids = stac9205_pin_nids;
f5fcc13c
TI		 2796 spec->board_config = snd_hda_check_board_config(codec, STAC_9205_MODELS,
2797 stac9205_models,
2798 stac9205_cfg_tbl);
9e507abd 2799 again:
11b44bbd
RF		 2800 if (spec->board_config < 0) {
2801 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC9205, using BIOS defaults\n");
2802 err = stac92xx_save_bios_config_regs(codec);
2803 if (err < 0) {
2804 stac92xx_free(codec);
2805 return err;
2806 }
2807 spec->pin_configs = spec->bios_pin_configs;
2808 } else {
f3302a59
MP		 2809 spec->pin_configs = stac9205_brd_tbl[spec->board_config];
2810 stac92xx_set_config_regs(codec);
2811 }
2812
2813 spec->adc_nids = stac9205_adc_nids;
9e05b7a3 2814 spec->num_adcs = ARRAY_SIZE(stac9205_adc_nids);
f3302a59 2815 spec->mux_nids = stac9205_mux_nids;
2549413e 2816 spec->num_muxes = ARRAY_SIZE(stac9205_mux_nids);
8b65727b 2817 spec->dmic_nids = stac9205_dmic_nids;
2549413e 2818 spec->num_dmics = ARRAY_SIZE(stac9205_dmic_nids);
8b65727b 2819 spec->dmux_nid = 0x1d;
f3302a59
MP		 2820
2821 spec->init = stac9205_core_init;
2822 spec->mixer = stac9205_mixer;
2823
2824 spec->multiout.dac_nids = spec->dac_nids;
87d48363 2825
ae0a8ed8 2826 switch (spec->board_config){
ae0a8ed8 2827 case STAC_9205_DELL_M43:
87d48363
MR		 2828 /* Enable SPDIF in/out */
2829 stac92xx_set_config_reg(codec, 0x1f, 0x01441030);
2830 stac92xx_set_config_reg(codec, 0x20, 0x1c410030);
2831
8259980e 2832 spec->gpio_mask = 0x00000007; /* GPIO0-2 */
87d48363
MR		 2833 /* GPIO0 High = EAPD, GPIO1 Low = DRM,
2834 * GPIO2 High = Headphone Mute
2835 */
8259980e 2836 spec->gpio_data = 0x00000005;
ae0a8ed8
TD		 2837 break;
2838 default:
2839 /* GPIO0 High = EAPD */
2840 spec->gpio_mask = spec->gpio_data = 0x00000001;
2841 break;
2842 }
33382403 2843
8259980e 2844 stac92xx_enable_gpio_mask(codec);
f3302a59 2845 err = stac92xx_parse_auto_config(codec, 0x1f, 0x20);
9e507abd
TI		 2846 if (!err) {
2847 if (spec->board_config < 0) {
2848 printk(KERN_WARNING "hda_codec: No auto-config is "
2849 "available, default to model=ref\n");
2850 spec->board_config = STAC_9205_REF;
2851 goto again;
2852 }
2853 err = -EINVAL;
2854 }
f3302a59
MP		 2855 if (err < 0) {
2856 stac92xx_free(codec);
2857 return err;
2858 }
2859
2860 codec->patch_ops = stac92xx_patch_ops;
2861
2862 return 0;
2863}
2864
db064e50 2865/*
6d859065 2866 * STAC9872 hack
db064e50
TI		 2867 */
2868
99ccc560 2869/* static config for Sony VAIO FE550G and Sony VAIO AR */
db064e50
TI		 2870static hda_nid_t vaio_dacs[] = { 0x2 };
2871#define VAIO_HP_DAC 0x5
2872static hda_nid_t vaio_adcs[] = { 0x8 /*,0x6*/ };
2873static hda_nid_t vaio_mux_nids[] = { 0x15 };
2874
2875static struct hda_input_mux vaio_mux = {
2876 .num_items = 2,
2877 .items = {
d773781c 2878 /* { "HP", 0x0 }, */
1624cb9a
TI		 2879 { "Mic Jack", 0x1 },
2880 { "Internal Mic", 0x2 },
db064e50
TI		 2881 { "PCM", 0x3 },
2882 }
2883};
2884
2885static struct hda_verb vaio_init[] = {
2886 {0x0a, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP }, /* HP <- 0x2 */
72e7b0dd 2887 {0x0a, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | STAC_HP_EVENT},
db064e50
TI		 2888 {0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, /* Speaker <- 0x5 */
2889 {0x0d, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? (<- 0x2) */
2890 {0x0e, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_IN }, /* CD */
2891 {0x14, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? */
1624cb9a 2892 {0x15, AC_VERB_SET_CONNECT_SEL, 0x1}, /* mic-sel: 0a,0d,14,02 */
db064e50
TI		 2893 {0x02, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* HP */
2894 {0x05, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* Speaker */
2895 {0x09, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_MUTE(0)}, /* capture sw/vol -> 0x8 */
2896 {0x07, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, /* CD-in -> 0x6 */
2897 {0x15, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE}, /* Mic-in -> 0x9 */
2898 {}
2899};
2900
6d859065
GM		 2901static struct hda_verb vaio_ar_init[] = {
2902 {0x0a, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP }, /* HP <- 0x2 */
2903 {0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, /* Speaker <- 0x5 */
2904 {0x0d, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? (<- 0x2) */
2905 {0x0e, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_IN }, /* CD */
2906/* {0x11, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },*/ /* Optical Out */
2907 {0x14, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? */
1624cb9a 2908 {0x15, AC_VERB_SET_CONNECT_SEL, 0x1}, /* mic-sel: 0a,0d,14,02 */
6d859065
GM		 2909 {0x02, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* HP */
2910 {0x05, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* Speaker */
2911/* {0x10, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE},*/ /* Optical Out */
2912 {0x09, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_MUTE(0)}, /* capture sw/vol -> 0x8 */
2913 {0x07, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, /* CD-in -> 0x6 */
2914 {0x15, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE}, /* Mic-in -> 0x9 */
2915 {}
2916};
2917
db064e50 2918/* bind volumes of both NID 0x02 and 0x05 */
cca3b371
TI		 2919static struct hda_bind_ctls vaio_bind_master_vol = {
2920 .ops = &snd_hda_bind_vol,
2921 .values = {
2922 HDA_COMPOSE_AMP_VAL(0x02, 3, 0, HDA_OUTPUT),
2923 HDA_COMPOSE_AMP_VAL(0x05, 3, 0, HDA_OUTPUT),
2924 0
2925 },
2926};
db064e50
TI		 2927
2928/* bind volumes of both NID 0x02 and 0x05 */
cca3b371
TI		 2929static struct hda_bind_ctls vaio_bind_master_sw = {
2930 .ops = &snd_hda_bind_sw,
2931 .values = {
2932 HDA_COMPOSE_AMP_VAL(0x02, 3, 0, HDA_OUTPUT),
2933 HDA_COMPOSE_AMP_VAL(0x05, 3, 0, HDA_OUTPUT),
2934 0,
2935 },
2936};
db064e50
TI		 2937
2938static struct snd_kcontrol_new vaio_mixer[] = {
cca3b371
TI		 2939 HDA_BIND_VOL("Master Playback Volume", &vaio_bind_master_vol),
2940 HDA_BIND_SW("Master Playback Switch", &vaio_bind_master_sw),
db064e50
TI		 2941 /* HDA_CODEC_VOLUME("CD Capture Volume", 0x07, 0, HDA_INPUT), */
2942 HDA_CODEC_VOLUME("Capture Volume", 0x09, 0, HDA_INPUT),
2943 HDA_CODEC_MUTE("Capture Switch", 0x09, 0, HDA_INPUT),
2944 {
2945 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2946 .name = "Capture Source",
2947 .count = 1,
2948 .info = stac92xx_mux_enum_info,
2949 .get = stac92xx_mux_enum_get,
2950 .put = stac92xx_mux_enum_put,
2951 },
2952 {}
2953};
2954
6d859065 2955static struct snd_kcontrol_new vaio_ar_mixer[] = {
cca3b371
TI		 2956 HDA_BIND_VOL("Master Playback Volume", &vaio_bind_master_vol),
2957 HDA_BIND_SW("Master Playback Switch", &vaio_bind_master_sw),
6d859065
GM		 2958 /* HDA_CODEC_VOLUME("CD Capture Volume", 0x07, 0, HDA_INPUT), */
2959 HDA_CODEC_VOLUME("Capture Volume", 0x09, 0, HDA_INPUT),
2960 HDA_CODEC_MUTE("Capture Switch", 0x09, 0, HDA_INPUT),
2961 /*HDA_CODEC_MUTE("Optical Out Switch", 0x10, 0, HDA_OUTPUT),
2962 HDA_CODEC_VOLUME("Optical Out Volume", 0x10, 0, HDA_OUTPUT),*/
2963 {
2964 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2965 .name = "Capture Source",
2966 .count = 1,
2967 .info = stac92xx_mux_enum_info,
2968 .get = stac92xx_mux_enum_get,
2969 .put = stac92xx_mux_enum_put,
2970 },
2971 {}
2972};
2973
2974static struct hda_codec_ops stac9872_patch_ops = {
db064e50
TI		 2975 .build_controls = stac92xx_build_controls,
2976 .build_pcms = stac92xx_build_pcms,
2977 .init = stac92xx_init,
2978 .free = stac92xx_free,
cb53c626 2979#ifdef SND_HDA_NEEDS_RESUME
db064e50
TI		 2980 .resume = stac92xx_resume,
2981#endif
2982};
2983
72e7b0dd
TI		 2984static int stac9872_vaio_init(struct hda_codec *codec)
2985{
2986 int err;
2987
2988 err = stac92xx_init(codec);
2989 if (err < 0)
2990 return err;
2991 if (codec->patch_ops.unsol_event)
2992 codec->patch_ops.unsol_event(codec, STAC_HP_EVENT << 26);
2993 return 0;
2994}
2995
2996static void stac9872_vaio_hp_detect(struct hda_codec *codec, unsigned int res)
2997{
2998 if (get_pin_presence(codec, 0x0a)) {
2999 stac92xx_reset_pinctl(codec, 0x0f, AC_PINCTL_OUT_EN);
3000 stac92xx_set_pinctl(codec, 0x0a, AC_PINCTL_OUT_EN);
3001 } else {
3002 stac92xx_reset_pinctl(codec, 0x0a, AC_PINCTL_OUT_EN);
3003 stac92xx_set_pinctl(codec, 0x0f, AC_PINCTL_OUT_EN);
3004 }
3005}
3006
3007static void stac9872_vaio_unsol_event(struct hda_codec *codec, unsigned int res)
3008{
3009 switch (res >> 26) {
3010 case STAC_HP_EVENT:
3011 stac9872_vaio_hp_detect(codec, res);
3012 break;
3013 }
3014}
3015
3016static struct hda_codec_ops stac9872_vaio_patch_ops = {
3017 .build_controls = stac92xx_build_controls,
3018 .build_pcms = stac92xx_build_pcms,
3019 .init = stac9872_vaio_init,
3020 .free = stac92xx_free,
3021 .unsol_event = stac9872_vaio_unsol_event,
3022#ifdef CONFIG_PM
3023 .resume = stac92xx_resume,
3024#endif
3025};
3026
6d859065
GM		 3027enum { /* FE and SZ series. id=0x83847661 and subsys=0x104D0700 or 104D1000. */
3028 CXD9872RD_VAIO,
3029 /* Unknown. id=0x83847662 and subsys=0x104D1200 or 104D1000. */
3030 STAC9872AK_VAIO,
3031 /* Unknown. id=0x83847661 and subsys=0x104D1200. */
3032 STAC9872K_VAIO,
3033 /* AR Series. id=0x83847664 and subsys=104D1300 */
f5fcc13c
TI		 3034 CXD9872AKD_VAIO,
3035 STAC_9872_MODELS,
3036};
3037
3038static const char *stac9872_models[STAC_9872_MODELS] = {
3039 [CXD9872RD_VAIO] = "vaio",
3040 [CXD9872AKD_VAIO] = "vaio-ar",
3041};
3042
3043static struct snd_pci_quirk stac9872_cfg_tbl[] = {
3044 SND_PCI_QUIRK(0x104d, 0x81e6, "Sony VAIO F/S", CXD9872RD_VAIO),
3045 SND_PCI_QUIRK(0x104d, 0x81ef, "Sony VAIO F/S", CXD9872RD_VAIO),
3046 SND_PCI_QUIRK(0x104d, 0x81fd, "Sony VAIO AR", CXD9872AKD_VAIO),
68e22543 3047 SND_PCI_QUIRK(0x104d, 0x8205, "Sony VAIO AR", CXD9872AKD_VAIO),
db064e50
TI		 3048 {}
3049};
3050
6d859065 3051static int patch_stac9872(struct hda_codec *codec)
db064e50
TI		 3052{
3053 struct sigmatel_spec *spec;
3054 int board_config;
3055
f5fcc13c
TI		 3056 board_config = snd_hda_check_board_config(codec, STAC_9872_MODELS,
3057 stac9872_models,
3058 stac9872_cfg_tbl);
db064e50
TI		 3059 if (board_config < 0)
3060 /* unknown config, let generic-parser do its job... */
3061 return snd_hda_parse_generic_codec(codec);
3062
3063 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3064 if (spec == NULL)
3065 return -ENOMEM;
3066
3067 codec->spec = spec;
3068 switch (board_config) {
6d859065
GM		 3069 case CXD9872RD_VAIO:
3070 case STAC9872AK_VAIO:
3071 case STAC9872K_VAIO:
db064e50
TI		 3072 spec->mixer = vaio_mixer;
3073 spec->init = vaio_init;
3074 spec->multiout.max_channels = 2;
3075 spec->multiout.num_dacs = ARRAY_SIZE(vaio_dacs);
3076 spec->multiout.dac_nids = vaio_dacs;
3077 spec->multiout.hp_nid = VAIO_HP_DAC;
3078 spec->num_adcs = ARRAY_SIZE(vaio_adcs);
3079 spec->adc_nids = vaio_adcs;
3080 spec->input_mux = &vaio_mux;
3081 spec->mux_nids = vaio_mux_nids;
72e7b0dd 3082 codec->patch_ops = stac9872_vaio_patch_ops;
db064e50 3083 break;
6d859065
GM		 3084
3085 case CXD9872AKD_VAIO:
3086 spec->mixer = vaio_ar_mixer;
3087 spec->init = vaio_ar_init;
3088 spec->multiout.max_channels = 2;
3089 spec->multiout.num_dacs = ARRAY_SIZE(vaio_dacs);
3090 spec->multiout.dac_nids = vaio_dacs;
3091 spec->multiout.hp_nid = VAIO_HP_DAC;
3092 spec->num_adcs = ARRAY_SIZE(vaio_adcs);
3093 spec->adc_nids = vaio_adcs;
3094 spec->input_mux = &vaio_mux;
3095 spec->mux_nids = vaio_mux_nids;
72e7b0dd 3096 codec->patch_ops = stac9872_patch_ops;
6d859065 3097 break;
db064e50
TI		 3098 }
3099
db064e50
TI		 3100 return 0;
3101}
3102
3103
2f2f4251
M		 3104/*
3105 * patch entries
3106 */
3107struct hda_codec_preset snd_hda_preset_sigmatel[] = {
3108 { .id = 0x83847690, .name = "STAC9200", .patch = patch_stac9200 },
3109 { .id = 0x83847882, .name = "STAC9220 A1", .patch = patch_stac922x },
3110 { .id = 0x83847680, .name = "STAC9221 A1", .patch = patch_stac922x },
3111 { .id = 0x83847880, .name = "STAC9220 A2", .patch = patch_stac922x },
3112 { .id = 0x83847681, .name = "STAC9220D/9223D A2", .patch = patch_stac922x },
3113 { .id = 0x83847682, .name = "STAC9221 A2", .patch = patch_stac922x },
3114 { .id = 0x83847683, .name = "STAC9221D A2", .patch = patch_stac922x },
22a27c7f
MP		 3115 { .id = 0x83847618, .name = "STAC9227", .patch = patch_stac927x },
3116 { .id = 0x83847619, .name = "STAC9227", .patch = patch_stac927x },
3117 { .id = 0x83847616, .name = "STAC9228", .patch = patch_stac927x },
3118 { .id = 0x83847617, .name = "STAC9228", .patch = patch_stac927x },
3119 { .id = 0x83847614, .name = "STAC9229", .patch = patch_stac927x },
3120 { .id = 0x83847615, .name = "STAC9229", .patch = patch_stac927x },
3cc08dc6
MP		 3121 { .id = 0x83847620, .name = "STAC9274", .patch = patch_stac927x },
3122 { .id = 0x83847621, .name = "STAC9274D", .patch = patch_stac927x },
3123 { .id = 0x83847622, .name = "STAC9273X", .patch = patch_stac927x },
3124 { .id = 0x83847623, .name = "STAC9273D", .patch = patch_stac927x },
3125 { .id = 0x83847624, .name = "STAC9272X", .patch = patch_stac927x },
3126 { .id = 0x83847625, .name = "STAC9272D", .patch = patch_stac927x },
3127 { .id = 0x83847626, .name = "STAC9271X", .patch = patch_stac927x },
3128 { .id = 0x83847627, .name = "STAC9271D", .patch = patch_stac927x },
3129 { .id = 0x83847628, .name = "STAC9274X5NH", .patch = patch_stac927x },
3130 { .id = 0x83847629, .name = "STAC9274D5NH", .patch = patch_stac927x },
8e21c34c
TD		 3131 { .id = 0x83847632, .name = "STAC9202", .patch = patch_stac925x },
3132 { .id = 0x83847633, .name = "STAC9202D", .patch = patch_stac925x },
3133 { .id = 0x83847634, .name = "STAC9250", .patch = patch_stac925x },
3134 { .id = 0x83847635, .name = "STAC9250D", .patch = patch_stac925x },
3135 { .id = 0x83847636, .name = "STAC9251", .patch = patch_stac925x },
3136 { .id = 0x83847637, .name = "STAC9250D", .patch = patch_stac925x },
6d859065
GM		 3137 /* The following does not take into account .id=0x83847661 when subsys =
3138 * 104D0C00 which is STAC9225s. Because of this, some SZ Notebooks are
3139 * currently not fully supported.
3140 */
3141 { .id = 0x83847661, .name = "CXD9872RD/K", .patch = patch_stac9872 },
3142 { .id = 0x83847662, .name = "STAC9872AK", .patch = patch_stac9872 },
3143 { .id = 0x83847664, .name = "CXD9872AKD", .patch = patch_stac9872 },
f3302a59
MP		 3144 { .id = 0x838476a0, .name = "STAC9205", .patch = patch_stac9205 },
3145 { .id = 0x838476a1, .name = "STAC9205D", .patch = patch_stac9205 },
3146 { .id = 0x838476a2, .name = "STAC9204", .patch = patch_stac9205 },
3147 { .id = 0x838476a3, .name = "STAC9204D", .patch = patch_stac9205 },
3148 { .id = 0x838476a4, .name = "STAC9255", .patch = patch_stac9205 },
3149 { .id = 0x838476a5, .name = "STAC9255D", .patch = patch_stac9205 },
3150 { .id = 0x838476a6, .name = "STAC9254", .patch = patch_stac9205 },
3151 { .id = 0x838476a7, .name = "STAC9254D", .patch = patch_stac9205 },
2f2f4251
M		 3152 {} /* terminator */
3153};
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