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ALSA: intelhdmi - sticky infoframe
[net-next-2.6.git] / sound / pci / hda / patch_intelhdmi.c
CommitLineData
91504877
WF		 1/*
2 *
3 * patch_intelhdmi.c - Patch for Intel HDMI codecs
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * Authors:
8 * Jiang Zhe <zhe.jiang@intel.com>
9 * Wu Fengguang <wfg@linux.intel.com>
10 *
11 * Maintained by:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the Free
16 * Software Foundation; either version 2 of the License, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
21 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 * for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software Foundation,
26 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32#include <sound/core.h>
91504877
WF		 33#include "hda_codec.h"
34#include "hda_local.h"
91504877 35
54a25f87
WF		 36/*
37 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
38 * could support two independent pipes, each of them can be connected to one or
39 * more ports (DVI, HDMI or DisplayPort).
40 *
41 * The HDA correspondence of pipes/ports are converter/pin nodes.
42 */
43#define INTEL_HDMI_CVTS 2
44#define INTEL_HDMI_PINS 3
91504877 45
54a25f87
WF		 46static char *intel_hdmi_pcm_names[INTEL_HDMI_CVTS] = {
47 "INTEL HDMI 0",
48 "INTEL HDMI 1",
49};
91504877 50
91504877 51struct intel_hdmi_spec {
54a25f87
WF		 52 int num_cvts;
53 int num_pins;
54 hda_nid_t cvt[INTEL_HDMI_CVTS+1]; /* audio sources */
55 hda_nid_t pin[INTEL_HDMI_PINS+1]; /* audio sinks */
56
57 /*
58 * source connection for each pin
59 */
60 hda_nid_t pin_cvt[INTEL_HDMI_PINS+1];
61
62 /*
63 * HDMI sink attached to each pin
64 */
54a25f87
WF		 65 struct hdmi_eld sink_eld[INTEL_HDMI_PINS];
66
67 /*
68 * export one pcm per pipe
69 */
70 struct hda_pcm pcm_rec[INTEL_HDMI_CVTS];
91504877
WF		 71};
72
91504877
WF		 73struct hdmi_audio_infoframe {
74 u8 type; /* 0x84 */
75 u8 ver; /* 0x01 */
76 u8 len; /* 0x0a */
77
78 u8 checksum; /* PB0 */
79 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
80 u8 SS01_SF24;
81 u8 CXT04;
82 u8 CA;
83 u8 LFEPBL01_LSV36_DM_INH7;
4e19c58f 84 u8 reserved[5]; /* PB6 - PB10 */
91504877
WF		 85};
86
698544de
WF		 87/*
88 * CEA speaker placement:
89 *
90 * FLH FCH FRH
91 * FLW FL FLC FC FRC FR FRW
92 *
93 * LFE
94 * TC
95 *
96 * RL RLC RC RRC RR
97 *
98 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
99 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
100 */
101enum cea_speaker_placement {
102 FL = (1 << 0), /* Front Left */
103 FC = (1 << 1), /* Front Center */
104 FR = (1 << 2), /* Front Right */
105 FLC = (1 << 3), /* Front Left Center */
106 FRC = (1 << 4), /* Front Right Center */
107 RL = (1 << 5), /* Rear Left */
108 RC = (1 << 6), /* Rear Center */
109 RR = (1 << 7), /* Rear Right */
110 RLC = (1 << 8), /* Rear Left Center */
111 RRC = (1 << 9), /* Rear Right Center */
112 LFE = (1 << 10), /* Low Frequency Effect */
113 FLW = (1 << 11), /* Front Left Wide */
114 FRW = (1 << 12), /* Front Right Wide */
115 FLH = (1 << 13), /* Front Left High */
116 FCH = (1 << 14), /* Front Center High */
117 FRH = (1 << 15), /* Front Right High */
118 TC = (1 << 16), /* Top Center */
119};
120
121/*
122 * ELD SA bits in the CEA Speaker Allocation data block
123 */
124static int eld_speaker_allocation_bits[] = {
125 [0] = FL | FR,
126 [1] = LFE,
127 [2] = FC,
128 [3] = RL | RR,
129 [4] = RC,
130 [5] = FLC | FRC,
131 [6] = RLC | RRC,
132 /* the following are not defined in ELD yet */
133 [7] = FLW | FRW,
134 [8] = FLH | FRH,
135 [9] = TC,
136 [10] = FCH,
137};
138
139struct cea_channel_speaker_allocation {
140 int ca_index;
141 int speakers[8];
142
143 /* derived values, just for convenience */
144 int channels;
145 int spk_mask;
146};
147
148/*
149 * This is an ordered list!
150 *
151 * The preceding ones have better chances to be selected by
152 * hdmi_setup_channel_allocation().
153 */
154static struct cea_channel_speaker_allocation channel_allocations[] = {
155/* channel: 8 7 6 5 4 3 2 1 */
156{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
157 /* 2.1 */
158{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
4e19c58f 159 /* Dolby Surround */
698544de
WF		 160{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
161{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
162{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
163{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
164{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
165{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
166{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
167{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
168{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
169 /* 5.1 */
170{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
171{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
172{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
173{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
174 /* 6.1 */
175{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
176{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
177{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
178{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
179 /* 7.1 */
180{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
181{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
182{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
183{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
184{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
185{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
186{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
187{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
188{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
189{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
190{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
191{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
192{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
193{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
194{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
195{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
196{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
197{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
198{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
199{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
200{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
201{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
202{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
203{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
204{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
205{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
206{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
207{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
208{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
209{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
210{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
211};
212
54a25f87 213
f424367c
WF		 214/*
215 * HDA/HDMI auto parsing
216 */
217
54a25f87
WF		 218static int hda_node_index(hda_nid_t *nids, hda_nid_t nid)
219{
220 int i;
221
222 for (i = 0; nids[i]; i++)
223 if (nids[i] == nid)
224 return i;
225
226 snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid);
227 return -EINVAL;
228}
229
f424367c
WF		 230static int intel_hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid)
231{
232 struct intel_hdmi_spec *spec = codec->spec;
233 hda_nid_t conn_list[HDA_MAX_CONNECTIONS];
234 int conn_len, curr;
235 int index;
236
237 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
238 snd_printk(KERN_WARNING
239 "HDMI: pin %d wcaps %#x "
240 "does not support connection list\n",
241 pin_nid, get_wcaps(codec, pin_nid));
242 return -EINVAL;
243 }
244
245 conn_len = snd_hda_get_connections(codec, pin_nid, conn_list,
246 HDA_MAX_CONNECTIONS);
247 if (conn_len > 1)
248 curr = snd_hda_codec_read(codec, pin_nid, 0,
249 AC_VERB_GET_CONNECT_SEL, 0);
250 else
251 curr = 0;
252
253 index = hda_node_index(spec->pin, pin_nid);
254 if (index < 0)
255 return -EINVAL;
256
257 spec->pin_cvt[index] = conn_list[curr];
258
259 return 0;
260}
261
3f54aa50
WF		 262static void hdmi_get_show_eld(struct hda_codec *codec, hda_nid_t pin_nid,
263 struct hdmi_eld *eld)
264{
265 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
266 snd_hdmi_show_eld(eld);
267}
268
269static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
270 struct hdmi_eld *eld)
271{
272 int present = snd_hda_pin_sense(codec, pin_nid);
273
274 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
275 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
276
277 if (present & AC_PINSENSE_ELDV)
278 hdmi_get_show_eld(codec, pin_nid, eld);
279}
280
f424367c
WF		 281static int intel_hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
282{
283 struct intel_hdmi_spec *spec = codec->spec;
284
285 if (spec->num_pins >= INTEL_HDMI_PINS) {
286 snd_printk(KERN_WARNING
287 "HDMI: no space for pin %d \n", pin_nid);
288 return -EINVAL;
289 }
290
3f54aa50
WF		 291 hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]);
292
f424367c
WF		 293 spec->pin[spec->num_pins] = pin_nid;
294 spec->num_pins++;
295
296 /*
297 * It is assumed that converter nodes come first in the node list and
298 * hence have been registered and usable now.
299 */
300 return intel_hdmi_read_pin_conn(codec, pin_nid);
301}
302
303static int intel_hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid)
304{
305 struct intel_hdmi_spec *spec = codec->spec;
306
307 if (spec->num_cvts >= INTEL_HDMI_CVTS) {
308 snd_printk(KERN_WARNING
309 "HDMI: no space for converter %d \n", nid);
310 return -EINVAL;
311 }
312
313 spec->cvt[spec->num_cvts] = nid;
314 spec->num_cvts++;
315
316 return 0;
317}
318
319static int intel_hdmi_parse_codec(struct hda_codec *codec)
320{
321 hda_nid_t nid;
322 int i, nodes;
323
324 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
325 if (!nid || nodes < 0) {
326 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
327 return -EINVAL;
328 }
329
330 for (i = 0; i < nodes; i++, nid++) {
331 unsigned int caps;
332 unsigned int type;
333
334 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
335 type = get_wcaps_type(caps);
336
337 if (!(caps & AC_WCAP_DIGITAL))
338 continue;
339
340 switch (type) {
341 case AC_WID_AUD_OUT:
342 if (intel_hdmi_add_cvt(codec, nid) < 0)
343 return -EINVAL;
344 break;
345 case AC_WID_PIN:
346 caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP);
347 if (!(caps & AC_PINCAP_HDMI))
348 continue;
349 if (intel_hdmi_add_pin(codec, nid) < 0)
350 return -EINVAL;
351 break;
352 }
353 }
354
355 return 0;
356}
357
91504877
WF		 358/*
359 * HDMI routines
360 */
361
beb0b9cf 362#ifdef BE_PARANOID
6797cf2b 363static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
91504877
WF		 364 int *packet_index, int *byte_index)
365{
366 int val;
367
6797cf2b
WF		 368 val = snd_hda_codec_read(codec, pin_nid, 0,
369 AC_VERB_GET_HDMI_DIP_INDEX, 0);
91504877
WF		 370
371 *packet_index = val >> 5;
372 *byte_index = val & 0x1f;
373}
beb0b9cf 374#endif
91504877 375
6797cf2b 376static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
91504877
WF		 377 int packet_index, int byte_index)
378{
379 int val;
380
381 val = (packet_index << 5) | (byte_index & 0x1f);
382
6797cf2b 383 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
91504877
WF		 384}
385
6797cf2b 386static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
91504877
WF		 387 unsigned char val)
388{
6797cf2b 389 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
91504877
WF		 390}
391
6797cf2b 392static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid)
91504877 393{
796359d1 394 /* Unmute */
559059b2
WF		 395 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
396 snd_hda_codec_write(codec, pin_nid, 0,
796359d1
WF		 397 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
398 /* Enable pin out */
559059b2
WF		 399 snd_hda_codec_write(codec, pin_nid, 0,
400 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
91504877
WF		 401}
402
606c0cee
WF		 403/*
404 * Enable Audio InfoFrame Transmission
405 */
6797cf2b
WF		 406static void hdmi_start_infoframe_trans(struct hda_codec *codec,
407 hda_nid_t pin_nid)
91504877 408{
559059b2
WF		 409 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
410 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
606c0cee
WF		 411 AC_DIPXMIT_BEST);
412}
91504877 413
606c0cee
WF		 414/*
415 * Disable Audio InfoFrame Transmission
416 */
6797cf2b
WF		 417static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
418 hda_nid_t pin_nid)
606c0cee 419{
559059b2
WF		 420 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
421 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
606c0cee 422 AC_DIPXMIT_DISABLE);
91504877
WF		 423}
424
6a5f96ce 425#ifdef CONFIG_SND_DEBUG_VERBOSE
6797cf2b 426static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid)
91504877 427{
6797cf2b 428 return 1 + snd_hda_codec_read(codec, nid, 0,
91504877
WF		 429 AC_VERB_GET_CVT_CHAN_COUNT, 0);
430}
6a5f96ce 431#endif
91504877 432
6797cf2b
WF		 433static void hdmi_set_channel_count(struct hda_codec *codec,
434 hda_nid_t nid, int chs)
91504877 435{
6797cf2b 436 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
91504877 437
6797cf2b
WF		 438#ifdef CONFIG_SND_DEBUG_VERBOSE
439 if (chs != hdmi_get_channel_count(codec, nid))
03284c8f 440 snd_printd(KERN_INFO "HDMI channel count: expect %d, get %d\n",
6797cf2b
WF		 441 chs, hdmi_get_channel_count(codec, nid));
442#endif
91504877
WF		 443}
444
6797cf2b 445static void hdmi_debug_channel_mapping(struct hda_codec *codec, hda_nid_t nid)
91504877
WF		 446{
447#ifdef CONFIG_SND_DEBUG_VERBOSE
448 int i;
449 int slot;
450
451 for (i = 0; i < 8; i++) {
6797cf2b 452 slot = snd_hda_codec_read(codec, nid, 0,
91504877 453 AC_VERB_GET_HDMI_CHAN_SLOT, i);
03284c8f 454 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
1e7c10fe 455 slot >> 4, slot & 0xf);
91504877
WF		 456 }
457#endif
458}
459
91504877
WF		 460
461/*
4e19c58f 462 * Audio InfoFrame routines
91504877
WF		 463 */
464
6797cf2b 465static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
91504877
WF		 466{
467#ifdef CONFIG_SND_DEBUG_VERBOSE
468 int i;
469 int size;
470
559059b2 471 size = snd_hdmi_get_eld_size(codec, pin_nid);
03284c8f 472 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
91504877
WF		 473
474 for (i = 0; i < 8; i++) {
559059b2 475 size = snd_hda_codec_read(codec, pin_nid, 0,
91504877 476 AC_VERB_GET_HDMI_DIP_SIZE, i);
03284c8f 477 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
91504877
WF		 478 }
479#endif
480}
481
6797cf2b 482static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
91504877
WF		 483{
484#ifdef BE_PARANOID
485 int i, j;
486 int size;
487 int pi, bi;
488 for (i = 0; i < 8; i++) {
559059b2 489 size = snd_hda_codec_read(codec, pin_nid, 0,
91504877
WF		 490 AC_VERB_GET_HDMI_DIP_SIZE, i);
491 if (size == 0)
492 continue;
493
559059b2 494 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
91504877 495 for (j = 1; j < 1000; j++) {
559059b2
WF		 496 hdmi_write_dip_byte(codec, pin_nid, 0x0);
497 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
91504877
WF		 498 if (pi != i)
499 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
500 bi, pi, i);
501 if (bi == 0) /* byte index wrapped around */
502 break;
503 }
504 snd_printd(KERN_INFO
03284c8f
WF		 505 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
506 i, size, j);
91504877
WF		 507 }
508#endif
509}
510
978be6d7
WF		 511static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *ai)
512{
513 u8 *bytes = (u8 *)ai;
514 u8 sum = 0;
515 int i;
516
517 ai->checksum = 0;
518
519 for (i = 0; i < sizeof(*ai); i++)
520 sum += bytes[i];
521
522 ai->checksum = - sum;
523}
524
5457a980 525static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
6797cf2b
WF		 526 hda_nid_t pin_nid,
527 struct hdmi_audio_infoframe *ai)
5457a980 528{
978be6d7 529 u8 *bytes = (u8 *)ai;
5457a980
WF		 530 int i;
531
6797cf2b
WF		 532 hdmi_debug_dip_size(codec, pin_nid);
533 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
5457a980 534
978be6d7 535 hdmi_checksum_audio_infoframe(ai);
9a957a24 536
559059b2 537 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
6f539a98 538 for (i = 0; i < sizeof(*ai); i++)
978be6d7 539 hdmi_write_dip_byte(codec, pin_nid, bytes[i]);
5457a980
WF		 540}
541
698544de
WF		 542/*
543 * Compute derived values in channel_allocations[].
544 */
545static void init_channel_allocations(void)
546{
547 int i, j;
548 struct cea_channel_speaker_allocation *p;
549
550 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
551 p = channel_allocations + i;
552 p->channels = 0;
553 p->spk_mask = 0;
554 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
555 if (p->speakers[j]) {
556 p->channels++;
557 p->spk_mask |= p->speakers[j];
558 }
559 }
560}
561
562/*
563 * The transformation takes two steps:
564 *
565 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
566 * spk_mask => (channel_allocations[]) => ai->CA
567 *
568 * TODO: it could select the wrong CA from multiple candidates.
569*/
6797cf2b 570static int hdmi_setup_channel_allocation(struct hda_codec *codec, hda_nid_t nid,
698544de
WF		 571 struct hdmi_audio_infoframe *ai)
572{
573 struct intel_hdmi_spec *spec = codec->spec;
54a25f87 574 struct hdmi_eld *eld;
698544de
WF		 575 int i;
576 int spk_mask = 0;
577 int channels = 1 + (ai->CC02_CT47 & 0x7);
578 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
579
580 /*
581 * CA defaults to 0 for basic stereo audio
582 */
698544de
WF		 583 if (channels <= 2)
584 return 0;
585
54a25f87
WF		 586 i = hda_node_index(spec->pin_cvt, nid);
587 if (i < 0)
588 return 0;
589 eld = &spec->sink_eld[i];
590
a1667e4e
WF		 591 /*
592 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
593 * in console or for audio devices. Assume the highest speakers
594 * configuration, to _not_ prohibit multi-channel audio playback.
595 */
596 if (!eld->spk_alloc)
597 eld->spk_alloc = 0xffff;
598
698544de
WF		 599 /*
600 * expand ELD's speaker allocation mask
601 *
602 * ELD tells the speaker mask in a compact(paired) form,
b83923a3 603 * expand ELD's notions to match the ones used by Audio InfoFrame.
698544de
WF		 604 */
605 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
606 if (eld->spk_alloc & (1 << i))
607 spk_mask |= eld_speaker_allocation_bits[i];
608 }
609
610 /* search for the first working match in the CA table */
611 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
612 if (channels == channel_allocations[i].channels &&
613 (spk_mask & channel_allocations[i].spk_mask) ==
614 channel_allocations[i].spk_mask) {
615 ai->CA = channel_allocations[i].ca_index;
cc02b83c 616 break;
698544de
WF		 617 }
618 }
619
620 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
cc02b83c
WF		 621 snd_printdd(KERN_INFO
622 "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
623 ai->CA, channels, buf);
624
625 return ai->CA;
698544de
WF		 626}
627
6797cf2b
WF		 628static void hdmi_setup_channel_mapping(struct hda_codec *codec, hda_nid_t nid,
629 struct hdmi_audio_infoframe *ai)
9c8641e8 630{
559059b2
WF		 631 int i;
632
9c8641e8
WF		 633 if (!ai->CA)
634 return;
635
636 /*
637 * TODO: adjust channel mapping if necessary
638 * ALSA sequence is front/surr/clfe/side?
639 */
640
559059b2 641 for (i = 0; i < 8; i++)
6797cf2b 642 snd_hda_codec_write(codec, nid, 0,
559059b2
WF		 643 AC_VERB_SET_HDMI_CHAN_SLOT,
644 (i << 4) | i);
645
6797cf2b 646 hdmi_debug_channel_mapping(codec, nid);
9c8641e8
WF		 647}
648
848de598
WF		 649static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
650 struct hdmi_audio_infoframe *ai)
651{
652 u8 *bytes = (u8 *)ai;
653 u8 val;
654 int i;
655
656 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
657 != AC_DIPXMIT_BEST)
658 return false;
659
660 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
661 for (i = 0; i < sizeof(*ai); i++) {
662 val = snd_hda_codec_read(codec, pin_nid, 0,
663 AC_VERB_GET_HDMI_DIP_DATA, 0);
664 if (val != bytes[i])
665 return false;
666 }
667
668 return true;
669}
9c8641e8 670
6797cf2b 671static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid,
91504877
WF		 672 struct snd_pcm_substream *substream)
673{
54a25f87
WF		 674 struct intel_hdmi_spec *spec = codec->spec;
675 hda_nid_t pin_nid;
676 int i;
5457a980 677 struct hdmi_audio_infoframe ai = {
91504877
WF		 678 .type = 0x84,
679 .ver = 0x01,
680 .len = 0x0a,
681 .CC02_CT47 = substream->runtime->channels - 1,
682 };
91504877 683
6797cf2b
WF		 684 hdmi_setup_channel_allocation(codec, nid, &ai);
685 hdmi_setup_channel_mapping(codec, nid, &ai);
698544de 686
54a25f87
WF		 687 for (i = 0; i < spec->num_pins; i++) {
688 if (spec->pin_cvt[i] != nid)
689 continue;
23ccc2bd 690 if (!spec->sink_eld[i].monitor_present)
54a25f87
WF		 691 continue;
692
693 pin_nid = spec->pin[i];
848de598
WF		 694 if (!hdmi_infoframe_uptodate(codec, pin_nid, &ai)) {
695 hdmi_stop_infoframe_trans(codec, pin_nid);
696 hdmi_fill_audio_infoframe(codec, pin_nid, &ai);
697 hdmi_start_infoframe_trans(codec, pin_nid);
698 }
54a25f87 699 }
91504877
WF		 700}
701
702
703/*
704 * Unsolicited events
705 */
706
707static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
708{
54a25f87
WF		 709 struct intel_hdmi_spec *spec = codec->spec;
710 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
91504877
WF		 711 int pind = !!(res & AC_UNSOL_RES_PD);
712 int eldv = !!(res & AC_UNSOL_RES_ELDV);
54a25f87 713 int index;
91504877 714
03284c8f 715 printk(KERN_INFO
54a25f87
WF		 716 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
717 tag, pind, eldv);
718
719 index = hda_node_index(spec->pin, tag);
720 if (index < 0)
721 return;
722
23ccc2bd
WF		 723 spec->sink_eld[index].monitor_present = pind;
724 spec->sink_eld[index].eld_valid = eldv;
91504877
WF		 725
726 if (pind && eldv) {
3f54aa50 727 hdmi_get_show_eld(codec, spec->pin[index], &spec->sink_eld[index]);
91504877
WF		 728 /* TODO: do real things about ELD */
729 }
730}
731
732static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
733{
54a25f87 734 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
91504877
WF		 735 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
736 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
737 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
738
03284c8f 739 printk(KERN_INFO
54a25f87
WF		 740 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
741 tag,
03284c8f
WF		 742 subtag,
743 cp_state,
744 cp_ready);
91504877 745
03284c8f 746 /* TODO */
91504877
WF		 747 if (cp_state)
748 ;
749 if (cp_ready)
750 ;
751}
752
753
754static void intel_hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
755{
54a25f87 756 struct intel_hdmi_spec *spec = codec->spec;
91504877
WF		 757 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
758 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
759
54a25f87 760 if (hda_node_index(spec->pin, tag) < 0) {
03284c8f 761 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
91504877
WF		 762 return;
763 }
764
765 if (subtag == 0)
766 hdmi_intrinsic_event(codec, res);
767 else
768 hdmi_non_intrinsic_event(codec, res);
769}
770
771/*
772 * Callbacks
773 */
774
ddb8152b 775static int intel_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
70ca35fb 776 struct hda_codec *codec,
ddb8152b
WF		 777 unsigned int stream_tag,
778 unsigned int format,
70ca35fb 779 struct snd_pcm_substream *substream)
91504877 780{
54a25f87 781 hdmi_set_channel_count(codec, hinfo->nid,
ddb8152b 782 substream->runtime->channels);
91504877 783
54a25f87 784 hdmi_setup_audio_infoframe(codec, hinfo->nid, substream);
91504877 785
ddb8152b 786 snd_hda_codec_setup_stream(codec, hinfo->nid, stream_tag, 0, format);
7bedb011 787 return 0;
91504877
WF		 788}
789
ddb8152b 790static int intel_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
91504877 791 struct hda_codec *codec,
91504877
WF		 792 struct snd_pcm_substream *substream)
793{
ddb8152b 794 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
91504877
WF		 795 return 0;
796}
797
798static struct hda_pcm_stream intel_hdmi_pcm_playback = {
799 .substreams = 1,
800 .channels_min = 2,
91504877 801 .ops = {
70ca35fb
WF		 802 .prepare = intel_hdmi_playback_pcm_prepare,
803 .cleanup = intel_hdmi_playback_pcm_cleanup,
91504877
WF		 804 },
805};
806
807static int intel_hdmi_build_pcms(struct hda_codec *codec)
808{
809 struct intel_hdmi_spec *spec = codec->spec;
54a25f87
WF		 810 struct hda_pcm *info = spec->pcm_rec;
811 int i;
91504877 812
54a25f87 813 codec->num_pcms = spec->num_cvts;
91504877
WF		 814 codec->pcm_info = info;
815
54a25f87 816 for (i = 0; i < codec->num_pcms; i++, info++) {
69fb3468
WF		 817 unsigned int chans;
818
819 chans = get_wcaps(codec, spec->cvt[i]);
820 chans = get_wcaps_channels(chans);
821
54a25f87
WF		 822 info->name = intel_hdmi_pcm_names[i];
823 info->pcm_type = HDA_PCM_TYPE_HDMI;
824 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
825 intel_hdmi_pcm_playback;
826 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->cvt[i];
69fb3468 827 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = chans;
54a25f87 828 }
91504877
WF		 829
830 return 0;
831}
832
833static int intel_hdmi_build_controls(struct hda_codec *codec)
834{
835 struct intel_hdmi_spec *spec = codec->spec;
836 int err;
54a25f87 837 int i;
91504877 838
54a25f87
WF		 839 for (i = 0; i < codec->num_pcms; i++) {
840 err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i]);
841 if (err < 0)
842 return err;
843 }
91504877
WF		 844
845 return 0;
846}
847
848static int intel_hdmi_init(struct hda_codec *codec)
849{
54a25f87
WF		 850 struct intel_hdmi_spec *spec = codec->spec;
851 int i;
91504877 852
54a25f87
WF		 853 for (i = 0; spec->pin[i]; i++) {
854 hdmi_enable_output(codec, spec->pin[i]);
855 snd_hda_codec_write(codec, spec->pin[i], 0,
856 AC_VERB_SET_UNSOLICITED_ENABLE,
857 AC_USRSP_EN | spec->pin[i]);
858 }
91504877
WF		 859 return 0;
860}
861
862static void intel_hdmi_free(struct hda_codec *codec)
863{
f208dba9 864 struct intel_hdmi_spec *spec = codec->spec;
54a25f87
WF		 865 int i;
866
867 for (i = 0; i < spec->num_pins; i++)
868 snd_hda_eld_proc_free(codec, &spec->sink_eld[i]);
f208dba9 869
f208dba9 870 kfree(spec);
91504877
WF		 871}
872
873static struct hda_codec_ops intel_hdmi_patch_ops = {
874 .init = intel_hdmi_init,
875 .free = intel_hdmi_free,
876 .build_pcms = intel_hdmi_build_pcms,
877 .build_controls = intel_hdmi_build_controls,
878 .unsol_event = intel_hdmi_unsol_event,
879};
880
fd080b2d 881static int patch_intel_hdmi(struct hda_codec *codec)
91504877
WF		 882{
883 struct intel_hdmi_spec *spec;
54a25f87 884 int i;
91504877
WF		 885
886 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
887 if (spec == NULL)
888 return -ENOMEM;
889
91504877 890 codec->spec = spec;
f424367c
WF		 891 if (intel_hdmi_parse_codec(codec) < 0) {
892 codec->spec = NULL;
893 kfree(spec);
894 return -EINVAL;
895 }
91504877
WF		 896 codec->patch_ops = intel_hdmi_patch_ops;
897
54a25f87
WF		 898 for (i = 0; i < spec->num_pins; i++)
899 snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i);
5f1e71b1 900
698544de
WF		 901 init_channel_allocations();
902
91504877
WF		 903 return 0;
904}
905
1289e9e8 906static struct hda_codec_preset snd_hda_preset_intelhdmi[] = {
74c61133
TI		 907 { .id = 0x808629fb, .name = "G45 DEVCL", .patch = patch_intel_hdmi },
908 { .id = 0x80862801, .name = "G45 DEVBLC", .patch = patch_intel_hdmi },
909 { .id = 0x80862802, .name = "G45 DEVCTG", .patch = patch_intel_hdmi },
910 { .id = 0x80862803, .name = "G45 DEVELK", .patch = patch_intel_hdmi },
fd080b2d
WF		 911 { .id = 0x80862804, .name = "G45 DEVIBX", .patch = patch_intel_hdmi },
912 { .id = 0x80860054, .name = "Q57 DEVIBX", .patch = patch_intel_hdmi },
3a95cb97 913 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_intel_hdmi },
91504877
WF		 914 {} /* terminator */
915};
1289e9e8
TI		 916
917MODULE_ALIAS("snd-hda-codec-id:808629fb");
918MODULE_ALIAS("snd-hda-codec-id:80862801");
919MODULE_ALIAS("snd-hda-codec-id:80862802");
920MODULE_ALIAS("snd-hda-codec-id:80862803");
a57c0eb6 921MODULE_ALIAS("snd-hda-codec-id:80862804");
87a8c370 922MODULE_ALIAS("snd-hda-codec-id:80860054");
1289e9e8
TI		 923MODULE_ALIAS("snd-hda-codec-id:10951392");
924
925MODULE_LICENSE("GPL");
926MODULE_DESCRIPTION("Intel HDMI HD-audio codec");
927
928static struct hda_codec_preset_list intel_list = {
929 .preset = snd_hda_preset_intelhdmi,
930 .owner = THIS_MODULE,
931};
932
933static int __init patch_intelhdmi_init(void)
934{
935 return snd_hda_add_codec_preset(&intel_list);
936}
937
938static void __exit patch_intelhdmi_exit(void)
939{
940 snd_hda_delete_codec_preset(&intel_list);
941}
942
943module_init(patch_intelhdmi_init)
944module_exit(patch_intelhdmi_exit)
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