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intelhdmi - dont power off HDA link
[net-next-2.6.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
71623855 63static int enable_msi = -1;
4ea6fbc8
TI		 64#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
2dca0bba
JK		 67#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
1da177e4 71
5aba4f8e 72module_param_array(index, int, NULL, 0444);
1da177e4 73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 74module_param_array(id, charp, NULL, 0444);
1da177e4 75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 76module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
1da177e4 79MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 80module_param_array(position_fix, int, NULL, 0444);
d01ce99f 81MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 82 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 83module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 85module_param_array(probe_mask, int, NULL, 0444);
606ad75f 86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 87module_param_array(probe_only, bool, NULL, 0444);
88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 89module_param(single_cmd, bool, 0444);
d01ce99f
TI		 90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
5aba4f8e 92module_param(enable_msi, int, 0444);
134a11f0 93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 94#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
2dca0bba
JK		 98#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
606ad75f 103
dee1b66c 104#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
1da177e4 109
dee1b66c
TI		 110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
1da177e4
LT		 119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
2f1b3818 122 "{Intel, ICH7},"
f5d40b30 123 "{Intel, ESB2},"
d2981393 124 "{Intel, ICH8},"
f9cc8a8b 125 "{Intel, ICH9},"
c34f5a04 126 "{Intel, ICH10},"
b29c2360 127 "{Intel, PCH},"
4979bca9 128 "{Intel, SCH},"
fc20a562 129 "{ATI, SB450},"
89be83f8 130 "{ATI, SB600},"
778b6e1b 131 "{ATI, RS600},"
5b15c95f 132 "{ATI, RS690},"
e6db1119
WL		 133 "{ATI, RS780},"
134 "{ATI, R600},"
2797f724
HRK		 135 "{ATI, RV630},"
136 "{ATI, RV610},"
27da1834
WL		 137 "{ATI, RV670},"
138 "{ATI, RV635},"
139 "{ATI, RV620},"
140 "{ATI, RV770},"
fc20a562 141 "{VIA, VT8251},"
47672310 142 "{VIA, VT8237A},"
07e4ca50
TI		 143 "{SiS, SIS966},"
144 "{ULI, M5461}}");
1da177e4
LT		 145MODULE_DESCRIPTION("Intel HDA driver");
146
4abc1cc2
TI		 147#ifdef CONFIG_SND_VERBOSE_PRINTK
148#define SFX /* nop */
149#else
1da177e4 150#define SFX "hda-intel: "
4abc1cc2 151#endif
cb53c626 152
1da177e4
LT		 153/*
154 * registers
155 */
156#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 157#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
158#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
159#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
160#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
161#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 162#define ICH6_REG_VMIN 0x02
163#define ICH6_REG_VMAJ 0x03
164#define ICH6_REG_OUTPAY 0x04
165#define ICH6_REG_INPAY 0x06
166#define ICH6_REG_GCTL 0x08
8a933ece 167#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 168#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
169#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 170#define ICH6_REG_WAKEEN 0x0c
171#define ICH6_REG_STATESTS 0x0e
172#define ICH6_REG_GSTS 0x10
b21fadb9 173#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 174#define ICH6_REG_INTCTL 0x20
175#define ICH6_REG_INTSTS 0x24
176#define ICH6_REG_WALCLK 0x30
177#define ICH6_REG_SYNC 0x34
178#define ICH6_REG_CORBLBASE 0x40
179#define ICH6_REG_CORBUBASE 0x44
180#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 181#define ICH6_REG_CORBRP 0x4a
182#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 183#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 184#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
185#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 186#define ICH6_REG_CORBSTS 0x4d
b21fadb9 187#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 188#define ICH6_REG_CORBSIZE 0x4e
189
190#define ICH6_REG_RIRBLBASE 0x50
191#define ICH6_REG_RIRBUBASE 0x54
192#define ICH6_REG_RIRBWP 0x58
b21fadb9 193#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 194#define ICH6_REG_RINTCNT 0x5a
195#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 196#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
197#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
198#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 199#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 200#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
201#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 202#define ICH6_REG_RIRBSIZE 0x5e
203
204#define ICH6_REG_IC 0x60
205#define ICH6_REG_IR 0x64
206#define ICH6_REG_IRS 0x68
207#define ICH6_IRS_VALID (1<<1)
208#define ICH6_IRS_BUSY (1<<0)
209
210#define ICH6_REG_DPLBASE 0x70
211#define ICH6_REG_DPUBASE 0x74
212#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
213
214/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
215enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
216
217/* stream register offsets from stream base */
218#define ICH6_REG_SD_CTL 0x00
219#define ICH6_REG_SD_STS 0x03
220#define ICH6_REG_SD_LPIB 0x04
221#define ICH6_REG_SD_CBL 0x08
222#define ICH6_REG_SD_LVI 0x0c
223#define ICH6_REG_SD_FIFOW 0x0e
224#define ICH6_REG_SD_FIFOSIZE 0x10
225#define ICH6_REG_SD_FORMAT 0x12
226#define ICH6_REG_SD_BDLPL 0x18
227#define ICH6_REG_SD_BDLPU 0x1c
228
229/* PCI space */
230#define ICH6_PCIREG_TCSEL 0x44
231
232/*
233 * other constants
234 */
235
236/* max number of SDs */
07e4ca50 237/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 238#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 239#define ICH6_NUM_PLAYBACK 4
240
241/* ULI has 6 playback and 5 capture */
07e4ca50 242#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 243#define ULI_NUM_PLAYBACK 6
244
778b6e1b 245/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 246#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 247#define ATIHDMI_NUM_PLAYBACK 1
248
f269002e
KY		 249/* TERA has 4 playback and 3 capture */
250#define TERA_NUM_CAPTURE 3
251#define TERA_NUM_PLAYBACK 4
252
07e4ca50
TI		 253/* this number is statically defined for simplicity */
254#define MAX_AZX_DEV 16
255
1da177e4 256/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 257#define BDL_SIZE 4096
258#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
259#define AZX_MAX_FRAG 32
1da177e4
LT		 260/* max buffer size - no h/w limit, you can increase as you like */
261#define AZX_MAX_BUF_SIZE (1024*1024*1024)
262/* max number of PCM devics per card */
7ba72ba1 263#define AZX_MAX_PCMS 8
1da177e4
LT		 264
265/* RIRB int mask: overrun[2], response[0] */
266#define RIRB_INT_RESPONSE 0x01
267#define RIRB_INT_OVERRUN 0x04
268#define RIRB_INT_MASK 0x05
269
2f5983f2
TI		 270/* STATESTS int mask: S3,SD2,SD1,SD0 */
271#define AZX_MAX_CODECS 4
deadff16 272#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 273
274/* SD_CTL bits */
275#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
276#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 277#define SD_CTL_STRIPE (3 << 16) /* stripe control */
278#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
279#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 280#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
281#define SD_CTL_STREAM_TAG_SHIFT 20
282
283/* SD_CTL and SD_STS */
284#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
285#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
286#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 287#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
288 SD_INT_COMPLETE)
1da177e4
LT		 289
290/* SD_STS */
291#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292
293/* INTCTL and INTSTS */
d01ce99f
TI		 294#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
295#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
296#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 297
1da177e4
LT		 298/* below are so far hardcoded - should read registers in future */
299#define ICH6_MAX_CORB_ENTRIES 256
300#define ICH6_MAX_RIRB_ENTRIES 256
301
c74db86b
TI		 302/* position fix mode */
303enum {
0be3b5d3 304 POS_FIX_AUTO,
d2e1c973 305 POS_FIX_LPIB,
0be3b5d3 306 POS_FIX_POSBUF,
c74db86b 307};
1da177e4 308
f5d40b30 309/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 310#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
311#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312
da3fca21
V		 313/* Defines for Nvidia HDA support */
314#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
315#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 316#define NVIDIA_HDA_ISTRM_COH 0x4d
317#define NVIDIA_HDA_OSTRM_COH 0x4c
318#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 319
90a5ad52
TI		 320/* Defines for Intel SCH HDA snoop control */
321#define INTEL_SCH_HDA_DEVC 0x78
322#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323
0e153474
JC		 324/* Define IN stream 0 FIFO size offset in VIA controller */
325#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
326/* Define VIA HD Audio Device ID*/
327#define VIA_HDAC_DEVICE_ID 0x3288
328
c4da29ca
YL		 329/* HD Audio class code */
330#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 331
1da177e4
LT		 332/*
333 */
334
a98f90fd 335struct azx_dev {
4ce107b9 336 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 337 u32 *posbuf; /* position buffer pointer */
1da177e4 338
d01ce99f 339 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 340 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 341 unsigned int frags; /* number for period in the play buffer */
342 unsigned int fifo_size; /* FIFO size */
fa00e046
JK		 343 unsigned long start_jiffies; /* start + minimum jiffies */
344 unsigned long min_jiffies; /* minimum jiffies before position is valid */
1da177e4 345
d01ce99f 346 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 347
d01ce99f 348 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 349
350 /* pcm support */
d01ce99f
TI		 351 struct snd_pcm_substream *substream; /* assigned substream,
352 * set in PCM open
353 */
354 unsigned int format_val; /* format value to be set in the
355 * controller and the codec
356 */
1da177e4
LT		 357 unsigned char stream_tag; /* assigned stream */
358 unsigned char index; /* stream index */
359
927fc866
PM		 360 unsigned int opened :1;
361 unsigned int running :1;
675f25d4 362 unsigned int irq_pending :1;
d523b0c8 363 unsigned int start_flag: 1; /* stream full start flag */
0e153474
JC		 364 /*
365 * For VIA:
366 * A flag to ensure DMA position is 0
367 * when link position is not greater than FIFO size
368 */
369 unsigned int insufficient :1;
1da177e4
LT		 370};
371
372/* CORB/RIRB */
a98f90fd 373struct azx_rb {
1da177e4
LT		 374 u32 *buf; /* CORB/RIRB buffer
375 * Each CORB entry is 4byte, RIRB is 8byte
376 */
377 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
378 /* for RIRB */
379 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 380 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
381 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 382};
383
a98f90fd
TI		 384struct azx {
385 struct snd_card *card;
1da177e4 386 struct pci_dev *pci;
555e219f 387 int dev_index;
1da177e4 388
07e4ca50
TI		 389 /* chip type specific */
390 int driver_type;
391 int playback_streams;
392 int playback_index_offset;
393 int capture_streams;
394 int capture_index_offset;
395 int num_streams;
396
1da177e4
LT		 397 /* pci resources */
398 unsigned long addr;
399 void __iomem *remap_addr;
400 int irq;
401
402 /* locks */
403 spinlock_t reg_lock;
62932df8 404 struct mutex open_mutex;
1da177e4 405
07e4ca50 406 /* streams (x num_streams) */
a98f90fd 407 struct azx_dev *azx_dev;
1da177e4
LT		 408
409 /* PCM */
a98f90fd 410 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 411
412 /* HD codec */
413 unsigned short codec_mask;
f1eaaeec 414 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 415 struct hda_bus *bus;
2dca0bba 416 unsigned int beep_mode;
1da177e4
LT		 417
418 /* CORB/RIRB */
a98f90fd
TI		 419 struct azx_rb corb;
420 struct azx_rb rirb;
1da177e4 421
4ce107b9 422 /* CORB/RIRB and position buffers */
1da177e4
LT		 423 struct snd_dma_buffer rb;
424 struct snd_dma_buffer posbuf;
c74db86b
TI		 425
426 /* flags */
427 int position_fix;
cb53c626 428 unsigned int running :1;
927fc866
PM		 429 unsigned int initialized :1;
430 unsigned int single_cmd :1;
431 unsigned int polling_mode :1;
68e7fffc 432 unsigned int msi :1;
a6a950a8 433 unsigned int irq_pending_warned :1;
0e153474 434 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 435 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 436
437 /* for debugging */
feb27340 438 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 439
440 /* for pending irqs */
441 struct work_struct irq_pending_work;
0cbf0098
TI		 442
443 /* reboot notifier (for mysterious hangup problem at power-down) */
444 struct notifier_block reboot_notifier;
1da177e4
LT		 445};
446
07e4ca50
TI		 447/* driver types */
448enum {
449 AZX_DRIVER_ICH,
4979bca9 450 AZX_DRIVER_SCH,
07e4ca50 451 AZX_DRIVER_ATI,
778b6e1b 452 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 453 AZX_DRIVER_VIA,
454 AZX_DRIVER_SIS,
455 AZX_DRIVER_ULI,
da3fca21 456 AZX_DRIVER_NVIDIA,
f269002e 457 AZX_DRIVER_TERA,
c4da29ca 458 AZX_DRIVER_GENERIC,
2f5983f2 459 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 460};
461
462static char *driver_short_names[] __devinitdata = {
463 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 464 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 465 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 466 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 467 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
468 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 469 [AZX_DRIVER_ULI] = "HDA ULI M5461",
470 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 471 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 472 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 473};
474
1da177e4
LT		 475/*
476 * macros for easy use
477 */
478#define azx_writel(chip,reg,value) \
479 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
480#define azx_readl(chip,reg) \
481 readl((chip)->remap_addr + ICH6_REG_##reg)
482#define azx_writew(chip,reg,value) \
483 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
484#define azx_readw(chip,reg) \
485 readw((chip)->remap_addr + ICH6_REG_##reg)
486#define azx_writeb(chip,reg,value) \
487 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
488#define azx_readb(chip,reg) \
489 readb((chip)->remap_addr + ICH6_REG_##reg)
490
491#define azx_sd_writel(dev,reg,value) \
492 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
493#define azx_sd_readl(dev,reg) \
494 readl((dev)->sd_addr + ICH6_REG_##reg)
495#define azx_sd_writew(dev,reg,value) \
496 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
497#define azx_sd_readw(dev,reg) \
498 readw((dev)->sd_addr + ICH6_REG_##reg)
499#define azx_sd_writeb(dev,reg,value) \
500 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
501#define azx_sd_readb(dev,reg) \
502 readb((dev)->sd_addr + ICH6_REG_##reg)
503
504/* for pcm support */
a98f90fd 505#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 506
68e7fffc 507static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 508
509/*
510 * Interface for HD codec
511 */
512
1da177e4
LT		 513/*
514 * CORB / RIRB interface
515 */
a98f90fd 516static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 517{
518 int err;
519
520 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 521 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
522 snd_dma_pci_data(chip->pci),
1da177e4
LT		 523 PAGE_SIZE, &chip->rb);
524 if (err < 0) {
525 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
526 return err;
527 }
528 return 0;
529}
530
a98f90fd 531static void azx_init_cmd_io(struct azx *chip)
1da177e4 532{
cdb1fbf2 533 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 534 /* CORB set up */
535 chip->corb.addr = chip->rb.addr;
536 chip->corb.buf = (u32 *)chip->rb.area;
537 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 538 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 539
07e4ca50
TI		 540 /* set the corb size to 256 entries (ULI requires explicitly) */
541 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 542 /* set the corb write pointer to 0 */
543 azx_writew(chip, CORBWP, 0);
544 /* reset the corb hw read pointer */
b21fadb9 545 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 546 /* enable corb dma */
b21fadb9 547 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 548
549 /* RIRB set up */
550 chip->rirb.addr = chip->rb.addr + 2048;
551 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 552 chip->rirb.wp = chip->rirb.rp = 0;
553 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 554 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 555 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 556
07e4ca50
TI		 557 /* set the rirb size to 256 entries (ULI requires explicitly) */
558 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 559 /* reset the rirb hw write pointer */
b21fadb9 560 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4
LT		 561 /* set N=1, get RIRB response interrupt for new entry */
562 azx_writew(chip, RINTCNT, 1);
563 /* enable rirb dma and response irq */
1da177e4 564 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 565 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 566}
567
a98f90fd 568static void azx_free_cmd_io(struct azx *chip)
1da177e4 569{
cdb1fbf2 570 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 571 /* disable ringbuffer DMAs */
572 azx_writeb(chip, RIRBCTL, 0);
573 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 574 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 575}
576
deadff16
WF		 577static unsigned int azx_command_addr(u32 cmd)
578{
579 unsigned int addr = cmd >> 28;
580
581 if (addr >= AZX_MAX_CODECS) {
582 snd_BUG();
583 addr = 0;
584 }
585
586 return addr;
587}
588
589static unsigned int azx_response_addr(u32 res)
590{
591 unsigned int addr = res & 0xf;
592
593 if (addr >= AZX_MAX_CODECS) {
594 snd_BUG();
595 addr = 0;
596 }
597
598 return addr;
1da177e4
LT		 599}
600
601/* send a command */
33fa35ed 602static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 603{
33fa35ed 604 struct azx *chip = bus->private_data;
deadff16 605 unsigned int addr = azx_command_addr(val);
1da177e4 606 unsigned int wp;
1da177e4 607
c32649fe
WF		 608 spin_lock_irq(&chip->reg_lock);
609
1da177e4
LT		 610 /* add command to corb */
611 wp = azx_readb(chip, CORBWP);
612 wp++;
613 wp %= ICH6_MAX_CORB_ENTRIES;
614
deadff16 615 chip->rirb.cmds[addr]++;
1da177e4
LT		 616 chip->corb.buf[wp] = cpu_to_le32(val);
617 azx_writel(chip, CORBWP, wp);
c32649fe 618
1da177e4
LT		 619 spin_unlock_irq(&chip->reg_lock);
620
621 return 0;
622}
623
624#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
625
626/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 627static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 628{
629 unsigned int rp, wp;
deadff16 630 unsigned int addr;
1da177e4
LT		 631 u32 res, res_ex;
632
633 wp = azx_readb(chip, RIRBWP);
634 if (wp == chip->rirb.wp)
635 return;
636 chip->rirb.wp = wp;
deadff16 637
1da177e4
LT		 638 while (chip->rirb.rp != wp) {
639 chip->rirb.rp++;
640 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
641
642 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
643 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
644 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 645 addr = azx_response_addr(res_ex);
1da177e4
LT		 646 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
647 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 648 else if (chip->rirb.cmds[addr]) {
649 chip->rirb.res[addr] = res;
2add9b92 650 smp_wmb();
deadff16 651 chip->rirb.cmds[addr]--;
e310bb06
WF		 652 } else
653 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
654 "last cmd=%#08x\n",
655 res, res_ex,
656 chip->last_cmd[addr]);
1da177e4
LT		 657 }
658}
659
660/* receive a response */
deadff16
WF		 661static unsigned int azx_rirb_get_response(struct hda_bus *bus,
662 unsigned int addr)
1da177e4 663{
33fa35ed 664 struct azx *chip = bus->private_data;
5c79b1f8 665 unsigned long timeout;
1da177e4 666
5c79b1f8
TI		 667 again:
668 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 669 for (;;) {
e96224ae
TI		 670 if (chip->polling_mode) {
671 spin_lock_irq(&chip->reg_lock);
672 azx_update_rirb(chip);
673 spin_unlock_irq(&chip->reg_lock);
674 }
deadff16 675 if (!chip->rirb.cmds[addr]) {
2add9b92 676 smp_rmb();
b613291f 677 bus->rirb_error = 0;
deadff16 678 return chip->rirb.res[addr]; /* the last value */
2add9b92 679 }
28a0d9df
TI		 680 if (time_after(jiffies, timeout))
681 break;
33fa35ed 682 if (bus->needs_damn_long_delay)
52987656
TI		 683 msleep(2); /* temporary workaround */
684 else {
685 udelay(10);
686 cond_resched();
687 }
28a0d9df 688 }
5c79b1f8 689
23c4a881
TI		 690 if (!chip->polling_mode) {
691 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
692 "switching to polling mode: last cmd=0x%08x\n",
693 chip->last_cmd[addr]);
694 chip->polling_mode = 1;
695 goto again;
696 }
697
68e7fffc 698 if (chip->msi) {
4abc1cc2 699 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 700 "disabling MSI: last cmd=0x%08x\n",
701 chip->last_cmd[addr]);
68e7fffc
TI		 702 free_irq(chip->irq, chip);
703 chip->irq = -1;
704 pci_disable_msi(chip->pci);
705 chip->msi = 0;
b613291f
TI		 706 if (azx_acquire_irq(chip, 1) < 0) {
707 bus->rirb_error = 1;
68e7fffc 708 return -1;
b613291f 709 }
68e7fffc
TI		 710 goto again;
711 }
712
6ce4a3bc
TI		 713 if (chip->probing) {
714 /* If this critical timeout happens during the codec probing
715 * phase, this is likely an access to a non-existing codec
716 * slot. Better to return an error and reset the system.
717 */
718 return -1;
719 }
720
8dd78330
TI		 721 /* a fatal communication error; need either to reset or to fallback
722 * to the single_cmd mode
723 */
b613291f 724 bus->rirb_error = 1;
b20f3b83 725 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 726 bus->response_reset = 1;
727 return -1; /* give a chance to retry */
728 }
729
730 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
731 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 732 chip->last_cmd[addr]);
8dd78330
TI		 733 chip->single_cmd = 1;
734 bus->response_reset = 0;
1a696978 735 /* release CORB/RIRB */
4fcd3920 736 azx_free_cmd_io(chip);
1a696978
TI		 737 /* disable unsolicited responses */
738 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 739 return -1;
1da177e4
LT		 740}
741
1da177e4
LT		 742/*
743 * Use the single immediate command instead of CORB/RIRB for simplicity
744 *
745 * Note: according to Intel, this is not preferred use. The command was
746 * intended for the BIOS only, and may get confused with unsolicited
747 * responses. So, we shouldn't use it for normal operation from the
748 * driver.
749 * I left the codes, however, for debugging/testing purposes.
750 */
751
b05a7d4f 752/* receive a response */
deadff16 753static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 754{
755 int timeout = 50;
756
757 while (timeout--) {
758 /* check IRV busy bit */
759 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
760 /* reuse rirb.res as the response return value */
deadff16 761 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 762 return 0;
763 }
764 udelay(1);
765 }
766 if (printk_ratelimit())
767 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
768 azx_readw(chip, IRS));
deadff16 769 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 770 return -EIO;
771}
772
1da177e4 773/* send a command */
33fa35ed 774static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 775{
33fa35ed 776 struct azx *chip = bus->private_data;
deadff16 777 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 778 int timeout = 50;
779
8dd78330 780 bus->rirb_error = 0;
1da177e4
LT		 781 while (timeout--) {
782 /* check ICB busy bit */
d01ce99f 783 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 784 /* Clear IRV valid bit */
d01ce99f
TI		 785 azx_writew(chip, IRS, azx_readw(chip, IRS) |
786 ICH6_IRS_VALID);
1da177e4 787 azx_writel(chip, IC, val);
d01ce99f
TI		 788 azx_writew(chip, IRS, azx_readw(chip, IRS) |
789 ICH6_IRS_BUSY);
deadff16 790 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 791 }
792 udelay(1);
793 }
1cfd52bc
MB		 794 if (printk_ratelimit())
795 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
796 azx_readw(chip, IRS), val);
1da177e4
LT		 797 return -EIO;
798}
799
800/* receive a response */
deadff16
WF		 801static unsigned int azx_single_get_response(struct hda_bus *bus,
802 unsigned int addr)
1da177e4 803{
33fa35ed 804 struct azx *chip = bus->private_data;
deadff16 805 return chip->rirb.res[addr];
1da177e4
LT		 806}
807
111d3af5
TI		 808/*
809 * The below are the main callbacks from hda_codec.
810 *
811 * They are just the skeleton to call sub-callbacks according to the
812 * current setting of chip->single_cmd.
813 */
814
815/* send a command */
33fa35ed 816static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 817{
33fa35ed 818 struct azx *chip = bus->private_data;
43bbb6cc 819
feb27340 820 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 821 if (chip->single_cmd)
33fa35ed 822 return azx_single_send_cmd(bus, val);
111d3af5 823 else
33fa35ed 824 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 825}
826
827/* get a response */
deadff16
WF		 828static unsigned int azx_get_response(struct hda_bus *bus,
829 unsigned int addr)
111d3af5 830{
33fa35ed 831 struct azx *chip = bus->private_data;
111d3af5 832 if (chip->single_cmd)
deadff16 833 return azx_single_get_response(bus, addr);
111d3af5 834 else
deadff16 835 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 836}
837
cb53c626 838#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 839static void azx_power_notify(struct hda_bus *bus);
cb53c626 840#endif
111d3af5 841
1da177e4 842/* reset codec link */
a98f90fd 843static int azx_reset(struct azx *chip)
1da177e4
LT		 844{
845 int count;
846
e8a7f136
DT		 847 /* clear STATESTS */
848 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
849
1da177e4
LT		 850 /* reset controller */
851 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
852
853 count = 50;
854 while (azx_readb(chip, GCTL) && --count)
855 msleep(1);
856
857 /* delay for >= 100us for codec PLL to settle per spec
858 * Rev 0.9 section 5.5.1
859 */
860 msleep(1);
861
862 /* Bring controller out of reset */
863 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
864
865 count = 50;
927fc866 866 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 867 msleep(1);
868
927fc866 869 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 870 msleep(1);
871
872 /* check to see if controller is ready */
927fc866 873 if (!azx_readb(chip, GCTL)) {
4abc1cc2 874 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 875 return -EBUSY;
876 }
877
41e2fce4 878 /* Accept unsolicited responses */
1a696978
TI		 879 if (!chip->single_cmd)
880 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
881 ICH6_GCTL_UNSOL);
41e2fce4 882
1da177e4 883 /* detect codecs */
927fc866 884 if (!chip->codec_mask) {
1da177e4 885 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 886 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 887 }
888
889 return 0;
890}
891
892
893/*
894 * Lowlevel interface
895 */
896
897/* enable interrupts */
a98f90fd 898static void azx_int_enable(struct azx *chip)
1da177e4
LT		 899{
900 /* enable controller CIE and GIE */
901 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
902 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
903}
904
905/* disable interrupts */
a98f90fd 906static void azx_int_disable(struct azx *chip)
1da177e4
LT		 907{
908 int i;
909
910 /* disable interrupts in stream descriptor */
07e4ca50 911 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 912 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 913 azx_sd_writeb(azx_dev, SD_CTL,
914 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
915 }
916
917 /* disable SIE for all streams */
918 azx_writeb(chip, INTCTL, 0);
919
920 /* disable controller CIE and GIE */
921 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
922 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
923}
924
925/* clear interrupts */
a98f90fd 926static void azx_int_clear(struct azx *chip)
1da177e4
LT		 927{
928 int i;
929
930 /* clear stream status */
07e4ca50 931 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 932 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 933 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
934 }
935
936 /* clear STATESTS */
937 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
938
939 /* clear rirb status */
940 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
941
942 /* clear int status */
943 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
944}
945
946/* start a stream */
a98f90fd 947static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 948{
0e153474
JC		 949 /*
950 * Before stream start, initialize parameter
951 */
952 azx_dev->insufficient = 1;
953
1da177e4
LT		 954 /* enable SIE */
955 azx_writeb(chip, INTCTL,
956 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
957 /* set DMA start and interrupt mask */
958 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
959 SD_CTL_DMA_START | SD_INT_MASK);
960}
961
1dddab40
TI		 962/* stop DMA */
963static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 964{
1da177e4
LT		 965 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
966 ~(SD_CTL_DMA_START | SD_INT_MASK));
967 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 968}
969
970/* stop a stream */
971static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
972{
973 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 974 /* disable SIE */
975 azx_writeb(chip, INTCTL,
976 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
977}
978
979
980/*
cb53c626 981 * reset and start the controller registers
1da177e4 982 */
a98f90fd 983static void azx_init_chip(struct azx *chip)
1da177e4 984{
cb53c626
TI		 985 if (chip->initialized)
986 return;
1da177e4
LT		 987
988 /* reset controller */
989 azx_reset(chip);
990
991 /* initialize interrupts */
992 azx_int_clear(chip);
993 azx_int_enable(chip);
994
995 /* initialize the codec command I/O */
1a696978
TI		 996 if (!chip->single_cmd)
997 azx_init_cmd_io(chip);
1da177e4 998
0be3b5d3
TI		 999 /* program the position buffer */
1000 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1001 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1002
cb53c626
TI		 1003 chip->initialized = 1;
1004}
1005
1006/*
1007 * initialize the PCI registers
1008 */
1009/* update bits in a PCI register byte */
1010static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1011 unsigned char mask, unsigned char val)
1012{
1013 unsigned char data;
1014
1015 pci_read_config_byte(pci, reg, &data);
1016 data &= ~mask;
1017 data |= (val & mask);
1018 pci_write_config_byte(pci, reg, data);
1019}
1020
1021static void azx_init_pci(struct azx *chip)
1022{
90a5ad52
TI		 1023 unsigned short snoop;
1024
cb53c626
TI		 1025 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1026 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1027 * Ensuring these bits are 0 clears playback static on some HD Audio
1028 * codecs
1029 */
1030 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1031
da3fca21
V		 1032 switch (chip->driver_type) {
1033 case AZX_DRIVER_ATI:
1034 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 1035 update_pci_byte(chip->pci,
1036 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1037 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 1038 break;
1039 case AZX_DRIVER_NVIDIA:
1040 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 1041 update_pci_byte(chip->pci,
1042 NVIDIA_HDA_TRANSREG_ADDR,
1043 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1044 update_pci_byte(chip->pci,
1045 NVIDIA_HDA_ISTRM_COH,
1046 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1047 update_pci_byte(chip->pci,
1048 NVIDIA_HDA_OSTRM_COH,
1049 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 1050 break;
90a5ad52
TI		 1051 case AZX_DRIVER_SCH:
1052 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1053 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 1054 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 1055 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1056 pci_read_config_word(chip->pci,
1057 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 1058 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1059 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 1060 ? "Failed" : "OK");
1061 }
1062 break;
1063
da3fca21 1064 }
1da177e4
LT		 1065}
1066
1067
9ad593f6
TI		 1068static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1069
1da177e4
LT		 1070/*
1071 * interrupt handler
1072 */
7d12e780 1073static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1074{
a98f90fd
TI		 1075 struct azx *chip = dev_id;
1076 struct azx_dev *azx_dev;
1da177e4 1077 u32 status;
fa00e046 1078 int i, ok;
1da177e4
LT		 1079
1080 spin_lock(&chip->reg_lock);
1081
1082 status = azx_readl(chip, INTSTS);
1083 if (status == 0) {
1084 spin_unlock(&chip->reg_lock);
1085 return IRQ_NONE;
1086 }
1087
07e4ca50 1088 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1089 azx_dev = &chip->azx_dev[i];
1090 if (status & azx_dev->sd_int_sta_mask) {
1091 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 1092 if (!azx_dev->substream || !azx_dev->running)
1093 continue;
1094 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1095 ok = azx_position_ok(chip, azx_dev);
1096 if (ok == 1) {
9ad593f6 1097 azx_dev->irq_pending = 0;
1da177e4
LT		 1098 spin_unlock(&chip->reg_lock);
1099 snd_pcm_period_elapsed(azx_dev->substream);
1100 spin_lock(&chip->reg_lock);
fa00e046 1101 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1102 /* bogus IRQ, process it later */
1103 azx_dev->irq_pending = 1;
6acaed38
TI		 1104 queue_work(chip->bus->workq,
1105 &chip->irq_pending_work);
1da177e4
LT		 1106 }
1107 }
1108 }
1109
1110 /* clear rirb int */
1111 status = azx_readb(chip, RIRBSTS);
1112 if (status & RIRB_INT_MASK) {
81740861 1113 if (status & RIRB_INT_RESPONSE)
1da177e4
LT		 1114 azx_update_rirb(chip);
1115 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1116 }
1117
1118#if 0
1119 /* clear state status int */
1120 if (azx_readb(chip, STATESTS) & 0x04)
1121 azx_writeb(chip, STATESTS, 0x04);
1122#endif
1123 spin_unlock(&chip->reg_lock);
1124
1125 return IRQ_HANDLED;
1126}
1127
1128
675f25d4
TI		 1129/*
1130 * set up a BDL entry
1131 */
1132static int setup_bdle(struct snd_pcm_substream *substream,
1133 struct azx_dev *azx_dev, u32 **bdlp,
1134 int ofs, int size, int with_ioc)
1135{
675f25d4
TI		 1136 u32 *bdl = *bdlp;
1137
1138 while (size > 0) {
1139 dma_addr_t addr;
1140 int chunk;
1141
1142 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1143 return -EINVAL;
1144
77a23f26 1145 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1146 /* program the address field of the BDL entry */
1147 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1148 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1149 /* program the size field of the BDL entry */
fc4abee8 1150 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1151 bdl[2] = cpu_to_le32(chunk);
1152 /* program the IOC to enable interrupt
1153 * only when the whole fragment is processed
1154 */
1155 size -= chunk;
1156 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1157 bdl += 4;
1158 azx_dev->frags++;
1159 ofs += chunk;
1160 }
1161 *bdlp = bdl;
1162 return ofs;
1163}
1164
1da177e4
LT		 1165/*
1166 * set up BDL entries
1167 */
555e219f
TI		 1168static int azx_setup_periods(struct azx *chip,
1169 struct snd_pcm_substream *substream,
4ce107b9 1170 struct azx_dev *azx_dev)
1da177e4 1171{
4ce107b9
TI		 1172 u32 *bdl;
1173 int i, ofs, periods, period_bytes;
555e219f 1174 int pos_adj;
1da177e4
LT		 1175
1176 /* reset BDL address */
1177 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1178 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1179
97b71c94 1180 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1181 periods = azx_dev->bufsize / period_bytes;
1182
1da177e4 1183 /* program the initial BDL entries */
4ce107b9
TI		 1184 bdl = (u32 *)azx_dev->bdl.area;
1185 ofs = 0;
1186 azx_dev->frags = 0;
555e219f
TI		 1187 pos_adj = bdl_pos_adj[chip->dev_index];
1188 if (pos_adj > 0) {
675f25d4 1189 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1190 int pos_align = pos_adj;
555e219f 1191 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1192 if (!pos_adj)
e785d3d8
TI		 1193 pos_adj = pos_align;
1194 else
1195 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1196 pos_align;
675f25d4
TI		 1197 pos_adj = frames_to_bytes(runtime, pos_adj);
1198 if (pos_adj >= period_bytes) {
4abc1cc2 1199 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1200 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1201 pos_adj = 0;
1202 } else {
1203 ofs = setup_bdle(substream, azx_dev,
1204 &bdl, ofs, pos_adj, 1);
1205 if (ofs < 0)
1206 goto error;
4ce107b9 1207 }
555e219f
TI		 1208 } else
1209 pos_adj = 0;
675f25d4
TI		 1210 for (i = 0; i < periods; i++) {
1211 if (i == periods - 1 && pos_adj)
1212 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1213 period_bytes - pos_adj, 0);
1214 else
1215 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1216 period_bytes, 1);
1217 if (ofs < 0)
1218 goto error;
1da177e4 1219 }
4ce107b9 1220 return 0;
675f25d4
TI		 1221
1222 error:
4abc1cc2 1223 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1224 azx_dev->bufsize, period_bytes);
675f25d4 1225 return -EINVAL;
1da177e4
LT		 1226}
1227
1dddab40
TI		 1228/* reset stream */
1229static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1230{
1231 unsigned char val;
1232 int timeout;
1233
1dddab40
TI		 1234 azx_stream_clear(chip, azx_dev);
1235
d01ce99f
TI		 1236 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1237 SD_CTL_STREAM_RESET);
1da177e4
LT		 1238 udelay(3);
1239 timeout = 300;
1240 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1241 --timeout)
1242 ;
1243 val &= ~SD_CTL_STREAM_RESET;
1244 azx_sd_writeb(azx_dev, SD_CTL, val);
1245 udelay(3);
1246
1247 timeout = 300;
1248 /* waiting for hardware to report that the stream is out of reset */
1249 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1250 --timeout)
1251 ;
fa00e046
JK		 1252
1253 /* reset first position - may not be synced with hw at this time */
1254 *azx_dev->posbuf = 0;
1dddab40 1255}
1da177e4 1256
1dddab40
TI		 1257/*
1258 * set up the SD for streaming
1259 */
1260static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1261{
1262 /* make sure the run bit is zero for SD */
1263 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1264 /* program the stream_tag */
1265 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1266 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1267 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1268
1269 /* program the length of samples in cyclic buffer */
1270 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1271
1272 /* program the stream format */
1273 /* this value needs to be the same as the one programmed */
1274 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1275
1276 /* program the stream LVI (last valid index) of the BDL */
1277 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1278
1279 /* program the BDL address */
1280 /* lower BDL address */
4ce107b9 1281 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1282 /* upper BDL address */
766979e0 1283 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1284
0be3b5d3 1285 /* enable the position buffer */
ee9d6b9a 1286 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1287 chip->position_fix == POS_FIX_AUTO ||
1288 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1289 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1290 azx_writel(chip, DPLBASE,
1291 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1292 }
c74db86b 1293
1da177e4 1294 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1295 azx_sd_writel(azx_dev, SD_CTL,
1296 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1297
1298 return 0;
1299}
1300
6ce4a3bc
TI		 1301/*
1302 * Probe the given codec address
1303 */
1304static int probe_codec(struct azx *chip, int addr)
1305{
1306 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1307 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1308 unsigned int res;
1309
a678cdee 1310 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1311 chip->probing = 1;
1312 azx_send_cmd(chip->bus, cmd);
deadff16 1313 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1314 chip->probing = 0;
a678cdee 1315 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1316 if (res == -1)
1317 return -EIO;
4abc1cc2 1318 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1319 return 0;
1320}
1321
33fa35ed
TI		 1322static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1323 struct hda_pcm *cpcm);
6ce4a3bc 1324static void azx_stop_chip(struct azx *chip);
1da177e4 1325
8dd78330
TI		 1326static void azx_bus_reset(struct hda_bus *bus)
1327{
1328 struct azx *chip = bus->private_data;
8dd78330
TI		 1329
1330 bus->in_reset = 1;
1331 azx_stop_chip(chip);
1332 azx_init_chip(chip);
65f75983 1333#ifdef CONFIG_PM
8dd78330 1334 if (chip->initialized) {
65f75983
AB		 1335 int i;
1336
8dd78330
TI		 1337 for (i = 0; i < AZX_MAX_PCMS; i++)
1338 snd_pcm_suspend_all(chip->pcm[i]);
1339 snd_hda_suspend(chip->bus);
1340 snd_hda_resume(chip->bus);
1341 }
65f75983 1342#endif
8dd78330
TI		 1343 bus->in_reset = 0;
1344}
1345
1da177e4
LT		 1346/*
1347 * Codec initialization
1348 */
1349
2f5983f2
TI		 1350/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1351static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
f269002e 1352 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1353};
1354
a1e21c90 1355static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1356{
1357 struct hda_bus_template bus_temp;
34c25350
TI		 1358 int c, codecs, err;
1359 int max_slots;
1da177e4
LT		 1360
1361 memset(&bus_temp, 0, sizeof(bus_temp));
1362 bus_temp.private_data = chip;
1363 bus_temp.modelname = model;
1364 bus_temp.pci = chip->pci;
111d3af5
TI		 1365 bus_temp.ops.command = azx_send_cmd;
1366 bus_temp.ops.get_response = azx_get_response;
176d5335 1367 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1368 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1369#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1370 bus_temp.power_save = &power_save;
cb53c626
TI		 1371 bus_temp.ops.pm_notify = azx_power_notify;
1372#endif
1da177e4 1373
d01ce99f
TI		 1374 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1375 if (err < 0)
1da177e4
LT		 1376 return err;
1377
dc9c8e21
WN		 1378 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1379 chip->bus->needs_damn_long_delay = 1;
1380
34c25350 1381 codecs = 0;
2f5983f2
TI		 1382 max_slots = azx_max_codecs[chip->driver_type];
1383 if (!max_slots)
1384 max_slots = AZX_MAX_CODECS;
6ce4a3bc
TI		 1385
1386 /* First try to probe all given codec slots */
1387 for (c = 0; c < max_slots; c++) {
f1eaaeec 1388 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1389 if (probe_codec(chip, c) < 0) {
1390 /* Some BIOSen give you wrong codec addresses
1391 * that don't exist
1392 */
4abc1cc2
TI		 1393 snd_printk(KERN_WARNING SFX
1394 "Codec #%d probe error; "
6ce4a3bc
TI		 1395 "disabling it...\n", c);
1396 chip->codec_mask &= ~(1 << c);
1397 /* More badly, accessing to a non-existing
1398 * codec often screws up the controller chip,
1399 * and distrubs the further communications.
1400 * Thus if an error occurs during probing,
1401 * better to reset the controller chip to
1402 * get back to the sanity state.
1403 */
1404 azx_stop_chip(chip);
1405 azx_init_chip(chip);
1406 }
1407 }
1408 }
1409
1410 /* Then create codec instances */
34c25350 1411 for (c = 0; c < max_slots; c++) {
f1eaaeec 1412 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1413 struct hda_codec *codec;
a1e21c90 1414 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1415 if (err < 0)
1416 continue;
2dca0bba 1417 codec->beep_mode = chip->beep_mode;
1da177e4 1418 codecs++;
19a982b6
TI		 1419 }
1420 }
1421 if (!codecs) {
1da177e4
LT		 1422 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1423 return -ENXIO;
1424 }
a1e21c90
TI		 1425 return 0;
1426}
1da177e4 1427
a1e21c90
TI		 1428/* configure each codec instance */
1429static int __devinit azx_codec_configure(struct azx *chip)
1430{
1431 struct hda_codec *codec;
1432 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1433 snd_hda_codec_configure(codec);
1434 }
1da177e4
LT		 1435 return 0;
1436}
1437
1438
1439/*
1440 * PCM support
1441 */
1442
1443/* assign a stream for the PCM */
a98f90fd 1444static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1445{
07e4ca50
TI		 1446 int dev, i, nums;
1447 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1448 dev = chip->playback_index_offset;
1449 nums = chip->playback_streams;
1450 } else {
1451 dev = chip->capture_index_offset;
1452 nums = chip->capture_streams;
1453 }
1454 for (i = 0; i < nums; i++, dev++)
d01ce99f 1455 if (!chip->azx_dev[dev].opened) {
1da177e4
LT		 1456 chip->azx_dev[dev].opened = 1;
1457 return &chip->azx_dev[dev];
1458 }
1459 return NULL;
1460}
1461
1462/* release the assigned stream */
a98f90fd 1463static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1464{
1465 azx_dev->opened = 0;
1466}
1467
a98f90fd 1468static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1469 .info = (SNDRV_PCM_INFO_MMAP |
1470 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1471 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1472 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1473 /* No full-resume yet implemented */
1474 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1475 SNDRV_PCM_INFO_PAUSE |
1476 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1477 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1478 .rates = SNDRV_PCM_RATE_48000,
1479 .rate_min = 48000,
1480 .rate_max = 48000,
1481 .channels_min = 2,
1482 .channels_max = 2,
1483 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1484 .period_bytes_min = 128,
1485 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1486 .periods_min = 2,
1487 .periods_max = AZX_MAX_FRAG,
1488 .fifo_size = 0,
1489};
1490
1491struct azx_pcm {
a98f90fd 1492 struct azx *chip;
1da177e4
LT		 1493 struct hda_codec *codec;
1494 struct hda_pcm_stream *hinfo[2];
1495};
1496
a98f90fd 1497static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1498{
1499 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1500 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1501 struct azx *chip = apcm->chip;
1502 struct azx_dev *azx_dev;
1503 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1504 unsigned long flags;
1505 int err;
1506
62932df8 1507 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1508 azx_dev = azx_assign_device(chip, substream->stream);
1509 if (azx_dev == NULL) {
62932df8 1510 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1511 return -EBUSY;
1512 }
1513 runtime->hw = azx_pcm_hw;
1514 runtime->hw.channels_min = hinfo->channels_min;
1515 runtime->hw.channels_max = hinfo->channels_max;
1516 runtime->hw.formats = hinfo->formats;
1517 runtime->hw.rates = hinfo->rates;
1518 snd_pcm_limit_hw_rates(runtime);
1519 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1520 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1521 128);
1522 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1523 128);
cb53c626 1524 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1525 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1526 if (err < 0) {
1da177e4 1527 azx_release_device(azx_dev);
cb53c626 1528 snd_hda_power_down(apcm->codec);
62932df8 1529 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1530 return err;
1531 }
70d321e6 1532 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1533 /* sanity check */
1534 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1535 snd_BUG_ON(!runtime->hw.channels_max) ||
1536 snd_BUG_ON(!runtime->hw.formats) ||
1537 snd_BUG_ON(!runtime->hw.rates)) {
1538 azx_release_device(azx_dev);
1539 hinfo->ops.close(hinfo, apcm->codec, substream);
1540 snd_hda_power_down(apcm->codec);
1541 mutex_unlock(&chip->open_mutex);
1542 return -EINVAL;
1543 }
1da177e4
LT		 1544 spin_lock_irqsave(&chip->reg_lock, flags);
1545 azx_dev->substream = substream;
1546 azx_dev->running = 0;
1547 spin_unlock_irqrestore(&chip->reg_lock, flags);
1548
1549 runtime->private_data = azx_dev;
850f0e52 1550 snd_pcm_set_sync(substream);
62932df8 1551 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1552 return 0;
1553}
1554
a98f90fd 1555static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1556{
1557 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1558 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1559 struct azx *chip = apcm->chip;
1560 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1561 unsigned long flags;
1562
62932df8 1563 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1564 spin_lock_irqsave(&chip->reg_lock, flags);
1565 azx_dev->substream = NULL;
1566 azx_dev->running = 0;
1567 spin_unlock_irqrestore(&chip->reg_lock, flags);
1568 azx_release_device(azx_dev);
1569 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1570 snd_hda_power_down(apcm->codec);
62932df8 1571 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1572 return 0;
1573}
1574
d01ce99f
TI		 1575static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1576 struct snd_pcm_hw_params *hw_params)
1da177e4 1577{
97b71c94
TI		 1578 struct azx_dev *azx_dev = get_azx_dev(substream);
1579
1580 azx_dev->bufsize = 0;
1581 azx_dev->period_bytes = 0;
1582 azx_dev->format_val = 0;
d01ce99f
TI		 1583 return snd_pcm_lib_malloc_pages(substream,
1584 params_buffer_bytes(hw_params));
1da177e4
LT		 1585}
1586
a98f90fd 1587static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1588{
1589 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1590 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1591 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1592
1593 /* reset BDL address */
1594 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1595 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1596 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1597 azx_dev->bufsize = 0;
1598 azx_dev->period_bytes = 0;
1599 azx_dev->format_val = 0;
1da177e4
LT		 1600
1601 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1602
1603 return snd_pcm_lib_free_pages(substream);
1604}
1605
a98f90fd 1606static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1607{
1608 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1609 struct azx *chip = apcm->chip;
1610 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1611 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1612 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1613 unsigned int bufsize, period_bytes, format_val;
1614 int err;
1da177e4 1615
fa00e046 1616 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1617 format_val = snd_hda_calc_stream_format(runtime->rate,
1618 runtime->channels,
1619 runtime->format,
1620 hinfo->maxbps);
1621 if (!format_val) {
d01ce99f
TI		 1622 snd_printk(KERN_ERR SFX
1623 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1624 runtime->rate, runtime->channels, runtime->format);
1625 return -EINVAL;
1626 }
1627
97b71c94
TI		 1628 bufsize = snd_pcm_lib_buffer_bytes(substream);
1629 period_bytes = snd_pcm_lib_period_bytes(substream);
1630
4abc1cc2 1631 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1632 bufsize, format_val);
1633
1634 if (bufsize != azx_dev->bufsize ||
1635 period_bytes != azx_dev->period_bytes ||
1636 format_val != azx_dev->format_val) {
1637 azx_dev->bufsize = bufsize;
1638 azx_dev->period_bytes = period_bytes;
1639 azx_dev->format_val = format_val;
1640 err = azx_setup_periods(chip, substream, azx_dev);
1641 if (err < 0)
1642 return err;
1643 }
1644
fa00e046
JK		 1645 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1646 (runtime->rate * 2);
1da177e4
LT		 1647 azx_setup_controller(chip, azx_dev);
1648 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1649 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1650 else
1651 azx_dev->fifo_size = 0;
1652
1653 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1654 azx_dev->format_val, substream);
1655}
1656
a98f90fd 1657static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1658{
1659 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1660 struct azx *chip = apcm->chip;
850f0e52
TI		 1661 struct azx_dev *azx_dev;
1662 struct snd_pcm_substream *s;
fa00e046 1663 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1664 int nwait, timeout;
1da177e4 1665
1da177e4 1666 switch (cmd) {
fa00e046
JK		 1667 case SNDRV_PCM_TRIGGER_START:
1668 rstart = 1;
1da177e4
LT		 1669 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1670 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1671 start = 1;
1da177e4
LT		 1672 break;
1673 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1674 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1675 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1676 start = 0;
1da177e4
LT		 1677 break;
1678 default:
850f0e52
TI		 1679 return -EINVAL;
1680 }
1681
1682 snd_pcm_group_for_each_entry(s, substream) {
1683 if (s->pcm->card != substream->pcm->card)
1684 continue;
1685 azx_dev = get_azx_dev(s);
1686 sbits |= 1 << azx_dev->index;
1687 nsync++;
1688 snd_pcm_trigger_done(s, substream);
1689 }
1690
1691 spin_lock(&chip->reg_lock);
1692 if (nsync > 1) {
1693 /* first, set SYNC bits of corresponding streams */
1694 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1695 }
1696 snd_pcm_group_for_each_entry(s, substream) {
1697 if (s->pcm->card != substream->pcm->card)
1698 continue;
1699 azx_dev = get_azx_dev(s);
fa00e046
JK		 1700 if (rstart) {
1701 azx_dev->start_flag = 1;
1702 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1703 }
850f0e52
TI		 1704 if (start)
1705 azx_stream_start(chip, azx_dev);
1706 else
1707 azx_stream_stop(chip, azx_dev);
1708 azx_dev->running = start;
1da177e4
LT		 1709 }
1710 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1711 if (start) {
1712 if (nsync == 1)
1713 return 0;
1714 /* wait until all FIFOs get ready */
1715 for (timeout = 5000; timeout; timeout--) {
1716 nwait = 0;
1717 snd_pcm_group_for_each_entry(s, substream) {
1718 if (s->pcm->card != substream->pcm->card)
1719 continue;
1720 azx_dev = get_azx_dev(s);
1721 if (!(azx_sd_readb(azx_dev, SD_STS) &
1722 SD_STS_FIFO_READY))
1723 nwait++;
1724 }
1725 if (!nwait)
1726 break;
1727 cpu_relax();
1728 }
1729 } else {
1730 /* wait until all RUN bits are cleared */
1731 for (timeout = 5000; timeout; timeout--) {
1732 nwait = 0;
1733 snd_pcm_group_for_each_entry(s, substream) {
1734 if (s->pcm->card != substream->pcm->card)
1735 continue;
1736 azx_dev = get_azx_dev(s);
1737 if (azx_sd_readb(azx_dev, SD_CTL) &
1738 SD_CTL_DMA_START)
1739 nwait++;
1740 }
1741 if (!nwait)
1742 break;
1743 cpu_relax();
1744 }
1da177e4 1745 }
850f0e52
TI		 1746 if (nsync > 1) {
1747 spin_lock(&chip->reg_lock);
1748 /* reset SYNC bits */
1749 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1750 spin_unlock(&chip->reg_lock);
1751 }
1752 return 0;
1da177e4
LT		 1753}
1754
0e153474
JC		 1755/* get the current DMA position with correction on VIA chips */
1756static unsigned int azx_via_get_position(struct azx *chip,
1757 struct azx_dev *azx_dev)
1758{
1759 unsigned int link_pos, mini_pos, bound_pos;
1760 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1761 unsigned int fifo_size;
1762
1763 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1764 if (azx_dev->index >= 4) {
1765 /* Playback, no problem using link position */
1766 return link_pos;
1767 }
1768
1769 /* Capture */
1770 /* For new chipset,
1771 * use mod to get the DMA position just like old chipset
1772 */
1773 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1774 mod_dma_pos %= azx_dev->period_bytes;
1775
1776 /* azx_dev->fifo_size can't get FIFO size of in stream.
1777 * Get from base address + offset.
1778 */
1779 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1780
1781 if (azx_dev->insufficient) {
1782 /* Link position never gather than FIFO size */
1783 if (link_pos <= fifo_size)
1784 return 0;
1785
1786 azx_dev->insufficient = 0;
1787 }
1788
1789 if (link_pos <= fifo_size)
1790 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1791 else
1792 mini_pos = link_pos - fifo_size;
1793
1794 /* Find nearest previous boudary */
1795 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1796 mod_link_pos = link_pos % azx_dev->period_bytes;
1797 if (mod_link_pos >= fifo_size)
1798 bound_pos = link_pos - mod_link_pos;
1799 else if (mod_dma_pos >= mod_mini_pos)
1800 bound_pos = mini_pos - mod_mini_pos;
1801 else {
1802 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1803 if (bound_pos >= azx_dev->bufsize)
1804 bound_pos = 0;
1805 }
1806
1807 /* Calculate real DMA position we want */
1808 return bound_pos + mod_dma_pos;
1809}
1810
9ad593f6
TI		 1811static unsigned int azx_get_position(struct azx *chip,
1812 struct azx_dev *azx_dev)
1da177e4 1813{
1da177e4
LT		 1814 unsigned int pos;
1815
0e153474
JC		 1816 if (chip->via_dmapos_patch)
1817 pos = azx_via_get_position(chip, azx_dev);
1818 else if (chip->position_fix == POS_FIX_POSBUF ||
1819 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1820 /* use the position buffer */
929861c6 1821 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1822 } else {
1823 /* read LPIB */
1824 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1825 }
1da177e4
LT		 1826 if (pos >= azx_dev->bufsize)
1827 pos = 0;
9ad593f6
TI		 1828 return pos;
1829}
1830
1831static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1832{
1833 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1834 struct azx *chip = apcm->chip;
1835 struct azx_dev *azx_dev = get_azx_dev(substream);
1836 return bytes_to_frames(substream->runtime,
1837 azx_get_position(chip, azx_dev));
1838}
1839
1840/*
1841 * Check whether the current DMA position is acceptable for updating
1842 * periods. Returns non-zero if it's OK.
1843 *
1844 * Many HD-audio controllers appear pretty inaccurate about
1845 * the update-IRQ timing. The IRQ is issued before actually the
1846 * data is processed. So, we need to process it afterwords in a
1847 * workqueue.
1848 */
1849static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1850{
1851 unsigned int pos;
1852
fa00e046
JK		 1853 if (azx_dev->start_flag &&
1854 time_before_eq(jiffies, azx_dev->start_jiffies))
1855 return -1; /* bogus (too early) interrupt */
1856 azx_dev->start_flag = 0;
1857
9ad593f6
TI		 1858 pos = azx_get_position(chip, azx_dev);
1859 if (chip->position_fix == POS_FIX_AUTO) {
1860 if (!pos) {
1861 printk(KERN_WARNING
1862 "hda-intel: Invalid position buffer, "
1863 "using LPIB read method instead.\n");
d2e1c973 1864 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1865 pos = azx_get_position(chip, azx_dev);
1866 } else
1867 chip->position_fix = POS_FIX_POSBUF;
1868 }
1869
a62741cf
TI		 1870 if (!bdl_pos_adj[chip->dev_index])
1871 return 1; /* no delayed ack */
9ad593f6
TI		 1872 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1873 return 0; /* NG - it's below the period boundary */
1874 return 1; /* OK, it's fine */
1875}
1876
1877/*
1878 * The work for pending PCM period updates.
1879 */
1880static void azx_irq_pending_work(struct work_struct *work)
1881{
1882 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1883 int i, pending;
1884
a6a950a8
TI		 1885 if (!chip->irq_pending_warned) {
1886 printk(KERN_WARNING
1887 "hda-intel: IRQ timing workaround is activated "
1888 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1889 chip->card->number);
1890 chip->irq_pending_warned = 1;
1891 }
1892
9ad593f6
TI		 1893 for (;;) {
1894 pending = 0;
1895 spin_lock_irq(&chip->reg_lock);
1896 for (i = 0; i < chip->num_streams; i++) {
1897 struct azx_dev *azx_dev = &chip->azx_dev[i];
1898 if (!azx_dev->irq_pending ||
1899 !azx_dev->substream ||
1900 !azx_dev->running)
1901 continue;
1902 if (azx_position_ok(chip, azx_dev)) {
1903 azx_dev->irq_pending = 0;
1904 spin_unlock(&chip->reg_lock);
1905 snd_pcm_period_elapsed(azx_dev->substream);
1906 spin_lock(&chip->reg_lock);
1907 } else
1908 pending++;
1909 }
1910 spin_unlock_irq(&chip->reg_lock);
1911 if (!pending)
1912 return;
1913 cond_resched();
1914 }
1915}
1916
1917/* clear irq_pending flags and assure no on-going workq */
1918static void azx_clear_irq_pending(struct azx *chip)
1919{
1920 int i;
1921
1922 spin_lock_irq(&chip->reg_lock);
1923 for (i = 0; i < chip->num_streams; i++)
1924 chip->azx_dev[i].irq_pending = 0;
1925 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1926}
1927
a98f90fd 1928static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1929 .open = azx_pcm_open,
1930 .close = azx_pcm_close,
1931 .ioctl = snd_pcm_lib_ioctl,
1932 .hw_params = azx_pcm_hw_params,
1933 .hw_free = azx_pcm_hw_free,
1934 .prepare = azx_pcm_prepare,
1935 .trigger = azx_pcm_trigger,
1936 .pointer = azx_pcm_pointer,
4ce107b9 1937 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1938};
1939
a98f90fd 1940static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1941{
176d5335
TI		 1942 struct azx_pcm *apcm = pcm->private_data;
1943 if (apcm) {
1944 apcm->chip->pcm[pcm->device] = NULL;
1945 kfree(apcm);
1946 }
1da177e4
LT		 1947}
1948
176d5335 1949static int
33fa35ed
TI		 1950azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1951 struct hda_pcm *cpcm)
1da177e4 1952{
33fa35ed 1953 struct azx *chip = bus->private_data;
a98f90fd 1954 struct snd_pcm *pcm;
1da177e4 1955 struct azx_pcm *apcm;
176d5335
TI		 1956 int pcm_dev = cpcm->device;
1957 int s, err;
1da177e4 1958
176d5335
TI		 1959 if (pcm_dev >= AZX_MAX_PCMS) {
1960 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1961 pcm_dev);
da3cec35 1962 return -EINVAL;
176d5335
TI		 1963 }
1964 if (chip->pcm[pcm_dev]) {
1965 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1966 return -EBUSY;
1967 }
1968 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1969 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1970 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 1971 &pcm);
1972 if (err < 0)
1973 return err;
18cb7109 1974 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 1975 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 1976 if (apcm == NULL)
1977 return -ENOMEM;
1978 apcm->chip = chip;
1979 apcm->codec = codec;
1da177e4
LT		 1980 pcm->private_data = apcm;
1981 pcm->private_free = azx_pcm_free;
176d5335
TI		 1982 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1983 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1984 chip->pcm[pcm_dev] = pcm;
1985 cpcm->pcm = pcm;
1986 for (s = 0; s < 2; s++) {
1987 apcm->hinfo[s] = &cpcm->stream[s];
1988 if (cpcm->stream[s].substreams)
1989 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1990 }
1991 /* buffer pre-allocation */
4ce107b9 1992 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 1993 snd_dma_pci_data(chip->pci),
fc4abee8 1994 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 1995 return 0;
1996}
1997
1998/*
1999 * mixer creation - all stuff is implemented in hda module
2000 */
a98f90fd 2001static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2002{
2003 return snd_hda_build_controls(chip->bus);
2004}
2005
2006
2007/*
2008 * initialize SD streams
2009 */
a98f90fd 2010static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2011{
2012 int i;
2013
2014 /* initialize each stream (aka device)
d01ce99f
TI		 2015 * assign the starting bdl address to each stream (device)
2016 * and initialize
1da177e4 2017 */
07e4ca50 2018 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2019 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2020 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2021 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2022 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2023 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2024 azx_dev->sd_int_sta_mask = 1 << i;
2025 /* stream tag: must be non-zero and unique */
2026 azx_dev->index = i;
2027 azx_dev->stream_tag = i + 1;
2028 }
2029
2030 return 0;
2031}
2032
68e7fffc
TI		 2033static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2034{
437a5a46
TI		 2035 if (request_irq(chip->pci->irq, azx_interrupt,
2036 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 2037 "HDA Intel", chip)) {
2038 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2039 "disabling device\n", chip->pci->irq);
2040 if (do_disconnect)
2041 snd_card_disconnect(chip->card);
2042 return -1;
2043 }
2044 chip->irq = chip->pci->irq;
69e13418 2045 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2046 return 0;
2047}
2048
1da177e4 2049
cb53c626
TI		 2050static void azx_stop_chip(struct azx *chip)
2051{
95e99fda 2052 if (!chip->initialized)
cb53c626
TI		 2053 return;
2054
2055 /* disable interrupts */
2056 azx_int_disable(chip);
2057 azx_int_clear(chip);
2058
2059 /* disable CORB/RIRB */
2060 azx_free_cmd_io(chip);
2061
2062 /* disable position buffer */
2063 azx_writel(chip, DPLBASE, 0);
2064 azx_writel(chip, DPUBASE, 0);
2065
2066 chip->initialized = 0;
2067}
2068
2069#ifdef CONFIG_SND_HDA_POWER_SAVE
2070/* power-up/down the controller */
33fa35ed 2071static void azx_power_notify(struct hda_bus *bus)
cb53c626 2072{
33fa35ed 2073 struct azx *chip = bus->private_data;
cb53c626
TI		 2074 struct hda_codec *c;
2075 int power_on = 0;
2076
33fa35ed 2077 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2078 if (c->power_on) {
2079 power_on = 1;
2080 break;
2081 }
2082 }
2083 if (power_on)
2084 azx_init_chip(chip);
0287d970
WF		 2085 else if (chip->running && power_save_controller &&
2086 !bus->power_keep_link_on)
cb53c626 2087 azx_stop_chip(chip);
cb53c626 2088}
5c0b9bec
TI		 2089#endif /* CONFIG_SND_HDA_POWER_SAVE */
2090
2091#ifdef CONFIG_PM
2092/*
2093 * power management
2094 */
986862bd
TI		 2095
2096static int snd_hda_codecs_inuse(struct hda_bus *bus)
2097{
2098 struct hda_codec *codec;
2099
2100 list_for_each_entry(codec, &bus->codec_list, list) {
2101 if (snd_hda_codec_needs_resume(codec))
2102 return 1;
2103 }
2104 return 0;
2105}
cb53c626 2106
421a1252 2107static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2108{
421a1252
TI		 2109 struct snd_card *card = pci_get_drvdata(pci);
2110 struct azx *chip = card->private_data;
1da177e4
LT		 2111 int i;
2112
421a1252 2113 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2114 azx_clear_irq_pending(chip);
7ba72ba1 2115 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 2116 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c 2117 if (chip->initialized)
8dd78330 2118 snd_hda_suspend(chip->bus);
cb53c626 2119 azx_stop_chip(chip);
30b35399 2120 if (chip->irq >= 0) {
43001c95 2121 free_irq(chip->irq, chip);
30b35399
TI		 2122 chip->irq = -1;
2123 }
68e7fffc 2124 if (chip->msi)
43001c95 2125 pci_disable_msi(chip->pci);
421a1252
TI		 2126 pci_disable_device(pci);
2127 pci_save_state(pci);
30b35399 2128 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2129 return 0;
2130}
2131
421a1252 2132static int azx_resume(struct pci_dev *pci)
1da177e4 2133{
421a1252
TI		 2134 struct snd_card *card = pci_get_drvdata(pci);
2135 struct azx *chip = card->private_data;
1da177e4 2136
d14a7e0b
TI		 2137 pci_set_power_state(pci, PCI_D0);
2138 pci_restore_state(pci);
30b35399
TI		 2139 if (pci_enable_device(pci) < 0) {
2140 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2141 "disabling device\n");
2142 snd_card_disconnect(card);
2143 return -EIO;
2144 }
2145 pci_set_master(pci);
68e7fffc
TI		 2146 if (chip->msi)
2147 if (pci_enable_msi(pci) < 0)
2148 chip->msi = 0;
2149 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2150 return -EIO;
cb53c626 2151 azx_init_pci(chip);
d804ad92
ML		 2152
2153 if (snd_hda_codecs_inuse(chip->bus))
2154 azx_init_chip(chip);
2155
1da177e4 2156 snd_hda_resume(chip->bus);
421a1252 2157 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2158 return 0;
2159}
2160#endif /* CONFIG_PM */
2161
2162
0cbf0098
TI		 2163/*
2164 * reboot notifier for hang-up problem at power-down
2165 */
2166static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2167{
2168 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2169 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2170 azx_stop_chip(chip);
2171 return NOTIFY_OK;
2172}
2173
2174static void azx_notifier_register(struct azx *chip)
2175{
2176 chip->reboot_notifier.notifier_call = azx_halt;
2177 register_reboot_notifier(&chip->reboot_notifier);
2178}
2179
2180static void azx_notifier_unregister(struct azx *chip)
2181{
2182 if (chip->reboot_notifier.notifier_call)
2183 unregister_reboot_notifier(&chip->reboot_notifier);
2184}
2185
1da177e4
LT		 2186/*
2187 * destructor
2188 */
a98f90fd 2189static int azx_free(struct azx *chip)
1da177e4 2190{
4ce107b9
TI		 2191 int i;
2192
0cbf0098
TI		 2193 azx_notifier_unregister(chip);
2194
ce43fbae 2195 if (chip->initialized) {
9ad593f6 2196 azx_clear_irq_pending(chip);
07e4ca50 2197 for (i = 0; i < chip->num_streams; i++)
1da177e4 2198 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2199 azx_stop_chip(chip);
1da177e4
LT		 2200 }
2201
f000fd80 2202 if (chip->irq >= 0)
1da177e4 2203 free_irq(chip->irq, (void*)chip);
68e7fffc 2204 if (chip->msi)
30b35399 2205 pci_disable_msi(chip->pci);
f079c25a
TI		 2206 if (chip->remap_addr)
2207 iounmap(chip->remap_addr);
1da177e4 2208
4ce107b9
TI		 2209 if (chip->azx_dev) {
2210 for (i = 0; i < chip->num_streams; i++)
2211 if (chip->azx_dev[i].bdl.area)
2212 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2213 }
1da177e4
LT		 2214 if (chip->rb.area)
2215 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2216 if (chip->posbuf.area)
2217 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2218 pci_release_regions(chip->pci);
2219 pci_disable_device(chip->pci);
07e4ca50 2220 kfree(chip->azx_dev);
1da177e4
LT		 2221 kfree(chip);
2222
2223 return 0;
2224}
2225
a98f90fd 2226static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2227{
2228 return azx_free(device->device_data);
2229}
2230
3372a153
TI		 2231/*
2232 * white/black-listing for position_fix
2233 */
623ec047 2234static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2235 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2236 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2237 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2238 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
45d4ebf1 2239 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3372a153
TI		 2240 {}
2241};
2242
2243static int __devinit check_position_fix(struct azx *chip, int fix)
2244{
2245 const struct snd_pci_quirk *q;
2246
c673ba1c
TI		 2247 switch (fix) {
2248 case POS_FIX_LPIB:
2249 case POS_FIX_POSBUF:
2250 return fix;
2251 }
2252
2253 /* Check VIA/ATI HD Audio Controller exist */
2254 switch (chip->driver_type) {
2255 case AZX_DRIVER_VIA:
2256 case AZX_DRIVER_ATI:
0e153474
JC		 2257 chip->via_dmapos_patch = 1;
2258 /* Use link position directly, avoid any transfer problem. */
2259 return POS_FIX_LPIB;
2260 }
2261 chip->via_dmapos_patch = 0;
2262
c673ba1c
TI		 2263 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2264 if (q) {
2265 printk(KERN_INFO
2266 "hda_intel: position_fix set to %d "
2267 "for device %04x:%04x\n",
2268 q->value, q->subvendor, q->subdevice);
2269 return q->value;
3372a153 2270 }
c673ba1c 2271 return POS_FIX_AUTO;
3372a153
TI		 2272}
2273
669ba27a
TI		 2274/*
2275 * black-lists for probe_mask
2276 */
2277static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2278 /* Thinkpad often breaks the controller communication when accessing
2279 * to the non-working (or non-existing) modem codec slot.
2280 */
2281 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2282 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2283 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2284 /* broken BIOS */
2285 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2286 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2287 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2288 /* forced codec slots */
93574844 2289 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2290 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2291 {}
2292};
2293
f1eaaeec
TI		 2294#define AZX_FORCE_CODEC_MASK 0x100
2295
5aba4f8e 2296static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2297{
2298 const struct snd_pci_quirk *q;
2299
f1eaaeec
TI		 2300 chip->codec_probe_mask = probe_mask[dev];
2301 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2302 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2303 if (q) {
2304 printk(KERN_INFO
2305 "hda_intel: probe_mask set to 0x%x "
2306 "for device %04x:%04x\n",
2307 q->value, q->subvendor, q->subdevice);
f1eaaeec 2308 chip->codec_probe_mask = q->value;
669ba27a
TI		 2309 }
2310 }
f1eaaeec
TI		 2311
2312 /* check forced option */
2313 if (chip->codec_probe_mask != -1 &&
2314 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2315 chip->codec_mask = chip->codec_probe_mask & 0xff;
2316 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2317 chip->codec_mask);
2318 }
669ba27a
TI		 2319}
2320
4d8e22e0 2321/*
71623855 2322 * white/black-list for enable_msi
4d8e22e0 2323 */
71623855 2324static struct snd_pci_quirk msi_black_list[] __devinitdata = {
4d8e22e0
TI		 2325 {}
2326};
2327
2328static void __devinit check_msi(struct azx *chip)
2329{
2330 const struct snd_pci_quirk *q;
2331
71623855
TI		 2332 if (enable_msi >= 0) {
2333 chip->msi = !!enable_msi;
4d8e22e0 2334 return;
71623855
TI		 2335 }
2336 chip->msi = 1; /* enable MSI as default */
2337 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2338 if (q) {
2339 printk(KERN_INFO
2340 "hda_intel: msi for device %04x:%04x set to %d\n",
2341 q->subvendor, q->subdevice, q->value);
2342 chip->msi = q->value;
2343 }
2344}
2345
669ba27a 2346
1da177e4
LT		 2347/*
2348 * constructor
2349 */
a98f90fd 2350static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2351 int dev, int driver_type,
a98f90fd 2352 struct azx **rchip)
1da177e4 2353{
a98f90fd 2354 struct azx *chip;
4ce107b9 2355 int i, err;
bcd72003 2356 unsigned short gcap;
a98f90fd 2357 static struct snd_device_ops ops = {
1da177e4
LT		 2358 .dev_free = azx_dev_free,
2359 };
2360
2361 *rchip = NULL;
bcd72003 2362
927fc866
PM		 2363 err = pci_enable_device(pci);
2364 if (err < 0)
1da177e4
LT		 2365 return err;
2366
e560d8d8 2367 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2368 if (!chip) {
1da177e4
LT		 2369 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2370 pci_disable_device(pci);
2371 return -ENOMEM;
2372 }
2373
2374 spin_lock_init(&chip->reg_lock);
62932df8 2375 mutex_init(&chip->open_mutex);
1da177e4
LT		 2376 chip->card = card;
2377 chip->pci = pci;
2378 chip->irq = -1;
07e4ca50 2379 chip->driver_type = driver_type;
4d8e22e0 2380 check_msi(chip);
555e219f 2381 chip->dev_index = dev;
9ad593f6 2382 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2383
5aba4f8e
TI		 2384 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2385 check_probe_mask(chip, dev);
3372a153 2386
27346166 2387 chip->single_cmd = single_cmd;
c74db86b 2388
5c0d7bc1
TI		 2389 if (bdl_pos_adj[dev] < 0) {
2390 switch (chip->driver_type) {
0c6341ac
TI		 2391 case AZX_DRIVER_ICH:
2392 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2393 break;
2394 default:
0c6341ac 2395 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2396 break;
2397 }
2398 }
2399
07e4ca50
TI		 2400#if BITS_PER_LONG != 64
2401 /* Fix up base address on ULI M5461 */
2402 if (chip->driver_type == AZX_DRIVER_ULI) {
2403 u16 tmp3;
2404 pci_read_config_word(pci, 0x40, &tmp3);
2405 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2406 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2407 }
2408#endif
2409
927fc866
PM		 2410 err = pci_request_regions(pci, "ICH HD audio");
2411 if (err < 0) {
1da177e4
LT		 2412 kfree(chip);
2413 pci_disable_device(pci);
2414 return err;
2415 }
2416
927fc866 2417 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2418 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2419 if (chip->remap_addr == NULL) {
2420 snd_printk(KERN_ERR SFX "ioremap error\n");
2421 err = -ENXIO;
2422 goto errout;
2423 }
2424
68e7fffc
TI		 2425 if (chip->msi)
2426 if (pci_enable_msi(pci) < 0)
2427 chip->msi = 0;
7376d013 2428
68e7fffc 2429 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2430 err = -EBUSY;
2431 goto errout;
2432 }
1da177e4
LT		 2433
2434 pci_set_master(pci);
2435 synchronize_irq(chip->irq);
2436
bcd72003 2437 gcap = azx_readw(chip, GCAP);
4abc1cc2 2438 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2439
dc4c2e6b
AB		 2440 /* disable SB600 64bit support for safety */
2441 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2442 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2443 struct pci_dev *p_smbus;
2444 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2445 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2446 NULL);
2447 if (p_smbus) {
2448 if (p_smbus->revision < 0x30)
2449 gcap &= ~ICH6_GCAP_64OK;
2450 pci_dev_put(p_smbus);
2451 }
2452 }
09240cf4 2453
396087ea
JK		 2454 /* disable 64bit DMA address for Teradici */
2455 /* it does not work with device 6549:1200 subsys e4a2:040b */
2456 if (chip->driver_type == AZX_DRIVER_TERA)
2457 gcap &= ~ICH6_GCAP_64OK;
2458
cf7aaca8 2459 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2460 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2461 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2462 else {
e930438c
YH		 2463 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2464 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2465 }
cf7aaca8 2466
8b6ed8e7
TI		 2467 /* read number of streams from GCAP register instead of using
2468 * hardcoded value
2469 */
2470 chip->capture_streams = (gcap >> 8) & 0x0f;
2471 chip->playback_streams = (gcap >> 12) & 0x0f;
2472 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2473 /* gcap didn't give any info, switching to old method */
2474
2475 switch (chip->driver_type) {
2476 case AZX_DRIVER_ULI:
2477 chip->playback_streams = ULI_NUM_PLAYBACK;
2478 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2479 break;
2480 case AZX_DRIVER_ATIHDMI:
2481 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2482 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2483 break;
c4da29ca 2484 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2485 default:
2486 chip->playback_streams = ICH6_NUM_PLAYBACK;
2487 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2488 break;
2489 }
07e4ca50 2490 }
8b6ed8e7
TI		 2491 chip->capture_index_offset = 0;
2492 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2493 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2494 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2495 GFP_KERNEL);
927fc866 2496 if (!chip->azx_dev) {
4abc1cc2 2497 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2498 goto errout;
2499 }
2500
4ce107b9
TI		 2501 for (i = 0; i < chip->num_streams; i++) {
2502 /* allocate memory for the BDL for each stream */
2503 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2504 snd_dma_pci_data(chip->pci),
2505 BDL_SIZE, &chip->azx_dev[i].bdl);
2506 if (err < 0) {
2507 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2508 goto errout;
2509 }
1da177e4 2510 }
0be3b5d3 2511 /* allocate memory for the position buffer */
d01ce99f
TI		 2512 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2513 snd_dma_pci_data(chip->pci),
2514 chip->num_streams * 8, &chip->posbuf);
2515 if (err < 0) {
0be3b5d3
TI		 2516 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2517 goto errout;
1da177e4 2518 }
1da177e4 2519 /* allocate CORB/RIRB */
81740861
TI		 2520 err = azx_alloc_cmd_io(chip);
2521 if (err < 0)
2522 goto errout;
1da177e4
LT		 2523
2524 /* initialize streams */
2525 azx_init_stream(chip);
2526
2527 /* initialize chip */
cb53c626 2528 azx_init_pci(chip);
1da177e4
LT		 2529 azx_init_chip(chip);
2530
2531 /* codec detection */
927fc866 2532 if (!chip->codec_mask) {
1da177e4
LT		 2533 snd_printk(KERN_ERR SFX "no codecs found!\n");
2534 err = -ENODEV;
2535 goto errout;
2536 }
2537
d01ce99f
TI		 2538 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2539 if (err <0) {
1da177e4
LT		 2540 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2541 goto errout;
2542 }
2543
07e4ca50 2544 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2545 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2546 sizeof(card->shortname));
2547 snprintf(card->longname, sizeof(card->longname),
2548 "%s at 0x%lx irq %i",
2549 card->shortname, chip->addr, chip->irq);
07e4ca50 2550
1da177e4
LT		 2551 *rchip = chip;
2552 return 0;
2553
2554 errout:
2555 azx_free(chip);
2556 return err;
2557}
2558
cb53c626
TI		 2559static void power_down_all_codecs(struct azx *chip)
2560{
2561#ifdef CONFIG_SND_HDA_POWER_SAVE
2562 /* The codecs were powered up in snd_hda_codec_new().
2563 * Now all initialization done, so turn them down if possible
2564 */
2565 struct hda_codec *codec;
2566 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2567 snd_hda_power_down(codec);
2568 }
2569#endif
2570}
2571
d01ce99f
TI		 2572static int __devinit azx_probe(struct pci_dev *pci,
2573 const struct pci_device_id *pci_id)
1da177e4 2574{
5aba4f8e 2575 static int dev;
a98f90fd
TI		 2576 struct snd_card *card;
2577 struct azx *chip;
927fc866 2578 int err;
1da177e4 2579
5aba4f8e
TI		 2580 if (dev >= SNDRV_CARDS)
2581 return -ENODEV;
2582 if (!enable[dev]) {
2583 dev++;
2584 return -ENOENT;
2585 }
2586
e58de7ba
TI		 2587 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2588 if (err < 0) {
1da177e4 2589 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2590 return err;
1da177e4
LT		 2591 }
2592
4ea6fbc8
TI		 2593 /* set this here since it's referred in snd_hda_load_patch() */
2594 snd_card_set_dev(card, &pci->dev);
2595
5aba4f8e 2596 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2597 if (err < 0)
2598 goto out_free;
421a1252 2599 card->private_data = chip;
1da177e4 2600
2dca0bba
JK		 2601#ifdef CONFIG_SND_HDA_INPUT_BEEP
2602 chip->beep_mode = beep_mode[dev];
2603#endif
2604
1da177e4 2605 /* create codec instances */
a1e21c90 2606 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 2607 if (err < 0)
2608 goto out_free;
4ea6fbc8
TI		 2609#ifdef CONFIG_SND_HDA_PATCH_LOADER
2610 if (patch[dev]) {
2611 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2612 patch[dev]);
2613 err = snd_hda_load_patch(chip->bus, patch[dev]);
2614 if (err < 0)
2615 goto out_free;
2616 }
2617#endif
a1e21c90
TI		 2618 if (!probe_only[dev]) {
2619 err = azx_codec_configure(chip);
2620 if (err < 0)
2621 goto out_free;
2622 }
1da177e4
LT		 2623
2624 /* create PCM streams */
176d5335 2625 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2626 if (err < 0)
2627 goto out_free;
1da177e4
LT		 2628
2629 /* create mixer controls */
d01ce99f 2630 err = azx_mixer_create(chip);
41dda0fd
WF		 2631 if (err < 0)
2632 goto out_free;
1da177e4 2633
d01ce99f 2634 err = snd_card_register(card);
41dda0fd
WF		 2635 if (err < 0)
2636 goto out_free;
1da177e4
LT		 2637
2638 pci_set_drvdata(pci, card);
cb53c626
TI		 2639 chip->running = 1;
2640 power_down_all_codecs(chip);
0cbf0098 2641 azx_notifier_register(chip);
1da177e4 2642
e25bcdba 2643 dev++;
1da177e4 2644 return err;
41dda0fd
WF		 2645out_free:
2646 snd_card_free(card);
2647 return err;
1da177e4
LT		 2648}
2649
2650static void __devexit azx_remove(struct pci_dev *pci)
2651{
2652 snd_card_free(pci_get_drvdata(pci));
2653 pci_set_drvdata(pci, NULL);
2654}
2655
2656/* PCI IDs */
f40b6890 2657static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2658 /* ICH 6..10 */
2659 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2660 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2661 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2662 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2663 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2664 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2665 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2666 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2667 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2668 /* PCH */
2669 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2670 /* SCH */
2671 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2672 /* ATI SB 450/600 */
2673 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2674 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2675 /* ATI HDMI */
2676 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2677 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2678 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2679 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2680 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2681 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2682 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2683 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2684 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2685 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2686 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2687 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2688 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2689 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2690 /* VIA VT8251/VT8237A */
2691 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2692 /* SIS966 */
2693 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2694 /* ULI M5461 */
2695 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2696 /* NVIDIA MCP */
2697 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2698 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2699 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2700 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2701 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2702 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2703 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2704 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
db32f998 2705 { PCI_DEVICE(0x10de, 0x0590), .driver_data = AZX_DRIVER_NVIDIA },
87218e9c
TI		 2706 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2707 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2708 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2709 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2710 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2711 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2712 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2713 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2714 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2715 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
bedfcebb 2716 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2717 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2718 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2719 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2720 /* Teradici */
2721 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2722 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2723#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2724 /* the following entry conflicts with snd-ctxfi driver,
2725 * as ctxfi driver mutates from HD-audio to native mode with
2726 * a special command sequence.
2727 */
4e01f54b
TI		 2728 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2729 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2730 .class_mask = 0xffffff,
2731 .driver_data = AZX_DRIVER_GENERIC },
313f6e2d
TI		 2732#else
2733 /* this entry seems still valid -- i.e. without emu20kx chip */
2734 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2735#endif
9176b672 2736 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2737 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2738 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2739 .class_mask = 0xffffff,
2740 .driver_data = AZX_DRIVER_GENERIC },
9176b672
AB		 2741 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2742 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2743 .class_mask = 0xffffff,
2744 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2745 { 0, }
2746};
2747MODULE_DEVICE_TABLE(pci, azx_ids);
2748
2749/* pci_driver definition */
2750static struct pci_driver driver = {
2751 .name = "HDA Intel",
2752 .id_table = azx_ids,
2753 .probe = azx_probe,
2754 .remove = __devexit_p(azx_remove),
421a1252
TI		 2755#ifdef CONFIG_PM
2756 .suspend = azx_suspend,
2757 .resume = azx_resume,
2758#endif
1da177e4
LT		 2759};
2760
2761static int __init alsa_card_azx_init(void)
2762{
01d25d46 2763 return pci_register_driver(&driver);
1da177e4
LT		 2764}
2765
2766static void __exit alsa_card_azx_exit(void)
2767{
2768 pci_unregister_driver(&driver);
2769}
2770
2771module_init(alsa_card_azx_init)
2772module_exit(alsa_card_azx_exit)
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