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sound/oss: convert to unlocked_ioctl
[net-next-2.6.git] / sound / oss / au1550_ac97.c
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1da177e4
LT		 1/*
2 * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
3 * Processor.
4 *
5 * Copyright 2004 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * Mostly copied from the au1000.c driver and some from the
9 * PowerMac dbdma driver.
10 * We assume the processor can do memory coherent DMA.
11 *
12 * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 */
35
36#undef DEBUG
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/string.h>
40#include <linux/ioport.h>
41#include <linux/sched.h>
42#include <linux/delay.h>
43#include <linux/sound.h>
44#include <linux/slab.h>
45#include <linux/soundcard.h>
90dc763f 46#include <linux/smp_lock.h>
1da177e4
LT		 47#include <linux/init.h>
48#include <linux/interrupt.h>
49#include <linux/kernel.h>
50#include <linux/poll.h>
1da177e4
LT		 51#include <linux/bitops.h>
52#include <linux/spinlock.h>
53#include <linux/smp_lock.h>
54#include <linux/ac97_codec.h>
910f5d20
IM		 55#include <linux/mutex.h>
56
1da177e4
LT		 57#include <asm/io.h>
58#include <asm/uaccess.h>
59#include <asm/hardirq.h>
1da177e4
LT		 60#include <asm/mach-au1x00/au1xxx_psc.h>
61#include <asm/mach-au1x00/au1xxx_dbdma.h>
f2c780c1 62#include <asm/mach-au1x00/au1xxx.h>
1da177e4
LT		 63
64#undef OSS_DOCUMENTED_MIXER_SEMANTICS
65
66/* misc stuff */
67#define POLL_COUNT 0x50000
68#define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
69
70/* The number of DBDMA ring descriptors to allocate. No sense making
71 * this too large....if you can't keep up with a few you aren't likely
72 * to be able to with lots of them, either.
73 */
74#define NUM_DBDMA_DESCRIPTORS 4
75
76#define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
77
78/* Boot options
79 * 0 = no VRA, 1 = use VRA if codec supports it
80 */
81static int vra = 1;
8d3b33f6 82module_param(vra, bool, 0);
1da177e4
LT		 83MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
84
85static struct au1550_state {
86 /* soundcore stuff */
87 int dev_audio;
88
89 struct ac97_codec *codec;
90 unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
91 unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
92 int no_vra; /* do not use VRA */
93
94 spinlock_t lock;
910f5d20
IM		 95 struct mutex open_mutex;
96 struct mutex sem;
aeb5d727 97 fmode_t open_mode;
1da177e4
LT		 98 wait_queue_head_t open_wait;
99
100 struct dmabuf {
101 u32 dmanr;
102 unsigned sample_rate;
103 unsigned src_factor;
104 unsigned sample_size;
105 int num_channels;
106 int dma_bytes_per_sample;
107 int user_bytes_per_sample;
108 int cnt_factor;
109
110 void *rawbuf;
111 unsigned buforder;
112 unsigned numfrag;
113 unsigned fragshift;
114 void *nextIn;
115 void *nextOut;
116 int count;
117 unsigned total_bytes;
118 unsigned error;
119 wait_queue_head_t wait;
120
121 /* redundant, but makes calculations easier */
122 unsigned fragsize;
123 unsigned dma_fragsize;
124 unsigned dmasize;
125 unsigned dma_qcount;
126
127 /* OSS stuff */
128 unsigned mapped:1;
129 unsigned ready:1;
130 unsigned stopped:1;
131 unsigned ossfragshift;
132 int ossmaxfrags;
133 unsigned subdivision;
134 } dma_dac, dma_adc;
135} au1550_state;
136
137static unsigned
138ld2(unsigned int x)
139{
140 unsigned r = 0;
141
142 if (x >= 0x10000) {
143 x >>= 16;
144 r += 16;
145 }
146 if (x >= 0x100) {
147 x >>= 8;
148 r += 8;
149 }
150 if (x >= 0x10) {
151 x >>= 4;
152 r += 4;
153 }
154 if (x >= 4) {
155 x >>= 2;
156 r += 2;
157 }
158 if (x >= 2)
159 r++;
160 return r;
161}
162
163static void
164au1550_delay(int msec)
165{
166 unsigned long tmo;
167 signed long tmo2;
168
169 if (in_interrupt())
170 return;
171
172 tmo = jiffies + (msec * HZ) / 1000;
173 for (;;) {
174 tmo2 = tmo - jiffies;
175 if (tmo2 <= 0)
176 break;
177 schedule_timeout(tmo2);
178 }
179}
180
181static u16
182rdcodec(struct ac97_codec *codec, u8 addr)
183{
184 struct au1550_state *s = (struct au1550_state *)codec->private_data;
185 unsigned long flags;
186 u32 cmd, val;
187 u16 data;
188 int i;
189
190 spin_lock_irqsave(&s->lock, flags);
191
192 for (i = 0; i < POLL_COUNT; i++) {
193 val = au_readl(PSC_AC97STAT);
194 au_sync();
195 if (!(val & PSC_AC97STAT_CP))
196 break;
197 }
198 if (i == POLL_COUNT)
199 err("rdcodec: codec cmd pending expired!");
200
201 cmd = (u32)PSC_AC97CDC_INDX(addr);
202 cmd |= PSC_AC97CDC_RD; /* read command */
203 au_writel(cmd, PSC_AC97CDC);
204 au_sync();
205
206 /* now wait for the data
207 */
208 for (i = 0; i < POLL_COUNT; i++) {
209 val = au_readl(PSC_AC97STAT);
210 au_sync();
211 if (!(val & PSC_AC97STAT_CP))
212 break;
213 }
214 if (i == POLL_COUNT) {
215 err("rdcodec: read poll expired!");
5e37ed37
DP		 216 data = 0;
217 goto out;
1da177e4
LT		 218 }
219
220 /* wait for command done?
221 */
222 for (i = 0; i < POLL_COUNT; i++) {
223 val = au_readl(PSC_AC97EVNT);
224 au_sync();
225 if (val & PSC_AC97EVNT_CD)
226 break;
227 }
228 if (i == POLL_COUNT) {
229 err("rdcodec: read cmdwait expired!");
5e37ed37
DP		 230 data = 0;
231 goto out;
1da177e4
LT		 232 }
233
234 data = au_readl(PSC_AC97CDC) & 0xffff;
235 au_sync();
236
237 /* Clear command done event.
238 */
239 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
240 au_sync();
241
5e37ed37 242 out:
1da177e4
LT		 243 spin_unlock_irqrestore(&s->lock, flags);
244
245 return data;
246}
247
248
249static void
250wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
251{
252 struct au1550_state *s = (struct au1550_state *)codec->private_data;
253 unsigned long flags;
254 u32 cmd, val;
255 int i;
256
257 spin_lock_irqsave(&s->lock, flags);
258
259 for (i = 0; i < POLL_COUNT; i++) {
260 val = au_readl(PSC_AC97STAT);
261 au_sync();
262 if (!(val & PSC_AC97STAT_CP))
263 break;
264 }
265 if (i == POLL_COUNT)
266 err("wrcodec: codec cmd pending expired!");
267
268 cmd = (u32)PSC_AC97CDC_INDX(addr);
269 cmd |= (u32)data;
270 au_writel(cmd, PSC_AC97CDC);
271 au_sync();
272
273 for (i = 0; i < POLL_COUNT; i++) {
274 val = au_readl(PSC_AC97STAT);
275 au_sync();
276 if (!(val & PSC_AC97STAT_CP))
277 break;
278 }
279 if (i == POLL_COUNT)
280 err("wrcodec: codec cmd pending expired!");
281
282 for (i = 0; i < POLL_COUNT; i++) {
283 val = au_readl(PSC_AC97EVNT);
284 au_sync();
285 if (val & PSC_AC97EVNT_CD)
286 break;
287 }
288 if (i == POLL_COUNT)
289 err("wrcodec: read cmdwait expired!");
290
291 /* Clear command done event.
292 */
293 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
294 au_sync();
295
296 spin_unlock_irqrestore(&s->lock, flags);
297}
298
299static void
300waitcodec(struct ac97_codec *codec)
301{
302 u16 temp;
303 u32 val;
304 int i;
305
306 /* codec_wait is used to wait for a ready state after
307 * an AC97C_RESET.
308 */
309 au1550_delay(10);
310
311 /* first poll the CODEC_READY tag bit
312 */
313 for (i = 0; i < POLL_COUNT; i++) {
314 val = au_readl(PSC_AC97STAT);
315 au_sync();
316 if (val & PSC_AC97STAT_CR)
317 break;
318 }
319 if (i == POLL_COUNT) {
320 err("waitcodec: CODEC_READY poll expired!");
321 return;
322 }
323
324 /* get AC'97 powerdown control/status register
325 */
326 temp = rdcodec(codec, AC97_POWER_CONTROL);
327
328 /* If anything is powered down, power'em up
329 */
330 if (temp & 0x7f00) {
331 /* Power on
332 */
333 wrcodec(codec, AC97_POWER_CONTROL, 0);
334 au1550_delay(100);
335
336 /* Reread
337 */
338 temp = rdcodec(codec, AC97_POWER_CONTROL);
339 }
340
341 /* Check if Codec REF,ANL,DAC,ADC ready
342 */
343 if ((temp & 0x7f0f) != 0x000f)
344 err("codec reg 26 status (0x%x) not ready!!", temp);
345}
346
347/* stop the ADC before calling */
348static void
349set_adc_rate(struct au1550_state *s, unsigned rate)
350{
351 struct dmabuf *adc = &s->dma_adc;
352 struct dmabuf *dac = &s->dma_dac;
353 unsigned adc_rate, dac_rate;
354 u16 ac97_extstat;
355
356 if (s->no_vra) {
357 /* calc SRC factor
358 */
359 adc->src_factor = ((96000 / rate) + 1) >> 1;
360 adc->sample_rate = 48000 / adc->src_factor;
361 return;
362 }
363
364 adc->src_factor = 1;
365
366 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
367
368 rate = rate > 48000 ? 48000 : rate;
369
370 /* enable VRA
371 */
372 wrcodec(s->codec, AC97_EXTENDED_STATUS,
373 ac97_extstat | AC97_EXTSTAT_VRA);
374
375 /* now write the sample rate
376 */
377 wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
378
379 /* read it back for actual supported rate
380 */
381 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
382
383 pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
384
385 /* some codec's don't allow unequal DAC and ADC rates, in which case
386 * writing one rate reg actually changes both.
387 */
388 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
389 if (dac->num_channels > 2)
390 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
391 if (dac->num_channels > 4)
392 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
393
394 adc->sample_rate = adc_rate;
395 dac->sample_rate = dac_rate;
396}
397
398/* stop the DAC before calling */
399static void
400set_dac_rate(struct au1550_state *s, unsigned rate)
401{
402 struct dmabuf *dac = &s->dma_dac;
403 struct dmabuf *adc = &s->dma_adc;
404 unsigned adc_rate, dac_rate;
405 u16 ac97_extstat;
406
407 if (s->no_vra) {
408 /* calc SRC factor
409 */
410 dac->src_factor = ((96000 / rate) + 1) >> 1;
411 dac->sample_rate = 48000 / dac->src_factor;
412 return;
413 }
414
415 dac->src_factor = 1;
416
417 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
418
419 rate = rate > 48000 ? 48000 : rate;
420
421 /* enable VRA
422 */
423 wrcodec(s->codec, AC97_EXTENDED_STATUS,
424 ac97_extstat | AC97_EXTSTAT_VRA);
425
426 /* now write the sample rate
427 */
428 wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
429
430 /* I don't support different sample rates for multichannel,
431 * so make these channels the same.
432 */
433 if (dac->num_channels > 2)
434 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
435 if (dac->num_channels > 4)
436 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
437 /* read it back for actual supported rate
438 */
439 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
440
441 pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
442
443 /* some codec's don't allow unequal DAC and ADC rates, in which case
444 * writing one rate reg actually changes both.
445 */
446 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
447
448 dac->sample_rate = dac_rate;
449 adc->sample_rate = adc_rate;
450}
451
452static void
453stop_dac(struct au1550_state *s)
454{
455 struct dmabuf *db = &s->dma_dac;
456 u32 stat;
457 unsigned long flags;
458
459 if (db->stopped)
460 return;
461
462 spin_lock_irqsave(&s->lock, flags);
463
464 au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
465 au_sync();
466
467 /* Wait for Transmit Busy to show disabled.
468 */
469 do {
05090fc9 470 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 471 au_sync();
472 } while ((stat & PSC_AC97STAT_TB) != 0);
473
474 au1xxx_dbdma_reset(db->dmanr);
475
476 db->stopped = 1;
477
478 spin_unlock_irqrestore(&s->lock, flags);
479}
480
481static void
482stop_adc(struct au1550_state *s)
483{
484 struct dmabuf *db = &s->dma_adc;
485 unsigned long flags;
486 u32 stat;
487
488 if (db->stopped)
489 return;
490
491 spin_lock_irqsave(&s->lock, flags);
492
493 au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
494 au_sync();
495
496 /* Wait for Receive Busy to show disabled.
497 */
498 do {
05090fc9 499 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 500 au_sync();
501 } while ((stat & PSC_AC97STAT_RB) != 0);
502
503 au1xxx_dbdma_reset(db->dmanr);
504
505 db->stopped = 1;
506
507 spin_unlock_irqrestore(&s->lock, flags);
508}
509
510
511static void
512set_xmit_slots(int num_channels)
513{
514 u32 ac97_config, stat;
515
516 ac97_config = au_readl(PSC_AC97CFG);
517 au_sync();
518 ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
519 au_writel(ac97_config, PSC_AC97CFG);
520 au_sync();
521
522 switch (num_channels) {
523 case 6: /* stereo with surround and center/LFE,
524 * slots 3,4,6,7,8,9
525 */
526 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
527 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
528
529 case 4: /* stereo with surround, slots 3,4,7,8 */
530 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
531 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
532
533 case 2: /* stereo, slots 3,4 */
534 case 1: /* mono */
535 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
536 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
537 }
538
539 au_writel(ac97_config, PSC_AC97CFG);
540 au_sync();
541
542 ac97_config |= PSC_AC97CFG_DE_ENABLE;
543 au_writel(ac97_config, PSC_AC97CFG);
544 au_sync();
545
546 /* Wait for Device ready.
547 */
548 do {
05090fc9 549 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 550 au_sync();
551 } while ((stat & PSC_AC97STAT_DR) == 0);
552}
553
554static void
555set_recv_slots(int num_channels)
556{
557 u32 ac97_config, stat;
558
559 ac97_config = au_readl(PSC_AC97CFG);
560 au_sync();
561 ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
562 au_writel(ac97_config, PSC_AC97CFG);
563 au_sync();
564
565 /* Always enable slots 3 and 4 (stereo). Slot 6 is
566 * optional Mic ADC, which we don't support yet.
567 */
568 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
569 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
570
571 au_writel(ac97_config, PSC_AC97CFG);
572 au_sync();
573
574 ac97_config |= PSC_AC97CFG_DE_ENABLE;
575 au_writel(ac97_config, PSC_AC97CFG);
576 au_sync();
577
578 /* Wait for Device ready.
579 */
580 do {
05090fc9 581 stat = au_readl(PSC_AC97STAT);
1da177e4
LT		 582 au_sync();
583 } while ((stat & PSC_AC97STAT_DR) == 0);
584}
585
7b666653 586/* Hold spinlock for both start_dac() and start_adc() calls */
1da177e4
LT		 587static void
588start_dac(struct au1550_state *s)
589{
590 struct dmabuf *db = &s->dma_dac;
1da177e4
LT		 591
592 if (!db->stopped)
593 return;
594
1da177e4
LT		 595 set_xmit_slots(db->num_channels);
596 au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
597 au_sync();
598 au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
599 au_sync();
600
601 au1xxx_dbdma_start(db->dmanr);
602
603 db->stopped = 0;
1da177e4
LT		 604}
605
606static void
607start_adc(struct au1550_state *s)
608{
609 struct dmabuf *db = &s->dma_adc;
610 int i;
611
612 if (!db->stopped)
613 return;
614
615 /* Put two buffers on the ring to get things started.
616 */
617 for (i=0; i<2; i++) {
963accbc 618 au1xxx_dbdma_put_dest(db->dmanr, virt_to_phys(db->nextIn),
ea071cc7 619 db->dma_fragsize, DDMA_FLAGS_IE);
1da177e4
LT		 620
621 db->nextIn += db->dma_fragsize;
622 if (db->nextIn >= db->rawbuf + db->dmasize)
623 db->nextIn -= db->dmasize;
624 }
625
626 set_recv_slots(db->num_channels);
627 au1xxx_dbdma_start(db->dmanr);
628 au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
629 au_sync();
630 au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
631 au_sync();
632
633 db->stopped = 0;
634}
635
636static int
637prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
638{
639 unsigned user_bytes_per_sec;
640 unsigned bufs;
641 unsigned rate = db->sample_rate;
642
643 if (!db->rawbuf) {
644 db->ready = db->mapped = 0;
645 db->buforder = 5; /* 32 * PAGE_SIZE */
646 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
647 if (!db->rawbuf)
648 return -ENOMEM;
649 }
650
651 db->cnt_factor = 1;
652 if (db->sample_size == 8)
653 db->cnt_factor *= 2;
654 if (db->num_channels == 1)
655 db->cnt_factor *= 2;
656 db->cnt_factor *= db->src_factor;
657
658 db->count = 0;
659 db->dma_qcount = 0;
660 db->nextIn = db->nextOut = db->rawbuf;
661
662 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
663 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
664 2 : db->num_channels);
665
666 user_bytes_per_sec = rate * db->user_bytes_per_sample;
667 bufs = PAGE_SIZE << db->buforder;
668 if (db->ossfragshift) {
669 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
670 db->fragshift = ld2(user_bytes_per_sec/1000);
671 else
672 db->fragshift = db->ossfragshift;
673 } else {
674 db->fragshift = ld2(user_bytes_per_sec / 100 /
675 (db->subdivision ? db->subdivision : 1));
676 if (db->fragshift < 3)
677 db->fragshift = 3;
678 }
679
680 db->fragsize = 1 << db->fragshift;
681 db->dma_fragsize = db->fragsize * db->cnt_factor;
682 db->numfrag = bufs / db->dma_fragsize;
683
684 while (db->numfrag < 4 && db->fragshift > 3) {
685 db->fragshift--;
686 db->fragsize = 1 << db->fragshift;
687 db->dma_fragsize = db->fragsize * db->cnt_factor;
688 db->numfrag = bufs / db->dma_fragsize;
689 }
690
691 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
692 db->numfrag = db->ossmaxfrags;
693
694 db->dmasize = db->dma_fragsize * db->numfrag;
695 memset(db->rawbuf, 0, bufs);
696
697 pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
698 rate, db->sample_size, db->num_channels);
699 pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
700 db->fragsize, db->cnt_factor, db->dma_fragsize);
701 pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
702
703 db->ready = 1;
704 return 0;
705}
706
707static int
708prog_dmabuf_adc(struct au1550_state *s)
709{
710 stop_adc(s);
711 return prog_dmabuf(s, &s->dma_adc);
712
713}
714
715static int
716prog_dmabuf_dac(struct au1550_state *s)
717{
718 stop_dac(s);
719 return prog_dmabuf(s, &s->dma_dac);
720}
721
722
53e62d3a 723static void dac_dma_interrupt(int irq, void *dev_id)
1da177e4
LT		 724{
725 struct au1550_state *s = (struct au1550_state *) dev_id;
726 struct dmabuf *db = &s->dma_dac;
727 u32 ac97c_stat;
728
7b666653
SS		 729 spin_lock(&s->lock);
730
1da177e4
LT		 731 ac97c_stat = au_readl(PSC_AC97STAT);
732 if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
733 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
734 db->dma_qcount--;
735
736 if (db->count >= db->fragsize) {
963accbc
ML		 737 if (au1xxx_dbdma_put_source(db->dmanr,
738 virt_to_phys(db->nextOut), db->fragsize,
739 DDMA_FLAGS_IE) == 0) {
1da177e4
LT		 740 err("qcount < 2 and no ring room!");
741 }
742 db->nextOut += db->fragsize;
743 if (db->nextOut >= db->rawbuf + db->dmasize)
744 db->nextOut -= db->dmasize;
745 db->count -= db->fragsize;
746 db->total_bytes += db->dma_fragsize;
747 db->dma_qcount++;
748 }
749
750 /* wake up anybody listening */
751 if (waitqueue_active(&db->wait))
752 wake_up(&db->wait);
7b666653
SS		 753
754 spin_unlock(&s->lock);
1da177e4
LT		 755}
756
757
53e62d3a 758static void adc_dma_interrupt(int irq, void *dev_id)
1da177e4
LT		 759{
760 struct au1550_state *s = (struct au1550_state *)dev_id;
761 struct dmabuf *dp = &s->dma_adc;
762 u32 obytes;
763 char *obuf;
764
7b666653
SS		 765 spin_lock(&s->lock);
766
1da177e4
LT		 767 /* Pull the buffer from the dma queue.
768 */
769 au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
770
771 if ((dp->count + obytes) > dp->dmasize) {
772 /* Overrun. Stop ADC and log the error
773 */
7b666653 774 spin_unlock(&s->lock);
1da177e4
LT		 775 stop_adc(s);
776 dp->error++;
777 err("adc overrun");
778 return;
779 }
780
781 /* Put a new empty buffer on the destination DMA.
782 */
963accbc 783 au1xxx_dbdma_put_dest(dp->dmanr, virt_to_phys(dp->nextIn),
ea071cc7 784 dp->dma_fragsize, DDMA_FLAGS_IE);
1da177e4
LT		 785
786 dp->nextIn += dp->dma_fragsize;
787 if (dp->nextIn >= dp->rawbuf + dp->dmasize)
788 dp->nextIn -= dp->dmasize;
789
790 dp->count += obytes;
791 dp->total_bytes += obytes;
792
793 /* wake up anybody listening
794 */
795 if (waitqueue_active(&dp->wait))
796 wake_up(&dp->wait);
797
7b666653 798 spin_unlock(&s->lock);
1da177e4
LT		 799}
800
801static loff_t
802au1550_llseek(struct file *file, loff_t offset, int origin)
803{
804 return -ESPIPE;
805}
806
807
808static int
809au1550_open_mixdev(struct inode *inode, struct file *file)
810{
90dc763f 811 lock_kernel();
1da177e4 812 file->private_data = &au1550_state;
90dc763f 813 unlock_kernel();
1da177e4
LT		 814 return 0;
815}
816
817static int
818au1550_release_mixdev(struct inode *inode, struct file *file)
819{
820 return 0;
821}
822
823static int
824mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
825 unsigned long arg)
826{
827 return codec->mixer_ioctl(codec, cmd, arg);
828}
829
d209974c
AB		 830static long
831au1550_ioctl_mixdev(struct file *file, unsigned int cmd, unsigned long arg)
1da177e4
LT		 832{
833 struct au1550_state *s = (struct au1550_state *)file->private_data;
834 struct ac97_codec *codec = s->codec;
d209974c
AB		 835 int ret;
836
837 lock_kernel();
838 ret = mixdev_ioctl(codec, cmd, arg);
839 unlock_kernel();
1da177e4 840
d209974c 841 return ret;
1da177e4
LT		 842}
843
844static /*const */ struct file_operations au1550_mixer_fops = {
d209974c
AB		 845 .owner = THIS_MODULE,
846 .llseek = au1550_llseek,
847 .unlocked_ioctl = au1550_ioctl_mixdev,
848 .open = au1550_open_mixdev,
849 .release = au1550_release_mixdev,
1da177e4
LT		 850};
851
852static int
853drain_dac(struct au1550_state *s, int nonblock)
854{
855 unsigned long flags;
856 int count, tmo;
857
858 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
859 return 0;
860
861 for (;;) {
862 spin_lock_irqsave(&s->lock, flags);
863 count = s->dma_dac.count;
864 spin_unlock_irqrestore(&s->lock, flags);
865 if (count <= s->dma_dac.fragsize)
866 break;
867 if (signal_pending(current))
868 break;
869 if (nonblock)
870 return -EBUSY;
871 tmo = 1000 * count / (s->no_vra ?
872 48000 : s->dma_dac.sample_rate);
873 tmo /= s->dma_dac.dma_bytes_per_sample;
874 au1550_delay(tmo);
875 }
876 if (signal_pending(current))
877 return -ERESTARTSYS;
878 return 0;
879}
880
881static inline u8 S16_TO_U8(s16 ch)
882{
883 return (u8) (ch >> 8) + 0x80;
884}
885static inline s16 U8_TO_S16(u8 ch)
886{
887 return (s16) (ch - 0x80) << 8;
888}
889
890/*
891 * Translates user samples to dma buffer suitable for AC'97 DAC data:
892 * If mono, copy left channel to right channel in dma buffer.
893 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
894 * If interpolating (no VRA), duplicate every audio frame src_factor times.
895 */
896static int
897translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
898 int dmacount)
899{
900 int sample, i;
901 int interp_bytes_per_sample;
902 int num_samples;
903 int mono = (db->num_channels == 1);
904 char usersample[12];
905 s16 ch, dmasample[6];
906
907 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
908 /* no translation necessary, just copy
909 */
910 if (copy_from_user(dmabuf, userbuf, dmacount))
911 return -EFAULT;
912 return dmacount;
913 }
914
915 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
916 num_samples = dmacount / interp_bytes_per_sample;
917
918 for (sample = 0; sample < num_samples; sample++) {
919 if (copy_from_user(usersample, userbuf,
920 db->user_bytes_per_sample)) {
921 return -EFAULT;
922 }
923
924 for (i = 0; i < db->num_channels; i++) {
925 if (db->sample_size == 8)
926 ch = U8_TO_S16(usersample[i]);
927 else
928 ch = *((s16 *) (&usersample[i * 2]));
929 dmasample[i] = ch;
930 if (mono)
931 dmasample[i + 1] = ch; /* right channel */
932 }
933
934 /* duplicate every audio frame src_factor times
935 */
936 for (i = 0; i < db->src_factor; i++)
937 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
938
939 userbuf += db->user_bytes_per_sample;
940 dmabuf += interp_bytes_per_sample;
941 }
942
943 return num_samples * interp_bytes_per_sample;
944}
945
946/*
947 * Translates AC'97 ADC samples to user buffer:
948 * If mono, send only left channel to user buffer.
949 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
950 * If decimating (no VRA), skip over src_factor audio frames.
951 */
952static int
953translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
954 int dmacount)
955{
956 int sample, i;
957 int interp_bytes_per_sample;
958 int num_samples;
959 int mono = (db->num_channels == 1);
960 char usersample[12];
961
962 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
963 /* no translation necessary, just copy
964 */
965 if (copy_to_user(userbuf, dmabuf, dmacount))
966 return -EFAULT;
967 return dmacount;
968 }
969
970 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
971 num_samples = dmacount / interp_bytes_per_sample;
972
973 for (sample = 0; sample < num_samples; sample++) {
974 for (i = 0; i < db->num_channels; i++) {
975 if (db->sample_size == 8)
976 usersample[i] =
977 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
978 else
979 *((s16 *) (&usersample[i * 2])) =
980 *((s16 *) (&dmabuf[i * 2]));
981 }
982
983 if (copy_to_user(userbuf, usersample,
984 db->user_bytes_per_sample)) {
985 return -EFAULT;
986 }
987
988 userbuf += db->user_bytes_per_sample;
989 dmabuf += interp_bytes_per_sample;
990 }
991
992 return num_samples * interp_bytes_per_sample;
993}
994
995/*
996 * Copy audio data to/from user buffer from/to dma buffer, taking care
997 * that we wrap when reading/writing the dma buffer. Returns actual byte
998 * count written to or read from the dma buffer.
999 */
1000static int
1001copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
1002{
1003 char *bufptr = to_user ? db->nextOut : db->nextIn;
1004 char *bufend = db->rawbuf + db->dmasize;
1005 int cnt, ret;
1006
1007 if (bufptr + count > bufend) {
1008 int partial = (int) (bufend - bufptr);
1009 if (to_user) {
1010 if ((cnt = translate_to_user(db, userbuf,
1011 bufptr, partial)) < 0)
1012 return cnt;
1013 ret = cnt;
1014 if ((cnt = translate_to_user(db, userbuf + partial,
1015 db->rawbuf,
1016 count - partial)) < 0)
1017 return cnt;
1018 ret += cnt;
1019 } else {
1020 if ((cnt = translate_from_user(db, bufptr, userbuf,
1021 partial)) < 0)
1022 return cnt;
1023 ret = cnt;
1024 if ((cnt = translate_from_user(db, db->rawbuf,
1025 userbuf + partial,
1026 count - partial)) < 0)
1027 return cnt;
1028 ret += cnt;
1029 }
1030 } else {
1031 if (to_user)
1032 ret = translate_to_user(db, userbuf, bufptr, count);
1033 else
1034 ret = translate_from_user(db, bufptr, userbuf, count);
1035 }
1036
1037 return ret;
1038}
1039
1040
1041static ssize_t
1042au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1043{
1044 struct au1550_state *s = (struct au1550_state *)file->private_data;
1045 struct dmabuf *db = &s->dma_adc;
1046 DECLARE_WAITQUEUE(wait, current);
1047 ssize_t ret;
1048 unsigned long flags;
1049 int cnt, usercnt, avail;
1050
1051 if (db->mapped)
1052 return -ENXIO;
1053 if (!access_ok(VERIFY_WRITE, buffer, count))
1054 return -EFAULT;
1055 ret = 0;
1056
1057 count *= db->cnt_factor;
1058
910f5d20 1059 mutex_lock(&s->sem);
1da177e4
LT		 1060 add_wait_queue(&db->wait, &wait);
1061
1062 while (count > 0) {
1063 /* wait for samples in ADC dma buffer
1064 */
1065 do {
7b666653 1066 spin_lock_irqsave(&s->lock, flags);
1da177e4
LT		 1067 if (db->stopped)
1068 start_adc(s);
1da177e4
LT		 1069 avail = db->count;
1070 if (avail <= 0)
1071 __set_current_state(TASK_INTERRUPTIBLE);
1072 spin_unlock_irqrestore(&s->lock, flags);
1073 if (avail <= 0) {
1074 if (file->f_flags & O_NONBLOCK) {
1075 if (!ret)
1076 ret = -EAGAIN;
1077 goto out;
1078 }
910f5d20 1079 mutex_unlock(&s->sem);
1da177e4
LT		 1080 schedule();
1081 if (signal_pending(current)) {
1082 if (!ret)
1083 ret = -ERESTARTSYS;
1084 goto out2;
1085 }
910f5d20 1086 mutex_lock(&s->sem);
1da177e4
LT		 1087 }
1088 } while (avail <= 0);
1089
1090 /* copy from nextOut to user
1091 */
1092 if ((cnt = copy_dmabuf_user(db, buffer,
1093 count > avail ?
1094 avail : count, 1)) < 0) {
1095 if (!ret)
1096 ret = -EFAULT;
1097 goto out;
1098 }
1099
1100 spin_lock_irqsave(&s->lock, flags);
1101 db->count -= cnt;
1102 db->nextOut += cnt;
1103 if (db->nextOut >= db->rawbuf + db->dmasize)
1104 db->nextOut -= db->dmasize;
1105 spin_unlock_irqrestore(&s->lock, flags);
1106
1107 count -= cnt;
1108 usercnt = cnt / db->cnt_factor;
1109 buffer += usercnt;
1110 ret += usercnt;
1111 } /* while (count > 0) */
1112
1113out:
910f5d20 1114 mutex_unlock(&s->sem);
1da177e4
LT		 1115out2:
1116 remove_wait_queue(&db->wait, &wait);
1117 set_current_state(TASK_RUNNING);
1118 return ret;
1119}
1120
1121static ssize_t
1122au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1123{
1124 struct au1550_state *s = (struct au1550_state *)file->private_data;
1125 struct dmabuf *db = &s->dma_dac;
1126 DECLARE_WAITQUEUE(wait, current);
1127 ssize_t ret = 0;
1128 unsigned long flags;
1129 int cnt, usercnt, avail;
1130
1131 pr_debug("write: count=%d\n", count);
1132
1133 if (db->mapped)
1134 return -ENXIO;
1135 if (!access_ok(VERIFY_READ, buffer, count))
1136 return -EFAULT;
1137
1138 count *= db->cnt_factor;
1139
910f5d20 1140 mutex_lock(&s->sem);
1da177e4
LT		 1141 add_wait_queue(&db->wait, &wait);
1142
1143 while (count > 0) {
1144 /* wait for space in playback buffer
1145 */
1146 do {
1147 spin_lock_irqsave(&s->lock, flags);
1148 avail = (int) db->dmasize - db->count;
1149 if (avail <= 0)
1150 __set_current_state(TASK_INTERRUPTIBLE);
1151 spin_unlock_irqrestore(&s->lock, flags);
1152 if (avail <= 0) {
1153 if (file->f_flags & O_NONBLOCK) {
1154 if (!ret)
1155 ret = -EAGAIN;
1156 goto out;
1157 }
910f5d20 1158 mutex_unlock(&s->sem);
1da177e4
LT		 1159 schedule();
1160 if (signal_pending(current)) {
1161 if (!ret)
1162 ret = -ERESTARTSYS;
1163 goto out2;
1164 }
910f5d20 1165 mutex_lock(&s->sem);
1da177e4
LT		 1166 }
1167 } while (avail <= 0);
1168
1169 /* copy from user to nextIn
1170 */
1171 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1172 count > avail ?
1173 avail : count, 0)) < 0) {
1174 if (!ret)
1175 ret = -EFAULT;
1176 goto out;
1177 }
1178
1179 spin_lock_irqsave(&s->lock, flags);
1180 db->count += cnt;
1181 db->nextIn += cnt;
1182 if (db->nextIn >= db->rawbuf + db->dmasize)
1183 db->nextIn -= db->dmasize;
1184
1185 /* If the data is available, we want to keep two buffers
1186 * on the dma queue. If the queue count reaches zero,
1187 * we know the dma has stopped.
1188 */
1189 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
ea071cc7 1190 if (au1xxx_dbdma_put_source(db->dmanr,
963accbc
ML		 1191 virt_to_phys(db->nextOut), db->fragsize,
1192 DDMA_FLAGS_IE) == 0) {
1da177e4
LT		 1193 err("qcount < 2 and no ring room!");
1194 }
1195 db->nextOut += db->fragsize;
1196 if (db->nextOut >= db->rawbuf + db->dmasize)
1197 db->nextOut -= db->dmasize;
1198 db->total_bytes += db->dma_fragsize;
1199 if (db->dma_qcount == 0)
1200 start_dac(s);
1201 db->dma_qcount++;
1202 }
1203 spin_unlock_irqrestore(&s->lock, flags);
1204
1205 count -= cnt;
1206 usercnt = cnt / db->cnt_factor;
1207 buffer += usercnt;
1208 ret += usercnt;
1209 } /* while (count > 0) */
1210
1211out:
910f5d20 1212 mutex_unlock(&s->sem);
1da177e4
LT		 1213out2:
1214 remove_wait_queue(&db->wait, &wait);
1215 set_current_state(TASK_RUNNING);
1216 return ret;
1217}
1218
1219
1220/* No kernel lock - we have our own spinlock */
1221static unsigned int
1222au1550_poll(struct file *file, struct poll_table_struct *wait)
1223{
1224 struct au1550_state *s = (struct au1550_state *)file->private_data;
1225 unsigned long flags;
1226 unsigned int mask = 0;
1227
1228 if (file->f_mode & FMODE_WRITE) {
1229 if (!s->dma_dac.ready)
1230 return 0;
1231 poll_wait(file, &s->dma_dac.wait, wait);
1232 }
1233 if (file->f_mode & FMODE_READ) {
1234 if (!s->dma_adc.ready)
1235 return 0;
1236 poll_wait(file, &s->dma_adc.wait, wait);
1237 }
1238
1239 spin_lock_irqsave(&s->lock, flags);
1240
1241 if (file->f_mode & FMODE_READ) {
1242 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1243 mask |= POLLIN | POLLRDNORM;
1244 }
1245 if (file->f_mode & FMODE_WRITE) {
1246 if (s->dma_dac.mapped) {
1247 if (s->dma_dac.count >=
1248 (signed)s->dma_dac.dma_fragsize)
1249 mask |= POLLOUT | POLLWRNORM;
1250 } else {
1251 if ((signed) s->dma_dac.dmasize >=
1252 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1253 mask |= POLLOUT | POLLWRNORM;
1254 }
1255 }
1256 spin_unlock_irqrestore(&s->lock, flags);
1257 return mask;
1258}
1259
1260static int
1261au1550_mmap(struct file *file, struct vm_area_struct *vma)
1262{
1263 struct au1550_state *s = (struct au1550_state *)file->private_data;
1264 struct dmabuf *db;
1265 unsigned long size;
1266 int ret = 0;
1267
1268 lock_kernel();
910f5d20 1269 mutex_lock(&s->sem);
1da177e4
LT		 1270 if (vma->vm_flags & VM_WRITE)
1271 db = &s->dma_dac;
1272 else if (vma->vm_flags & VM_READ)
1273 db = &s->dma_adc;
1274 else {
1275 ret = -EINVAL;
1276 goto out;
1277 }
1278 if (vma->vm_pgoff != 0) {
1279 ret = -EINVAL;
1280 goto out;
1281 }
1282 size = vma->vm_end - vma->vm_start;
1283 if (size > (PAGE_SIZE << db->buforder)) {
1284 ret = -EINVAL;
1285 goto out;
1286 }
1287 if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1288 size, vma->vm_page_prot)) {
1289 ret = -EAGAIN;
1290 goto out;
1291 }
1292 vma->vm_flags &= ~VM_IO;
1293 db->mapped = 1;
1294out:
910f5d20 1295 mutex_unlock(&s->sem);
1da177e4
LT		 1296 unlock_kernel();
1297 return ret;
1298}
1299
1300#ifdef DEBUG
1301static struct ioctl_str_t {
1302 unsigned int cmd;
1303 const char *str;
1304} ioctl_str[] = {
1305 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1306 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1307 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1308 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1309 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1310 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1311 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1312 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1313 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1314 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1315 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1316 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1317 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1318 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1319 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1320 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1321 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1322 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1323 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1324 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1325 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1326 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1327 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1328 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1329 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1330 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1331 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1332 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1333 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1334 {OSS_GETVERSION, "OSS_GETVERSION"},
1335 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1336 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1337 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1338 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1339};
1340#endif
1341
1342static int
1343dma_count_done(struct dmabuf *db)
1344{
1345 if (db->stopped)
1346 return 0;
1347
1348 return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1349}
1350
1351
1352static int
d209974c 1353au1550_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1da177e4
LT		 1354{
1355 struct au1550_state *s = (struct au1550_state *)file->private_data;
1356 unsigned long flags;
1357 audio_buf_info abinfo;
1358 count_info cinfo;
1359 int count;
1360 int val, mapped, ret, diff;
1361
1362 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1363 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1364
1365#ifdef DEBUG
8b5925fd 1366 for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
1da177e4
LT		 1367 if (ioctl_str[count].cmd == cmd)
1368 break;
1369 }
8b5925fd 1370 if (count < ARRAY_SIZE(ioctl_str))
1da177e4
LT		 1371 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1372 else
1373 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1374#endif
1375
1376 switch (cmd) {
1377 case OSS_GETVERSION:
1378 return put_user(SOUND_VERSION, (int *) arg);
1379
1380 case SNDCTL_DSP_SYNC:
1381 if (file->f_mode & FMODE_WRITE)
1382 return drain_dac(s, file->f_flags & O_NONBLOCK);
1383 return 0;
1384
1385 case SNDCTL_DSP_SETDUPLEX:
1386 return 0;
1387
1388 case SNDCTL_DSP_GETCAPS:
1389 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1390 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1391
1392 case SNDCTL_DSP_RESET:
1393 if (file->f_mode & FMODE_WRITE) {
1394 stop_dac(s);
1395 synchronize_irq();
1396 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1397 s->dma_dac.nextIn = s->dma_dac.nextOut =
1398 s->dma_dac.rawbuf;
1399 }
1400 if (file->f_mode & FMODE_READ) {
1401 stop_adc(s);
1402 synchronize_irq();
1403 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1404 s->dma_adc.nextIn = s->dma_adc.nextOut =
1405 s->dma_adc.rawbuf;
1406 }
1407 return 0;
1408
1409 case SNDCTL_DSP_SPEED:
1410 if (get_user(val, (int *) arg))
1411 return -EFAULT;
1412 if (val >= 0) {
1413 if (file->f_mode & FMODE_READ) {
1414 stop_adc(s);
1415 set_adc_rate(s, val);
1416 }
1417 if (file->f_mode & FMODE_WRITE) {
1418 stop_dac(s);
1419 set_dac_rate(s, val);
1420 }
1421 if (s->open_mode & FMODE_READ)
1422 if ((ret = prog_dmabuf_adc(s)))
1423 return ret;
1424 if (s->open_mode & FMODE_WRITE)
1425 if ((ret = prog_dmabuf_dac(s)))
1426 return ret;
1427 }
1428 return put_user((file->f_mode & FMODE_READ) ?
1429 s->dma_adc.sample_rate :
1430 s->dma_dac.sample_rate,
1431 (int *)arg);
1432
1433 case SNDCTL_DSP_STEREO:
1434 if (get_user(val, (int *) arg))
1435 return -EFAULT;
1436 if (file->f_mode & FMODE_READ) {
1437 stop_adc(s);
1438 s->dma_adc.num_channels = val ? 2 : 1;
1439 if ((ret = prog_dmabuf_adc(s)))
1440 return ret;
1441 }
1442 if (file->f_mode & FMODE_WRITE) {
1443 stop_dac(s);
1444 s->dma_dac.num_channels = val ? 2 : 1;
1445 if (s->codec_ext_caps & AC97_EXT_DACS) {
1446 /* disable surround and center/lfe in AC'97
1447 */
1448 u16 ext_stat = rdcodec(s->codec,
1449 AC97_EXTENDED_STATUS);
1450 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1451 ext_stat | (AC97_EXTSTAT_PRI |
1452 AC97_EXTSTAT_PRJ |
1453 AC97_EXTSTAT_PRK));
1454 }
1455 if ((ret = prog_dmabuf_dac(s)))
1456 return ret;
1457 }
1458 return 0;
1459
1460 case SNDCTL_DSP_CHANNELS:
1461 if (get_user(val, (int *) arg))
1462 return -EFAULT;
1463 if (val != 0) {
1464 if (file->f_mode & FMODE_READ) {
1465 if (val < 0 || val > 2)
1466 return -EINVAL;
1467 stop_adc(s);
1468 s->dma_adc.num_channels = val;
1469 if ((ret = prog_dmabuf_adc(s)))
1470 return ret;
1471 }
1472 if (file->f_mode & FMODE_WRITE) {
1473 switch (val) {
1474 case 1:
1475 case 2:
1476 break;
1477 case 3:
1478 case 5:
1479 return -EINVAL;
1480 case 4:
1481 if (!(s->codec_ext_caps &
1482 AC97_EXTID_SDAC))
1483 return -EINVAL;
1484 break;
1485 case 6:
1486 if ((s->codec_ext_caps &
1487 AC97_EXT_DACS) != AC97_EXT_DACS)
1488 return -EINVAL;
1489 break;
1490 default:
1491 return -EINVAL;
1492 }
1493
1494 stop_dac(s);
1495 if (val <= 2 &&
1496 (s->codec_ext_caps & AC97_EXT_DACS)) {
1497 /* disable surround and center/lfe
1498 * channels in AC'97
1499 */
1500 u16 ext_stat =
1501 rdcodec(s->codec,
1502 AC97_EXTENDED_STATUS);
1503 wrcodec(s->codec,
1504 AC97_EXTENDED_STATUS,
1505 ext_stat | (AC97_EXTSTAT_PRI |
1506 AC97_EXTSTAT_PRJ |
1507 AC97_EXTSTAT_PRK));
1508 } else if (val >= 4) {
1509 /* enable surround, center/lfe
1510 * channels in AC'97
1511 */
1512 u16 ext_stat =
1513 rdcodec(s->codec,
1514 AC97_EXTENDED_STATUS);
1515 ext_stat &= ~AC97_EXTSTAT_PRJ;
1516 if (val == 6)
1517 ext_stat &=
1518 ~(AC97_EXTSTAT_PRI |
1519 AC97_EXTSTAT_PRK);
1520 wrcodec(s->codec,
1521 AC97_EXTENDED_STATUS,
1522 ext_stat);
1523 }
1524
1525 s->dma_dac.num_channels = val;
1526 if ((ret = prog_dmabuf_dac(s)))
1527 return ret;
1528 }
1529 }
1530 return put_user(val, (int *) arg);
1531
1532 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1533 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1534
1535 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1536 if (get_user(val, (int *) arg))
1537 return -EFAULT;
1538 if (val != AFMT_QUERY) {
1539 if (file->f_mode & FMODE_READ) {
1540 stop_adc(s);
1541 if (val == AFMT_S16_LE)
1542 s->dma_adc.sample_size = 16;
1543 else {
1544 val = AFMT_U8;
1545 s->dma_adc.sample_size = 8;
1546 }
1547 if ((ret = prog_dmabuf_adc(s)))
1548 return ret;
1549 }
1550 if (file->f_mode & FMODE_WRITE) {
1551 stop_dac(s);
1552 if (val == AFMT_S16_LE)
1553 s->dma_dac.sample_size = 16;
1554 else {
1555 val = AFMT_U8;
1556 s->dma_dac.sample_size = 8;
1557 }
1558 if ((ret = prog_dmabuf_dac(s)))
1559 return ret;
1560 }
1561 } else {
1562 if (file->f_mode & FMODE_READ)
1563 val = (s->dma_adc.sample_size == 16) ?
1564 AFMT_S16_LE : AFMT_U8;
1565 else
1566 val = (s->dma_dac.sample_size == 16) ?
1567 AFMT_S16_LE : AFMT_U8;
1568 }
1569 return put_user(val, (int *) arg);
1570
1571 case SNDCTL_DSP_POST:
1572 return 0;
1573
1574 case SNDCTL_DSP_GETTRIGGER:
1575 val = 0;
1576 spin_lock_irqsave(&s->lock, flags);
1577 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1578 val |= PCM_ENABLE_INPUT;
1579 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1580 val |= PCM_ENABLE_OUTPUT;
1581 spin_unlock_irqrestore(&s->lock, flags);
1582 return put_user(val, (int *) arg);
1583
1584 case SNDCTL_DSP_SETTRIGGER:
1585 if (get_user(val, (int *) arg))
1586 return -EFAULT;
1587 if (file->f_mode & FMODE_READ) {
7b666653
SS		 1588 if (val & PCM_ENABLE_INPUT) {
1589 spin_lock_irqsave(&s->lock, flags);
1da177e4 1590 start_adc(s);
7b666653
SS		 1591 spin_unlock_irqrestore(&s->lock, flags);
1592 } else
1da177e4
LT		 1593 stop_adc(s);
1594 }
1595 if (file->f_mode & FMODE_WRITE) {
7b666653
SS		 1596 if (val & PCM_ENABLE_OUTPUT) {
1597 spin_lock_irqsave(&s->lock, flags);
1da177e4 1598 start_dac(s);
7b666653
SS		 1599 spin_unlock_irqrestore(&s->lock, flags);
1600 } else
1da177e4
LT		 1601 stop_dac(s);
1602 }
1603 return 0;
1604
1605 case SNDCTL_DSP_GETOSPACE:
1606 if (!(file->f_mode & FMODE_WRITE))
1607 return -EINVAL;
1608 abinfo.fragsize = s->dma_dac.fragsize;
1609 spin_lock_irqsave(&s->lock, flags);
1610 count = s->dma_dac.count;
1611 count -= dma_count_done(&s->dma_dac);
1612 spin_unlock_irqrestore(&s->lock, flags);
1613 if (count < 0)
1614 count = 0;
1615 abinfo.bytes = (s->dma_dac.dmasize - count) /
1616 s->dma_dac.cnt_factor;
1617 abinfo.fragstotal = s->dma_dac.numfrag;
1618 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1619 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1620 return copy_to_user((void *) arg, &abinfo,
1621 sizeof(abinfo)) ? -EFAULT : 0;
1622
1623 case SNDCTL_DSP_GETISPACE:
1624 if (!(file->f_mode & FMODE_READ))
1625 return -EINVAL;
1626 abinfo.fragsize = s->dma_adc.fragsize;
1627 spin_lock_irqsave(&s->lock, flags);
1628 count = s->dma_adc.count;
1629 count += dma_count_done(&s->dma_adc);
1630 spin_unlock_irqrestore(&s->lock, flags);
1631 if (count < 0)
1632 count = 0;
1633 abinfo.bytes = count / s->dma_adc.cnt_factor;
1634 abinfo.fragstotal = s->dma_adc.numfrag;
1635 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1636 return copy_to_user((void *) arg, &abinfo,
1637 sizeof(abinfo)) ? -EFAULT : 0;
1638
1639 case SNDCTL_DSP_NONBLOCK:
db1dd4d3 1640 spin_lock(&file->f_lock);
1da177e4 1641 file->f_flags |= O_NONBLOCK;
db1dd4d3 1642 spin_unlock(&file->f_lock);
1da177e4
LT		 1643 return 0;
1644
1645 case SNDCTL_DSP_GETODELAY:
1646 if (!(file->f_mode & FMODE_WRITE))
1647 return -EINVAL;
1648 spin_lock_irqsave(&s->lock, flags);
1649 count = s->dma_dac.count;
1650 count -= dma_count_done(&s->dma_dac);
1651 spin_unlock_irqrestore(&s->lock, flags);
1652 if (count < 0)
1653 count = 0;
1654 count /= s->dma_dac.cnt_factor;
1655 return put_user(count, (int *) arg);
1656
1657 case SNDCTL_DSP_GETIPTR:
1658 if (!(file->f_mode & FMODE_READ))
1659 return -EINVAL;
1660 spin_lock_irqsave(&s->lock, flags);
1661 cinfo.bytes = s->dma_adc.total_bytes;
1662 count = s->dma_adc.count;
1663 if (!s->dma_adc.stopped) {
1664 diff = dma_count_done(&s->dma_adc);
1665 count += diff;
1666 cinfo.bytes += diff;
1667 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1668 virt_to_phys(s->dma_adc.rawbuf);
1669 } else
1670 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1671 virt_to_phys(s->dma_adc.rawbuf);
1672 if (s->dma_adc.mapped)
1673 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1674 spin_unlock_irqrestore(&s->lock, flags);
1675 if (count < 0)
1676 count = 0;
1677 cinfo.blocks = count >> s->dma_adc.fragshift;
1678 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1679
1680 case SNDCTL_DSP_GETOPTR:
1681 if (!(file->f_mode & FMODE_READ))
1682 return -EINVAL;
1683 spin_lock_irqsave(&s->lock, flags);
1684 cinfo.bytes = s->dma_dac.total_bytes;
1685 count = s->dma_dac.count;
1686 if (!s->dma_dac.stopped) {
1687 diff = dma_count_done(&s->dma_dac);
1688 count -= diff;
1689 cinfo.bytes += diff;
1690 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1691 virt_to_phys(s->dma_dac.rawbuf);
1692 } else
1693 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1694 virt_to_phys(s->dma_dac.rawbuf);
1695 if (s->dma_dac.mapped)
1696 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1697 spin_unlock_irqrestore(&s->lock, flags);
1698 if (count < 0)
1699 count = 0;
1700 cinfo.blocks = count >> s->dma_dac.fragshift;
1701 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1702
1703 case SNDCTL_DSP_GETBLKSIZE:
1704 if (file->f_mode & FMODE_WRITE)
1705 return put_user(s->dma_dac.fragsize, (int *) arg);
1706 else
1707 return put_user(s->dma_adc.fragsize, (int *) arg);
1708
1709 case SNDCTL_DSP_SETFRAGMENT:
1710 if (get_user(val, (int *) arg))
1711 return -EFAULT;
1712 if (file->f_mode & FMODE_READ) {
1713 stop_adc(s);
1714 s->dma_adc.ossfragshift = val & 0xffff;
1715 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1716 if (s->dma_adc.ossfragshift < 4)
1717 s->dma_adc.ossfragshift = 4;
1718 if (s->dma_adc.ossfragshift > 15)
1719 s->dma_adc.ossfragshift = 15;
1720 if (s->dma_adc.ossmaxfrags < 4)
1721 s->dma_adc.ossmaxfrags = 4;
1722 if ((ret = prog_dmabuf_adc(s)))
1723 return ret;
1724 }
1725 if (file->f_mode & FMODE_WRITE) {
1726 stop_dac(s);
1727 s->dma_dac.ossfragshift = val & 0xffff;
1728 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1729 if (s->dma_dac.ossfragshift < 4)
1730 s->dma_dac.ossfragshift = 4;
1731 if (s->dma_dac.ossfragshift > 15)
1732 s->dma_dac.ossfragshift = 15;
1733 if (s->dma_dac.ossmaxfrags < 4)
1734 s->dma_dac.ossmaxfrags = 4;
1735 if ((ret = prog_dmabuf_dac(s)))
1736 return ret;
1737 }
1738 return 0;
1739
1740 case SNDCTL_DSP_SUBDIVIDE:
1741 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1742 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1743 return -EINVAL;
1744 if (get_user(val, (int *) arg))
1745 return -EFAULT;
1746 if (val != 1 && val != 2 && val != 4)
1747 return -EINVAL;
1748 if (file->f_mode & FMODE_READ) {
1749 stop_adc(s);
1750 s->dma_adc.subdivision = val;
1751 if ((ret = prog_dmabuf_adc(s)))
1752 return ret;
1753 }
1754 if (file->f_mode & FMODE_WRITE) {
1755 stop_dac(s);
1756 s->dma_dac.subdivision = val;
1757 if ((ret = prog_dmabuf_dac(s)))
1758 return ret;
1759 }
1760 return 0;
1761
1762 case SOUND_PCM_READ_RATE:
1763 return put_user((file->f_mode & FMODE_READ) ?
1764 s->dma_adc.sample_rate :
1765 s->dma_dac.sample_rate,
1766 (int *)arg);
1767
1768 case SOUND_PCM_READ_CHANNELS:
1769 if (file->f_mode & FMODE_READ)
1770 return put_user(s->dma_adc.num_channels, (int *)arg);
1771 else
1772 return put_user(s->dma_dac.num_channels, (int *)arg);
1773
1774 case SOUND_PCM_READ_BITS:
1775 if (file->f_mode & FMODE_READ)
1776 return put_user(s->dma_adc.sample_size, (int *)arg);
1777 else
1778 return put_user(s->dma_dac.sample_size, (int *)arg);
1779
1780 case SOUND_PCM_WRITE_FILTER:
1781 case SNDCTL_DSP_SETSYNCRO:
1782 case SOUND_PCM_READ_FILTER:
1783 return -EINVAL;
1784 }
1785
1786 return mixdev_ioctl(s->codec, cmd, arg);
1787}
1788
d209974c
AB		 1789static long
1790au1550_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1791{
1792 int ret;
1793
1794 lock_kernel();
1795 ret = au1550_ioctl(file, cmd, arg);
1796 unlock_kernel();
1797
1798 return ret;
1799}
1da177e4
LT		 1800
1801static int
1802au1550_open(struct inode *inode, struct file *file)
1803{
1804 int minor = MINOR(inode->i_rdev);
1805 DECLARE_WAITQUEUE(wait, current);
1806 struct au1550_state *s = &au1550_state;
1807 int ret;
1808
1809#ifdef DEBUG
1810 if (file->f_flags & O_NONBLOCK)
1811 pr_debug("open: non-blocking\n");
1812 else
1813 pr_debug("open: blocking\n");
1814#endif
1815
1816 file->private_data = s;
90dc763f 1817 lock_kernel();
1da177e4 1818 /* wait for device to become free */
910f5d20 1819 mutex_lock(&s->open_mutex);
1da177e4 1820 while (s->open_mode & file->f_mode) {
90dc763f
AB		 1821 ret = -EBUSY;
1822 if (file->f_flags & O_NONBLOCK)
1823 goto out;
1da177e4
LT		 1824 add_wait_queue(&s->open_wait, &wait);
1825 __set_current_state(TASK_INTERRUPTIBLE);
910f5d20 1826 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1827 schedule();
1828 remove_wait_queue(&s->open_wait, &wait);
1829 set_current_state(TASK_RUNNING);
90dc763f 1830 ret = -ERESTARTSYS;
1da177e4 1831 if (signal_pending(current))
90dc763f 1832 goto out2;
910f5d20 1833 mutex_lock(&s->open_mutex);
1da177e4
LT		 1834 }
1835
1836 stop_dac(s);
1837 stop_adc(s);
1838
1839 if (file->f_mode & FMODE_READ) {
1840 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1841 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1842 s->dma_adc.num_channels = 1;
1843 s->dma_adc.sample_size = 8;
1844 set_adc_rate(s, 8000);
1845 if ((minor & 0xf) == SND_DEV_DSP16)
1846 s->dma_adc.sample_size = 16;
1847 }
1848
1849 if (file->f_mode & FMODE_WRITE) {
1850 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1851 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1852 s->dma_dac.num_channels = 1;
1853 s->dma_dac.sample_size = 8;
1854 set_dac_rate(s, 8000);
1855 if ((minor & 0xf) == SND_DEV_DSP16)
1856 s->dma_dac.sample_size = 16;
1857 }
1858
1859 if (file->f_mode & FMODE_READ) {
1860 if ((ret = prog_dmabuf_adc(s)))
90dc763f 1861 goto out;
1da177e4
LT		 1862 }
1863 if (file->f_mode & FMODE_WRITE) {
1864 if ((ret = prog_dmabuf_dac(s)))
90dc763f 1865 goto out;
1da177e4
LT		 1866 }
1867
1868 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
910f5d20 1869 mutex_init(&s->sem);
90dc763f
AB		 1870 ret = 0;
1871out:
1872 mutex_unlock(&s->open_mutex);
1873out2:
1874 unlock_kernel();
1875 return ret;
1da177e4
LT		 1876}
1877
1878static int
1879au1550_release(struct inode *inode, struct file *file)
1880{
1881 struct au1550_state *s = (struct au1550_state *)file->private_data;
1882
1883 lock_kernel();
1884
1885 if (file->f_mode & FMODE_WRITE) {
1886 unlock_kernel();
1887 drain_dac(s, file->f_flags & O_NONBLOCK);
1888 lock_kernel();
1889 }
1890
910f5d20 1891 mutex_lock(&s->open_mutex);
1da177e4
LT		 1892 if (file->f_mode & FMODE_WRITE) {
1893 stop_dac(s);
1894 kfree(s->dma_dac.rawbuf);
1895 s->dma_dac.rawbuf = NULL;
1896 }
1897 if (file->f_mode & FMODE_READ) {
1898 stop_adc(s);
1899 kfree(s->dma_adc.rawbuf);
1900 s->dma_adc.rawbuf = NULL;
1901 }
1902 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
910f5d20 1903 mutex_unlock(&s->open_mutex);
1da177e4
LT		 1904 wake_up(&s->open_wait);
1905 unlock_kernel();
1906 return 0;
1907}
1908
1909static /*const */ struct file_operations au1550_audio_fops = {
d209974c
AB		 1910 .owner = THIS_MODULE,
1911 .llseek = au1550_llseek,
1912 .read = au1550_read,
1913 .write = au1550_write,
1914 .poll = au1550_poll,
1915 .unlocked_ioctl = au1550_unlocked_ioctl,
1916 .mmap = au1550_mmap,
1917 .open = au1550_open,
1918 .release = au1550_release,
1da177e4
LT		 1919};
1920
1921MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1922MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
bb12b76e
DP		 1923MODULE_LICENSE("GPL");
1924
1da177e4
LT		 1925
1926static int __devinit
1927au1550_probe(void)
1928{
1929 struct au1550_state *s = &au1550_state;
1930 int val;
1931
1932 memset(s, 0, sizeof(struct au1550_state));
1933
1934 init_waitqueue_head(&s->dma_adc.wait);
1935 init_waitqueue_head(&s->dma_dac.wait);
1936 init_waitqueue_head(&s->open_wait);
910f5d20 1937 mutex_init(&s->open_mutex);
1da177e4
LT		 1938 spin_lock_init(&s->lock);
1939
1940 s->codec = ac97_alloc_codec();
1941 if(s->codec == NULL) {
1942 err("Out of memory");
1943 return -1;
1944 }
1945 s->codec->private_data = s;
1946 s->codec->id = 0;
1947 s->codec->codec_read = rdcodec;
1948 s->codec->codec_write = wrcodec;
1949 s->codec->codec_wait = waitcodec;
1950
1951 if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1952 0x30, "Au1550 AC97")) {
1953 err("AC'97 ports in use");
1954 }
1955
1956 /* Allocate the DMA Channels
1957 */
1958 if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1959 DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1960 err("Can't get DAC DMA");
1961 goto err_dma1;
1962 }
1963 au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1964 if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1965 NUM_DBDMA_DESCRIPTORS) == 0) {
1966 err("Can't get DAC DMA descriptors");
1967 goto err_dma1;
1968 }
1969
1970 if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1971 DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1972 err("Can't get ADC DMA");
1973 goto err_dma2;
1974 }
1975 au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1976 if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1977 NUM_DBDMA_DESCRIPTORS) == 0) {
1978 err("Can't get ADC DMA descriptors");
1979 goto err_dma2;
1980 }
1981
1982 pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1983
1984 /* register devices */
1985
1986 if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1987 goto err_dev1;
1988 if ((s->codec->dev_mixer =
1989 register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1990 goto err_dev2;
1991
1992 /* The GPIO for the appropriate PSC was configured by the
1993 * board specific start up.
1994 *
1995 * configure PSC for AC'97
1996 */
1997 au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
1998 au_sync();
1999 au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
2000 au_sync();
2001
2002 /* cold reset the AC'97
2003 */
2004 au_writel(PSC_AC97RST_RST, PSC_AC97RST);
2005 au_sync();
2006 au1550_delay(10);
2007 au_writel(0, PSC_AC97RST);
2008 au_sync();
2009
2010 /* need to delay around 500msec(bleech) to give
2011 some CODECs enough time to wakeup */
2012 au1550_delay(500);
2013
2014 /* warm reset the AC'97 to start the bitclk
2015 */
2016 au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
2017 au_sync();
2018 udelay(100);
2019 au_writel(0, PSC_AC97RST);
2020 au_sync();
2021
2022 /* Enable PSC
2023 */
2024 au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
2025 au_sync();
2026
2027 /* Wait for PSC ready.
2028 */
2029 do {
05090fc9 2030 val = au_readl(PSC_AC97STAT);
1da177e4
LT		 2031 au_sync();
2032 } while ((val & PSC_AC97STAT_SR) == 0);
2033
2034 /* Configure AC97 controller.
2035 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2036 */
2037 val = PSC_AC97CFG_SET_LEN(16);
2038 val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2039
2040 /* Enable device so we can at least
2041 * talk over the AC-link.
2042 */
2043 au_writel(val, PSC_AC97CFG);
2044 au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2045 au_sync();
2046 val |= PSC_AC97CFG_DE_ENABLE;
2047 au_writel(val, PSC_AC97CFG);
2048 au_sync();
2049
2050 /* Wait for Device ready.
2051 */
2052 do {
05090fc9 2053 val = au_readl(PSC_AC97STAT);
1da177e4
LT		 2054 au_sync();
2055 } while ((val & PSC_AC97STAT_DR) == 0);
2056
2057 /* codec init */
2058 if (!ac97_probe_codec(s->codec))
2059 goto err_dev3;
2060
2061 s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2062 s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2063 pr_info("AC'97 Base/Extended ID = %04x/%04x",
2064 s->codec_base_caps, s->codec_ext_caps);
2065
2066 if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2067 /* codec does not support VRA
2068 */
2069 s->no_vra = 1;
2070 } else if (!vra) {
2071 /* Boot option says disable VRA
2072 */
2073 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2074 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2075 ac97_extstat & ~AC97_EXTSTAT_VRA);
2076 s->no_vra = 1;
2077 }
2078 if (s->no_vra)
2079 pr_info("no VRA, interpolating and decimating");
2080
2081 /* set mic to be the recording source */
2082 val = SOUND_MASK_MIC;
2083 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2084 (unsigned long) &val);
2085
2086 return 0;
2087
2088 err_dev3:
2089 unregister_sound_mixer(s->codec->dev_mixer);
2090 err_dev2:
2091 unregister_sound_dsp(s->dev_audio);
2092 err_dev1:
2093 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2094 err_dma2:
2095 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2096 err_dma1:
2097 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2098
2099 ac97_release_codec(s->codec);
2100 return -1;
2101}
2102
2103static void __devinit
2104au1550_remove(void)
2105{
2106 struct au1550_state *s = &au1550_state;
2107
2108 if (!s)
2109 return;
2110 synchronize_irq();
2111 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2112 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2113 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2114 unregister_sound_dsp(s->dev_audio);
2115 unregister_sound_mixer(s->codec->dev_mixer);
2116 ac97_release_codec(s->codec);
2117}
2118
2119static int __init
2120init_au1550(void)
2121{
2122 return au1550_probe();
2123}
2124
2125static void __exit
2126cleanup_au1550(void)
2127{
2128 au1550_remove();
2129}
2130
2131module_init(init_au1550);
2132module_exit(cleanup_au1550);
2133
2134#ifndef MODULE
2135
2136static int __init
2137au1550_setup(char *options)
2138{
2139 char *this_opt;
2140
2141 if (!options || !*options)
2142 return 0;
2143
2144 while ((this_opt = strsep(&options, ","))) {
2145 if (!*this_opt)
2146 continue;
2147 if (!strncmp(this_opt, "vra", 3)) {
2148 vra = 1;
2149 }
2150 }
2151
2152 return 1;
2153}
2154
2155__setup("au1550_audio=", au1550_setup);
2156
2157#endif /* MODULE */
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