[net-next-2.6.git] / include / sound / ad1848.h

#ifndef __SOUND_AD1848_H
#define __SOUND_AD1848_H

/*
 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
 *  Definitions for AD1847/AD1848/CS4248 chips
 *
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#include "pcm.h"
#include <linux/interrupt.h>

/* IO ports */

#define AD1848P( chip, x ) ( (chip) -> port + c_d_c_AD1848##x )

#define c_d_c_AD1848REGSEL	0
#define c_d_c_AD1848REG		1
#define c_d_c_AD1848STATUS	2
#define c_d_c_AD1848PIO		3

/* codec registers */

#define AD1848_LEFT_INPUT	0x00	/* left input control */
#define AD1848_RIGHT_INPUT	0x01	/* right input control */
#define AD1848_AUX1_LEFT_INPUT	0x02	/* left AUX1 input control */
#define AD1848_AUX1_RIGHT_INPUT	0x03	/* right AUX1 input control */
#define AD1848_AUX2_LEFT_INPUT	0x04	/* left AUX2 input control */
#define AD1848_AUX2_RIGHT_INPUT	0x05	/* right AUX2 input control */
#define AD1848_LEFT_OUTPUT	0x06	/* left output control register */
#define AD1848_RIGHT_OUTPUT	0x07	/* right output control register */
#define AD1848_DATA_FORMAT	0x08	/* clock and data format - playback/capture - bits 7-0 MCE */
#define AD1848_IFACE_CTRL	0x09	/* interface control - bits 7-2 MCE */
#define AD1848_PIN_CTRL		0x0a	/* pin control */
#define AD1848_TEST_INIT	0x0b	/* test and initialization */
#define AD1848_MISC_INFO	0x0c	/* miscellaneaous information */
#define AD1848_LOOPBACK		0x0d	/* loopback control */
#define AD1848_DATA_UPR_CNT	0x0e	/* playback/capture upper base count */
#define AD1848_DATA_LWR_CNT	0x0f	/* playback/capture lower base count */

/* definitions for codec register select port - CODECP( REGSEL ) */

#define AD1848_INIT		0x80	/* CODEC is initializing */
#define AD1848_MCE		0x40	/* mode change enable */
#define AD1848_TRD		0x20	/* transfer request disable */

/* definitions for codec status register - CODECP( STATUS ) */

#define AD1848_GLOBALIRQ	0x01	/* IRQ is active */

/* definitions for AD1848_LEFT_INPUT and AD1848_RIGHT_INPUT registers */

#define AD1848_ENABLE_MIC_GAIN	0x20

#define AD1848_MIXS_LINE1	0x00
#define AD1848_MIXS_AUX1	0x40
#define AD1848_MIXS_LINE2	0x80
#define AD1848_MIXS_ALL		0xc0

/* definitions for clock and data format register - AD1848_PLAYBK_FORMAT */

#define AD1848_LINEAR_8		0x00	/* 8-bit unsigned data */
#define AD1848_ALAW_8		0x60	/* 8-bit A-law companded */
#define AD1848_ULAW_8		0x20	/* 8-bit U-law companded */
#define AD1848_LINEAR_16	0x40	/* 16-bit twos complement data - little endian */
#define AD1848_STEREO		0x10	/* stereo mode */
/* bits 3-1 define frequency divisor */
#define AD1848_XTAL1		0x00	/* 24.576 crystal */
#define AD1848_XTAL2		0x01	/* 16.9344 crystal */

/* definitions for interface control register - AD1848_IFACE_CTRL */

#define AD1848_CAPTURE_PIO	0x80	/* capture PIO enable */
#define AD1848_PLAYBACK_PIO	0x40	/* playback PIO enable */
#define AD1848_CALIB_MODE	0x18	/* calibration mode bits */
#define AD1848_AUTOCALIB	0x08	/* auto calibrate */
#define AD1848_SINGLE_DMA	0x04	/* use single DMA channel */
#define AD1848_CAPTURE_ENABLE	0x02	/* capture enable */
#define AD1848_PLAYBACK_ENABLE	0x01	/* playback enable */

/* definitions for pin control register - AD1848_PIN_CTRL */

#define AD1848_IRQ_ENABLE	0x02	/* enable IRQ */
#define AD1848_XCTL1		0x40	/* external control #1 */
#define AD1848_XCTL0		0x80	/* external control #0 */

/* definitions for test and init register - AD1848_TEST_INIT */

#define AD1848_CALIB_IN_PROGRESS 0x20	/* auto calibrate in progress */
#define AD1848_DMA_REQUEST	0x10	/* DMA request in progress */

/* defines for codec.mode */

#define AD1848_MODE_NONE	0x0000
#define AD1848_MODE_PLAY	0x0001
#define AD1848_MODE_CAPTURE	0x0002
#define AD1848_MODE_TIMER	0x0004
#define AD1848_MODE_OPEN	(AD1848_MODE_PLAY|AD1848_MODE_CAPTURE|AD1848_MODE_TIMER)
#define AD1848_MODE_RUNNING	0x0010

/* defines for codec.hardware */

#define AD1848_HW_DETECT	0x0000	/* let AD1848 driver detect chip */
#define AD1848_HW_AD1847	0x0001	/* AD1847 chip */
#define AD1848_HW_AD1848	0x0002	/* AD1848 chip */
#define AD1848_HW_CS4248	0x0003	/* CS4248 chip */
#define AD1848_HW_CMI8330	0x0004	/* CMI8330 chip */
#define AD1848_HW_THINKPAD	0x0005	/* Thinkpad 360/750/755 */

/* IBM Thinkpad specific stuff */
#define AD1848_THINKPAD_CTL_PORT1		0x15e8
#define AD1848_THINKPAD_CTL_PORT2		0x15e9
#define AD1848_THINKPAD_CS4248_ENABLE_BIT	0x02

struct snd_ad1848 {
	unsigned long port;		/* i/o port */
	struct resource *res_port;
	int irq;			/* IRQ line */
	int dma;			/* data DMA */
	unsigned short version;		/* version of CODEC chip */
	unsigned short mode;		/* see to AD1848_MODE_XXXX */
	unsigned short hardware;	/* see to AD1848_HW_XXXX */
	unsigned short single_dma:1;	/* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */

	struct snd_pcm *pcm;
	struct snd_pcm_substream *playback_substream;
	struct snd_pcm_substream *capture_substream;
	struct snd_card *card;

	unsigned char image[32];	/* SGalaxy needs an access to extended registers */
	int mce_bit;
	int calibrate_mute;
	int dma_size;
	int thinkpad_flag;		/* Thinkpad CS4248 needs some extra help */

#ifdef CONFIG_PM
	void (*suspend)(struct snd_ad1848 *chip);
	void (*resume)(struct snd_ad1848 *chip);
#endif

	spinlock_t reg_lock;
	struct mutex open_mutex;
};

/* exported functions */

void snd_ad1848_out(struct snd_ad1848 *chip, unsigned char reg, unsigned char value);

int snd_ad1848_create(struct snd_card *card,
		      unsigned long port,
		      int irq, int dma,
		      unsigned short hardware,
		      struct snd_ad1848 ** chip);

int snd_ad1848_pcm(struct snd_ad1848 * chip, int device, struct snd_pcm **rpcm);
const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction);
int snd_ad1848_mixer(struct snd_ad1848 * chip);

/* exported mixer stuffs */
enum { AD1848_MIX_SINGLE, AD1848_MIX_DOUBLE, AD1848_MIX_CAPTURE };

#define AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) \
	((reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24))
#define AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) \
	((left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22))

/* for ease of use */
struct ad1848_mix_elem {
	const char *name;
	int index;
	int type;
	unsigned long private_value;
	const unsigned int *tlv;
};

#define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
{ .name = xname, \
  .index = xindex, \
  .type = AD1848_MIX_SINGLE, \
  .private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) }

#define AD1848_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
{ .name = xname, \
  .index = xindex, \
  .type = AD1848_MIX_SINGLE, \
  .private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert), \
  .tlv = xtlv }

#define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
{ .name = xname, \
  .index = xindex, \
  .type = AD1848_MIX_DOUBLE, \
  .private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) }

#define AD1848_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
{ .name = xname, \
  .index = xindex, \
  .type = AD1848_MIX_DOUBLE, \
  .private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert), \
  .tlv = xtlv }

int snd_ad1848_add_ctl_elem(struct snd_ad1848 *chip, const struct ad1848_mix_elem *c);

#endif /* __SOUND_AD1848_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __SOUND_AD1848_H
	2	#define __SOUND_AD1848_H
	3
	4	/*
c1017a4c	5	* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
1da177e4 LT	6	* Definitions for AD1847/AD1848/CS4248 chips
	7	*
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#include "pcm.h"
	26	#include <linux/interrupt.h>
	27
	28	/* IO ports */
	29
3304cd36	30	#define AD1848P( chip, x ) ( (chip) -> port + c_d_c_AD1848##x )
1da177e4 LT	31
	32	#define c_d_c_AD1848REGSEL 0
	33	#define c_d_c_AD1848REG 1
	34	#define c_d_c_AD1848STATUS 2
	35	#define c_d_c_AD1848PIO 3
	36
	37	/* codec registers */
	38
	39	#define AD1848_LEFT_INPUT 0x00 /* left input control */
	40	#define AD1848_RIGHT_INPUT 0x01 /* right input control */
	41	#define AD1848_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
	42	#define AD1848_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
	43	#define AD1848_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
	44	#define AD1848_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
	45	#define AD1848_LEFT_OUTPUT 0x06 /* left output control register */
	46	#define AD1848_RIGHT_OUTPUT 0x07 /* right output control register */
	47	#define AD1848_DATA_FORMAT 0x08 /* clock and data format - playback/capture - bits 7-0 MCE */
	48	#define AD1848_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
	49	#define AD1848_PIN_CTRL 0x0a /* pin control */
	50	#define AD1848_TEST_INIT 0x0b /* test and initialization */
	51	#define AD1848_MISC_INFO 0x0c /* miscellaneaous information */
	52	#define AD1848_LOOPBACK 0x0d /* loopback control */
	53	#define AD1848_DATA_UPR_CNT 0x0e /* playback/capture upper base count */
	54	#define AD1848_DATA_LWR_CNT 0x0f /* playback/capture lower base count */
	55
	56	/* definitions for codec register select port - CODECP( REGSEL ) */
	57
	58	#define AD1848_INIT 0x80 /* CODEC is initializing */
	59	#define AD1848_MCE 0x40 /* mode change enable */
	60	#define AD1848_TRD 0x20 /* transfer request disable */
	61
	62	/* definitions for codec status register - CODECP( STATUS ) */
	63
	64	#define AD1848_GLOBALIRQ 0x01 /* IRQ is active */
	65
	66	/* definitions for AD1848_LEFT_INPUT and AD1848_RIGHT_INPUT registers */
	67
	68	#define AD1848_ENABLE_MIC_GAIN 0x20
	69
	70	#define AD1848_MIXS_LINE1 0x00
	71	#define AD1848_MIXS_AUX1 0x40
	72	#define AD1848_MIXS_LINE2 0x80
	73	#define AD1848_MIXS_ALL 0xc0
	74
	75	/* definitions for clock and data format register - AD1848_PLAYBK_FORMAT */
	76
	77	#define AD1848_LINEAR_8 0x00 /* 8-bit unsigned data */
	78	#define AD1848_ALAW_8 0x60 /* 8-bit A-law companded */
	79	#define AD1848_ULAW_8 0x20 /* 8-bit U-law companded */
	80	#define AD1848_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
	81	#define AD1848_STEREO 0x10 /* stereo mode */
	82	/* bits 3-1 define frequency divisor */
	83	#define AD1848_XTAL1 0x00 /* 24.576 crystal */
	84	#define AD1848_XTAL2 0x01 /* 16.9344 crystal */
	85
	86	/* definitions for interface control register - AD1848_IFACE_CTRL */
	87
	88	#define AD1848_CAPTURE_PIO 0x80 /* capture PIO enable */
	89	#define AD1848_PLAYBACK_PIO 0x40 /* playback PIO enable */
	90	#define AD1848_CALIB_MODE 0x18 /* calibration mode bits */
	91	#define AD1848_AUTOCALIB 0x08 /* auto calibrate */
	92	#define AD1848_SINGLE_DMA 0x04 /* use single DMA channel */
	93	#define AD1848_CAPTURE_ENABLE 0x02 /* capture enable */
	94	#define AD1848_PLAYBACK_ENABLE 0x01 /* playback enable */
95
96	/* definitions for pin control register - AD1848_PIN_CTRL */
97
98	#define AD1848_IRQ_ENABLE 0x02 /* enable IRQ */
99	#define AD1848_XCTL1 0x40 /* external control #1 */
100	#define AD1848_XCTL0 0x80 /* external control #0 */
101
102	/* definitions for test and init register - AD1848_TEST_INIT */
103
104	#define AD1848_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
105	#define AD1848_DMA_REQUEST 0x10 /* DMA request in progress */
106
107	/* defines for codec.mode */
108
109	#define AD1848_MODE_NONE 0x0000
110	#define AD1848_MODE_PLAY 0x0001
111	#define AD1848_MODE_CAPTURE 0x0002
112	#define AD1848_MODE_TIMER 0x0004
113	#define AD1848_MODE_OPEN (AD1848_MODE_PLAY\|AD1848_MODE_CAPTURE\|AD1848_MODE_TIMER)
114	#define AD1848_MODE_RUNNING 0x0010
115
116	/* defines for codec.hardware */
117
118	#define AD1848_HW_DETECT 0x0000 /* let AD1848 driver detect chip */
119	#define AD1848_HW_AD1847 0x0001 /* AD1847 chip */
120	#define AD1848_HW_AD1848 0x0002 /* AD1848 chip */
121	#define AD1848_HW_CS4248 0x0003 /* CS4248 chip */
122	#define AD1848_HW_CMI8330 0x0004 /* CMI8330 chip */
123	#define AD1848_HW_THINKPAD 0x0005 /* Thinkpad 360/750/755 */
124
125	/* IBM Thinkpad specific stuff */
126	#define AD1848_THINKPAD_CTL_PORT1 0x15e8
127	#define AD1848_THINKPAD_CTL_PORT2 0x15e9
128	#define AD1848_THINKPAD_CS4248_ENABLE_BIT 0x02
129
c8ff6647	130	struct snd_ad1848 {
1da177e4 LT	131	unsigned long port; /* i/o port */
	132	struct resource *res_port;
	133	int irq; /* IRQ line */
	134	int dma; /* data DMA */
	135	unsigned short version; /* version of CODEC chip */
	136	unsigned short mode; /* see to AD1848_MODE_XXXX */
	137	unsigned short hardware; /* see to AD1848_HW_XXXX */
	138	unsigned short single_dma:1; /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
	139
c8ff6647 TI	140	struct snd_pcm *pcm;
	141	struct snd_pcm_substream *playback_substream;
	142	struct snd_pcm_substream *capture_substream;
	143	struct snd_card *card;
1da177e4 LT	144
	145	unsigned char image[32]; /* SGalaxy needs an access to extended registers */
	146	int mce_bit;
	147	int calibrate_mute;
	148	int dma_size;
	149	int thinkpad_flag; /* Thinkpad CS4248 needs some extra help */
	150
c66d7f72 TI	151	#ifdef CONFIG_PM
	152	void (suspend)(struct snd_ad1848 chip);
	153	void (resume)(struct snd_ad1848 chip);
	154	#endif
	155
1da177e4	156	spinlock_t reg_lock;
8b7547f9	157	struct mutex open_mutex;
1da177e4 LT	158	};
1da177e4 LT	159
1da177e4 LT	160	/* exported functions */
1da177e4 LT	161
c8ff6647	162	void snd_ad1848_out(struct snd_ad1848 *chip, unsigned char reg, unsigned char value);
1da177e4	163
c8ff6647	164	int snd_ad1848_create(struct snd_card *card,
1da177e4 LT	165	unsigned long port,
	166	int irq, int dma,
	167	unsigned short hardware,
c8ff6647	168	struct snd_ad1848 ** chip);
1da177e4	169
c8ff6647 TI	170	int snd_ad1848_pcm(struct snd_ad1848 * chip, int device, struct snd_pcm **rpcm);
	171	const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction);
	172	int snd_ad1848_mixer(struct snd_ad1848 * chip);
1da177e4 LT	173
	174	/* exported mixer stuffs */
	175	enum { AD1848_MIX_SINGLE, AD1848_MIX_DOUBLE, AD1848_MIX_CAPTURE };
	176
	177	#define AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) \
	178	((reg) \| ((shift) << 8) \| ((mask) << 16) \| ((invert) << 24))
	179	#define AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) \
	180	((left_reg) \| ((right_reg) << 8) \| ((shift_left) << 16) \| ((shift_right) << 19) \| ((mask) << 24) \| ((invert) << 22))
	181
1da177e4 LT	182	/* for ease of use */
	183	struct ad1848_mix_elem {
	184	const char *name;
	185	int index;
	186	int type;
	187	unsigned long private_value;
0cb29ea0	188	const unsigned int *tlv;
1da177e4 LT	189	};
	190
	191	#define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
	192	{ .name = xname, \
	193	.index = xindex, \
	194	.type = AD1848_MIX_SINGLE, \
	195	.private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) }
	196
eac06a10 TI	197	#define AD1848_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
	198	{ .name = xname, \
	199	.index = xindex, \
	200	.type = AD1848_MIX_SINGLE, \
	201	.private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert), \
	202	.tlv = xtlv }
	203
1da177e4 LT	204	#define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
	205	{ .name = xname, \
	206	.index = xindex, \
	207	.type = AD1848_MIX_DOUBLE, \
	208	.private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) }
	209
eac06a10 TI	210	#define AD1848_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
	211	{ .name = xname, \
	212	.index = xindex, \
	213	.type = AD1848_MIX_DOUBLE, \
	214	.private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert), \
	215	.tlv = xtlv }
	216
	217	int snd_ad1848_add_ctl_elem(struct snd_ad1848 chip, const struct ad1848_mix_elem c);
1da177e4 LT	218
1da177e4 LT	219	#endif /* __SOUND_AD1848_H */