[net-next-2.6.git] / include / linux / sh_clk.h

#ifndef __SH_CLOCK_H
#define __SH_CLOCK_H

#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/cpufreq.h>
#include <linux/types.h>
#include <linux/kref.h>
#include <linux/clk.h>
#include <linux/err.h>

struct clk;

struct clk_mapping {
	phys_addr_t		phys;
	void __iomem		*base;
	unsigned long		len;
	struct kref		ref;
};

struct clk_ops {
	void (*init)(struct clk *clk);
	int (*enable)(struct clk *clk);
	void (*disable)(struct clk *clk);
	unsigned long (*recalc)(struct clk *clk);
	int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
	int (*set_parent)(struct clk *clk, struct clk *parent);
	long (*round_rate)(struct clk *clk, unsigned long rate);
};

struct clk {
	struct list_head	node;
	struct clk		*parent;
	struct clk		**parent_table;	/* list of parents to */
	unsigned short		parent_num;	/* choose between */
	unsigned char		src_shift;	/* source clock field in the */
	unsigned char		src_width;	/* configuration register */
	struct clk_ops		*ops;

	struct list_head	children;
	struct list_head	sibling;	/* node for children */

	int			usecount;

	unsigned long		rate;
	unsigned long		flags;

	void __iomem		*enable_reg;
	unsigned int		enable_bit;

	unsigned long		arch_flags;
	void			*priv;
	struct dentry		*dentry;
	struct clk_mapping	*mapping;
	struct cpufreq_frequency_table *freq_table;
	unsigned int		nr_freqs;
};

#define CLK_ENABLE_ON_INIT	(1 << 0)

/* drivers/sh/clk.c */
unsigned long followparent_recalc(struct clk *);
void recalculate_root_clocks(void);
void propagate_rate(struct clk *);
int clk_reparent(struct clk *child, struct clk *parent);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
void clk_enable_init_clocks(void);

/**
 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
 * @clk: clock source
 * @rate: desired clock rate in Hz
 * @algo_id: algorithm id to be passed down to ops->set_rate
 *
 * Returns success (0) or negative errno.
 */
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);

enum clk_sh_algo_id {
	NO_CHANGE = 0,

	IUS_N1_N1,
	IUS_322,
	IUS_522,
	IUS_N11,

	SB_N1,

	SB3_N1,
	SB3_32,
	SB3_43,
	SB3_54,

	BP_N1,

	IP_N1,
};

struct clk_div_mult_table {
	unsigned int *divisors;
	unsigned int nr_divisors;
	unsigned int *multipliers;
	unsigned int nr_multipliers;
};

struct cpufreq_frequency_table;
void clk_rate_table_build(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  int nr_freqs,
			  struct clk_div_mult_table *src_table,
			  unsigned long *bitmap);

long clk_rate_table_round(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  unsigned long rate);

int clk_rate_table_find(struct clk *clk,
			struct cpufreq_frequency_table *freq_table,
			unsigned long rate);

long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
			      unsigned int div_max, unsigned long rate);

long clk_round_parent(struct clk *clk, unsigned long target,
		      unsigned long *best_freq, unsigned long *parent_freq,
		      unsigned int div_min, unsigned int div_max);

#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags)	\
{									\
	.parent		= _parent,					\
	.enable_reg	= (void __iomem *)_enable_reg,			\
	.enable_bit	= _enable_bit,					\
	.flags		= _flags,					\
}

int sh_clk_mstp32_register(struct clk *clks, int nr);

#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags)	\
{								\
	.parent = _parent,					\
	.enable_reg = (void __iomem *)_reg,			\
	.enable_bit = _shift,					\
	.arch_flags = _div_bitmap,				\
	.flags = _flags,					\
}

struct clk_div4_table {
	struct clk_div_mult_table *div_mult_table;
	void (*kick)(struct clk *clk);
};

int sh_clk_div4_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_enable_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_reparent_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);

#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents,	\
			_num_parents, _src_shift, _src_width)	\
{								\
	.parent = _parent,					\
	.enable_reg = (void __iomem *)_reg,			\
	.flags = _flags,					\
	.parent_table = _parents,				\
	.parent_num = _num_parents,				\
	.src_shift = _src_shift,				\
	.src_width = _src_width,				\
}

#define SH_CLK_DIV6(_parent, _reg, _flags)			\
	SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)

int sh_clk_div6_register(struct clk *clks, int nr);
int sh_clk_div6_reparent_register(struct clk *clks, int nr);

#endif /* __SH_CLOCK_H */
Commit	Line	Data
d28bdf05 MD	1	#ifndef __SH_CLOCK_H
	2	#define __SH_CLOCK_H
	3
	4	#include <linux/list.h>
	5	#include <linux/seq_file.h>
	6	#include <linux/cpufreq.h>
28085bc5 PM	7	#include <linux/types.h>
28085bc5 PM	8	#include <linux/kref.h>
d28bdf05 MD	9	#include <linux/clk.h>
	10	#include <linux/err.h>
	11
	12	struct clk;
	13
28085bc5 PM	14	struct clk_mapping {
	15	phys_addr_t phys;
	16	void __iomem *base;
	17	unsigned long len;
	18	struct kref ref;
	19	};
	20
d28bdf05 MD	21	struct clk_ops {
	22	void (init)(struct clk clk);
	23	int (enable)(struct clk clk);
	24	void (disable)(struct clk clk);
	25	unsigned long (recalc)(struct clk clk);
	26	int (set_rate)(struct clk clk, unsigned long rate, int algo_id);
	27	int (set_parent)(struct clk clk, struct clk *parent);
	28	long (round_rate)(struct clk clk, unsigned long rate);
	29	};
	30
	31	struct clk {
	32	struct list_head node;
d28bdf05	33	struct clk *parent;
b5272b50 GL	34	struct clk *parent_table; / list of parents to */
	35	unsigned short parent_num; /* choose between */
	36	unsigned char src_shift; /* source clock field in the */
	37	unsigned char src_width; /* configuration register */
d28bdf05 MD	38	struct clk_ops *ops;
	39
	40	struct list_head children;
	41	struct list_head sibling; /* node for children */
	42
	43	int usecount;
	44
	45	unsigned long rate;
	46	unsigned long flags;
	47
	48	void __iomem *enable_reg;
	49	unsigned int enable_bit;
	50
	51	unsigned long arch_flags;
	52	void *priv;
	53	struct dentry *dentry;
28085bc5	54	struct clk_mapping *mapping;
d28bdf05	55	struct cpufreq_frequency_table *freq_table;
f586903d	56	unsigned int nr_freqs;
d28bdf05 MD	57	};
	58
	59	#define CLK_ENABLE_ON_INIT (1 << 0)
	60
a71ba096	61	/* drivers/sh/clk.c */
d28bdf05 MD	62	unsigned long followparent_recalc(struct clk *);
	63	void recalculate_root_clocks(void);
	64	void propagate_rate(struct clk *);
	65	int clk_reparent(struct clk child, struct clk parent);
	66	int clk_register(struct clk *);
	67	void clk_unregister(struct clk *);
8b5ee113	68	void clk_enable_init_clocks(void);
d28bdf05	69
d28bdf05 MD	70	/**
	71	* clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
	72	* @clk: clock source
	73	* @rate: desired clock rate in Hz
	74	* @algo_id: algorithm id to be passed down to ops->set_rate
	75	*
	76	* Returns success (0) or negative errno.
	77	*/
	78	int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
	79
	80	enum clk_sh_algo_id {
	81	NO_CHANGE = 0,
	82
	83	IUS_N1_N1,
	84	IUS_322,
	85	IUS_522,
	86	IUS_N11,
	87
	88	SB_N1,
	89
	90	SB3_N1,
	91	SB3_32,
	92	SB3_43,
	93	SB3_54,
	94
	95	BP_N1,
	96
	97	IP_N1,
	98	};
	99
	100	struct clk_div_mult_table {
	101	unsigned int *divisors;
	102	unsigned int nr_divisors;
	103	unsigned int *multipliers;
	104	unsigned int nr_multipliers;
	105	};
	106
	107	struct cpufreq_frequency_table;
	108	void clk_rate_table_build(struct clk *clk,
	109	struct cpufreq_frequency_table *freq_table,
	110	int nr_freqs,
	111	struct clk_div_mult_table *src_table,
	112	unsigned long *bitmap);
	113
	114	long clk_rate_table_round(struct clk *clk,
	115	struct cpufreq_frequency_table *freq_table,
	116	unsigned long rate);
	117
	118	int clk_rate_table_find(struct clk *clk,
	119	struct cpufreq_frequency_table *freq_table,
	120	unsigned long rate);
	121
8e122db6 PM	122	long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
	123	unsigned int div_max, unsigned long rate);
	124
6af26c6c GL	125	long clk_round_parent(struct clk *clk, unsigned long target,
	126	unsigned long best_freq, unsigned long parent_freq,
	127	unsigned int div_min, unsigned int div_max);
	128
d28bdf05 MD	129	#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
	130	{ \
	131	.parent = _parent, \
	132	.enable_reg = (void __iomem *)_enable_reg, \
	133	.enable_bit = _enable_bit, \
	134	.flags = _flags, \
	135	}
	136
	137	int sh_clk_mstp32_register(struct clk *clks, int nr);
	138
	139	#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
	140	{ \
	141	.parent = _parent, \
	142	.enable_reg = (void __iomem *)_reg, \
	143	.enable_bit = _shift, \
	144	.arch_flags = _div_bitmap, \
	145	.flags = _flags, \
	146	}
	147
	148	struct clk_div4_table {
	149	struct clk_div_mult_table *div_mult_table;
	150	void (kick)(struct clk clk);
	151	};
	152
	153	int sh_clk_div4_register(struct clk *clks, int nr,
	154	struct clk_div4_table *table);
	155	int sh_clk_div4_enable_register(struct clk *clks, int nr,
	156	struct clk_div4_table *table);
	157	int sh_clk_div4_reparent_register(struct clk *clks, int nr,
	158	struct clk_div4_table *table);
	159
b3dd51a8 GL	160	#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \
	161	_num_parents, _src_shift, _src_width) \
	162	{ \
	163	.parent = _parent, \
	164	.enable_reg = (void __iomem *)_reg, \
	165	.flags = _flags, \
	166	.parent_table = _parents, \
	167	.parent_num = _num_parents, \
	168	.src_shift = _src_shift, \
	169	.src_width = _src_width, \
d28bdf05 MD	170	}
d28bdf05 MD	171
b3dd51a8 GL	172	#define SH_CLK_DIV6(_parent, _reg, _flags) \
	173	SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)
	174
d28bdf05	175	int sh_clk_div6_register(struct clk *clks, int nr);
b3dd51a8	176	int sh_clk_div6_reparent_register(struct clk *clks, int nr);
d28bdf05 MD	177
d28bdf05 MD	178	#endif /* __SH_CLOCK_H */