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Commit | Line | Data |
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0793a61d TG |
1 | /* |
2 | * Performance counters: | |
3 | * | |
a308444c IM |
4 | * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009, Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2008-2009, Red Hat, Inc., Peter Zijlstra | |
0793a61d TG |
7 | * |
8 | * Data type definitions, declarations, prototypes. | |
9 | * | |
a308444c | 10 | * Started by: Thomas Gleixner and Ingo Molnar |
0793a61d TG |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | #ifndef _LINUX_PERF_COUNTER_H | |
15 | #define _LINUX_PERF_COUNTER_H | |
16 | ||
f3dfd265 PM |
17 | #include <linux/types.h> |
18 | #include <linux/ioctl.h> | |
9aaa131a | 19 | #include <asm/byteorder.h> |
0793a61d TG |
20 | |
21 | /* | |
9f66a381 IM |
22 | * User-space ABI bits: |
23 | */ | |
24 | ||
25 | /* | |
0d48696f | 26 | * attr.type |
0793a61d | 27 | */ |
1c432d89 | 28 | enum perf_type_id { |
a308444c IM |
29 | PERF_TYPE_HARDWARE = 0, |
30 | PERF_TYPE_SOFTWARE = 1, | |
31 | PERF_TYPE_TRACEPOINT = 2, | |
32 | PERF_TYPE_HW_CACHE = 3, | |
33 | PERF_TYPE_RAW = 4, | |
b8e83514 | 34 | |
a308444c | 35 | PERF_TYPE_MAX, /* non-ABI */ |
b8e83514 | 36 | }; |
6c594c21 | 37 | |
b8e83514 | 38 | /* |
a308444c IM |
39 | * Generalized performance counter event types, used by the |
40 | * attr.event_id parameter of the sys_perf_counter_open() | |
41 | * syscall: | |
b8e83514 | 42 | */ |
1c432d89 | 43 | enum perf_hw_id { |
9f66a381 | 44 | /* |
b8e83514 | 45 | * Common hardware events, generalized by the kernel: |
9f66a381 | 46 | */ |
f4dbfa8f PZ |
47 | PERF_COUNT_HW_CPU_CYCLES = 0, |
48 | PERF_COUNT_HW_INSTRUCTIONS = 1, | |
49 | PERF_COUNT_HW_CACHE_REFERENCES = 2, | |
50 | PERF_COUNT_HW_CACHE_MISSES = 3, | |
51 | PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, | |
52 | PERF_COUNT_HW_BRANCH_MISSES = 5, | |
53 | PERF_COUNT_HW_BUS_CYCLES = 6, | |
54 | ||
a308444c | 55 | PERF_COUNT_HW_MAX, /* non-ABI */ |
b8e83514 | 56 | }; |
e077df4f | 57 | |
8326f44d IM |
58 | /* |
59 | * Generalized hardware cache counters: | |
60 | * | |
8be6e8f3 | 61 | * { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x |
8326f44d IM |
62 | * { read, write, prefetch } x |
63 | * { accesses, misses } | |
64 | */ | |
1c432d89 | 65 | enum perf_hw_cache_id { |
a308444c IM |
66 | PERF_COUNT_HW_CACHE_L1D = 0, |
67 | PERF_COUNT_HW_CACHE_L1I = 1, | |
68 | PERF_COUNT_HW_CACHE_LL = 2, | |
69 | PERF_COUNT_HW_CACHE_DTLB = 3, | |
70 | PERF_COUNT_HW_CACHE_ITLB = 4, | |
71 | PERF_COUNT_HW_CACHE_BPU = 5, | |
72 | ||
73 | PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ | |
8326f44d IM |
74 | }; |
75 | ||
1c432d89 | 76 | enum perf_hw_cache_op_id { |
a308444c IM |
77 | PERF_COUNT_HW_CACHE_OP_READ = 0, |
78 | PERF_COUNT_HW_CACHE_OP_WRITE = 1, | |
79 | PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, | |
8326f44d | 80 | |
a308444c | 81 | PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ |
8326f44d IM |
82 | }; |
83 | ||
1c432d89 PZ |
84 | enum perf_hw_cache_op_result_id { |
85 | PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, | |
86 | PERF_COUNT_HW_CACHE_RESULT_MISS = 1, | |
8326f44d | 87 | |
a308444c | 88 | PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ |
8326f44d IM |
89 | }; |
90 | ||
b8e83514 PZ |
91 | /* |
92 | * Special "software" counters provided by the kernel, even if the hardware | |
93 | * does not support performance counters. These counters measure various | |
94 | * physical and sw events of the kernel (and allow the profiling of them as | |
95 | * well): | |
96 | */ | |
1c432d89 | 97 | enum perf_sw_ids { |
a308444c IM |
98 | PERF_COUNT_SW_CPU_CLOCK = 0, |
99 | PERF_COUNT_SW_TASK_CLOCK = 1, | |
100 | PERF_COUNT_SW_PAGE_FAULTS = 2, | |
101 | PERF_COUNT_SW_CONTEXT_SWITCHES = 3, | |
102 | PERF_COUNT_SW_CPU_MIGRATIONS = 4, | |
103 | PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, | |
104 | PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, | |
105 | ||
106 | PERF_COUNT_SW_MAX, /* non-ABI */ | |
0793a61d TG |
107 | }; |
108 | ||
8a057d84 | 109 | /* |
0d48696f | 110 | * Bits that can be set in attr.sample_type to request information |
8a057d84 PZ |
111 | * in the overflow packets. |
112 | */ | |
b23f3325 | 113 | enum perf_counter_sample_format { |
a308444c IM |
114 | PERF_SAMPLE_IP = 1U << 0, |
115 | PERF_SAMPLE_TID = 1U << 1, | |
116 | PERF_SAMPLE_TIME = 1U << 2, | |
117 | PERF_SAMPLE_ADDR = 1U << 3, | |
118 | PERF_SAMPLE_GROUP = 1U << 4, | |
119 | PERF_SAMPLE_CALLCHAIN = 1U << 5, | |
120 | PERF_SAMPLE_ID = 1U << 6, | |
121 | PERF_SAMPLE_CPU = 1U << 7, | |
122 | PERF_SAMPLE_PERIOD = 1U << 8, | |
974802ea PZ |
123 | |
124 | PERF_SAMPLE_MAX = 1U << 9, /* non-ABI */ | |
8a057d84 PZ |
125 | }; |
126 | ||
53cfbf59 | 127 | /* |
0d48696f | 128 | * Bits that can be set in attr.read_format to request that |
53cfbf59 PM |
129 | * reads on the counter should return the indicated quantities, |
130 | * in increasing order of bit value, after the counter value. | |
131 | */ | |
132 | enum perf_counter_read_format { | |
a308444c IM |
133 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, |
134 | PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, | |
135 | PERF_FORMAT_ID = 1U << 2, | |
974802ea PZ |
136 | |
137 | PERF_FORMAT_MAX = 1U << 3, /* non-ABI */ | |
53cfbf59 PM |
138 | }; |
139 | ||
974802ea PZ |
140 | #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ |
141 | ||
9f66a381 IM |
142 | /* |
143 | * Hardware event to monitor via a performance monitoring counter: | |
144 | */ | |
0d48696f | 145 | struct perf_counter_attr { |
974802ea | 146 | |
f4a2deb4 | 147 | /* |
a21ca2ca IM |
148 | * Major type: hardware/software/tracepoint/etc. |
149 | */ | |
150 | __u32 type; | |
974802ea PZ |
151 | |
152 | /* | |
153 | * Size of the attr structure, for fwd/bwd compat. | |
154 | */ | |
155 | __u32 size; | |
a21ca2ca IM |
156 | |
157 | /* | |
158 | * Type specific configuration information. | |
f4a2deb4 PZ |
159 | */ |
160 | __u64 config; | |
9f66a381 | 161 | |
60db5e09 | 162 | union { |
b23f3325 PZ |
163 | __u64 sample_period; |
164 | __u64 sample_freq; | |
60db5e09 PZ |
165 | }; |
166 | ||
b23f3325 PZ |
167 | __u64 sample_type; |
168 | __u64 read_format; | |
9f66a381 | 169 | |
2743a5b0 | 170 | __u64 disabled : 1, /* off by default */ |
0475f9ea PM |
171 | inherit : 1, /* children inherit it */ |
172 | pinned : 1, /* must always be on PMU */ | |
173 | exclusive : 1, /* only group on PMU */ | |
174 | exclude_user : 1, /* don't count user */ | |
175 | exclude_kernel : 1, /* ditto kernel */ | |
176 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 177 | exclude_idle : 1, /* don't count when idle */ |
0a4a9391 | 178 | mmap : 1, /* include mmap data */ |
8d1b2d93 | 179 | comm : 1, /* include comm data */ |
60db5e09 | 180 | freq : 1, /* use freq, not period */ |
0475f9ea | 181 | |
974802ea | 182 | __reserved_1 : 53; |
2743a5b0 | 183 | |
c457810a | 184 | __u32 wakeup_events; /* wakeup every n events */ |
974802ea | 185 | __u32 __reserved_2; |
9f66a381 | 186 | |
974802ea | 187 | __u64 __reserved_3; |
eab656ae TG |
188 | }; |
189 | ||
d859e29f PM |
190 | /* |
191 | * Ioctls that can be done on a perf counter fd: | |
192 | */ | |
08247e31 PZ |
193 | #define PERF_COUNTER_IOC_ENABLE _IO ('$', 0) |
194 | #define PERF_COUNTER_IOC_DISABLE _IO ('$', 1) | |
195 | #define PERF_COUNTER_IOC_REFRESH _IO ('$', 2) | |
196 | #define PERF_COUNTER_IOC_RESET _IO ('$', 3) | |
197 | #define PERF_COUNTER_IOC_PERIOD _IOW('$', 4, u64) | |
3df5edad PZ |
198 | |
199 | enum perf_counter_ioc_flags { | |
200 | PERF_IOC_FLAG_GROUP = 1U << 0, | |
201 | }; | |
d859e29f | 202 | |
37d81828 PM |
203 | /* |
204 | * Structure of the page that can be mapped via mmap | |
205 | */ | |
206 | struct perf_counter_mmap_page { | |
207 | __u32 version; /* version number of this structure */ | |
208 | __u32 compat_version; /* lowest version this is compat with */ | |
38ff667b PZ |
209 | |
210 | /* | |
211 | * Bits needed to read the hw counters in user-space. | |
212 | * | |
92f22a38 PZ |
213 | * u32 seq; |
214 | * s64 count; | |
38ff667b | 215 | * |
a2e87d06 PZ |
216 | * do { |
217 | * seq = pc->lock; | |
38ff667b | 218 | * |
a2e87d06 PZ |
219 | * barrier() |
220 | * if (pc->index) { | |
221 | * count = pmc_read(pc->index - 1); | |
222 | * count += pc->offset; | |
223 | * } else | |
224 | * goto regular_read; | |
38ff667b | 225 | * |
a2e87d06 PZ |
226 | * barrier(); |
227 | * } while (pc->lock != seq); | |
38ff667b | 228 | * |
92f22a38 PZ |
229 | * NOTE: for obvious reason this only works on self-monitoring |
230 | * processes. | |
38ff667b | 231 | */ |
37d81828 PM |
232 | __u32 lock; /* seqlock for synchronization */ |
233 | __u32 index; /* hardware counter identifier */ | |
234 | __s64 offset; /* add to hardware counter value */ | |
7b732a75 | 235 | |
41f95331 PZ |
236 | /* |
237 | * Hole for extension of the self monitor capabilities | |
238 | */ | |
239 | ||
240 | __u64 __reserved[125]; /* align to 1k */ | |
241 | ||
38ff667b PZ |
242 | /* |
243 | * Control data for the mmap() data buffer. | |
244 | * | |
43a21ea8 PZ |
245 | * User-space reading the @data_head value should issue an rmb(), on |
246 | * SMP capable platforms, after reading this value -- see | |
247 | * perf_counter_wakeup(). | |
248 | * | |
249 | * When the mapping is PROT_WRITE the @data_tail value should be | |
250 | * written by userspace to reflect the last read data. In this case | |
251 | * the kernel will not over-write unread data. | |
38ff667b | 252 | */ |
8e3747c1 | 253 | __u64 data_head; /* head in the data section */ |
43a21ea8 | 254 | __u64 data_tail; /* user-space written tail */ |
37d81828 PM |
255 | }; |
256 | ||
a308444c IM |
257 | #define PERF_EVENT_MISC_CPUMODE_MASK (3 << 0) |
258 | #define PERF_EVENT_MISC_CPUMODE_UNKNOWN (0 << 0) | |
259 | #define PERF_EVENT_MISC_KERNEL (1 << 0) | |
260 | #define PERF_EVENT_MISC_USER (2 << 0) | |
261 | #define PERF_EVENT_MISC_HYPERVISOR (3 << 0) | |
262 | #define PERF_EVENT_MISC_OVERFLOW (1 << 2) | |
6fab0192 | 263 | |
5c148194 PZ |
264 | struct perf_event_header { |
265 | __u32 type; | |
6fab0192 PZ |
266 | __u16 misc; |
267 | __u16 size; | |
5c148194 PZ |
268 | }; |
269 | ||
270 | enum perf_event_type { | |
5ed00415 | 271 | |
0c593b34 PZ |
272 | /* |
273 | * The MMAP events record the PROT_EXEC mappings so that we can | |
274 | * correlate userspace IPs to code. They have the following structure: | |
275 | * | |
276 | * struct { | |
0127c3ea | 277 | * struct perf_event_header header; |
0c593b34 | 278 | * |
0127c3ea IM |
279 | * u32 pid, tid; |
280 | * u64 addr; | |
281 | * u64 len; | |
282 | * u64 pgoff; | |
283 | * char filename[]; | |
0c593b34 PZ |
284 | * }; |
285 | */ | |
8a057d84 | 286 | PERF_EVENT_MMAP = 1, |
0a4a9391 | 287 | |
43a21ea8 PZ |
288 | /* |
289 | * struct { | |
290 | * struct perf_event_header header; | |
291 | * u64 id; | |
292 | * u64 lost; | |
293 | * }; | |
294 | */ | |
295 | PERF_EVENT_LOST = 2, | |
296 | ||
8d1b2d93 PZ |
297 | /* |
298 | * struct { | |
0127c3ea | 299 | * struct perf_event_header header; |
8d1b2d93 | 300 | * |
0127c3ea IM |
301 | * u32 pid, tid; |
302 | * char comm[]; | |
8d1b2d93 PZ |
303 | * }; |
304 | */ | |
305 | PERF_EVENT_COMM = 3, | |
306 | ||
26b119bc PZ |
307 | /* |
308 | * struct { | |
0127c3ea IM |
309 | * struct perf_event_header header; |
310 | * u64 time; | |
689802b2 | 311 | * u64 id; |
b23f3325 | 312 | * u64 sample_period; |
26b119bc PZ |
313 | * }; |
314 | */ | |
315 | PERF_EVENT_PERIOD = 4, | |
316 | ||
a78ac325 PZ |
317 | /* |
318 | * struct { | |
0127c3ea IM |
319 | * struct perf_event_header header; |
320 | * u64 time; | |
cca3f454 | 321 | * u64 id; |
a78ac325 PZ |
322 | * }; |
323 | */ | |
324 | PERF_EVENT_THROTTLE = 5, | |
325 | PERF_EVENT_UNTHROTTLE = 6, | |
326 | ||
60313ebe PZ |
327 | /* |
328 | * struct { | |
a21ca2ca IM |
329 | * struct perf_event_header header; |
330 | * u32 pid, ppid; | |
60313ebe PZ |
331 | * }; |
332 | */ | |
333 | PERF_EVENT_FORK = 7, | |
334 | ||
8a057d84 | 335 | /* |
6b6e5486 | 336 | * When header.misc & PERF_EVENT_MISC_OVERFLOW the event_type field |
43a21ea8 | 337 | * will be PERF_SAMPLE_* |
0c593b34 PZ |
338 | * |
339 | * struct { | |
0127c3ea | 340 | * struct perf_event_header header; |
0c593b34 | 341 | * |
43a21ea8 PZ |
342 | * { u64 ip; } && PERF_SAMPLE_IP |
343 | * { u32 pid, tid; } && PERF_SAMPLE_TID | |
344 | * { u64 time; } && PERF_SAMPLE_TIME | |
345 | * { u64 addr; } && PERF_SAMPLE_ADDR | |
346 | * { u64 config; } && PERF_SAMPLE_CONFIG | |
347 | * { u32 cpu, res; } && PERF_SAMPLE_CPU | |
0c593b34 | 348 | * |
0127c3ea | 349 | * { u64 nr; |
43a21ea8 | 350 | * { u64 id, val; } cnt[nr]; } && PERF_SAMPLE_GROUP |
0c593b34 | 351 | * |
f9188e02 | 352 | * { u64 nr, |
43a21ea8 | 353 | * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN |
0c593b34 | 354 | * }; |
8a057d84 | 355 | */ |
5c148194 PZ |
356 | }; |
357 | ||
f9188e02 PZ |
358 | enum perf_callchain_context { |
359 | PERF_CONTEXT_HV = (__u64)-32, | |
360 | PERF_CONTEXT_KERNEL = (__u64)-128, | |
361 | PERF_CONTEXT_USER = (__u64)-512, | |
7522060c | 362 | |
f9188e02 PZ |
363 | PERF_CONTEXT_GUEST = (__u64)-2048, |
364 | PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, | |
365 | PERF_CONTEXT_GUEST_USER = (__u64)-2560, | |
366 | ||
367 | PERF_CONTEXT_MAX = (__u64)-4095, | |
7522060c IM |
368 | }; |
369 | ||
f3dfd265 | 370 | #ifdef __KERNEL__ |
9f66a381 | 371 | /* |
f3dfd265 | 372 | * Kernel-internal data types and definitions: |
9f66a381 IM |
373 | */ |
374 | ||
f3dfd265 PM |
375 | #ifdef CONFIG_PERF_COUNTERS |
376 | # include <asm/perf_counter.h> | |
377 | #endif | |
378 | ||
379 | #include <linux/list.h> | |
380 | #include <linux/mutex.h> | |
381 | #include <linux/rculist.h> | |
382 | #include <linux/rcupdate.h> | |
383 | #include <linux/spinlock.h> | |
d6d020e9 | 384 | #include <linux/hrtimer.h> |
3c446b3d | 385 | #include <linux/fs.h> |
709e50cf | 386 | #include <linux/pid_namespace.h> |
f3dfd265 PM |
387 | #include <asm/atomic.h> |
388 | ||
f9188e02 PZ |
389 | #define PERF_MAX_STACK_DEPTH 255 |
390 | ||
391 | struct perf_callchain_entry { | |
392 | __u64 nr; | |
393 | __u64 ip[PERF_MAX_STACK_DEPTH]; | |
394 | }; | |
395 | ||
f3dfd265 PM |
396 | struct task_struct; |
397 | ||
0793a61d | 398 | /** |
9f66a381 | 399 | * struct hw_perf_counter - performance counter hardware details: |
0793a61d TG |
400 | */ |
401 | struct hw_perf_counter { | |
ee06094f | 402 | #ifdef CONFIG_PERF_COUNTERS |
d6d020e9 PZ |
403 | union { |
404 | struct { /* hardware */ | |
a308444c IM |
405 | u64 config; |
406 | unsigned long config_base; | |
407 | unsigned long counter_base; | |
408 | int idx; | |
d6d020e9 PZ |
409 | }; |
410 | union { /* software */ | |
a308444c IM |
411 | atomic64_t count; |
412 | struct hrtimer hrtimer; | |
d6d020e9 PZ |
413 | }; |
414 | }; | |
ee06094f | 415 | atomic64_t prev_count; |
b23f3325 | 416 | u64 sample_period; |
9e350de3 | 417 | u64 last_period; |
ee06094f | 418 | atomic64_t period_left; |
60db5e09 | 419 | u64 interrupts; |
6a24ed6c PZ |
420 | |
421 | u64 freq_count; | |
422 | u64 freq_interrupts; | |
bd2b5b12 | 423 | u64 freq_stamp; |
ee06094f | 424 | #endif |
0793a61d TG |
425 | }; |
426 | ||
621a01ea IM |
427 | struct perf_counter; |
428 | ||
429 | /** | |
4aeb0b42 | 430 | * struct pmu - generic performance monitoring unit |
621a01ea | 431 | */ |
4aeb0b42 | 432 | struct pmu { |
95cdd2e7 | 433 | int (*enable) (struct perf_counter *counter); |
7671581f IM |
434 | void (*disable) (struct perf_counter *counter); |
435 | void (*read) (struct perf_counter *counter); | |
a78ac325 | 436 | void (*unthrottle) (struct perf_counter *counter); |
621a01ea IM |
437 | }; |
438 | ||
6a930700 IM |
439 | /** |
440 | * enum perf_counter_active_state - the states of a counter | |
441 | */ | |
442 | enum perf_counter_active_state { | |
3b6f9e5c | 443 | PERF_COUNTER_STATE_ERROR = -2, |
6a930700 IM |
444 | PERF_COUNTER_STATE_OFF = -1, |
445 | PERF_COUNTER_STATE_INACTIVE = 0, | |
446 | PERF_COUNTER_STATE_ACTIVE = 1, | |
447 | }; | |
448 | ||
9b51f66d IM |
449 | struct file; |
450 | ||
7b732a75 PZ |
451 | struct perf_mmap_data { |
452 | struct rcu_head rcu_head; | |
8740f941 | 453 | int nr_pages; /* nr of data pages */ |
43a21ea8 | 454 | int writable; /* are we writable */ |
c5078f78 | 455 | int nr_locked; /* nr pages mlocked */ |
8740f941 | 456 | |
c33a0bc4 | 457 | atomic_t poll; /* POLL_ for wakeups */ |
8740f941 PZ |
458 | atomic_t events; /* event limit */ |
459 | ||
8e3747c1 PZ |
460 | atomic_long_t head; /* write position */ |
461 | atomic_long_t done_head; /* completed head */ | |
462 | ||
c33a0bc4 | 463 | atomic_t lock; /* concurrent writes */ |
c66de4a5 | 464 | atomic_t wakeup; /* needs a wakeup */ |
43a21ea8 | 465 | atomic_t lost; /* nr records lost */ |
c66de4a5 | 466 | |
7b732a75 | 467 | struct perf_counter_mmap_page *user_page; |
0127c3ea | 468 | void *data_pages[0]; |
7b732a75 PZ |
469 | }; |
470 | ||
671dec5d PZ |
471 | struct perf_pending_entry { |
472 | struct perf_pending_entry *next; | |
473 | void (*func)(struct perf_pending_entry *); | |
925d519a PZ |
474 | }; |
475 | ||
0793a61d TG |
476 | /** |
477 | * struct perf_counter - performance counter kernel representation: | |
478 | */ | |
479 | struct perf_counter { | |
ee06094f | 480 | #ifdef CONFIG_PERF_COUNTERS |
04289bb9 | 481 | struct list_head list_entry; |
592903cd | 482 | struct list_head event_entry; |
04289bb9 | 483 | struct list_head sibling_list; |
0127c3ea | 484 | int nr_siblings; |
04289bb9 | 485 | struct perf_counter *group_leader; |
4aeb0b42 | 486 | const struct pmu *pmu; |
04289bb9 | 487 | |
6a930700 | 488 | enum perf_counter_active_state state; |
0793a61d | 489 | atomic64_t count; |
ee06094f | 490 | |
53cfbf59 PM |
491 | /* |
492 | * These are the total time in nanoseconds that the counter | |
493 | * has been enabled (i.e. eligible to run, and the task has | |
494 | * been scheduled in, if this is a per-task counter) | |
495 | * and running (scheduled onto the CPU), respectively. | |
496 | * | |
497 | * They are computed from tstamp_enabled, tstamp_running and | |
498 | * tstamp_stopped when the counter is in INACTIVE or ACTIVE state. | |
499 | */ | |
500 | u64 total_time_enabled; | |
501 | u64 total_time_running; | |
502 | ||
503 | /* | |
504 | * These are timestamps used for computing total_time_enabled | |
505 | * and total_time_running when the counter is in INACTIVE or | |
506 | * ACTIVE state, measured in nanoseconds from an arbitrary point | |
507 | * in time. | |
508 | * tstamp_enabled: the notional time when the counter was enabled | |
509 | * tstamp_running: the notional time when the counter was scheduled on | |
510 | * tstamp_stopped: in INACTIVE state, the notional time when the | |
511 | * counter was scheduled off. | |
512 | */ | |
513 | u64 tstamp_enabled; | |
514 | u64 tstamp_running; | |
515 | u64 tstamp_stopped; | |
516 | ||
0d48696f | 517 | struct perf_counter_attr attr; |
0793a61d TG |
518 | struct hw_perf_counter hw; |
519 | ||
520 | struct perf_counter_context *ctx; | |
9b51f66d | 521 | struct file *filp; |
0793a61d | 522 | |
53cfbf59 PM |
523 | /* |
524 | * These accumulate total time (in nanoseconds) that children | |
525 | * counters have been enabled and running, respectively. | |
526 | */ | |
527 | atomic64_t child_total_time_enabled; | |
528 | atomic64_t child_total_time_running; | |
529 | ||
0793a61d | 530 | /* |
d859e29f | 531 | * Protect attach/detach and child_list: |
0793a61d | 532 | */ |
fccc714b PZ |
533 | struct mutex child_mutex; |
534 | struct list_head child_list; | |
535 | struct perf_counter *parent; | |
0793a61d TG |
536 | |
537 | int oncpu; | |
538 | int cpu; | |
539 | ||
082ff5a2 PZ |
540 | struct list_head owner_entry; |
541 | struct task_struct *owner; | |
542 | ||
7b732a75 PZ |
543 | /* mmap bits */ |
544 | struct mutex mmap_mutex; | |
545 | atomic_t mmap_count; | |
546 | struct perf_mmap_data *data; | |
37d81828 | 547 | |
7b732a75 | 548 | /* poll related */ |
0793a61d | 549 | wait_queue_head_t waitq; |
3c446b3d | 550 | struct fasync_struct *fasync; |
79f14641 PZ |
551 | |
552 | /* delayed work for NMIs and such */ | |
553 | int pending_wakeup; | |
4c9e2542 | 554 | int pending_kill; |
79f14641 | 555 | int pending_disable; |
671dec5d | 556 | struct perf_pending_entry pending; |
592903cd | 557 | |
79f14641 PZ |
558 | atomic_t event_limit; |
559 | ||
e077df4f | 560 | void (*destroy)(struct perf_counter *); |
592903cd | 561 | struct rcu_head rcu_head; |
709e50cf PZ |
562 | |
563 | struct pid_namespace *ns; | |
8e5799b1 | 564 | u64 id; |
ee06094f | 565 | #endif |
0793a61d TG |
566 | }; |
567 | ||
568 | /** | |
569 | * struct perf_counter_context - counter context structure | |
570 | * | |
571 | * Used as a container for task counters and CPU counters as well: | |
572 | */ | |
573 | struct perf_counter_context { | |
0793a61d | 574 | /* |
d859e29f PM |
575 | * Protect the states of the counters in the list, |
576 | * nr_active, and the list: | |
0793a61d | 577 | */ |
a308444c | 578 | spinlock_t lock; |
d859e29f PM |
579 | /* |
580 | * Protect the list of counters. Locking either mutex or lock | |
581 | * is sufficient to ensure the list doesn't change; to change | |
582 | * the list you need to lock both the mutex and the spinlock. | |
583 | */ | |
a308444c | 584 | struct mutex mutex; |
04289bb9 | 585 | |
a308444c IM |
586 | struct list_head counter_list; |
587 | struct list_head event_list; | |
588 | int nr_counters; | |
589 | int nr_active; | |
590 | int is_active; | |
591 | atomic_t refcount; | |
592 | struct task_struct *task; | |
53cfbf59 PM |
593 | |
594 | /* | |
4af4998b | 595 | * Context clock, runs when context enabled. |
53cfbf59 | 596 | */ |
a308444c IM |
597 | u64 time; |
598 | u64 timestamp; | |
564c2b21 PM |
599 | |
600 | /* | |
601 | * These fields let us detect when two contexts have both | |
602 | * been cloned (inherited) from a common ancestor. | |
603 | */ | |
a308444c IM |
604 | struct perf_counter_context *parent_ctx; |
605 | u64 parent_gen; | |
606 | u64 generation; | |
607 | int pin_count; | |
608 | struct rcu_head rcu_head; | |
0793a61d TG |
609 | }; |
610 | ||
611 | /** | |
612 | * struct perf_counter_cpu_context - per cpu counter context structure | |
613 | */ | |
614 | struct perf_cpu_context { | |
615 | struct perf_counter_context ctx; | |
616 | struct perf_counter_context *task_ctx; | |
617 | int active_oncpu; | |
618 | int max_pertask; | |
3b6f9e5c | 619 | int exclusive; |
96f6d444 PZ |
620 | |
621 | /* | |
622 | * Recursion avoidance: | |
623 | * | |
624 | * task, softirq, irq, nmi context | |
625 | */ | |
22a4f650 | 626 | int recursion[4]; |
0793a61d TG |
627 | }; |
628 | ||
829b42dd RR |
629 | #ifdef CONFIG_PERF_COUNTERS |
630 | ||
0793a61d TG |
631 | /* |
632 | * Set by architecture code: | |
633 | */ | |
634 | extern int perf_max_counters; | |
635 | ||
4aeb0b42 | 636 | extern const struct pmu *hw_perf_counter_init(struct perf_counter *counter); |
621a01ea | 637 | |
0793a61d | 638 | extern void perf_counter_task_sched_in(struct task_struct *task, int cpu); |
564c2b21 PM |
639 | extern void perf_counter_task_sched_out(struct task_struct *task, |
640 | struct task_struct *next, int cpu); | |
0793a61d | 641 | extern void perf_counter_task_tick(struct task_struct *task, int cpu); |
6ab423e0 | 642 | extern int perf_counter_init_task(struct task_struct *child); |
9b51f66d | 643 | extern void perf_counter_exit_task(struct task_struct *child); |
bbbee908 | 644 | extern void perf_counter_free_task(struct task_struct *task); |
9974458e | 645 | extern void set_perf_counter_pending(void); |
925d519a | 646 | extern void perf_counter_do_pending(void); |
0793a61d | 647 | extern void perf_counter_print_debug(void); |
9e35ad38 PZ |
648 | extern void __perf_disable(void); |
649 | extern bool __perf_enable(void); | |
650 | extern void perf_disable(void); | |
651 | extern void perf_enable(void); | |
1d1c7ddb IM |
652 | extern int perf_counter_task_disable(void); |
653 | extern int perf_counter_task_enable(void); | |
3cbed429 PM |
654 | extern int hw_perf_group_sched_in(struct perf_counter *group_leader, |
655 | struct perf_cpu_context *cpuctx, | |
656 | struct perf_counter_context *ctx, int cpu); | |
37d81828 | 657 | extern void perf_counter_update_userpage(struct perf_counter *counter); |
5c92d124 | 658 | |
df1a132b | 659 | struct perf_sample_data { |
a308444c IM |
660 | struct pt_regs *regs; |
661 | u64 addr; | |
662 | u64 period; | |
df1a132b PZ |
663 | }; |
664 | ||
665 | extern int perf_counter_overflow(struct perf_counter *counter, int nmi, | |
666 | struct perf_sample_data *data); | |
667 | ||
3b6f9e5c PM |
668 | /* |
669 | * Return 1 for a software counter, 0 for a hardware counter | |
670 | */ | |
671 | static inline int is_software_counter(struct perf_counter *counter) | |
672 | { | |
a21ca2ca | 673 | return (counter->attr.type != PERF_TYPE_RAW) && |
f1a3c979 PZ |
674 | (counter->attr.type != PERF_TYPE_HARDWARE) && |
675 | (counter->attr.type != PERF_TYPE_HW_CACHE); | |
3b6f9e5c PM |
676 | } |
677 | ||
f29ac756 PZ |
678 | extern atomic_t perf_swcounter_enabled[PERF_COUNT_SW_MAX]; |
679 | ||
680 | extern void __perf_swcounter_event(u32, u64, int, struct pt_regs *, u64); | |
681 | ||
682 | static inline void | |
683 | perf_swcounter_event(u32 event, u64 nr, int nmi, struct pt_regs *regs, u64 addr) | |
684 | { | |
685 | if (atomic_read(&perf_swcounter_enabled[event])) | |
686 | __perf_swcounter_event(event, nr, nmi, regs, addr); | |
687 | } | |
15dbf27c | 688 | |
089dd79d PZ |
689 | extern void __perf_counter_mmap(struct vm_area_struct *vma); |
690 | ||
691 | static inline void perf_counter_mmap(struct vm_area_struct *vma) | |
692 | { | |
693 | if (vma->vm_flags & VM_EXEC) | |
694 | __perf_counter_mmap(vma); | |
695 | } | |
0a4a9391 | 696 | |
8d1b2d93 | 697 | extern void perf_counter_comm(struct task_struct *tsk); |
60313ebe | 698 | extern void perf_counter_fork(struct task_struct *tsk); |
8d1b2d93 | 699 | |
394ee076 PZ |
700 | extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); |
701 | ||
0764771d | 702 | extern int sysctl_perf_counter_paranoid; |
c5078f78 | 703 | extern int sysctl_perf_counter_mlock; |
df58ab24 | 704 | extern int sysctl_perf_counter_sample_rate; |
1ccd1549 | 705 | |
0d905bca IM |
706 | extern void perf_counter_init(void); |
707 | ||
9d23a90a PM |
708 | #ifndef perf_misc_flags |
709 | #define perf_misc_flags(regs) (user_mode(regs) ? PERF_EVENT_MISC_USER : \ | |
710 | PERF_EVENT_MISC_KERNEL) | |
711 | #define perf_instruction_pointer(regs) instruction_pointer(regs) | |
712 | #endif | |
713 | ||
0793a61d TG |
714 | #else |
715 | static inline void | |
716 | perf_counter_task_sched_in(struct task_struct *task, int cpu) { } | |
717 | static inline void | |
910431c7 IM |
718 | perf_counter_task_sched_out(struct task_struct *task, |
719 | struct task_struct *next, int cpu) { } | |
0793a61d TG |
720 | static inline void |
721 | perf_counter_task_tick(struct task_struct *task, int cpu) { } | |
d3e78ee3 | 722 | static inline int perf_counter_init_task(struct task_struct *child) { return 0; } |
9b51f66d | 723 | static inline void perf_counter_exit_task(struct task_struct *child) { } |
bbbee908 | 724 | static inline void perf_counter_free_task(struct task_struct *task) { } |
925d519a | 725 | static inline void perf_counter_do_pending(void) { } |
0793a61d | 726 | static inline void perf_counter_print_debug(void) { } |
9e35ad38 PZ |
727 | static inline void perf_disable(void) { } |
728 | static inline void perf_enable(void) { } | |
1d1c7ddb IM |
729 | static inline int perf_counter_task_disable(void) { return -EINVAL; } |
730 | static inline int perf_counter_task_enable(void) { return -EINVAL; } | |
15dbf27c | 731 | |
925d519a | 732 | static inline void |
78f13e95 PZ |
733 | perf_swcounter_event(u32 event, u64 nr, int nmi, |
734 | struct pt_regs *regs, u64 addr) { } | |
0a4a9391 | 735 | |
089dd79d | 736 | static inline void perf_counter_mmap(struct vm_area_struct *vma) { } |
8d1b2d93 | 737 | static inline void perf_counter_comm(struct task_struct *tsk) { } |
60313ebe | 738 | static inline void perf_counter_fork(struct task_struct *tsk) { } |
0d905bca | 739 | static inline void perf_counter_init(void) { } |
0793a61d TG |
740 | #endif |
741 | ||
f3dfd265 | 742 | #endif /* __KERNEL__ */ |
0793a61d | 743 | #endif /* _LINUX_PERF_COUNTER_H */ |