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1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
4352dfd5
GKH		 20/* Include the pci register defines */
21#include <linux/pci_regs.h>
1da177e4 22
1da177e4
LT		 23/*
24 * The PCI interface treats multi-function devices as independent
25 * devices. The slot/function address of each device is encoded
26 * in a single byte as follows:
27 *
28 * 7:3 = slot
29 * 2:0 = function
30 */
31#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
32#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
33#define PCI_FUNC(devfn) ((devfn) & 0x07)
34
35/* Ioctls for /proc/bus/pci/X/Y nodes. */
36#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
37#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
38#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
39#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
40#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
41
42#ifdef __KERNEL__
43
778382e0
DW		 44#include <linux/mod_devicetable.h>
45
1da177e4 46#include <linux/types.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
bae94d02 51#include <asm/atomic.h>
1da177e4
LT		 52#include <linux/device.h>
53
7e7a43c3
AB		 54/* Include the ID list */
55#include <linux/pci_ids.h>
56
1da177e4
LT		 57/* File state for mmap()s on /proc/bus/pci/X/Y */
58enum pci_mmap_state {
59 pci_mmap_io,
60 pci_mmap_mem
61};
62
63/* This defines the direction arg to the DMA mapping routines. */
64#define PCI_DMA_BIDIRECTIONAL 0
65#define PCI_DMA_TODEVICE 1
66#define PCI_DMA_FROMDEVICE 2
67#define PCI_DMA_NONE 3
68
69#define DEVICE_COUNT_COMPATIBLE 4
70#define DEVICE_COUNT_RESOURCE 12
71
72typedef int __bitwise pci_power_t;
73
4352dfd5
GKH		 74#define PCI_D0 ((pci_power_t __force) 0)
75#define PCI_D1 ((pci_power_t __force) 1)
76#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 77#define PCI_D3hot ((pci_power_t __force) 3)
78#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 79#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 80#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 81
392a1ce7
LV		 82/** The pci_channel state describes connectivity between the CPU and
83 * the pci device. If some PCI bus between here and the pci device
84 * has crashed or locked up, this info is reflected here.
85 */
86typedef unsigned int __bitwise pci_channel_state_t;
87
88enum pci_channel_state {
89 /* I/O channel is in normal state */
90 pci_channel_io_normal = (__force pci_channel_state_t) 1,
91
92 /* I/O to channel is blocked */
93 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
94
95 /* PCI card is dead */
96 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
97};
98
6e325a62
MT		 99typedef unsigned short __bitwise pci_bus_flags_t;
100enum pci_bus_flags {
e778272d 101 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
6e325a62
MT		 102};
103
41017f0c
SL		 104struct pci_cap_saved_state {
105 struct hlist_node next;
106 char cap_nr;
107 u32 data[0];
108};
109
1da177e4
LT		 110/*
111 * The pci_dev structure is used to describe PCI devices.
112 */
113struct pci_dev {
114 struct list_head global_list; /* node in list of all PCI devices */
115 struct list_head bus_list; /* node in per-bus list */
116 struct pci_bus *bus; /* bus this device is on */
117 struct pci_bus *subordinate; /* bus this device bridges to */
118
119 void *sysdata; /* hook for sys-specific extension */
120 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
121
122 unsigned int devfn; /* encoded device & function index */
123 unsigned short vendor;
124 unsigned short device;
125 unsigned short subsystem_vendor;
126 unsigned short subsystem_device;
127 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
128 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
129 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 130 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 131
132 struct pci_driver *driver; /* which driver has allocated this device */
133 u64 dma_mask; /* Mask of the bits of bus address this
134 device implements. Normally this is
135 0xffffffff. You only need to change
136 this if your device has broken DMA
137 or supports 64-bit transfers. */
138
139 pci_power_t current_state; /* Current operating state. In ACPI-speak,
140 this is D0-D3, D0 being fully functional,
141 and D3 being off. */
142
392a1ce7 143 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 144 struct device dev; /* Generic device interface */
145
146 /* device is compatible with these IDs */
147 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
148 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
149
150 int cfg_size; /* Size of configuration space */
151
152 /*
153 * Instead of touching interrupt line and base address registers
154 * directly, use the values stored here. They might be different!
155 */
156 unsigned int irq;
157 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
158
159 /* These fields are used by common fixups */
160 unsigned int transparent:1; /* Transparent PCI bridge */
161 unsigned int multifunction:1;/* Part of multi-function device */
162 /* keep track of device state */
1da177e4 163 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 164 unsigned int no_msi:1; /* device may not use msi */
ffadcc2f 165 unsigned int no_d1d2:1; /* only allow d0 or d3 */
e04b0ea2 166 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
bd8481e1 167 unsigned int broken_parity_status:1; /* Device generates false positive parity */
99dc804d
SL		 168 unsigned int msi_enabled:1;
169 unsigned int msix_enabled:1;
bae94d02 170 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 171
1da177e4 172 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 173 struct hlist_head saved_cap_space;
1da177e4
LT		 174 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
175 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
176 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
1da177e4
LT		 177};
178
179#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
180#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
181#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
182#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
183
41017f0c
SL		 184static inline struct pci_cap_saved_state *pci_find_saved_cap(
185 struct pci_dev *pci_dev,char cap)
186{
187 struct pci_cap_saved_state *tmp;
188 struct hlist_node *pos;
189
190 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
191 if (tmp->cap_nr == cap)
192 return tmp;
193 }
194 return NULL;
195}
196
197static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
198 struct pci_cap_saved_state *new_cap)
199{
200 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
201}
202
203static inline void pci_remove_saved_cap(struct pci_cap_saved_state *cap)
204{
205 hlist_del(&cap->next);
206}
207
1da177e4
LT		 208/*
209 * For PCI devices, the region numbers are assigned this way:
210 *
211 * 0-5 standard PCI regions
212 * 6 expansion ROM
213 * 7-10 bridges: address space assigned to buses behind the bridge
214 */
215
4352dfd5
GKH		 216#define PCI_ROM_RESOURCE 6
217#define PCI_BRIDGE_RESOURCES 7
218#define PCI_NUM_RESOURCES 11
1da177e4
LT		 219
220#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 221#define PCI_BUS_NUM_RESOURCES 8
1da177e4 222#endif
4352dfd5
GKH		 223
224#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 225
226struct pci_bus {
227 struct list_head node; /* node in list of buses */
228 struct pci_bus *parent; /* parent bus this bridge is on */
229 struct list_head children; /* list of child buses */
230 struct list_head devices; /* list of devices on this bus */
231 struct pci_dev *self; /* bridge device as seen by parent */
232 struct resource *resource[PCI_BUS_NUM_RESOURCES];
233 /* address space routed to this bus */
234
235 struct pci_ops *ops; /* configuration access functions */
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
238
239 unsigned char number; /* bus number */
240 unsigned char primary; /* number of primary bridge */
241 unsigned char secondary; /* number of secondary bridge */
242 unsigned char subordinate; /* max number of subordinate buses */
243
244 char name[48];
245
246 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 247 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4
LT		 248 struct device *bridge;
249 struct class_device class_dev;
250 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
251 struct bin_attribute *legacy_mem; /* legacy mem */
252};
253
254#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
255#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
256
257/*
258 * Error values that may be returned by PCI functions.
259 */
260#define PCIBIOS_SUCCESSFUL 0x00
261#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
262#define PCIBIOS_BAD_VENDOR_ID 0x83
263#define PCIBIOS_DEVICE_NOT_FOUND 0x86
264#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
265#define PCIBIOS_SET_FAILED 0x88
266#define PCIBIOS_BUFFER_TOO_SMALL 0x89
267
268/* Low-level architecture-dependent routines */
269
270struct pci_ops {
271 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
272 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
273};
274
275struct pci_raw_ops {
276 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
277 int reg, int len, u32 *val);
278 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
279 int reg, int len, u32 val);
280};
281
282extern struct pci_raw_ops *raw_pci_ops;
283
284struct pci_bus_region {
285 unsigned long start;
286 unsigned long end;
287};
288
289struct pci_dynids {
290 spinlock_t lock; /* protects list, index */
291 struct list_head list; /* for IDs added at runtime */
292 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
293};
294
392a1ce7
LV		 295/* ---------------------------------------------------------------- */
296/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
297 * a set fof callbacks in struct pci_error_handlers, then that device driver
298 * will be notified of PCI bus errors, and will be driven to recovery
299 * when an error occurs.
300 */
301
302typedef unsigned int __bitwise pci_ers_result_t;
303
304enum pci_ers_result {
305 /* no result/none/not supported in device driver */
306 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
307
308 /* Device driver can recover without slot reset */
309 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
310
311 /* Device driver wants slot to be reset. */
312 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
313
314 /* Device has completely failed, is unrecoverable */
315 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
316
317 /* Device driver is fully recovered and operational */
318 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
319};
320
321/* PCI bus error event callbacks */
322struct pci_error_handlers
323{
324 /* PCI bus error detected on this device */
325 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
326 enum pci_channel_state error);
327
328 /* MMIO has been re-enabled, but not DMA */
329 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
330
331 /* PCI Express link has been reset */
332 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
333
334 /* PCI slot has been reset */
335 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
336
337 /* Device driver may resume normal operations */
338 void (*resume)(struct pci_dev *dev);
339};
340
341/* ---------------------------------------------------------------- */
342
1da177e4
LT		 343struct module;
344struct pci_driver {
345 struct list_head node;
346 char *name;
1da177e4
LT		 347 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
348 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
349 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
350 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 351 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
352 int (*resume_early) (struct pci_dev *dev);
1da177e4 353 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 354 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 355 void (*shutdown) (struct pci_dev *dev);
1da177e4 356
392a1ce7 357 struct pci_error_handlers *err_handler;
1da177e4
LT		 358 struct device_driver driver;
359 struct pci_dynids dynids;
50b00755
AC		 360
361 int multithread_probe;
1da177e4
LT		 362};
363
364#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
365
366/**
367 * PCI_DEVICE - macro used to describe a specific pci device
368 * @vend: the 16 bit PCI Vendor ID
369 * @dev: the 16 bit PCI Device ID
370 *
371 * This macro is used to create a struct pci_device_id that matches a
372 * specific device. The subvendor and subdevice fields will be set to
373 * PCI_ANY_ID.
374 */
375#define PCI_DEVICE(vend,dev) \
376 .vendor = (vend), .device = (dev), \
377 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
378
379/**
380 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
381 * @dev_class: the class, subclass, prog-if triple for this device
382 * @dev_class_mask: the class mask for this device
383 *
384 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 385 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 386 * fields will be set to PCI_ANY_ID.
387 */
388#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
389 .class = (dev_class), .class_mask = (dev_class_mask), \
390 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
391 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
392
4352dfd5 393/*
1da177e4
LT		 394 * pci_module_init is obsolete, this stays here till we fix up all usages of it
395 * in the tree.
396 */
397#define pci_module_init pci_register_driver
398
1597cacb
AC		 399/**
400 * PCI_VDEVICE - macro used to describe a specific pci device in short form
401 * @vend: the vendor name
402 * @dev: the 16 bit PCI Device ID
403 *
404 * This macro is used to create a struct pci_device_id that matches a
405 * specific PCI device. The subvendor, and subdevice fields will be set
406 * to PCI_ANY_ID. The macro allows the next field to follow as the device
407 * private data.
408 */
409
410#define PCI_VDEVICE(vendor, device) \
411 PCI_VENDOR_ID_##vendor, (device), \
412 PCI_ANY_ID, PCI_ANY_ID, 0, 0
413
1da177e4
LT		 414/* these external functions are only available when PCI support is enabled */
415#ifdef CONFIG_PCI
416
417extern struct bus_type pci_bus_type;
418
419/* Do NOT directly access these two variables, unless you are arch specific pci
420 * code, or pci core code. */
421extern struct list_head pci_root_buses; /* list of all known PCI buses */
422extern struct list_head pci_devices; /* list of all devices */
423
424void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 425int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1da177e4
LT		 426char *pcibios_setup (char *str);
427
428/* Used only when drivers/pci/setup.c is used */
e31dd6e4
GKH		 429void pcibios_align_resource(void *, struct resource *, resource_size_t,
430 resource_size_t);
1da177e4
LT		 431void pcibios_update_irq(struct pci_dev *, int irq);
432
433/* Generic PCI functions used internally */
434
435extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 436void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 437struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
438static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
439{
c431ada4
RS		 440 struct pci_bus *root_bus;
441 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
442 if (root_bus)
443 pci_bus_add_devices(root_bus);
444 return root_bus;
1da177e4 445}
cdb9b9f7
PM		 446struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
447struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
1da177e4
LT		 448int pci_scan_slot(struct pci_bus *bus, int devfn);
449struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 450void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 451unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 452int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 453void pci_read_bridge_bases(struct pci_bus *child);
454struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
455int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
456extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
457extern void pci_dev_put(struct pci_dev *dev);
458extern void pci_remove_bus(struct pci_bus *b);
459extern void pci_remove_bus_device(struct pci_dev *dev);
24f8aa9b 460extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 461void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 462extern void pci_sort_breadthfirst(void);
1da177e4
LT		 463
464/* Generic PCI functions exported to card drivers */
465
466struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
467struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
468struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
469int pci_find_capability (struct pci_dev *dev, int cap);
24a4e377 470int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
3a720d72 471int pci_find_ext_capability (struct pci_dev *dev, int cap);
687d5fe3
ME		 472int pci_find_ht_capability (struct pci_dev *dev, int ht_cap);
473int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 474struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 475
d42552c3
AM		 476struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
477 struct pci_dev *from);
478struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
479 struct pci_dev *from);
480
1da177e4
LT		 481struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
482 unsigned int ss_vendor, unsigned int ss_device,
483 struct pci_dev *from);
484struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
29f3eb64 485struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
1da177e4
LT		 486struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
487int pci_dev_present(const struct pci_device_id *ids);
d86f90f9 488const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
1da177e4
LT		 489
490int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
491int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
492int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
493int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
494int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
495int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
496
497static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
498{
499 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
500}
501static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
502{
503 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
504}
505static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
506{
507 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
508}
509static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
510{
511 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
512}
513static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
514{
515 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
516}
517static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
518{
519 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
520}
521
4a7fb636
AM		 522int __must_check pci_enable_device(struct pci_dev *dev);
523int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
1da177e4
LT		 524void pci_disable_device(struct pci_dev *dev);
525void pci_set_master(struct pci_dev *dev);
526#define HAVE_PCI_SET_MWI
4a7fb636 527int __must_check pci_set_mwi(struct pci_dev *dev);
1da177e4 528void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 529void pci_intx(struct pci_dev *dev, int enable);
9c8550ee
LT		 530int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
531int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 532void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
4a7fb636
AM		 533int __must_check pci_assign_resource(struct pci_dev *dev, int i);
534int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
064b53db 535void pci_restore_bars(struct pci_dev *dev);
1da177e4
LT		 536
537/* ROM control related routines */
144a50ea
DJ		 538void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
539void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 540void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
541void pci_remove_rom(struct pci_dev *pdev);
542
543/* Power management related routines */
544int pci_save_state(struct pci_dev *dev);
545int pci_restore_state(struct pci_dev *dev);
9c8550ee
LT		 546int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
547pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
548int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 549
550/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
551void pci_bus_assign_resources(struct pci_bus *bus);
552void pci_bus_size_bridges(struct pci_bus *bus);
553int pci_claim_resource(struct pci_dev *, int);
554void pci_assign_unassigned_resources(void);
555void pdev_enable_device(struct pci_dev *);
556void pdev_sort_resources(struct pci_dev *, struct resource_list *);
557void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
558 int (*)(struct pci_dev *, u8, u8));
559#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 560int __must_check pci_request_regions(struct pci_dev *, const char *);
1da177e4 561void pci_release_regions(struct pci_dev *);
4a7fb636 562int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4
LT		 563void pci_release_region(struct pci_dev *, int);
564
565/* drivers/pci/bus.c */
4a7fb636
AM		 566int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
567 struct resource *res, resource_size_t size,
568 resource_size_t align, resource_size_t min,
569 unsigned int type_mask,
570 void (*alignf)(void *, struct resource *,
571 resource_size_t, resource_size_t),
572 void *alignf_data);
1da177e4
LT		 573void pci_enable_bridges(struct pci_bus *bus);
574
863b18f4 575/* Proper probing supporting hot-pluggable devices */
4a7fb636
AM		 576int __must_check __pci_register_driver(struct pci_driver *, struct module *);
577static inline int __must_check pci_register_driver(struct pci_driver *driver)
863b18f4
L		 578{
579 return __pci_register_driver(driver, THIS_MODULE);
580}
581
1da177e4
LT		 582void pci_unregister_driver(struct pci_driver *);
583void pci_remove_behind_bridge(struct pci_dev *);
584struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 585const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
586const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 587int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
588
cecf4864
PM		 589void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
590 void *userdata);
ac7dc65a 591int pci_cfg_space_size(struct pci_dev *dev);
b82db5ce 592unsigned char pci_bus_max_busnr(struct pci_bus* bus);
cecf4864 593
1da177e4
LT		 594/* kmem_cache style wrapper around pci_alloc_consistent() */
595
596#include <linux/dmapool.h>
597
598#define pci_pool dma_pool
599#define pci_pool_create(name, pdev, size, align, allocation) \
600 dma_pool_create(name, &pdev->dev, size, align, allocation)
601#define pci_pool_destroy(pool) dma_pool_destroy(pool)
602#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
603#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
604
e24c2d96
DM		 605enum pci_dma_burst_strategy {
606 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
607 strategy_parameter is N/A */
608 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
609 byte boundaries */
610 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
611 strategy_parameter byte boundaries */
612};
613
1da177e4
LT		 614#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
615extern struct pci_dev *isa_bridge;
616#endif
617
618struct msix_entry {
619 u16 vector; /* kernel uses to write allocated vector */
620 u16 entry; /* driver uses to specify entry, OS writes */
621};
622
0366f8f7 623
1da177e4
LT		 624#ifndef CONFIG_PCI_MSI
625static inline void pci_scan_msi_device(struct pci_dev *dev) {}
626static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
627static inline void pci_disable_msi(struct pci_dev *dev) {}
628static inline int pci_enable_msix(struct pci_dev* dev,
629 struct msix_entry *entries, int nvec) {return -1;}
630static inline void pci_disable_msix(struct pci_dev *dev) {}
631static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
632#else
633extern void pci_scan_msi_device(struct pci_dev *dev);
634extern int pci_enable_msi(struct pci_dev *dev);
635extern void pci_disable_msi(struct pci_dev *dev);
636extern int pci_enable_msix(struct pci_dev* dev,
637 struct msix_entry *entries, int nvec);
638extern void pci_disable_msix(struct pci_dev *dev);
639extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
640#endif
641
8b955b0d 642#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 643/* The functions a driver should call */
644int ht_create_irq(struct pci_dev *dev, int idx);
645void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 646#endif /* CONFIG_HT_IRQ */
647
e04b0ea2
BK		 648extern void pci_block_user_cfg_access(struct pci_dev *dev);
649extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
650
4352dfd5
GKH		 651/*
652 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
653 * a PCI domain is defined to be a set of PCI busses which share
654 * configuration space.
655 */
656#ifndef CONFIG_PCI_DOMAINS
657static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
658static inline int pci_proc_domain(struct pci_bus *bus)
659{
660 return 0;
661}
662#endif
1da177e4 663
4352dfd5 664#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 665
666/*
667 * If the system does not have PCI, clearly these return errors. Define
668 * these as simple inline functions to avoid hair in drivers.
669 */
670
1da177e4
LT		 671#define _PCI_NOP(o,s,t) \
672 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
673 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
674#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
675 _PCI_NOP(o,word,u16 x) \
676 _PCI_NOP(o,dword,u32 x)
677_PCI_NOP_ALL(read, *)
678_PCI_NOP_ALL(write,)
679
680static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
681{ return NULL; }
682
683static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
684{ return NULL; }
685
d42552c3
AM		 686static inline struct pci_dev *pci_get_device(unsigned int vendor,
687 unsigned int device, struct pci_dev *from)
688{ return NULL; }
689
690static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
691 unsigned int device, struct pci_dev *from)
1da177e4
LT		 692{ return NULL; }
693
694static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
695unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
696{ return NULL; }
697
698static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
699{ return NULL; }
700
701#define pci_dev_present(ids) (0)
d86f90f9 702#define pci_find_present(ids) (NULL)
1da177e4
LT		 703#define pci_dev_put(dev) do { } while (0)
704
705static inline void pci_set_master(struct pci_dev *dev) { }
706static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
707static inline void pci_disable_device(struct pci_dev *dev) { }
708static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4 709static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
863b18f4 710static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
1da177e4
LT		 711static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
712static inline void pci_unregister_driver(struct pci_driver *drv) { }
713static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
24a4e377 714static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
3a720d72 715static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
1da177e4
LT		 716static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
717
718/* Power management related routines */
719static inline int pci_save_state(struct pci_dev *dev) { return 0; }
720static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
721static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 722static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 723static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
724
725#define isa_bridge ((struct pci_dev *)NULL)
726
a46e8126
KG		 727#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
728
e04b0ea2
BK		 729static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
730static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
731
4352dfd5 732#endif /* CONFIG_PCI */
1da177e4 733
4352dfd5
GKH		 734/* Include architecture-dependent settings and functions */
735
736#include <asm/pci.h>
1da177e4
LT		 737
738/* these helpers provide future and backwards compatibility
739 * for accessing popular PCI BAR info */
740#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
741#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
742#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
743#define pci_resource_len(dev,bar) \
744 ((pci_resource_start((dev),(bar)) == 0 && \
745 pci_resource_end((dev),(bar)) == \
746 pci_resource_start((dev),(bar))) ? 0 : \
747 \
748 (pci_resource_end((dev),(bar)) - \
749 pci_resource_start((dev),(bar)) + 1))
750
751/* Similar to the helpers above, these manipulate per-pci_dev
752 * driver-specific data. They are really just a wrapper around
753 * the generic device structure functions of these calls.
754 */
755static inline void *pci_get_drvdata (struct pci_dev *pdev)
756{
757 return dev_get_drvdata(&pdev->dev);
758}
759
760static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
761{
762 dev_set_drvdata(&pdev->dev, data);
763}
764
765/* If you want to know what to call your pci_dev, ask this function.
766 * Again, it's a wrapper around the generic device.
767 */
768static inline char *pci_name(struct pci_dev *pdev)
769{
770 return pdev->dev.bus_id;
771}
772
2311b1f2
ME		 773
774/* Some archs don't want to expose struct resource to userland as-is
775 * in sysfs and /proc
776 */
777#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
778static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
e31dd6e4
GKH		 779 const struct resource *rsrc, resource_size_t *start,
780 resource_size_t *end)
2311b1f2
ME		 781{
782 *start = rsrc->start;
783 *end = rsrc->end;
784}
785#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
786
787
1da177e4
LT		 788/*
789 * The world is not perfect and supplies us with broken PCI devices.
790 * For at least a part of these bugs we need a work-around, so both
791 * generic (drivers/pci/quirks.c) and per-architecture code can define
792 * fixup hooks to be called for particular buggy devices.
793 */
794
795struct pci_fixup {
796 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
797 void (*hook)(struct pci_dev *dev);
798};
799
800enum pci_fixup_pass {
801 pci_fixup_early, /* Before probing BARs */
802 pci_fixup_header, /* After reading configuration header */
803 pci_fixup_final, /* Final phase of device fixups */
804 pci_fixup_enable, /* pci_enable_device() time */
1597cacb 805 pci_fixup_resume, /* pci_enable_device() time */
1da177e4
LT		 806};
807
808/* Anonymous variables would be nice... */
809#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 810 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 811 __attribute__((__section__(#section))) = { vendor, device, hook };
812#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
813 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
814 vendor##device##hook, vendor, device, hook)
815#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
816 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
817 vendor##device##hook, vendor, device, hook)
818#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
820 vendor##device##hook, vendor, device, hook)
821#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
822 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
823 vendor##device##hook, vendor, device, hook)
1597cacb
AC		 824#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
825 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
826 resume##vendor##device##hook, vendor, device, hook)
1da177e4
LT		 827
828
829void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
830
831extern int pci_pci_problems;
236561e5 832#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 833#define PCIPCI_TRITON 2
834#define PCIPCI_NATOMA 4
835#define PCIPCI_VIAETBF 8
836#define PCIPCI_VSFX 16
236561e5
AC		 837#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
838#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4
LT		 839
840#endif /* __KERNEL__ */
841#endif /* LINUX_PCI_H */
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