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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
f46753c5 | 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
1da177e4 | 21 | |
1da177e4 LT |
22 | /* |
23 | * The PCI interface treats multi-function devices as independent | |
24 | * devices. The slot/function address of each device is encoded | |
25 | * in a single byte as follows: | |
26 | * | |
27 | * 7:3 = slot | |
28 | * 2:0 = function | |
29 | */ | |
05cca6e5 | 30 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
31 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
32 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
33 | ||
34 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
35 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
36 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
37 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
38 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
39 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
40 | ||
41 | #ifdef __KERNEL__ | |
42 | ||
778382e0 DW |
43 | #include <linux/mod_devicetable.h> |
44 | ||
1da177e4 | 45 | #include <linux/types.h> |
98db6f19 | 46 | #include <linux/init.h> |
1da177e4 LT |
47 | #include <linux/ioport.h> |
48 | #include <linux/list.h> | |
4a7fb636 | 49 | #include <linux/compiler.h> |
1da177e4 | 50 | #include <linux/errno.h> |
f46753c5 | 51 | #include <linux/kobject.h> |
bae94d02 | 52 | #include <asm/atomic.h> |
1da177e4 | 53 | #include <linux/device.h> |
1388cc96 | 54 | #include <linux/io.h> |
74bb1bcc | 55 | #include <linux/irqreturn.h> |
1da177e4 | 56 | |
7e7a43c3 AB |
57 | /* Include the ID list */ |
58 | #include <linux/pci_ids.h> | |
59 | ||
f46753c5 AC |
60 | /* pci_slot represents a physical slot */ |
61 | struct pci_slot { | |
62 | struct pci_bus *bus; /* The bus this slot is on */ | |
63 | struct list_head list; /* node in list of slots on this bus */ | |
64 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
65 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
66 | struct kobject kobj; | |
67 | }; | |
68 | ||
0ad772ec AC |
69 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
70 | { | |
71 | return kobject_name(&slot->kobj); | |
72 | } | |
73 | ||
1da177e4 LT |
74 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
75 | enum pci_mmap_state { | |
76 | pci_mmap_io, | |
77 | pci_mmap_mem | |
78 | }; | |
79 | ||
80 | /* This defines the direction arg to the DMA mapping routines. */ | |
81 | #define PCI_DMA_BIDIRECTIONAL 0 | |
82 | #define PCI_DMA_TODEVICE 1 | |
83 | #define PCI_DMA_FROMDEVICE 2 | |
84 | #define PCI_DMA_NONE 3 | |
85 | ||
fde09c6d YZ |
86 | /* |
87 | * For PCI devices, the region numbers are assigned this way: | |
88 | */ | |
89 | enum { | |
90 | /* #0-5: standard PCI resources */ | |
91 | PCI_STD_RESOURCES, | |
92 | PCI_STD_RESOURCE_END = 5, | |
93 | ||
94 | /* #6: expansion ROM resource */ | |
95 | PCI_ROM_RESOURCE, | |
96 | ||
d1b054da YZ |
97 | /* device specific resources */ |
98 | #ifdef CONFIG_PCI_IOV | |
99 | PCI_IOV_RESOURCES, | |
100 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
101 | #endif | |
102 | ||
fde09c6d YZ |
103 | /* resources assigned to buses behind the bridge */ |
104 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
105 | ||
106 | PCI_BRIDGE_RESOURCES, | |
107 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
108 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
109 | ||
110 | /* total resources associated with a PCI device */ | |
111 | PCI_NUM_RESOURCES, | |
112 | ||
113 | /* preserve this for compatibility */ | |
114 | DEVICE_COUNT_RESOURCE | |
115 | }; | |
1da177e4 LT |
116 | |
117 | typedef int __bitwise pci_power_t; | |
118 | ||
4352dfd5 GKH |
119 | #define PCI_D0 ((pci_power_t __force) 0) |
120 | #define PCI_D1 ((pci_power_t __force) 1) | |
121 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
122 | #define PCI_D3hot ((pci_power_t __force) 3) |
123 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 124 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 125 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 126 | |
00240c38 AS |
127 | /* Remember to update this when the list above changes! */ |
128 | extern const char *pci_power_names[]; | |
129 | ||
130 | static inline const char *pci_power_name(pci_power_t state) | |
131 | { | |
132 | return pci_power_names[1 + (int) state]; | |
133 | } | |
134 | ||
aa8c6c93 RW |
135 | #define PCI_PM_D2_DELAY 200 |
136 | #define PCI_PM_D3_WAIT 10 | |
137 | #define PCI_PM_BUS_WAIT 50 | |
138 | ||
392a1ce7 LV |
139 | /** The pci_channel state describes connectivity between the CPU and |
140 | * the pci device. If some PCI bus between here and the pci device | |
141 | * has crashed or locked up, this info is reflected here. | |
142 | */ | |
143 | typedef unsigned int __bitwise pci_channel_state_t; | |
144 | ||
145 | enum pci_channel_state { | |
146 | /* I/O channel is in normal state */ | |
147 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
148 | ||
149 | /* I/O to channel is blocked */ | |
150 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
151 | ||
152 | /* PCI card is dead */ | |
153 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
154 | }; | |
155 | ||
f7bdd12d BK |
156 | typedef unsigned int __bitwise pcie_reset_state_t; |
157 | ||
158 | enum pcie_reset_state { | |
159 | /* Reset is NOT asserted (Use to deassert reset) */ | |
160 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
161 | ||
162 | /* Use #PERST to reset PCI-E device */ | |
163 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
164 | ||
165 | /* Use PCI-E Hot Reset to reset device */ | |
166 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
167 | }; | |
168 | ||
ba698ad4 DM |
169 | typedef unsigned short __bitwise pci_dev_flags_t; |
170 | enum pci_dev_flags { | |
171 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
172 | * generation too. | |
173 | */ | |
174 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
979b1791 AC |
175 | /* Device configuration is irrevocably lost if disabled into D3 */ |
176 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, | |
ba698ad4 DM |
177 | }; |
178 | ||
e1d3a908 SA |
179 | enum pci_irq_reroute_variant { |
180 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
181 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
182 | }; | |
183 | ||
6e325a62 MT |
184 | typedef unsigned short __bitwise pci_bus_flags_t; |
185 | enum pci_bus_flags { | |
d556ad4b PO |
186 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
187 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
188 | }; |
189 | ||
41017f0c SL |
190 | struct pci_cap_saved_state { |
191 | struct hlist_node next; | |
192 | char cap_nr; | |
193 | u32 data[0]; | |
194 | }; | |
195 | ||
7d715a6c | 196 | struct pcie_link_state; |
ee69439c | 197 | struct pci_vpd; |
d1b054da | 198 | struct pci_sriov; |
302b4215 | 199 | struct pci_ats; |
ee69439c | 200 | |
1da177e4 LT |
201 | /* |
202 | * The pci_dev structure is used to describe PCI devices. | |
203 | */ | |
204 | struct pci_dev { | |
1da177e4 LT |
205 | struct list_head bus_list; /* node in per-bus list */ |
206 | struct pci_bus *bus; /* bus this device is on */ | |
207 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
208 | ||
209 | void *sysdata; /* hook for sys-specific extension */ | |
210 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 211 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
212 | |
213 | unsigned int devfn; /* encoded device & function index */ | |
214 | unsigned short vendor; | |
215 | unsigned short device; | |
216 | unsigned short subsystem_vendor; | |
217 | unsigned short subsystem_device; | |
218 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 219 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 220 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
994a65e2 | 221 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 222 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 223 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
224 | |
225 | struct pci_driver *driver; /* which driver has allocated this device */ | |
226 | u64 dma_mask; /* Mask of the bits of bus address this | |
227 | device implements. Normally this is | |
228 | 0xffffffff. You only need to change | |
229 | this if your device has broken DMA | |
230 | or supports 64-bit transfers. */ | |
231 | ||
4d57cdfa FT |
232 | struct device_dma_parameters dma_parms; |
233 | ||
1da177e4 LT |
234 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
235 | this is D0-D3, D0 being fully functional, | |
236 | and D3 being off. */ | |
337001b6 RW |
237 | int pm_cap; /* PM capability offset in the |
238 | configuration space */ | |
239 | unsigned int pme_support:5; /* Bitmask of states from which PME# | |
240 | can be generated */ | |
241 | unsigned int d1_support:1; /* Low power state D1 is supported */ | |
242 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
243 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ | |
1da177e4 | 244 | |
7d715a6c SL |
245 | #ifdef CONFIG_PCIEASPM |
246 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
247 | #endif | |
248 | ||
392a1ce7 | 249 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
250 | struct device dev; /* Generic device interface */ |
251 | ||
1da177e4 LT |
252 | int cfg_size; /* Size of configuration space */ |
253 | ||
254 | /* | |
255 | * Instead of touching interrupt line and base address registers | |
256 | * directly, use the values stored here. They might be different! | |
257 | */ | |
258 | unsigned int irq; | |
259 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
260 | ||
261 | /* These fields are used by common fixups */ | |
262 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
263 | unsigned int multifunction:1;/* Part of multi-function device */ | |
264 | /* keep track of device state */ | |
8a1bc901 | 265 | unsigned int is_added:1; |
1da177e4 | 266 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 267 | unsigned int no_msi:1; /* device may not use msi */ |
e04b0ea2 | 268 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 269 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 270 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
99dc804d SL |
271 | unsigned int msi_enabled:1; |
272 | unsigned int msix_enabled:1; | |
58c3a727 | 273 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 274 | unsigned int is_managed:1; |
994a65e2 | 275 | unsigned int is_pcie:1; |
aa8c6c93 | 276 | unsigned int state_saved:1; |
d1b054da | 277 | unsigned int is_physfn:1; |
dd7cc44d | 278 | unsigned int is_virtfn:1; |
711d5779 | 279 | unsigned int reset_fn:1; |
ba698ad4 | 280 | pci_dev_flags_t dev_flags; |
bae94d02 | 281 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 282 | |
1da177e4 | 283 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 284 | struct hlist_head saved_cap_space; |
1da177e4 LT |
285 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
286 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
287 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 288 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 289 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 290 | struct list_head msi_list; |
ded86d8d | 291 | #endif |
94e61088 | 292 | struct pci_vpd *vpd; |
d1b054da | 293 | #ifdef CONFIG_PCI_IOV |
dd7cc44d YZ |
294 | union { |
295 | struct pci_sriov *sriov; /* SR-IOV capability related */ | |
296 | struct pci_dev *physfn; /* the PF this VF is associated with */ | |
297 | }; | |
302b4215 | 298 | struct pci_ats *ats; /* Address Translation Service */ |
d1b054da | 299 | #endif |
1da177e4 LT |
300 | }; |
301 | ||
65891215 ME |
302 | extern struct pci_dev *alloc_pci_dev(void); |
303 | ||
1da177e4 LT |
304 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
305 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
306 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
307 | ||
a7369f1f LV |
308 | static inline int pci_channel_offline(struct pci_dev *pdev) |
309 | { | |
310 | return (pdev->error_state != pci_channel_io_normal); | |
311 | } | |
312 | ||
41017f0c | 313 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 314 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
315 | { |
316 | struct pci_cap_saved_state *tmp; | |
317 | struct hlist_node *pos; | |
318 | ||
319 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
320 | if (tmp->cap_nr == cap) | |
321 | return tmp; | |
322 | } | |
323 | return NULL; | |
324 | } | |
325 | ||
326 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
327 | struct pci_cap_saved_state *new_cap) | |
328 | { | |
329 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
330 | } | |
331 | ||
1da177e4 | 332 | #ifndef PCI_BUS_NUM_RESOURCES |
30a18d6c | 333 | #define PCI_BUS_NUM_RESOURCES 16 |
1da177e4 | 334 | #endif |
4352dfd5 GKH |
335 | |
336 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
337 | |
338 | struct pci_bus { | |
339 | struct list_head node; /* node in list of buses */ | |
340 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
341 | struct list_head children; /* list of child buses */ | |
342 | struct list_head devices; /* list of devices on this bus */ | |
343 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 344 | struct list_head slots; /* list of slots on this bus */ |
1da177e4 LT |
345 | struct resource *resource[PCI_BUS_NUM_RESOURCES]; |
346 | /* address space routed to this bus */ | |
347 | ||
348 | struct pci_ops *ops; /* configuration access functions */ | |
349 | void *sysdata; /* hook for sys-specific extension */ | |
350 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
351 | ||
352 | unsigned char number; /* bus number */ | |
353 | unsigned char primary; /* number of primary bridge */ | |
354 | unsigned char secondary; /* number of secondary bridge */ | |
355 | unsigned char subordinate; /* max number of subordinate buses */ | |
356 | ||
357 | char name[48]; | |
358 | ||
359 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 360 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 361 | struct device *bridge; |
fd7d1ced | 362 | struct device dev; |
1da177e4 LT |
363 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
364 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 365 | unsigned int is_added:1; |
1da177e4 LT |
366 | }; |
367 | ||
368 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 369 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 370 | |
79af72d7 KK |
371 | /* |
372 | * Returns true if the pci bus is root (behind host-pci bridge), | |
373 | * false otherwise | |
374 | */ | |
375 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
376 | { | |
377 | return !(pbus->parent); | |
378 | } | |
379 | ||
16cf0ebc RW |
380 | #ifdef CONFIG_PCI_MSI |
381 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
382 | { | |
383 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
384 | } | |
385 | #else | |
386 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
387 | #endif | |
388 | ||
1da177e4 LT |
389 | /* |
390 | * Error values that may be returned by PCI functions. | |
391 | */ | |
392 | #define PCIBIOS_SUCCESSFUL 0x00 | |
393 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
394 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
395 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
396 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
397 | #define PCIBIOS_SET_FAILED 0x88 | |
398 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
399 | ||
400 | /* Low-level architecture-dependent routines */ | |
401 | ||
402 | struct pci_ops { | |
403 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
404 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
405 | }; | |
406 | ||
b6ce068a MW |
407 | /* |
408 | * ACPI needs to be able to access PCI config space before we've done a | |
409 | * PCI bus scan and created pci_bus structures. | |
410 | */ | |
411 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
412 | unsigned int devfn, int reg, int len, u32 *val); | |
413 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
414 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
415 | |
416 | struct pci_bus_region { | |
c40a22e0 BH |
417 | resource_size_t start; |
418 | resource_size_t end; | |
1da177e4 LT |
419 | }; |
420 | ||
421 | struct pci_dynids { | |
422 | spinlock_t lock; /* protects list, index */ | |
423 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
424 | }; |
425 | ||
392a1ce7 LV |
426 | /* ---------------------------------------------------------------- */ |
427 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 428 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 LV |
429 | * will be notified of PCI bus errors, and will be driven to recovery |
430 | * when an error occurs. | |
431 | */ | |
432 | ||
433 | typedef unsigned int __bitwise pci_ers_result_t; | |
434 | ||
435 | enum pci_ers_result { | |
436 | /* no result/none/not supported in device driver */ | |
437 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
438 | ||
439 | /* Device driver can recover without slot reset */ | |
440 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
441 | ||
442 | /* Device driver wants slot to be reset. */ | |
443 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
444 | ||
445 | /* Device has completely failed, is unrecoverable */ | |
446 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
447 | ||
448 | /* Device driver is fully recovered and operational */ | |
449 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
450 | }; | |
451 | ||
452 | /* PCI bus error event callbacks */ | |
05cca6e5 | 453 | struct pci_error_handlers { |
392a1ce7 LV |
454 | /* PCI bus error detected on this device */ |
455 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 456 | enum pci_channel_state error); |
392a1ce7 LV |
457 | |
458 | /* MMIO has been re-enabled, but not DMA */ | |
459 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
460 | ||
461 | /* PCI Express link has been reset */ | |
462 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
463 | ||
464 | /* PCI slot has been reset */ | |
465 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
466 | ||
467 | /* Device driver may resume normal operations */ | |
468 | void (*resume)(struct pci_dev *dev); | |
469 | }; | |
470 | ||
471 | /* ---------------------------------------------------------------- */ | |
472 | ||
1da177e4 LT |
473 | struct module; |
474 | struct pci_driver { | |
475 | struct list_head node; | |
476 | char *name; | |
1da177e4 LT |
477 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
478 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
479 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
480 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
481 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
482 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 483 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 484 | void (*shutdown) (struct pci_dev *dev); |
392a1ce7 | 485 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
486 | struct device_driver driver; |
487 | struct pci_dynids dynids; | |
488 | }; | |
489 | ||
05cca6e5 | 490 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 491 | |
90a1ba0c | 492 | /** |
9f9351bb | 493 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
494 | * @_table: device table name |
495 | * | |
496 | * This macro is used to create a struct pci_device_id array (a device table) | |
497 | * in a generic manner. | |
498 | */ | |
9f9351bb | 499 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
500 | const struct pci_device_id _table[] __devinitconst |
501 | ||
1da177e4 LT |
502 | /** |
503 | * PCI_DEVICE - macro used to describe a specific pci device | |
504 | * @vend: the 16 bit PCI Vendor ID | |
505 | * @dev: the 16 bit PCI Device ID | |
506 | * | |
507 | * This macro is used to create a struct pci_device_id that matches a | |
508 | * specific device. The subvendor and subdevice fields will be set to | |
509 | * PCI_ANY_ID. | |
510 | */ | |
511 | #define PCI_DEVICE(vend,dev) \ | |
512 | .vendor = (vend), .device = (dev), \ | |
513 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
514 | ||
515 | /** | |
516 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
517 | * @dev_class: the class, subclass, prog-if triple for this device | |
518 | * @dev_class_mask: the class mask for this device | |
519 | * | |
520 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 521 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
522 | * fields will be set to PCI_ANY_ID. |
523 | */ | |
524 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
525 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
526 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
527 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
528 | ||
1597cacb AC |
529 | /** |
530 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c322b28a ZY |
531 | * @vendor: the vendor name |
532 | * @device: the 16 bit PCI Device ID | |
1597cacb AC |
533 | * |
534 | * This macro is used to create a struct pci_device_id that matches a | |
535 | * specific PCI device. The subvendor, and subdevice fields will be set | |
536 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
537 | * private data. | |
538 | */ | |
539 | ||
540 | #define PCI_VDEVICE(vendor, device) \ | |
541 | PCI_VENDOR_ID_##vendor, (device), \ | |
542 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
543 | ||
1da177e4 LT |
544 | /* these external functions are only available when PCI support is enabled */ |
545 | #ifdef CONFIG_PCI | |
546 | ||
547 | extern struct bus_type pci_bus_type; | |
548 | ||
549 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
550 | * code, or pci core code. */ | |
551 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
552 | /* Some device drivers need know if pci is initiated */ |
553 | extern int no_pci_devices(void); | |
1da177e4 LT |
554 | |
555 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 556 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 557 | char *pcibios_setup(char *str); |
1da177e4 LT |
558 | |
559 | /* Used only when drivers/pci/setup.c is used */ | |
e31dd6e4 GKH |
560 | void pcibios_align_resource(void *, struct resource *, resource_size_t, |
561 | resource_size_t); | |
1da177e4 LT |
562 | void pcibios_update_irq(struct pci_dev *, int irq); |
563 | ||
564 | /* Generic PCI functions used internally */ | |
565 | ||
566 | extern struct pci_bus *pci_find_bus(int domain, int busnr); | |
c48f1670 | 567 | void pci_bus_add_devices(const struct pci_bus *bus); |
05cca6e5 GKH |
568 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
569 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 570 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 571 | void *sysdata) |
1da177e4 | 572 | { |
c431ada4 RS |
573 | struct pci_bus *root_bus; |
574 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
575 | if (root_bus) | |
576 | pci_bus_add_devices(root_bus); | |
577 | return root_bus; | |
1da177e4 | 578 | } |
05cca6e5 GKH |
579 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
580 | struct pci_ops *ops, void *sysdata); | |
581 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
582 | int busnr); | |
f46753c5 | 583 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
584 | const char *name, |
585 | struct hotplug_slot *hotplug); | |
f46753c5 | 586 | void pci_destroy_slot(struct pci_slot *slot); |
d25b7c8d | 587 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
1da177e4 | 588 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 589 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 590 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 591 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 592 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 593 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
594 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
595 | struct resource *res); | |
57c2cf71 | 596 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
1da177e4 | 597 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 598 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
1da177e4 LT |
599 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); |
600 | extern void pci_dev_put(struct pci_dev *dev); | |
601 | extern void pci_remove_bus(struct pci_bus *b); | |
602 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 603 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 604 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 605 | extern void pci_sort_breadthfirst(void); |
1da177e4 LT |
606 | |
607 | /* Generic PCI functions exported to card drivers */ | |
608 | ||
bd3989e0 | 609 | #ifdef CONFIG_PCI_LEGACY |
05cca6e5 GKH |
610 | struct pci_dev __deprecated *pci_find_device(unsigned int vendor, |
611 | unsigned int device, | |
b08508c4 | 612 | struct pci_dev *from); |
bd3989e0 JG |
613 | #endif /* CONFIG_PCI_LEGACY */ |
614 | ||
388c8c16 JB |
615 | enum pci_lost_interrupt_reason { |
616 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
617 | PCI_LOST_IRQ_DISABLE_MSI, | |
618 | PCI_LOST_IRQ_DISABLE_MSIX, | |
619 | PCI_LOST_IRQ_DISABLE_ACPI, | |
620 | }; | |
621 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
622 | int pci_find_capability(struct pci_dev *dev, int cap); |
623 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
624 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
625 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
626 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 627 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 628 | |
d42552c3 AM |
629 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
630 | struct pci_dev *from); | |
05cca6e5 | 631 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 632 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 633 | struct pci_dev *from); |
05cca6e5 GKH |
634 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
635 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); | |
636 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); | |
1da177e4 LT |
637 | int pci_dev_present(const struct pci_device_id *ids); |
638 | ||
05cca6e5 GKH |
639 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
640 | int where, u8 *val); | |
641 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
642 | int where, u16 *val); | |
643 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
644 | int where, u32 *val); | |
645 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
646 | int where, u8 val); | |
647 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
648 | int where, u16 val); | |
649 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
650 | int where, u32 val); | |
a72b46c3 | 651 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 LT |
652 | |
653 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
654 | { | |
05cca6e5 | 655 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
656 | } |
657 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
658 | { | |
05cca6e5 | 659 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 660 | } |
05cca6e5 GKH |
661 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
662 | u32 *val) | |
1da177e4 | 663 | { |
05cca6e5 | 664 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
665 | } |
666 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
667 | { | |
05cca6e5 | 668 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
669 | } |
670 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
671 | { | |
05cca6e5 | 672 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 673 | } |
05cca6e5 GKH |
674 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
675 | u32 val) | |
1da177e4 | 676 | { |
05cca6e5 | 677 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
678 | } |
679 | ||
4a7fb636 | 680 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
681 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
682 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 683 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
684 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
685 | void pcim_pin_device(struct pci_dev *pdev); | |
686 | ||
296ccb08 YS |
687 | static inline int pci_is_enabled(struct pci_dev *pdev) |
688 | { | |
689 | return (atomic_read(&pdev->enable_cnt) > 0); | |
690 | } | |
691 | ||
9ac7849e TH |
692 | static inline int pci_is_managed(struct pci_dev *pdev) |
693 | { | |
694 | return pdev->is_managed; | |
695 | } | |
696 | ||
1da177e4 LT |
697 | void pci_disable_device(struct pci_dev *dev); |
698 | void pci_set_master(struct pci_dev *dev); | |
6a479079 | 699 | void pci_clear_master(struct pci_dev *dev); |
f7bdd12d | 700 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
1da177e4 | 701 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 702 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 703 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 704 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 705 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 706 | void pci_msi_off(struct pci_dev *dev); |
9c8550ee LT |
707 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
708 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); | |
4d57cdfa | 709 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 710 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
711 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
712 | int pcix_get_mmrbc(struct pci_dev *dev); | |
713 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 714 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 715 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
8c1c699f | 716 | int __pci_reset_function(struct pci_dev *dev); |
8dd7f803 | 717 | int pci_reset_function(struct pci_dev *dev); |
14add80b | 718 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 719 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
c87deff7 | 720 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
721 | |
722 | /* ROM control related routines */ | |
e416de5e AC |
723 | int pci_enable_rom(struct pci_dev *pdev); |
724 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 725 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 726 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
97c44836 | 727 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
1da177e4 LT |
728 | |
729 | /* Power management related routines */ | |
730 | int pci_save_state(struct pci_dev *dev); | |
731 | int pci_restore_state(struct pci_dev *dev); | |
0e5dd46b | 732 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
733 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
734 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 735 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 736 | void pci_pme_active(struct pci_dev *dev, bool enable); |
7d9a73f6 | 737 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); |
0235c4fc | 738 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
e5899e1b | 739 | pci_power_t pci_target_state(struct pci_dev *dev); |
404cc2d8 RW |
740 | int pci_prepare_to_sleep(struct pci_dev *dev); |
741 | int pci_back_from_sleep(struct pci_dev *dev); | |
1da177e4 | 742 | |
ce5ccdef | 743 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 744 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
3ed4fd96 AC |
745 | #ifdef CONFIG_HOTPLUG |
746 | unsigned int pci_rescan_bus(struct pci_bus *bus); | |
747 | #endif | |
ce5ccdef | 748 | |
287d19ce SH |
749 | /* Vital product data routines */ |
750 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
751 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
db567943 | 752 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
287d19ce | 753 | |
1da177e4 | 754 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
ea741551 | 755 | void pci_bus_assign_resources(const struct pci_bus *bus); |
1da177e4 LT |
756 | void pci_bus_size_bridges(struct pci_bus *bus); |
757 | int pci_claim_resource(struct pci_dev *, int); | |
758 | void pci_assign_unassigned_resources(void); | |
759 | void pdev_enable_device(struct pci_dev *); | |
760 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 761 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 LT |
762 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
763 | int (*)(struct pci_dev *, u8, u8)); | |
764 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 765 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 766 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 767 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 768 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 769 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 770 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 771 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 772 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 773 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
774 | |
775 | /* drivers/pci/bus.c */ | |
4a7fb636 AM |
776 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
777 | struct resource *res, resource_size_t size, | |
778 | resource_size_t align, resource_size_t min, | |
779 | unsigned int type_mask, | |
780 | void (*alignf)(void *, struct resource *, | |
781 | resource_size_t, resource_size_t), | |
782 | void *alignf_data); | |
1da177e4 LT |
783 | void pci_enable_bridges(struct pci_bus *bus); |
784 | ||
863b18f4 | 785 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
786 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
787 | const char *mod_name); | |
bba81165 AM |
788 | |
789 | /* | |
790 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
791 | */ | |
792 | #define pci_register_driver(driver) \ | |
793 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 794 | |
05cca6e5 GKH |
795 | void pci_unregister_driver(struct pci_driver *dev); |
796 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
797 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
798 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
799 | struct pci_dev *dev); | |
800 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
801 | int pass); | |
1da177e4 | 802 | |
70298c6e | 803 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 804 | void *userdata); |
70b9f7dc | 805 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 806 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 807 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
cecf4864 | 808 | |
deb2d2ec BH |
809 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
810 | unsigned int command_bits, bool change_bridge); | |
1da177e4 LT |
811 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
812 | ||
813 | #include <linux/dmapool.h> | |
814 | ||
815 | #define pci_pool dma_pool | |
816 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
817 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
818 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
819 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
820 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
821 | ||
e24c2d96 DM |
822 | enum pci_dma_burst_strategy { |
823 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
824 | strategy_parameter is N/A */ | |
825 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
826 | byte boundaries */ | |
827 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
828 | strategy_parameter byte boundaries */ | |
829 | }; | |
830 | ||
1da177e4 | 831 | struct msix_entry { |
16dbef4a | 832 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
833 | u16 entry; /* driver uses to specify entry, OS writes */ |
834 | }; | |
835 | ||
0366f8f7 | 836 | |
1da177e4 | 837 | #ifndef CONFIG_PCI_MSI |
1c8d7b0a | 838 | static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) |
05cca6e5 GKH |
839 | { |
840 | return -1; | |
841 | } | |
842 | ||
d52877c7 YL |
843 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
844 | { } | |
05cca6e5 GKH |
845 | static inline void pci_disable_msi(struct pci_dev *dev) |
846 | { } | |
847 | ||
a52e2e35 RW |
848 | static inline int pci_msix_table_size(struct pci_dev *dev) |
849 | { | |
850 | return 0; | |
851 | } | |
05cca6e5 GKH |
852 | static inline int pci_enable_msix(struct pci_dev *dev, |
853 | struct msix_entry *entries, int nvec) | |
854 | { | |
855 | return -1; | |
856 | } | |
857 | ||
d52877c7 YL |
858 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
859 | { } | |
05cca6e5 GKH |
860 | static inline void pci_disable_msix(struct pci_dev *dev) |
861 | { } | |
862 | ||
863 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
864 | { } | |
865 | ||
866 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
867 | { } | |
07ae95f9 AP |
868 | static inline int pci_msi_enabled(void) |
869 | { | |
870 | return 0; | |
871 | } | |
1da177e4 | 872 | #else |
1c8d7b0a | 873 | extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); |
d52877c7 | 874 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 875 | extern void pci_disable_msi(struct pci_dev *dev); |
a52e2e35 | 876 | extern int pci_msix_table_size(struct pci_dev *dev); |
05cca6e5 | 877 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 878 | struct msix_entry *entries, int nvec); |
d52877c7 | 879 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
880 | extern void pci_disable_msix(struct pci_dev *dev); |
881 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 882 | extern void pci_restore_msi_state(struct pci_dev *dev); |
07ae95f9 | 883 | extern int pci_msi_enabled(void); |
1da177e4 LT |
884 | #endif |
885 | ||
3e1b1600 AP |
886 | #ifndef CONFIG_PCIEASPM |
887 | static inline int pcie_aspm_enabled(void) | |
888 | { | |
889 | return 0; | |
890 | } | |
891 | #else | |
892 | extern int pcie_aspm_enabled(void); | |
893 | #endif | |
894 | ||
43c16408 AP |
895 | #ifndef CONFIG_PCIE_ECRC |
896 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) | |
897 | { | |
898 | return; | |
899 | } | |
900 | static inline void pcie_ecrc_get_policy(char *str) {}; | |
901 | #else | |
902 | extern void pcie_set_ecrc_checking(struct pci_dev *dev); | |
903 | extern void pcie_ecrc_get_policy(char *str); | |
904 | #endif | |
905 | ||
1c8d7b0a MW |
906 | #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) |
907 | ||
8b955b0d | 908 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
909 | /* The functions a driver should call */ |
910 | int ht_create_irq(struct pci_dev *dev, int idx); | |
911 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
912 | #endif /* CONFIG_HT_IRQ */ |
913 | ||
e04b0ea2 BK |
914 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
915 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
916 | ||
4352dfd5 GKH |
917 | /* |
918 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
919 | * a PCI domain is defined to be a set of PCI busses which share | |
920 | * configuration space. | |
921 | */ | |
32a2eea7 JG |
922 | #ifdef CONFIG_PCI_DOMAINS |
923 | extern int pci_domains_supported; | |
924 | #else | |
925 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
926 | static inline int pci_domain_nr(struct pci_bus *bus) |
927 | { | |
928 | return 0; | |
929 | } | |
930 | ||
4352dfd5 GKH |
931 | static inline int pci_proc_domain(struct pci_bus *bus) |
932 | { | |
933 | return 0; | |
934 | } | |
32a2eea7 | 935 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 936 | |
4352dfd5 | 937 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
938 | |
939 | /* | |
940 | * If the system does not have PCI, clearly these return errors. Define | |
941 | * these as simple inline functions to avoid hair in drivers. | |
942 | */ | |
943 | ||
05cca6e5 GKH |
944 | #define _PCI_NOP(o, s, t) \ |
945 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
946 | int where, t val) \ | |
1da177e4 | 947 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
948 | |
949 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
950 | _PCI_NOP(o, word, u16 x) \ | |
951 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
952 | _PCI_NOP_ALL(read, *) |
953 | _PCI_NOP_ALL(write,) | |
954 | ||
05cca6e5 GKH |
955 | static inline struct pci_dev *pci_find_device(unsigned int vendor, |
956 | unsigned int device, | |
b08508c4 | 957 | struct pci_dev *from) |
05cca6e5 GKH |
958 | { |
959 | return NULL; | |
960 | } | |
1da177e4 | 961 | |
d42552c3 | 962 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
963 | unsigned int device, |
964 | struct pci_dev *from) | |
965 | { | |
966 | return NULL; | |
967 | } | |
d42552c3 | 968 | |
05cca6e5 GKH |
969 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
970 | unsigned int device, | |
971 | unsigned int ss_vendor, | |
972 | unsigned int ss_device, | |
b08508c4 | 973 | struct pci_dev *from) |
05cca6e5 GKH |
974 | { |
975 | return NULL; | |
976 | } | |
1da177e4 | 977 | |
05cca6e5 GKH |
978 | static inline struct pci_dev *pci_get_class(unsigned int class, |
979 | struct pci_dev *from) | |
980 | { | |
981 | return NULL; | |
982 | } | |
1da177e4 LT |
983 | |
984 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 985 | #define no_pci_devices() (1) |
1da177e4 LT |
986 | #define pci_dev_put(dev) do { } while (0) |
987 | ||
05cca6e5 GKH |
988 | static inline void pci_set_master(struct pci_dev *dev) |
989 | { } | |
990 | ||
991 | static inline int pci_enable_device(struct pci_dev *dev) | |
992 | { | |
993 | return -EIO; | |
994 | } | |
995 | ||
996 | static inline void pci_disable_device(struct pci_dev *dev) | |
997 | { } | |
998 | ||
999 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1000 | { | |
1001 | return -EIO; | |
1002 | } | |
1003 | ||
80be0385 RD |
1004 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
1005 | { | |
1006 | return -EIO; | |
1007 | } | |
1008 | ||
4d57cdfa FT |
1009 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
1010 | unsigned int size) | |
1011 | { | |
1012 | return -EIO; | |
1013 | } | |
1014 | ||
59fc67de FT |
1015 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
1016 | unsigned long mask) | |
1017 | { | |
1018 | return -EIO; | |
1019 | } | |
1020 | ||
05cca6e5 GKH |
1021 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
1022 | { | |
1023 | return -EBUSY; | |
1024 | } | |
1025 | ||
1026 | static inline int __pci_register_driver(struct pci_driver *drv, | |
1027 | struct module *owner) | |
1028 | { | |
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static inline int pci_register_driver(struct pci_driver *drv) | |
1033 | { | |
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
1038 | { } | |
1039 | ||
1040 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
1041 | { | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
1046 | int cap) | |
1047 | { | |
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
1052 | { | |
1053 | return 0; | |
1054 | } | |
1055 | ||
1da177e4 | 1056 | /* Power management related routines */ |
05cca6e5 GKH |
1057 | static inline int pci_save_state(struct pci_dev *dev) |
1058 | { | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static inline int pci_restore_state(struct pci_dev *dev) | |
1063 | { | |
1064 | return 0; | |
1065 | } | |
1da177e4 | 1066 | |
05cca6e5 GKH |
1067 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
1068 | { | |
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, | |
1073 | pm_message_t state) | |
1074 | { | |
1075 | return PCI_D0; | |
1076 | } | |
1077 | ||
1078 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
1079 | int enable) | |
1080 | { | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) | |
1085 | { | |
1086 | return -EIO; | |
1087 | } | |
1088 | ||
1089 | static inline void pci_release_regions(struct pci_dev *dev) | |
1090 | { } | |
0da0ead9 | 1091 | |
a46e8126 KG |
1092 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1093 | ||
05cca6e5 GKH |
1094 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
1095 | { } | |
1096 | ||
1097 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
1098 | { } | |
e04b0ea2 | 1099 | |
d80d0217 RD |
1100 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1101 | { return NULL; } | |
1102 | ||
1103 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
1104 | unsigned int devfn) | |
1105 | { return NULL; } | |
1106 | ||
1107 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
1108 | unsigned int devfn) | |
1109 | { return NULL; } | |
1110 | ||
4352dfd5 | 1111 | #endif /* CONFIG_PCI */ |
1da177e4 | 1112 | |
4352dfd5 GKH |
1113 | /* Include architecture-dependent settings and functions */ |
1114 | ||
1115 | #include <asm/pci.h> | |
1da177e4 | 1116 | |
1f82de10 YL |
1117 | #ifndef PCIBIOS_MAX_MEM_32 |
1118 | #define PCIBIOS_MAX_MEM_32 (-1) | |
1119 | #endif | |
1120 | ||
1da177e4 LT |
1121 | /* these helpers provide future and backwards compatibility |
1122 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1123 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1124 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1125 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1126 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1127 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1128 | pci_resource_end((dev), (bar)) == \ | |
1129 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1130 | \ | |
1131 | (pci_resource_end((dev), (bar)) - \ | |
1132 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1133 | |
1134 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1135 | * driver-specific data. They are really just a wrapper around | |
1136 | * the generic device structure functions of these calls. | |
1137 | */ | |
05cca6e5 | 1138 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1139 | { |
1140 | return dev_get_drvdata(&pdev->dev); | |
1141 | } | |
1142 | ||
05cca6e5 | 1143 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1144 | { |
1145 | dev_set_drvdata(&pdev->dev, data); | |
1146 | } | |
1147 | ||
1148 | /* If you want to know what to call your pci_dev, ask this function. | |
1149 | * Again, it's a wrapper around the generic device. | |
1150 | */ | |
2fc90f61 | 1151 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1152 | { |
c6c4f070 | 1153 | return dev_name(&pdev->dev); |
1da177e4 LT |
1154 | } |
1155 | ||
2311b1f2 ME |
1156 | |
1157 | /* Some archs don't want to expose struct resource to userland as-is | |
1158 | * in sysfs and /proc | |
1159 | */ | |
1160 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1161 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1162 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1163 | resource_size_t *end) |
2311b1f2 ME |
1164 | { |
1165 | *start = rsrc->start; | |
1166 | *end = rsrc->end; | |
1167 | } | |
1168 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1169 | ||
1170 | ||
1da177e4 LT |
1171 | /* |
1172 | * The world is not perfect and supplies us with broken PCI devices. | |
1173 | * For at least a part of these bugs we need a work-around, so both | |
1174 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1175 | * fixup hooks to be called for particular buggy devices. | |
1176 | */ | |
1177 | ||
1178 | struct pci_fixup { | |
1179 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1180 | void (*hook)(struct pci_dev *dev); | |
1181 | }; | |
1182 | ||
1183 | enum pci_fixup_pass { | |
1184 | pci_fixup_early, /* Before probing BARs */ | |
1185 | pci_fixup_header, /* After reading configuration header */ | |
1186 | pci_fixup_final, /* Final phase of device fixups */ | |
1187 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1188 | pci_fixup_resume, /* pci_device_resume() */ |
1189 | pci_fixup_suspend, /* pci_device_suspend */ | |
1190 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1191 | }; |
1192 | ||
1193 | /* Anonymous variables would be nice... */ | |
1194 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1195 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1196 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1197 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1198 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1199 | vendor##device##hook, vendor, device, hook) | |
1200 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1201 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1202 | vendor##device##hook, vendor, device, hook) | |
1203 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1204 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1205 | vendor##device##hook, vendor, device, hook) | |
1206 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1207 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1208 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1209 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1210 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1211 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1212 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1213 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1214 | resume_early##vendor##device##hook, vendor, device, hook) | |
1215 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1216 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1217 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 LT |
1218 | |
1219 | ||
1220 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); | |
1221 | ||
05cca6e5 | 1222 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1223 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1224 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1225 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1226 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1227 | const char *name); | |
ec04b075 | 1228 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1229 | |
1da177e4 | 1230 | extern int pci_pci_problems; |
236561e5 | 1231 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1232 | #define PCIPCI_TRITON 2 |
1233 | #define PCIPCI_NATOMA 4 | |
1234 | #define PCIPCI_VIAETBF 8 | |
1235 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1236 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1237 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1238 | |
4516a618 AN |
1239 | extern unsigned long pci_cardbus_io_size; |
1240 | extern unsigned long pci_cardbus_mem_size; | |
1241 | ||
19792a08 AB |
1242 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1243 | void pcibios_disable_device(struct pci_dev *dev); | |
1244 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1245 | enum pcie_reset_state state); | |
575e3348 | 1246 | |
7752d5cf | 1247 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1248 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1249 | extern void __init pci_mmcfg_late_init(void); |
1250 | #else | |
bb63b421 | 1251 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1252 | static inline void pci_mmcfg_late_init(void) { } |
1253 | #endif | |
1254 | ||
0ef5f8f6 AP |
1255 | int pci_ext_cfg_avail(struct pci_dev *dev); |
1256 | ||
1684f5dd | 1257 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1258 | |
dd7cc44d YZ |
1259 | #ifdef CONFIG_PCI_IOV |
1260 | extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); | |
1261 | extern void pci_disable_sriov(struct pci_dev *dev); | |
74bb1bcc | 1262 | extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); |
dd7cc44d YZ |
1263 | #else |
1264 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) | |
1265 | { | |
1266 | return -ENODEV; | |
1267 | } | |
1268 | static inline void pci_disable_sriov(struct pci_dev *dev) | |
1269 | { | |
1270 | } | |
74bb1bcc YZ |
1271 | static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) |
1272 | { | |
1273 | return IRQ_NONE; | |
1274 | } | |
dd7cc44d YZ |
1275 | #endif |
1276 | ||
c825bc94 KK |
1277 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
1278 | extern void pci_hp_create_module_link(struct pci_slot *pci_slot); | |
1279 | extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
1280 | #endif | |
1281 | ||
1da177e4 LT |
1282 | #endif /* __KERNEL__ */ |
1283 | #endif /* LINUX_PCI_H */ |