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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
503e5763 | 20 | #include <linux/gfp.h> |
908dcecd | 21 | #include <linux/irqreturn.h> |
dd3a1db9 | 22 | #include <linux/irqnr.h> |
77904fd6 | 23 | #include <linux/errno.h> |
503e5763 | 24 | #include <linux/topology.h> |
3aa551c9 | 25 | #include <linux/wait.h> |
1da177e4 LT |
26 | |
27 | #include <asm/irq.h> | |
28 | #include <asm/ptrace.h> | |
7d12e780 | 29 | #include <asm/irq_regs.h> |
1da177e4 | 30 | |
57a58a94 | 31 | struct irq_desc; |
ec701584 | 32 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 33 | struct irq_desc *desc); |
57a58a94 DH |
34 | |
35 | ||
1da177e4 LT |
36 | /* |
37 | * IRQ line status. | |
6e213616 | 38 | * |
950f4427 | 39 | * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h |
6e213616 TG |
40 | * |
41 | * IRQ types | |
1da177e4 | 42 | */ |
6e213616 TG |
43 | #define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ |
44 | #define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ | |
45 | #define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ | |
46 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) | |
47 | #define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ | |
48 | #define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ | |
49 | #define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ | |
50 | #define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ | |
51 | ||
52 | /* Internal flags */ | |
950f4427 TG |
53 | #define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */ |
54 | #define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */ | |
55 | #define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */ | |
56 | #define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */ | |
57 | #define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */ | |
58 | #define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */ | |
59 | #define IRQ_LEVEL 0x00004000 /* IRQ level triggered */ | |
60 | #define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */ | |
61 | #define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */ | |
62 | #define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */ | |
63 | #define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */ | |
64 | #define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */ | |
d7e25f33 IM |
65 | #define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */ |
66 | #define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */ | |
67 | #define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */ | |
1adb0850 | 68 | #define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */ |
f6d87f4b TG |
69 | #define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */ |
70 | #define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/ | |
0a0c5168 | 71 | #define IRQ_SUSPENDED 0x04000000 /* IRQ has gone through suspend sequence */ |
b25c340c | 72 | #define IRQ_ONESHOT 0x08000000 /* IRQ is not unmasked after hardirq */ |
399b5da2 | 73 | #define IRQ_NESTED_THREAD 0x10000000 /* IRQ is nested into another, no own handler thread */ |
950f4427 | 74 | |
0d7012a9 | 75 | #ifdef CONFIG_IRQ_PER_CPU |
f26fdd59 | 76 | # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU) |
950f4427 | 77 | # define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
f26fdd59 KW |
78 | #else |
79 | # define CHECK_IRQ_PER_CPU(var) 0 | |
950f4427 | 80 | # define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING |
f26fdd59 | 81 | #endif |
1da177e4 | 82 | |
6a6de9ef | 83 | struct proc_dir_entry; |
5b912c10 | 84 | struct msi_desc; |
6a6de9ef | 85 | |
ff7dcd44 TG |
86 | /** |
87 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
88 | * @irq: interrupt number | |
89 | * @node: node index useful for balancing | |
90 | * @chip: low level interrupt hardware access | |
91 | * @handler_data: per-IRQ data for the irq_chip methods | |
92 | * @chip_data: platform-specific per-chip private data for the chip | |
93 | * methods, to allow shared chip implementations | |
94 | * @msi_desc: MSI descriptor | |
95 | * @affinity: IRQ affinity on SMP | |
96 | * @irq_2_iommu: iommu with this irq | |
97 | * | |
98 | * The fields here need to overlay the ones in irq_desc until we | |
99 | * cleaned up the direct references and switched everything over to | |
100 | * irq_data. | |
101 | */ | |
102 | struct irq_data { | |
103 | unsigned int irq; | |
104 | unsigned int node; | |
105 | struct irq_chip *chip; | |
106 | void *handler_data; | |
107 | void *chip_data; | |
108 | struct msi_desc *msi_desc; | |
109 | #ifdef CONFIG_SMP | |
110 | cpumask_var_t affinity; | |
111 | #endif | |
112 | #ifdef CONFIG_INTR_REMAP | |
113 | struct irq_2_iommu *irq_2_iommu; | |
114 | #endif | |
115 | }; | |
116 | ||
8fee5c36 | 117 | /** |
6a6de9ef | 118 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
119 | * |
120 | * @name: name for /proc/interrupts | |
f8822657 TG |
121 | * @startup: deprecated, replaced by irq_startup |
122 | * @shutdown: deprecated, replaced by irq_shutdown | |
123 | * @enable: deprecated, replaced by irq_enable | |
124 | * @disable: deprecated, replaced by irq_disable | |
125 | * @ack: deprecated, replaced by irq_ack | |
126 | * @mask: deprecated, replaced by irq_mask | |
127 | * @mask_ack: deprecated, replaced by irq_mask_ack | |
128 | * @unmask: deprecated, replaced by irq_unmask | |
129 | * @eoi: deprecated, replaced by irq_eoi | |
130 | * @end: deprecated, will go away with __do_IRQ() | |
131 | * @set_affinity: deprecated, replaced by irq_set_affinity | |
132 | * @retrigger: deprecated, replaced by irq_retrigger | |
133 | * @set_type: deprecated, replaced by irq_set_type | |
134 | * @set_wake: deprecated, replaced by irq_wake | |
135 | * @bus_lock: deprecated, replaced by irq_bus_lock | |
136 | * @bus_sync_unlock: deprecated, replaced by irq_bus_sync_unlock | |
8fee5c36 | 137 | * |
f8822657 TG |
138 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
139 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
140 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
141 | * @irq_disable: disable the interrupt | |
142 | * @irq_ack: start of a new interrupt | |
143 | * @irq_mask: mask an interrupt source | |
144 | * @irq_mask_ack: ack and mask an interrupt source | |
145 | * @irq_unmask: unmask an interrupt source | |
146 | * @irq_eoi: end of interrupt | |
147 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
148 | * @irq_retrigger: resend an IRQ to the CPU | |
149 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
150 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
151 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
152 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
70aedd24 | 153 | * |
8fee5c36 | 154 | * @release: release function solely used by UML |
1da177e4 | 155 | */ |
6a6de9ef TG |
156 | struct irq_chip { |
157 | const char *name; | |
bd151412 | 158 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
71d218b7 IM |
159 | unsigned int (*startup)(unsigned int irq); |
160 | void (*shutdown)(unsigned int irq); | |
161 | void (*enable)(unsigned int irq); | |
162 | void (*disable)(unsigned int irq); | |
6a6de9ef | 163 | |
71d218b7 | 164 | void (*ack)(unsigned int irq); |
6a6de9ef TG |
165 | void (*mask)(unsigned int irq); |
166 | void (*mask_ack)(unsigned int irq); | |
167 | void (*unmask)(unsigned int irq); | |
47c2a3aa | 168 | void (*eoi)(unsigned int irq); |
6a6de9ef | 169 | |
71d218b7 | 170 | void (*end)(unsigned int irq); |
d5dedd45 | 171 | int (*set_affinity)(unsigned int irq, |
0de26520 | 172 | const struct cpumask *dest); |
c0ad90a3 | 173 | int (*retrigger)(unsigned int irq); |
6a6de9ef TG |
174 | int (*set_type)(unsigned int irq, unsigned int flow_type); |
175 | int (*set_wake)(unsigned int irq, unsigned int on); | |
c0ad90a3 | 176 | |
70aedd24 TG |
177 | void (*bus_lock)(unsigned int irq); |
178 | void (*bus_sync_unlock)(unsigned int irq); | |
bd151412 | 179 | #endif |
f8822657 TG |
180 | unsigned int (*irq_startup)(struct irq_data *data); |
181 | void (*irq_shutdown)(struct irq_data *data); | |
182 | void (*irq_enable)(struct irq_data *data); | |
183 | void (*irq_disable)(struct irq_data *data); | |
184 | ||
185 | void (*irq_ack)(struct irq_data *data); | |
186 | void (*irq_mask)(struct irq_data *data); | |
187 | void (*irq_mask_ack)(struct irq_data *data); | |
188 | void (*irq_unmask)(struct irq_data *data); | |
189 | void (*irq_eoi)(struct irq_data *data); | |
190 | ||
191 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
192 | int (*irq_retrigger)(struct irq_data *data); | |
193 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
194 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
195 | ||
196 | void (*irq_bus_lock)(struct irq_data *data); | |
197 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
198 | ||
b77d6adc PBG |
199 | /* Currently used only by UML, might disappear one day.*/ |
200 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 201 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 202 | #endif |
1da177e4 LT |
203 | }; |
204 | ||
0b8f1efa YL |
205 | struct timer_rand_state; |
206 | struct irq_2_iommu; | |
8fee5c36 IM |
207 | /** |
208 | * struct irq_desc - interrupt descriptor | |
ff7dcd44 | 209 | * @irq_data: per irq and chip data passed down to chip functions |
078a55db YL |
210 | * @timer_rand_state: pointer to timer rand state struct |
211 | * @kstat_irqs: irq stats per cpu | |
6a6de9ef | 212 | * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()] |
8fee5c36 IM |
213 | * @action: the irq action chain |
214 | * @status: status information | |
215 | * @depth: disable-depth, for nested irq_disable() calls | |
15a647eb | 216 | * @wake_depth: enable depth, for multiple set_irq_wake() callers |
8fee5c36 | 217 | * @irq_count: stats field to detect stalled irqs |
5ac4d823 | 218 | * @last_unhandled: aging timer for unhandled count |
e262a7ba | 219 | * @irqs_unhandled: stats field for spurious unhandled interrupts |
8fee5c36 | 220 | * @lock: locking for SMP |
8fee5c36 | 221 | * @pending_mask: pending rebalanced interrupts |
3aa551c9 TG |
222 | * @threads_active: number of irqaction threads currently running |
223 | * @wait_for_threads: wait queue for sync_irq to wait for threaded handlers | |
8fee5c36 | 224 | * @dir: /proc/irq/ procfs entry |
a460e745 | 225 | * @name: flow handler name for /proc/interrupts output |
1da177e4 | 226 | */ |
34ffdb72 | 227 | struct irq_desc { |
ff7dcd44 | 228 | |
bd151412 TG |
229 | #ifdef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
230 | struct irq_data irq_data; | |
231 | #else | |
ff7dcd44 TG |
232 | /* |
233 | * This union will go away, once we fixed the direct access to | |
234 | * irq_desc all over the place. The direct fields are a 1:1 | |
235 | * overlay of irq_data. | |
236 | */ | |
237 | union { | |
238 | struct irq_data irq_data; | |
239 | struct { | |
240 | unsigned int irq; | |
241 | unsigned int node; | |
242 | struct irq_chip *chip; | |
243 | void *handler_data; | |
244 | void *chip_data; | |
245 | struct msi_desc *msi_desc; | |
246 | #ifdef CONFIG_SMP | |
247 | cpumask_var_t affinity; | |
248 | #endif | |
d7e51e66 | 249 | #ifdef CONFIG_INTR_REMAP |
ff7dcd44 | 250 | struct irq_2_iommu *irq_2_iommu; |
0b8f1efa | 251 | #endif |
ff7dcd44 TG |
252 | }; |
253 | }; | |
bd151412 TG |
254 | #endif |
255 | ||
ff7dcd44 TG |
256 | struct timer_rand_state *timer_rand_state; |
257 | unsigned int *kstat_irqs; | |
57a58a94 | 258 | irq_flow_handler_t handle_irq; |
71d218b7 IM |
259 | struct irqaction *action; /* IRQ action list */ |
260 | unsigned int status; /* IRQ status */ | |
6a6de9ef | 261 | |
71d218b7 | 262 | unsigned int depth; /* nested irq disables */ |
15a647eb | 263 | unsigned int wake_depth; /* nested wake enables */ |
71d218b7 | 264 | unsigned int irq_count; /* For detecting broken IRQs */ |
4f27c00b | 265 | unsigned long last_unhandled; /* Aging timer for unhandled count */ |
e262a7ba | 266 | unsigned int irqs_unhandled; |
239007b8 | 267 | raw_spinlock_t lock; |
a53da52f | 268 | #ifdef CONFIG_SMP |
e7a297b0 | 269 | const struct cpumask *affinity_hint; |
8b8e8c1b | 270 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
7f7ace0c MT |
271 | cpumask_var_t pending_mask; |
272 | #endif | |
54d5d424 | 273 | #endif |
3aa551c9 TG |
274 | atomic_t threads_active; |
275 | wait_queue_head_t wait_for_threads; | |
4a733ee1 | 276 | #ifdef CONFIG_PROC_FS |
a460e745 | 277 | struct proc_dir_entry *dir; |
4a733ee1 | 278 | #endif |
a460e745 | 279 | const char *name; |
e729aa16 | 280 | } ____cacheline_internodealigned_in_smp; |
1da177e4 | 281 | |
0b8f1efa | 282 | extern void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 283 | struct irq_desc *desc, int node); |
0b8f1efa | 284 | extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc); |
9059d8fa | 285 | |
0b8f1efa | 286 | #ifndef CONFIG_SPARSE_IRQ |
34ffdb72 | 287 | extern struct irq_desc irq_desc[NR_IRQS]; |
15e957d0 YL |
288 | #endif |
289 | ||
290 | #ifdef CONFIG_NUMA_IRQ_DESC | |
85ac16d0 | 291 | extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int node); |
15e957d0 YL |
292 | #else |
293 | static inline struct irq_desc *move_irq_desc(struct irq_desc *desc, int node) | |
294 | { | |
295 | return desc; | |
296 | } | |
297 | #endif | |
0b8f1efa | 298 | |
85ac16d0 | 299 | extern struct irq_desc *irq_to_desc_alloc_node(unsigned int irq, int node); |
0b8f1efa | 300 | |
34ffdb72 IM |
301 | /* |
302 | * Pick up the arch-dependent methods: | |
303 | */ | |
304 | #include <asm/hw_irq.h> | |
1da177e4 | 305 | |
06fcb0c6 | 306 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 307 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
1da177e4 LT |
308 | |
309 | #ifdef CONFIG_GENERIC_HARDIRQS | |
06fcb0c6 | 310 | |
54d5d424 AR |
311 | #ifdef CONFIG_SMP |
312 | ||
8b8e8c1b | 313 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54d5d424 | 314 | |
c777ac55 | 315 | void move_native_irq(int irq); |
e7b946e9 | 316 | void move_masked_irq(int irq); |
54d5d424 | 317 | |
8b8e8c1b | 318 | #else /* CONFIG_GENERIC_PENDING_IRQ */ |
06fcb0c6 IM |
319 | |
320 | static inline void move_irq(int irq) | |
321 | { | |
322 | } | |
323 | ||
324 | static inline void move_native_irq(int irq) | |
325 | { | |
326 | } | |
327 | ||
e7b946e9 EB |
328 | static inline void move_masked_irq(int irq) |
329 | { | |
330 | } | |
331 | ||
06fcb0c6 | 332 | #endif /* CONFIG_GENERIC_PENDING_IRQ */ |
54d5d424 | 333 | |
06fcb0c6 | 334 | #else /* CONFIG_SMP */ |
54d5d424 | 335 | |
54d5d424 | 336 | #define move_native_irq(x) |
e7b946e9 | 337 | #define move_masked_irq(x) |
54d5d424 | 338 | |
06fcb0c6 | 339 | #endif /* CONFIG_SMP */ |
54d5d424 | 340 | |
1da177e4 | 341 | extern int no_irq_affinity; |
1da177e4 | 342 | |
950f4427 TG |
343 | static inline int irq_balancing_disabled(unsigned int irq) |
344 | { | |
08678b08 YL |
345 | struct irq_desc *desc; |
346 | ||
347 | desc = irq_to_desc(irq); | |
348 | return desc->status & IRQ_NO_BALANCING_MASK; | |
950f4427 TG |
349 | } |
350 | ||
6a6de9ef | 351 | /* Handle irq action chains: */ |
bedd30d9 | 352 | extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action); |
6a6de9ef TG |
353 | |
354 | /* | |
355 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 356 | * callable via desc->handle_irq() |
6a6de9ef | 357 | */ |
ec701584 HH |
358 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
359 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
360 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
361 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); | |
362 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
363 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); | |
31b47cf7 | 364 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 365 | |
2e60bbb6 | 366 | /* |
6a6de9ef | 367 | * Monolithic do_IRQ implementation. |
2e60bbb6 | 368 | */ |
af8c65b5 | 369 | #ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ |
ec701584 | 370 | extern unsigned int __do_IRQ(unsigned int irq); |
af8c65b5 | 371 | #endif |
2e60bbb6 | 372 | |
dae86204 IM |
373 | /* |
374 | * Architectures call this to let the generic IRQ layer | |
375 | * handle an interrupt. If the descriptor is attached to an | |
376 | * irqchip-style controller then we call the ->handle_irq() handler, | |
377 | * and it calls __do_IRQ() if it's attached to an irqtype-style controller. | |
378 | */ | |
46926b67 | 379 | static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc) |
dae86204 | 380 | { |
af8c65b5 | 381 | #ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ |
7d12e780 | 382 | desc->handle_irq(irq, desc); |
af8c65b5 | 383 | #else |
dae86204 | 384 | if (likely(desc->handle_irq)) |
7d12e780 | 385 | desc->handle_irq(irq, desc); |
dae86204 | 386 | else |
7d12e780 | 387 | __do_IRQ(irq); |
af8c65b5 | 388 | #endif |
dae86204 IM |
389 | } |
390 | ||
46926b67 YL |
391 | static inline void generic_handle_irq(unsigned int irq) |
392 | { | |
393 | generic_handle_irq_desc(irq, irq_to_desc(irq)); | |
394 | } | |
395 | ||
6a6de9ef | 396 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 397 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 398 | irqreturn_t action_ret); |
1da177e4 | 399 | |
a4633adc TG |
400 | /* Resending of interrupts :*/ |
401 | void check_irq_resend(struct irq_desc *desc, unsigned int irq); | |
402 | ||
6a6de9ef TG |
403 | /* Enable/disable irq debugging output: */ |
404 | extern int noirqdebug_setup(char *str); | |
405 | ||
406 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
407 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
408 | ||
f8b5473f | 409 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 410 | extern struct irq_chip no_irq_chip; |
f8b5473f | 411 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 412 | |
145fc655 IM |
413 | extern void |
414 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
415 | irq_flow_handler_t handle); | |
6a6de9ef | 416 | extern void |
a460e745 IM |
417 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
418 | irq_flow_handler_t handle, const char *name); | |
419 | ||
6a6de9ef | 420 | extern void |
a460e745 IM |
421 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
422 | const char *name); | |
1da177e4 | 423 | |
b019e573 KH |
424 | /* caller has locked the irq_desc and both params are valid */ |
425 | static inline void __set_irq_handler_unlocked(int irq, | |
426 | irq_flow_handler_t handler) | |
427 | { | |
08678b08 YL |
428 | struct irq_desc *desc; |
429 | ||
430 | desc = irq_to_desc(irq); | |
431 | desc->handle_irq = handler; | |
b019e573 KH |
432 | } |
433 | ||
6a6de9ef TG |
434 | /* |
435 | * Set a highlevel flow handler for a given IRQ: | |
436 | */ | |
437 | static inline void | |
57a58a94 | 438 | set_irq_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 439 | { |
a460e745 | 440 | __set_irq_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
441 | } |
442 | ||
443 | /* | |
444 | * Set a highlevel chained flow handler for a given IRQ. | |
445 | * (a chained handler is automatically enabled and set to | |
446 | * IRQ_NOREQUEST and IRQ_NOPROBE) | |
447 | */ | |
448 | static inline void | |
449 | set_irq_chained_handler(unsigned int irq, | |
57a58a94 | 450 | irq_flow_handler_t handle) |
6a6de9ef | 451 | { |
a460e745 | 452 | __set_irq_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
453 | } |
454 | ||
399b5da2 TG |
455 | extern void set_irq_nested_thread(unsigned int irq, int nest); |
456 | ||
46f4f8f6 RB |
457 | extern void set_irq_noprobe(unsigned int irq); |
458 | extern void set_irq_probe(unsigned int irq); | |
459 | ||
3a16d713 | 460 | /* Handle dynamic irq creation and destruction */ |
d047f53a | 461 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
3a16d713 EB |
462 | extern int create_irq(void); |
463 | extern void destroy_irq(unsigned int irq); | |
464 | ||
1f80025e EB |
465 | /* Test to see if a driver has successfully requested an irq */ |
466 | static inline int irq_has_action(unsigned int irq) | |
467 | { | |
08678b08 | 468 | struct irq_desc *desc = irq_to_desc(irq); |
1f80025e EB |
469 | return desc->action != NULL; |
470 | } | |
471 | ||
3a16d713 EB |
472 | /* Dynamic irq helper functions */ |
473 | extern void dynamic_irq_init(unsigned int irq); | |
ced5b697 | 474 | void dynamic_irq_init_keep_chip_data(unsigned int irq); |
3a16d713 | 475 | extern void dynamic_irq_cleanup(unsigned int irq); |
ced5b697 | 476 | void dynamic_irq_cleanup_keep_chip_data(unsigned int irq); |
dd87eb3a | 477 | |
3a16d713 | 478 | /* Set/get chip/data for an IRQ: */ |
dd87eb3a TG |
479 | extern int set_irq_chip(unsigned int irq, struct irq_chip *chip); |
480 | extern int set_irq_data(unsigned int irq, void *data); | |
481 | extern int set_irq_chip_data(unsigned int irq, void *data); | |
482 | extern int set_irq_type(unsigned int irq, unsigned int type); | |
5b912c10 | 483 | extern int set_irq_msi(unsigned int irq, struct msi_desc *entry); |
dd87eb3a | 484 | |
ff7dcd44 TG |
485 | #define get_irq_chip(irq) (irq_to_desc(irq)->irq_data.chip) |
486 | #define get_irq_chip_data(irq) (irq_to_desc(irq)->irq_data.chip_data) | |
487 | #define get_irq_data(irq) (irq_to_desc(irq)->irq_data.handler_data) | |
488 | #define get_irq_msi(irq) (irq_to_desc(irq)->irq_data.msi_desc) | |
dd87eb3a | 489 | |
ff7dcd44 TG |
490 | #define get_irq_desc_chip(desc) ((desc)->irq_data.chip) |
491 | #define get_irq_desc_chip_data(desc) ((desc)->irq_data.chip_data) | |
492 | #define get_irq_desc_data(desc) ((desc)->irq_data.handler_data) | |
493 | #define get_irq_desc_msi(desc) ((desc)->irq_data.msi_desc) | |
0b8f1efa | 494 | |
6a6de9ef | 495 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 496 | |
06fcb0c6 | 497 | #endif /* !CONFIG_S390 */ |
1da177e4 | 498 | |
7f7ace0c MT |
499 | #ifdef CONFIG_SMP |
500 | /** | |
9ec4fa27 | 501 | * alloc_desc_masks - allocate cpumasks for irq_desc |
7f7ace0c | 502 | * @desc: pointer to irq_desc struct |
ab33dcff | 503 | * @node: node which will be handling the cpumasks |
7f7ace0c MT |
504 | * @boot: true if need bootmem |
505 | * | |
506 | * Allocates affinity and pending_mask cpumask if required. | |
507 | * Returns true if successful (or not required). | |
7f7ace0c | 508 | */ |
85ac16d0 | 509 | static inline bool alloc_desc_masks(struct irq_desc *desc, int node, |
38c7fed2 | 510 | bool boot) |
7f7ace0c | 511 | { |
38c7fed2 | 512 | gfp_t gfp = GFP_ATOMIC; |
7f7ace0c | 513 | |
38c7fed2 YL |
514 | if (boot) |
515 | gfp = GFP_NOWAIT; | |
7f7ace0c | 516 | |
38c7fed2 | 517 | #ifdef CONFIG_CPUMASK_OFFSTACK |
6b8ff312 | 518 | if (!alloc_cpumask_var_node(&desc->irq_data.affinity, gfp, node)) |
7f7ace0c | 519 | return false; |
7f7ace0c MT |
520 | |
521 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
38c7fed2 | 522 | if (!alloc_cpumask_var_node(&desc->pending_mask, gfp, node)) { |
6b8ff312 | 523 | free_cpumask_var(desc->irq_data.affinity); |
7f7ace0c MT |
524 | return false; |
525 | } | |
9ec4fa27 | 526 | #endif |
7f7ace0c MT |
527 | #endif |
528 | return true; | |
529 | } | |
530 | ||
9ec4fa27 YL |
531 | static inline void init_desc_masks(struct irq_desc *desc) |
532 | { | |
6b8ff312 | 533 | cpumask_setall(desc->irq_data.affinity); |
9ec4fa27 YL |
534 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
535 | cpumask_clear(desc->pending_mask); | |
536 | #endif | |
537 | } | |
538 | ||
7f7ace0c MT |
539 | /** |
540 | * init_copy_desc_masks - copy cpumasks for irq_desc | |
541 | * @old_desc: pointer to old irq_desc struct | |
542 | * @new_desc: pointer to new irq_desc struct | |
543 | * | |
544 | * Insures affinity and pending_masks are copied to new irq_desc. | |
545 | * If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the | |
546 | * irq_desc struct so the copy is redundant. | |
547 | */ | |
548 | ||
549 | static inline void init_copy_desc_masks(struct irq_desc *old_desc, | |
550 | struct irq_desc *new_desc) | |
551 | { | |
9ec4fa27 | 552 | #ifdef CONFIG_CPUMASK_OFFSTACK |
6b8ff312 | 553 | cpumask_copy(new_desc->irq_data.affinity, old_desc->irq_data.affinity); |
7f7ace0c MT |
554 | |
555 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
556 | cpumask_copy(new_desc->pending_mask, old_desc->pending_mask); | |
557 | #endif | |
558 | #endif | |
559 | } | |
560 | ||
9756b15e YL |
561 | static inline void free_desc_masks(struct irq_desc *old_desc, |
562 | struct irq_desc *new_desc) | |
563 | { | |
6b8ff312 | 564 | free_cpumask_var(old_desc->irq_data.affinity); |
9756b15e YL |
565 | |
566 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
567 | free_cpumask_var(old_desc->pending_mask); | |
568 | #endif | |
569 | } | |
570 | ||
7f7ace0c MT |
571 | #else /* !CONFIG_SMP */ |
572 | ||
85ac16d0 | 573 | static inline bool alloc_desc_masks(struct irq_desc *desc, int node, |
7f7ace0c MT |
574 | bool boot) |
575 | { | |
576 | return true; | |
577 | } | |
578 | ||
9ec4fa27 YL |
579 | static inline void init_desc_masks(struct irq_desc *desc) |
580 | { | |
581 | } | |
582 | ||
7f7ace0c MT |
583 | static inline void init_copy_desc_masks(struct irq_desc *old_desc, |
584 | struct irq_desc *new_desc) | |
585 | { | |
586 | } | |
587 | ||
9756b15e YL |
588 | static inline void free_desc_masks(struct irq_desc *old_desc, |
589 | struct irq_desc *new_desc) | |
590 | { | |
591 | } | |
7f7ace0c MT |
592 | #endif /* CONFIG_SMP */ |
593 | ||
06fcb0c6 | 594 | #endif /* _LINUX_IRQ_H */ |