[net-next-2.6.git] / include / linux / irq.h

#ifndef _LINUX_IRQ_H
#define _LINUX_IRQ_H

/*
 * Please do not include this file in generic code.  There is currently
 * no requirement for any architecture to implement anything held
 * within this file.
 *
 * Thanks. --rmk
 */

#include <linux/smp.h>

#ifndef CONFIG_S390

#include <linux/linkage.h>
#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>
#include <linux/irqnr.h>
#include <linux/errno.h>

#include <asm/irq.h>
#include <asm/ptrace.h>
#include <asm/irq_regs.h>

struct irq_desc;
typedef	void (*irq_flow_handler_t)(unsigned int irq,
					    struct irq_desc *desc);


/*
 * IRQ line status.
 *
 * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
 *
 * IRQ types
 */
#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */

/* Internal flags */
#define IRQ_INPROGRESS		0x00000100	/* IRQ handler active - do not enter! */
#define IRQ_DISABLED		0x00000200	/* IRQ disabled - do not enter! */
#define IRQ_PENDING		0x00000400	/* IRQ pending - replay on enable */
#define IRQ_REPLAY		0x00000800	/* IRQ has been replayed but not acked yet */
#define IRQ_AUTODETECT		0x00001000	/* IRQ is being autodetected */
#define IRQ_WAITING		0x00002000	/* IRQ not yet seen - for autodetection */
#define IRQ_LEVEL		0x00004000	/* IRQ level triggered */
#define IRQ_MASKED		0x00008000	/* IRQ masked - shouldn't be seen again */
#define IRQ_PER_CPU		0x00010000	/* IRQ is per CPU */
#define IRQ_NOPROBE		0x00020000	/* IRQ is not valid for probing */
#define IRQ_NOREQUEST		0x00040000	/* IRQ cannot be requested */
#define IRQ_NOAUTOEN		0x00080000	/* IRQ will not be enabled on request irq */
#define IRQ_WAKEUP		0x00100000	/* IRQ triggers system wakeup */
#define IRQ_MOVE_PENDING	0x00200000	/* need to re-target IRQ destination */
#define IRQ_NO_BALANCING	0x00400000	/* IRQ is excluded from balancing */
#define IRQ_SPURIOUS_DISABLED	0x00800000	/* IRQ was disabled by the spurious trap */
#define IRQ_MOVE_PCNTXT		0x01000000	/* IRQ migration from process context */
#define IRQ_AFFINITY_SET	0x02000000	/* IRQ affinity was set from userspace*/

#ifdef CONFIG_IRQ_PER_CPU
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
# define IRQ_NO_BALANCING_MASK	(IRQ_PER_CPU | IRQ_NO_BALANCING)
#else
# define CHECK_IRQ_PER_CPU(var) 0
# define IRQ_NO_BALANCING_MASK	IRQ_NO_BALANCING
#endif

struct proc_dir_entry;
struct msi_desc;

/**
 * struct irq_chip - hardware interrupt chip descriptor
 *
 * @name:		name for /proc/interrupts
 * @startup:		start up the interrupt (defaults to ->enable if NULL)
 * @shutdown:		shut down the interrupt (defaults to ->disable if NULL)
 * @enable:		enable the interrupt (defaults to chip->unmask if NULL)
 * @disable:		disable the interrupt (defaults to chip->mask if NULL)
 * @ack:		start of a new interrupt
 * @mask:		mask an interrupt source
 * @mask_ack:		ack and mask an interrupt source
 * @unmask:		unmask an interrupt source
 * @eoi:		end of interrupt - chip level
 * @end:		end of interrupt - flow level
 * @set_affinity:	set the CPU affinity on SMP machines
 * @retrigger:		resend an IRQ to the CPU
 * @set_type:		set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 * @set_wake:		enable/disable power-management wake-on of an IRQ
 *
 * @release:		release function solely used by UML
 * @typename:		obsoleted by name, kept as migration helper
 */
struct irq_chip {
	const char	*name;
	unsigned int	(*startup)(unsigned int irq);
	void		(*shutdown)(unsigned int irq);
	void		(*enable)(unsigned int irq);
	void		(*disable)(unsigned int irq);

	void		(*ack)(unsigned int irq);
	void		(*mask)(unsigned int irq);
	void		(*mask_ack)(unsigned int irq);
	void		(*unmask)(unsigned int irq);
	void		(*eoi)(unsigned int irq);

	void		(*end)(unsigned int irq);
	void		(*set_affinity)(unsigned int irq,
					const struct cpumask *dest);
	int		(*retrigger)(unsigned int irq);
	int		(*set_type)(unsigned int irq, unsigned int flow_type);
	int		(*set_wake)(unsigned int irq, unsigned int on);

	/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
	void		(*release)(unsigned int irq, void *dev_id);
#endif
	/*
	 * For compatibility, ->typename is copied into ->name.
	 * Will disappear.
	 */
	const char	*typename;
};

struct timer_rand_state;
struct irq_2_iommu;
/**
 * struct irq_desc - interrupt descriptor
 * @irq:		interrupt number for this descriptor
 * @timer_rand_state:	pointer to timer rand state struct
 * @kstat_irqs:		irq stats per cpu
 * @irq_2_iommu:	iommu with this irq
 * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
 * @chip:		low level interrupt hardware access
 * @msi_desc:		MSI descriptor
 * @handler_data:	per-IRQ data for the irq_chip methods
 * @chip_data:		platform-specific per-chip private data for the chip
 *			methods, to allow shared chip implementations
 * @action:		the irq action chain
 * @status:		status information
 * @depth:		disable-depth, for nested irq_disable() calls
 * @wake_depth:		enable depth, for multiple set_irq_wake() callers
 * @irq_count:		stats field to detect stalled irqs
 * @last_unhandled:	aging timer for unhandled count
 * @irqs_unhandled:	stats field for spurious unhandled interrupts
 * @lock:		locking for SMP
 * @affinity:		IRQ affinity on SMP
 * @cpu:		cpu index useful for balancing
 * @pending_mask:	pending rebalanced interrupts
 * @dir:		/proc/irq/ procfs entry
 * @name:		flow handler name for /proc/interrupts output
 */
struct irq_desc {
	unsigned int		irq;
	struct timer_rand_state *timer_rand_state;
	unsigned int            *kstat_irqs;
#ifdef CONFIG_INTR_REMAP
	struct irq_2_iommu      *irq_2_iommu;
#endif
	irq_flow_handler_t	handle_irq;
	struct irq_chip		*chip;
	struct msi_desc		*msi_desc;
	void			*handler_data;
	void			*chip_data;
	struct irqaction	*action;	/* IRQ action list */
	unsigned int		status;		/* IRQ status */

	unsigned int		depth;		/* nested irq disables */
	unsigned int		wake_depth;	/* nested wake enables */
	unsigned int		irq_count;	/* For detecting broken IRQs */
	unsigned long		last_unhandled;	/* Aging timer for unhandled count */
	unsigned int		irqs_unhandled;
	spinlock_t		lock;
#ifdef CONFIG_SMP
	cpumask_var_t		affinity;
	unsigned int		cpu;
#ifdef CONFIG_GENERIC_PENDING_IRQ
	cpumask_var_t		pending_mask;
#endif
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry	*dir;
#endif
	const char		*name;
} ____cacheline_internodealigned_in_smp;

extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
					struct irq_desc *desc, int cpu);
extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc);

#ifndef CONFIG_SPARSE_IRQ
extern struct irq_desc irq_desc[NR_IRQS];
#else /* CONFIG_SPARSE_IRQ */
extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int cpu);
#endif /* CONFIG_SPARSE_IRQ */

extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu);

static inline struct irq_desc *
irq_remap_to_desc(unsigned int irq, struct irq_desc *desc)
{
#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
	return irq_to_desc(irq);
#else
	return desc;
#endif
}

/*
 * Migration helpers for obsolete names, they will go away:
 */
#define hw_interrupt_type	irq_chip
#define no_irq_type		no_irq_chip
typedef struct irq_desc		irq_desc_t;

/*
 * Pick up the arch-dependent methods:
 */
#include <asm/hw_irq.h>

extern int setup_irq(unsigned int irq, struct irqaction *new);
extern void remove_irq(unsigned int irq, struct irqaction *act);

#ifdef CONFIG_GENERIC_HARDIRQS

#ifdef CONFIG_SMP

#ifdef CONFIG_GENERIC_PENDING_IRQ

void move_native_irq(int irq);
void move_masked_irq(int irq);

#else /* CONFIG_GENERIC_PENDING_IRQ */

static inline void move_irq(int irq)
{
}

static inline void move_native_irq(int irq)
{
}

static inline void move_masked_irq(int irq)
{
}

#endif /* CONFIG_GENERIC_PENDING_IRQ */

#else /* CONFIG_SMP */

#define move_native_irq(x)
#define move_masked_irq(x)

#endif /* CONFIG_SMP */

extern int no_irq_affinity;

static inline int irq_balancing_disabled(unsigned int irq)
{
	struct irq_desc *desc;

	desc = irq_to_desc(irq);
	return desc->status & IRQ_NO_BALANCING_MASK;
}

/* Handle irq action chains: */
extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);

/*
 * Built-in IRQ handlers for various IRQ types,
 * callable via desc->chip->handle_irq()
 */
extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);

/*
 * Monolithic do_IRQ implementation.
 */
#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
extern unsigned int __do_IRQ(unsigned int irq);
#endif

/*
 * Architectures call this to let the generic IRQ layer
 * handle an interrupt. If the descriptor is attached to an
 * irqchip-style controller then we call the ->handle_irq() handler,
 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
 */
static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
{
#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
	desc->handle_irq(irq, desc);
#else
	if (likely(desc->handle_irq))
		desc->handle_irq(irq, desc);
	else
		__do_IRQ(irq);
#endif
}

static inline void generic_handle_irq(unsigned int irq)
{
	generic_handle_irq_desc(irq, irq_to_desc(irq));
}

/* Handling of unhandled and spurious interrupts: */
extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
			   irqreturn_t action_ret);

/* Resending of interrupts :*/
void check_irq_resend(struct irq_desc *desc, unsigned int irq);

/* Enable/disable irq debugging output: */
extern int noirqdebug_setup(char *str);

/* Checks whether the interrupt can be requested by request_irq(): */
extern int can_request_irq(unsigned int irq, unsigned long irqflags);

/* Dummy irq-chip implementations: */
extern struct irq_chip no_irq_chip;
extern struct irq_chip dummy_irq_chip;

extern void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
			 irq_flow_handler_t handle);
extern void
set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
			      irq_flow_handler_t handle, const char *name);

extern void
__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
		  const char *name);

/* caller has locked the irq_desc and both params are valid */
static inline void __set_irq_handler_unlocked(int irq,
					      irq_flow_handler_t handler)
{
	struct irq_desc *desc;

	desc = irq_to_desc(irq);
	desc->handle_irq = handler;
}

/*
 * Set a highlevel flow handler for a given IRQ:
 */
static inline void
set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
{
	__set_irq_handler(irq, handle, 0, NULL);
}

/*
 * Set a highlevel chained flow handler for a given IRQ.
 * (a chained handler is automatically enabled and set to
 *  IRQ_NOREQUEST and IRQ_NOPROBE)
 */
static inline void
set_irq_chained_handler(unsigned int irq,
			irq_flow_handler_t handle)
{
	__set_irq_handler(irq, handle, 1, NULL);
}

extern void set_irq_noprobe(unsigned int irq);
extern void set_irq_probe(unsigned int irq);

/* Handle dynamic irq creation and destruction */
extern unsigned int create_irq_nr(unsigned int irq_want);
extern int create_irq(void);
extern void destroy_irq(unsigned int irq);

/* Test to see if a driver has successfully requested an irq */
static inline int irq_has_action(unsigned int irq)
{
	struct irq_desc *desc = irq_to_desc(irq);
	return desc->action != NULL;
}

/* Dynamic irq helper functions */
extern void dynamic_irq_init(unsigned int irq);
extern void dynamic_irq_cleanup(unsigned int irq);

/* Set/get chip/data for an IRQ: */
extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
extern int set_irq_data(unsigned int irq, void *data);
extern int set_irq_chip_data(unsigned int irq, void *data);
extern int set_irq_type(unsigned int irq, unsigned int type);
extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);

#define get_irq_chip(irq)	(irq_to_desc(irq)->chip)
#define get_irq_chip_data(irq)	(irq_to_desc(irq)->chip_data)
#define get_irq_data(irq)	(irq_to_desc(irq)->handler_data)
#define get_irq_msi(irq)	(irq_to_desc(irq)->msi_desc)

#define get_irq_desc_chip(desc)		((desc)->chip)
#define get_irq_desc_chip_data(desc)	((desc)->chip_data)
#define get_irq_desc_data(desc)		((desc)->handler_data)
#define get_irq_desc_msi(desc)		((desc)->msi_desc)

#endif /* CONFIG_GENERIC_HARDIRQS */

#endif /* !CONFIG_S390 */

#ifdef CONFIG_SMP
/**
 * init_alloc_desc_masks - allocate cpumasks for irq_desc
 * @desc:	pointer to irq_desc struct
 * @cpu:	cpu which will be handling the cpumasks
 * @boot:	true if need bootmem
 *
 * Allocates affinity and pending_mask cpumask if required.
 * Returns true if successful (or not required).
 * Side effect: affinity has all bits set, pending_mask has all bits clear.
 */
static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
								bool boot)
{
	int node;

	if (boot) {
		alloc_bootmem_cpumask_var(&desc->affinity);
		cpumask_setall(desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
		alloc_bootmem_cpumask_var(&desc->pending_mask);
		cpumask_clear(desc->pending_mask);
#endif
		return true;
	}

	node = cpu_to_node(cpu);

	if (!alloc_cpumask_var_node(&desc->affinity, GFP_ATOMIC, node))
		return false;
	cpumask_setall(desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
	if (!alloc_cpumask_var_node(&desc->pending_mask, GFP_ATOMIC, node)) {
		free_cpumask_var(desc->affinity);
		return false;
	}
	cpumask_clear(desc->pending_mask);
#endif
	return true;
}

/**
 * init_copy_desc_masks - copy cpumasks for irq_desc
 * @old_desc:	pointer to old irq_desc struct
 * @new_desc:	pointer to new irq_desc struct
 *
 * Insures affinity and pending_masks are copied to new irq_desc.
 * If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
 * irq_desc struct so the copy is redundant.
 */

static inline void init_copy_desc_masks(struct irq_desc *old_desc,
					struct irq_desc *new_desc)
{
#ifdef CONFIG_CPUMASKS_OFFSTACK
	cpumask_copy(new_desc->affinity, old_desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
	cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
#endif
#endif
}

#else /* !CONFIG_SMP */

static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
								bool boot)
{
	return true;
}

static inline void init_copy_desc_masks(struct irq_desc *old_desc,
					struct irq_desc *new_desc)
{
}

#endif	/* CONFIG_SMP */

#endif /* _LINUX_IRQ_H */
Commit	Line	Data
06fcb0c6 IM	1	#ifndef _LINUX_IRQ_H
06fcb0c6 IM	2	#define _LINUX_IRQ_H
1da177e4 LT	3
	4	/*
	5	* Please do not include this file in generic code. There is currently
	6	* no requirement for any architecture to implement anything held
	7	* within this file.
	8	*
	9	* Thanks. --rmk
	10	*/
	11
23f9b317	12	#include <linux/smp.h>
1da177e4	13
06fcb0c6	14	#ifndef CONFIG_S390
1da177e4 LT	15
	16	#include <linux/linkage.h>
	17	#include <linux/cache.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/cpumask.h>
908dcecd	20	#include <linux/irqreturn.h>
dd3a1db9	21	#include <linux/irqnr.h>
77904fd6	22	#include <linux/errno.h>
1da177e4 LT	23
	24	#include <asm/irq.h>
	25	#include <asm/ptrace.h>
7d12e780	26	#include <asm/irq_regs.h>
1da177e4	27
57a58a94	28	struct irq_desc;
ec701584	29	typedef void (*irq_flow_handler_t)(unsigned int irq,
7d12e780	30	struct irq_desc *desc);
57a58a94 DH	31
57a58a94 DH	32
1da177e4 LT	33	/*
1da177e4 LT	34	* IRQ line status.
6e213616	35	*
950f4427	36	* Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
6e213616 TG	37	*
6e213616 TG	38	* IRQ types
1da177e4	39	*/
6e213616 TG	40	#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
	41	#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
	42	#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
	43	#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING)
	44	#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
	45	#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
	46	#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
	47	#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
	48
	49	/* Internal flags */
950f4427 TG	50	#define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */
	51	#define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */
	52	#define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */
	53	#define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */
	54	#define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */
	55	#define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */
	56	#define IRQ_LEVEL 0x00004000 /* IRQ level triggered */
	57	#define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */
	58	#define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */
	59	#define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */
	60	#define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */
	61	#define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */
d7e25f33 IM	62	#define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */
	63	#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
	64	#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
1adb0850	65	#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
f6d87f4b TG	66	#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
f6d87f4b TG	67	#define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/
950f4427	68
0d7012a9	69	#ifdef CONFIG_IRQ_PER_CPU
f26fdd59	70	# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
950f4427	71	# define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU \| IRQ_NO_BALANCING)
f26fdd59 KW	72	#else
f26fdd59 KW	73	# define CHECK_IRQ_PER_CPU(var) 0
950f4427	74	# define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING
f26fdd59	75	#endif
1da177e4	76
6a6de9ef	77	struct proc_dir_entry;
5b912c10	78	struct msi_desc;
6a6de9ef	79
8fee5c36	80	/**
6a6de9ef	81	* struct irq_chip - hardware interrupt chip descriptor
8fee5c36 IM	82	*
	83	* @name: name for /proc/interrupts
	84	* @startup: start up the interrupt (defaults to ->enable if NULL)
	85	* @shutdown: shut down the interrupt (defaults to ->disable if NULL)
	86	* @enable: enable the interrupt (defaults to chip->unmask if NULL)
	87	* @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36 IM	88	* @ack: start of a new interrupt
	89	* @mask: mask an interrupt source
	90	* @mask_ack: ack and mask an interrupt source
	91	* @unmask: unmask an interrupt source
47c2a3aa IM	92	* @eoi: end of interrupt - chip level
47c2a3aa IM	93	* @end: end of interrupt - flow level
8fee5c36 IM	94	* @set_affinity: set the CPU affinity on SMP machines
	95	* @retrigger: resend an IRQ to the CPU
	96	* @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
	97	* @set_wake: enable/disable power-management wake-on of an IRQ
	98	*
	99	* @release: release function solely used by UML
6a6de9ef	100	* @typename: obsoleted by name, kept as migration helper
1da177e4	101	*/
6a6de9ef TG	102	struct irq_chip {
6a6de9ef TG	103	const char *name;
71d218b7 IM	104	unsigned int (*startup)(unsigned int irq);
	105	void (*shutdown)(unsigned int irq);
	106	void (*enable)(unsigned int irq);
	107	void (*disable)(unsigned int irq);
6a6de9ef	108
71d218b7	109	void (*ack)(unsigned int irq);
6a6de9ef TG	110	void (*mask)(unsigned int irq);
	111	void (*mask_ack)(unsigned int irq);
	112	void (*unmask)(unsigned int irq);
47c2a3aa	113	void (*eoi)(unsigned int irq);
6a6de9ef	114
71d218b7	115	void (*end)(unsigned int irq);
0de26520 RR	116	void (*set_affinity)(unsigned int irq,
0de26520 RR	117	const struct cpumask *dest);
c0ad90a3	118	int (*retrigger)(unsigned int irq);
6a6de9ef TG	119	int (*set_type)(unsigned int irq, unsigned int flow_type);
6a6de9ef TG	120	int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3	121
b77d6adc PBG	122	/* Currently used only by UML, might disappear one day.*/
b77d6adc PBG	123	#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7	124	void (release)(unsigned int irq, void dev_id);
b77d6adc	125	#endif
6a6de9ef TG	126	/*
	127	* For compatibility, ->typename is copied into ->name.
	128	* Will disappear.
	129	*/
	130	const char *typename;
1da177e4 LT	131	};
1da177e4 LT	132
0b8f1efa YL	133	struct timer_rand_state;
0b8f1efa YL	134	struct irq_2_iommu;
8fee5c36 IM	135	/**
8fee5c36 IM	136	* struct irq_desc - interrupt descriptor
2ed1cdcf	137	* @irq: interrupt number for this descriptor
078a55db YL	138	* @timer_rand_state: pointer to timer rand state struct
	139	* @kstat_irqs: irq stats per cpu
	140	* @irq_2_iommu: iommu with this irq
6a6de9ef TG	141	* @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
6a6de9ef TG	142	* @chip: low level interrupt hardware access
472900b8	143	* @msi_desc: MSI descriptor
6a6de9ef TG	144	* @handler_data: per-IRQ data for the irq_chip methods
	145	* @chip_data: platform-specific per-chip private data for the chip
	146	* methods, to allow shared chip implementations
8fee5c36 IM	147	* @action: the irq action chain
	148	* @status: status information
	149	* @depth: disable-depth, for nested irq_disable() calls
15a647eb	150	* @wake_depth: enable depth, for multiple set_irq_wake() callers
8fee5c36	151	* @irq_count: stats field to detect stalled irqs
5ac4d823	152	* @last_unhandled: aging timer for unhandled count
e262a7ba	153	* @irqs_unhandled: stats field for spurious unhandled interrupts
8fee5c36 IM	154	* @lock: locking for SMP
8fee5c36 IM	155	* @affinity: IRQ affinity on SMP
6a6de9ef	156	* @cpu: cpu index useful for balancing
8fee5c36	157	* @pending_mask: pending rebalanced interrupts
8fee5c36	158	* @dir: /proc/irq/ procfs entry
a460e745	159	* @name: flow handler name for /proc/interrupts output
1da177e4	160	*/
34ffdb72	161	struct irq_desc {
08678b08	162	unsigned int irq;
0b8f1efa YL	163	struct timer_rand_state *timer_rand_state;
0b8f1efa YL	164	unsigned int *kstat_irqs;
d7e51e66	165	#ifdef CONFIG_INTR_REMAP
0b8f1efa	166	struct irq_2_iommu *irq_2_iommu;
0b8f1efa	167	#endif
57a58a94	168	irq_flow_handler_t handle_irq;
6a6de9ef	169	struct irq_chip *chip;
5b912c10	170	struct msi_desc *msi_desc;
6a6de9ef	171	void *handler_data;
71d218b7 IM	172	void *chip_data;
	173	struct irqaction action; / IRQ action list */
	174	unsigned int status; /* IRQ status */
6a6de9ef	175
71d218b7	176	unsigned int depth; /* nested irq disables */
15a647eb	177	unsigned int wake_depth; /* nested wake enables */
71d218b7	178	unsigned int irq_count; /* For detecting broken IRQs */
4f27c00b	179	unsigned long last_unhandled; /* Aging timer for unhandled count */
e262a7ba	180	unsigned int irqs_unhandled;
71d218b7	181	spinlock_t lock;
a53da52f	182	#ifdef CONFIG_SMP
7f7ace0c	183	cpumask_var_t affinity;
6a6de9ef	184	unsigned int cpu;
8b8e8c1b	185	#ifdef CONFIG_GENERIC_PENDING_IRQ
7f7ace0c MT	186	cpumask_var_t pending_mask;
7f7ace0c MT	187	#endif
54d5d424	188	#endif
4a733ee1	189	#ifdef CONFIG_PROC_FS
a460e745	190	struct proc_dir_entry *dir;
4a733ee1	191	#endif
a460e745	192	const char *name;
e729aa16	193	} ____cacheline_internodealigned_in_smp;
1da177e4	194
0b8f1efa YL	195	extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
	196	struct irq_desc *desc, int cpu);
	197	extern void arch_free_chip_data(struct irq_desc old_desc, struct irq_desc desc);
9059d8fa	198
0b8f1efa	199	#ifndef CONFIG_SPARSE_IRQ
34ffdb72	200	extern struct irq_desc irq_desc[NR_IRQS];
f9af0e70	201	#else /* CONFIG_SPARSE_IRQ */
0b8f1efa	202	extern struct irq_desc move_irq_desc(struct irq_desc old_desc, int cpu);
d7e51e66	203	#endif /* CONFIG_SPARSE_IRQ */
0b8f1efa	204
f9af0e70	205	extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu);
0b8f1efa	206
48a1b10a YL	207	static inline struct irq_desc *
	208	irq_remap_to_desc(unsigned int irq, struct irq_desc *desc)
	209	{
	210	#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
	211	return irq_to_desc(irq);
	212	#else
	213	return desc;
	214	#endif
c6b7674f TG	215	}
c6b7674f TG	216
34ffdb72 IM	217	/*
	218	* Migration helpers for obsolete names, they will go away:
	219	*/
6a6de9ef	220	#define hw_interrupt_type irq_chip
6a6de9ef	221	#define no_irq_type no_irq_chip
34ffdb72 IM	222	typedef struct irq_desc irq_desc_t;
	223
	224	/*
	225	* Pick up the arch-dependent methods:
	226	*/
	227	#include <asm/hw_irq.h>
1da177e4	228
06fcb0c6	229	extern int setup_irq(unsigned int irq, struct irqaction *new);
cbf94f06	230	extern void remove_irq(unsigned int irq, struct irqaction *act);
1da177e4 LT	231
1da177e4 LT	232	#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6	233
54d5d424 AR	234	#ifdef CONFIG_SMP
54d5d424 AR	235
8b8e8c1b	236	#ifdef CONFIG_GENERIC_PENDING_IRQ
54d5d424	237
c777ac55	238	void move_native_irq(int irq);
e7b946e9	239	void move_masked_irq(int irq);
54d5d424	240
8b8e8c1b	241	#else /* CONFIG_GENERIC_PENDING_IRQ */
06fcb0c6 IM	242
	243	static inline void move_irq(int irq)
	244	{
	245	}
	246
	247	static inline void move_native_irq(int irq)
	248	{
	249	}
	250
e7b946e9 EB	251	static inline void move_masked_irq(int irq)
	252	{
	253	}
	254
06fcb0c6	255	#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424	256
06fcb0c6	257	#else /* CONFIG_SMP */
54d5d424	258
54d5d424	259	#define move_native_irq(x)
e7b946e9	260	#define move_masked_irq(x)
54d5d424	261
06fcb0c6	262	#endif /* CONFIG_SMP */
54d5d424	263
1da177e4	264	extern int no_irq_affinity;
1da177e4	265
950f4427 TG	266	static inline int irq_balancing_disabled(unsigned int irq)
950f4427 TG	267	{
08678b08 YL	268	struct irq_desc *desc;
	269
	270	desc = irq_to_desc(irq);
	271	return desc->status & IRQ_NO_BALANCING_MASK;
950f4427 TG	272	}
950f4427 TG	273
6a6de9ef	274	/* Handle irq action chains: */
bedd30d9	275	extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);
6a6de9ef TG	276
	277	/*
	278	* Built-in IRQ handlers for various IRQ types,
	279	* callable via desc->chip->handle_irq()
	280	*/
ec701584 HH	281	extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
	282	extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
	283	extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
	284	extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
	285	extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
	286	extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
6a6de9ef	287
2e60bbb6	288	/*
6a6de9ef	289	* Monolithic do_IRQ implementation.
2e60bbb6	290	*/
af8c65b5	291	#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
ec701584	292	extern unsigned int __do_IRQ(unsigned int irq);
af8c65b5	293	#endif
2e60bbb6	294
dae86204 IM	295	/*
	296	* Architectures call this to let the generic IRQ layer
	297	* handle an interrupt. If the descriptor is attached to an
	298	* irqchip-style controller then we call the ->handle_irq() handler,
	299	* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
	300	*/
46926b67	301	static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
dae86204	302	{
af8c65b5	303	#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
7d12e780	304	desc->handle_irq(irq, desc);
af8c65b5	305	#else
dae86204	306	if (likely(desc->handle_irq))
7d12e780	307	desc->handle_irq(irq, desc);
dae86204	308	else
7d12e780	309	__do_IRQ(irq);
af8c65b5	310	#endif
dae86204 IM	311	}
dae86204 IM	312
46926b67 YL	313	static inline void generic_handle_irq(unsigned int irq)
	314	{
	315	generic_handle_irq_desc(irq, irq_to_desc(irq));
	316	}
	317
6a6de9ef	318	/* Handling of unhandled and spurious interrupts: */
34ffdb72	319	extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
bedd30d9	320	irqreturn_t action_ret);
1da177e4	321
a4633adc TG	322	/* Resending of interrupts :*/
	323	void check_irq_resend(struct irq_desc *desc, unsigned int irq);
	324
6a6de9ef TG	325	/* Enable/disable irq debugging output: */
	326	extern int noirqdebug_setup(char *str);
	327
	328	/* Checks whether the interrupt can be requested by request_irq(): */
	329	extern int can_request_irq(unsigned int irq, unsigned long irqflags);
	330
f8b5473f	331	/* Dummy irq-chip implementations: */
6a6de9ef	332	extern struct irq_chip no_irq_chip;
f8b5473f	333	extern struct irq_chip dummy_irq_chip;
6a6de9ef	334
145fc655 IM	335	extern void
	336	set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
	337	irq_flow_handler_t handle);
6a6de9ef	338	extern void
a460e745 IM	339	set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
	340	irq_flow_handler_t handle, const char *name);
	341
6a6de9ef	342	extern void
a460e745 IM	343	__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 IM	344	const char *name);
1da177e4	345
b019e573 KH	346	/* caller has locked the irq_desc and both params are valid */
	347	static inline void __set_irq_handler_unlocked(int irq,
	348	irq_flow_handler_t handler)
	349	{
08678b08 YL	350	struct irq_desc *desc;
	351
	352	desc = irq_to_desc(irq);
	353	desc->handle_irq = handler;
b019e573 KH	354	}
b019e573 KH	355
6a6de9ef TG	356	/*
	357	* Set a highlevel flow handler for a given IRQ:
	358	*/
	359	static inline void
57a58a94	360	set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef	361	{
a460e745	362	__set_irq_handler(irq, handle, 0, NULL);
6a6de9ef TG	363	}
	364
	365	/*
	366	* Set a highlevel chained flow handler for a given IRQ.
	367	* (a chained handler is automatically enabled and set to
	368	* IRQ_NOREQUEST and IRQ_NOPROBE)
	369	*/
	370	static inline void
	371	set_irq_chained_handler(unsigned int irq,
57a58a94	372	irq_flow_handler_t handle)
6a6de9ef	373	{
a460e745	374	__set_irq_handler(irq, handle, 1, NULL);
6a6de9ef TG	375	}
6a6de9ef TG	376
46f4f8f6 RB	377	extern void set_irq_noprobe(unsigned int irq);
	378	extern void set_irq_probe(unsigned int irq);
	379
3a16d713	380	/* Handle dynamic irq creation and destruction */
6d50bc26	381	extern unsigned int create_irq_nr(unsigned int irq_want);
3a16d713 EB	382	extern int create_irq(void);
	383	extern void destroy_irq(unsigned int irq);
	384
1f80025e EB	385	/* Test to see if a driver has successfully requested an irq */
	386	static inline int irq_has_action(unsigned int irq)
	387	{
08678b08	388	struct irq_desc *desc = irq_to_desc(irq);
1f80025e EB	389	return desc->action != NULL;
	390	}
	391
3a16d713 EB	392	/* Dynamic irq helper functions */
	393	extern void dynamic_irq_init(unsigned int irq);
	394	extern void dynamic_irq_cleanup(unsigned int irq);
dd87eb3a	395
3a16d713	396	/* Set/get chip/data for an IRQ: */
dd87eb3a TG	397	extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
	398	extern int set_irq_data(unsigned int irq, void *data);
	399	extern int set_irq_chip_data(unsigned int irq, void *data);
	400	extern int set_irq_type(unsigned int irq, unsigned int type);
5b912c10	401	extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);
dd87eb3a	402
08678b08 YL	403	#define get_irq_chip(irq) (irq_to_desc(irq)->chip)
	404	#define get_irq_chip_data(irq) (irq_to_desc(irq)->chip_data)
	405	#define get_irq_data(irq) (irq_to_desc(irq)->handler_data)
	406	#define get_irq_msi(irq) (irq_to_desc(irq)->msi_desc)
dd87eb3a	407
0b8f1efa YL	408	#define get_irq_desc_chip(desc) ((desc)->chip)
	409	#define get_irq_desc_chip_data(desc) ((desc)->chip_data)
	410	#define get_irq_desc_data(desc) ((desc)->handler_data)
	411	#define get_irq_desc_msi(desc) ((desc)->msi_desc)
	412
6a6de9ef	413	#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4	414
06fcb0c6	415	#endif /* !CONFIG_S390 */
1da177e4	416
7f7ace0c MT	417	#ifdef CONFIG_SMP
	418	/**
	419	* init_alloc_desc_masks - allocate cpumasks for irq_desc
	420	* @desc: pointer to irq_desc struct
802bf931	421	* @cpu: cpu which will be handling the cpumasks
7f7ace0c MT	422	* @boot: true if need bootmem
	423	*
	424	* Allocates affinity and pending_mask cpumask if required.
	425	* Returns true if successful (or not required).
	426	* Side effect: affinity has all bits set, pending_mask has all bits clear.
	427	*/
802bf931	428	static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
7f7ace0c MT	429	bool boot)
7f7ace0c MT	430	{
802bf931 MT	431	int node;
802bf931 MT	432
7f7ace0c MT	433	if (boot) {
	434	alloc_bootmem_cpumask_var(&desc->affinity);
	435	cpumask_setall(desc->affinity);
	436
	437	#ifdef CONFIG_GENERIC_PENDING_IRQ
	438	alloc_bootmem_cpumask_var(&desc->pending_mask);
	439	cpumask_clear(desc->pending_mask);
	440	#endif
	441	return true;
	442	}
	443
802bf931 MT	444	node = cpu_to_node(cpu);
802bf931 MT	445
7f7ace0c MT	446	if (!alloc_cpumask_var_node(&desc->affinity, GFP_ATOMIC, node))
	447	return false;
	448	cpumask_setall(desc->affinity);
	449
	450	#ifdef CONFIG_GENERIC_PENDING_IRQ
	451	if (!alloc_cpumask_var_node(&desc->pending_mask, GFP_ATOMIC, node)) {
	452	free_cpumask_var(desc->affinity);
	453	return false;
	454	}
	455	cpumask_clear(desc->pending_mask);
	456	#endif
	457	return true;
	458	}
	459
	460	/**
	461	* init_copy_desc_masks - copy cpumasks for irq_desc
	462	* @old_desc: pointer to old irq_desc struct
	463	* @new_desc: pointer to new irq_desc struct
	464	*
	465	* Insures affinity and pending_masks are copied to new irq_desc.
	466	* If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
	467	* irq_desc struct so the copy is redundant.
	468	*/
	469
	470	static inline void init_copy_desc_masks(struct irq_desc *old_desc,
	471	struct irq_desc *new_desc)
	472	{
	473	#ifdef CONFIG_CPUMASKS_OFFSTACK
	474	cpumask_copy(new_desc->affinity, old_desc->affinity);
	475
	476	#ifdef CONFIG_GENERIC_PENDING_IRQ
	477	cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
	478	#endif
	479	#endif
	480	}
	481
	482	#else /* !CONFIG_SMP */
	483
802bf931	484	static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
7f7ace0c MT	485	bool boot)
	486	{
	487	return true;
	488	}
	489
	490	static inline void init_copy_desc_masks(struct irq_desc *old_desc,
	491	struct irq_desc *new_desc)
	492	{
	493	}
	494
	495	#endif /* CONFIG_SMP */
	496
06fcb0c6	497	#endif /* _LINUX_IRQ_H */