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genirq: Provide compat handling for chip->retrigger()
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06fcb0c6
IM
1#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
1da177e4
LT
3
4/*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
23f9b317 12#include <linux/smp.h>
1da177e4 13
06fcb0c6 14#ifndef CONFIG_S390
1da177e4
LT
15
16#include <linux/linkage.h>
17#include <linux/cache.h>
18#include <linux/spinlock.h>
19#include <linux/cpumask.h>
503e5763 20#include <linux/gfp.h>
908dcecd 21#include <linux/irqreturn.h>
dd3a1db9 22#include <linux/irqnr.h>
77904fd6 23#include <linux/errno.h>
503e5763 24#include <linux/topology.h>
3aa551c9 25#include <linux/wait.h>
1da177e4
LT
26
27#include <asm/irq.h>
28#include <asm/ptrace.h>
7d12e780 29#include <asm/irq_regs.h>
1da177e4 30
57a58a94 31struct irq_desc;
ec701584 32typedef void (*irq_flow_handler_t)(unsigned int irq,
7d12e780 33 struct irq_desc *desc);
57a58a94
DH
34
35
1da177e4
LT
36/*
37 * IRQ line status.
6e213616 38 *
950f4427 39 * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
6e213616
TG
40 *
41 * IRQ types
1da177e4 42 */
6e213616
TG
43#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
44#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
45#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
46#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
47#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
48#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
49#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
50#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
51
52/* Internal flags */
950f4427
TG
53#define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */
54#define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */
55#define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */
56#define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */
57#define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */
58#define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */
59#define IRQ_LEVEL 0x00004000 /* IRQ level triggered */
60#define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */
61#define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */
62#define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */
63#define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */
64#define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */
d7e25f33
IM
65#define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */
66#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
67#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
1adb0850 68#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
f6d87f4b
TG
69#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
70#define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/
0a0c5168 71#define IRQ_SUSPENDED 0x04000000 /* IRQ has gone through suspend sequence */
b25c340c 72#define IRQ_ONESHOT 0x08000000 /* IRQ is not unmasked after hardirq */
399b5da2 73#define IRQ_NESTED_THREAD 0x10000000 /* IRQ is nested into another, no own handler thread */
950f4427 74
0d7012a9 75#ifdef CONFIG_IRQ_PER_CPU
f26fdd59 76# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
950f4427 77# define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
f26fdd59
KW
78#else
79# define CHECK_IRQ_PER_CPU(var) 0
950f4427 80# define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING
f26fdd59 81#endif
1da177e4 82
6a6de9ef 83struct proc_dir_entry;
5b912c10 84struct msi_desc;
6a6de9ef 85
ff7dcd44
TG
86/**
87 * struct irq_data - per irq and irq chip data passed down to chip functions
88 * @irq: interrupt number
89 * @node: node index useful for balancing
90 * @chip: low level interrupt hardware access
91 * @handler_data: per-IRQ data for the irq_chip methods
92 * @chip_data: platform-specific per-chip private data for the chip
93 * methods, to allow shared chip implementations
94 * @msi_desc: MSI descriptor
95 * @affinity: IRQ affinity on SMP
96 * @irq_2_iommu: iommu with this irq
97 *
98 * The fields here need to overlay the ones in irq_desc until we
99 * cleaned up the direct references and switched everything over to
100 * irq_data.
101 */
102struct irq_data {
103 unsigned int irq;
104 unsigned int node;
105 struct irq_chip *chip;
106 void *handler_data;
107 void *chip_data;
108 struct msi_desc *msi_desc;
109#ifdef CONFIG_SMP
110 cpumask_var_t affinity;
111#endif
112#ifdef CONFIG_INTR_REMAP
113 struct irq_2_iommu *irq_2_iommu;
114#endif
115};
116
8fee5c36 117/**
6a6de9ef 118 * struct irq_chip - hardware interrupt chip descriptor
8fee5c36
IM
119 *
120 * @name: name for /proc/interrupts
f8822657
TG
121 * @startup: deprecated, replaced by irq_startup
122 * @shutdown: deprecated, replaced by irq_shutdown
123 * @enable: deprecated, replaced by irq_enable
124 * @disable: deprecated, replaced by irq_disable
125 * @ack: deprecated, replaced by irq_ack
126 * @mask: deprecated, replaced by irq_mask
127 * @mask_ack: deprecated, replaced by irq_mask_ack
128 * @unmask: deprecated, replaced by irq_unmask
129 * @eoi: deprecated, replaced by irq_eoi
130 * @end: deprecated, will go away with __do_IRQ()
131 * @set_affinity: deprecated, replaced by irq_set_affinity
132 * @retrigger: deprecated, replaced by irq_retrigger
133 * @set_type: deprecated, replaced by irq_set_type
134 * @set_wake: deprecated, replaced by irq_wake
135 * @bus_lock: deprecated, replaced by irq_bus_lock
136 * @bus_sync_unlock: deprecated, replaced by irq_bus_sync_unlock
8fee5c36 137 *
f8822657
TG
138 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
139 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
140 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
141 * @irq_disable: disable the interrupt
142 * @irq_ack: start of a new interrupt
143 * @irq_mask: mask an interrupt source
144 * @irq_mask_ack: ack and mask an interrupt source
145 * @irq_unmask: unmask an interrupt source
146 * @irq_eoi: end of interrupt
147 * @irq_set_affinity: set the CPU affinity on SMP machines
148 * @irq_retrigger: resend an IRQ to the CPU
149 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
150 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
151 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
152 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
70aedd24 153 *
8fee5c36 154 * @release: release function solely used by UML
1da177e4 155 */
6a6de9ef
TG
156struct irq_chip {
157 const char *name;
71d218b7
IM
158 unsigned int (*startup)(unsigned int irq);
159 void (*shutdown)(unsigned int irq);
160 void (*enable)(unsigned int irq);
161 void (*disable)(unsigned int irq);
6a6de9ef 162
71d218b7 163 void (*ack)(unsigned int irq);
6a6de9ef
TG
164 void (*mask)(unsigned int irq);
165 void (*mask_ack)(unsigned int irq);
166 void (*unmask)(unsigned int irq);
47c2a3aa 167 void (*eoi)(unsigned int irq);
6a6de9ef 168
71d218b7 169 void (*end)(unsigned int irq);
d5dedd45 170 int (*set_affinity)(unsigned int irq,
0de26520 171 const struct cpumask *dest);
c0ad90a3 172 int (*retrigger)(unsigned int irq);
6a6de9ef
TG
173 int (*set_type)(unsigned int irq, unsigned int flow_type);
174 int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3 175
70aedd24
TG
176 void (*bus_lock)(unsigned int irq);
177 void (*bus_sync_unlock)(unsigned int irq);
178
f8822657
TG
179 unsigned int (*irq_startup)(struct irq_data *data);
180 void (*irq_shutdown)(struct irq_data *data);
181 void (*irq_enable)(struct irq_data *data);
182 void (*irq_disable)(struct irq_data *data);
183
184 void (*irq_ack)(struct irq_data *data);
185 void (*irq_mask)(struct irq_data *data);
186 void (*irq_mask_ack)(struct irq_data *data);
187 void (*irq_unmask)(struct irq_data *data);
188 void (*irq_eoi)(struct irq_data *data);
189
190 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
191 int (*irq_retrigger)(struct irq_data *data);
192 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
193 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
194
195 void (*irq_bus_lock)(struct irq_data *data);
196 void (*irq_bus_sync_unlock)(struct irq_data *data);
197
b77d6adc
PBG
198 /* Currently used only by UML, might disappear one day.*/
199#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7 200 void (*release)(unsigned int irq, void *dev_id);
b77d6adc 201#endif
1da177e4
LT
202};
203
0b8f1efa
YL
204struct timer_rand_state;
205struct irq_2_iommu;
8fee5c36
IM
206/**
207 * struct irq_desc - interrupt descriptor
ff7dcd44 208 * @irq_data: per irq and chip data passed down to chip functions
078a55db
YL
209 * @timer_rand_state: pointer to timer rand state struct
210 * @kstat_irqs: irq stats per cpu
6a6de9ef 211 * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
8fee5c36
IM
212 * @action: the irq action chain
213 * @status: status information
214 * @depth: disable-depth, for nested irq_disable() calls
15a647eb 215 * @wake_depth: enable depth, for multiple set_irq_wake() callers
8fee5c36 216 * @irq_count: stats field to detect stalled irqs
5ac4d823 217 * @last_unhandled: aging timer for unhandled count
e262a7ba 218 * @irqs_unhandled: stats field for spurious unhandled interrupts
8fee5c36 219 * @lock: locking for SMP
8fee5c36 220 * @pending_mask: pending rebalanced interrupts
3aa551c9
TG
221 * @threads_active: number of irqaction threads currently running
222 * @wait_for_threads: wait queue for sync_irq to wait for threaded handlers
8fee5c36 223 * @dir: /proc/irq/ procfs entry
a460e745 224 * @name: flow handler name for /proc/interrupts output
1da177e4 225 */
34ffdb72 226struct irq_desc {
ff7dcd44
TG
227
228 /*
229 * This union will go away, once we fixed the direct access to
230 * irq_desc all over the place. The direct fields are a 1:1
231 * overlay of irq_data.
232 */
233 union {
234 struct irq_data irq_data;
235 struct {
236 unsigned int irq;
237 unsigned int node;
238 struct irq_chip *chip;
239 void *handler_data;
240 void *chip_data;
241 struct msi_desc *msi_desc;
242#ifdef CONFIG_SMP
243 cpumask_var_t affinity;
244#endif
d7e51e66 245#ifdef CONFIG_INTR_REMAP
ff7dcd44 246 struct irq_2_iommu *irq_2_iommu;
0b8f1efa 247#endif
ff7dcd44
TG
248 };
249 };
250 struct timer_rand_state *timer_rand_state;
251 unsigned int *kstat_irqs;
57a58a94 252 irq_flow_handler_t handle_irq;
71d218b7
IM
253 struct irqaction *action; /* IRQ action list */
254 unsigned int status; /* IRQ status */
6a6de9ef 255
71d218b7 256 unsigned int depth; /* nested irq disables */
15a647eb 257 unsigned int wake_depth; /* nested wake enables */
71d218b7 258 unsigned int irq_count; /* For detecting broken IRQs */
4f27c00b 259 unsigned long last_unhandled; /* Aging timer for unhandled count */
e262a7ba 260 unsigned int irqs_unhandled;
239007b8 261 raw_spinlock_t lock;
a53da52f 262#ifdef CONFIG_SMP
e7a297b0 263 const struct cpumask *affinity_hint;
8b8e8c1b 264#ifdef CONFIG_GENERIC_PENDING_IRQ
7f7ace0c
MT
265 cpumask_var_t pending_mask;
266#endif
54d5d424 267#endif
3aa551c9
TG
268 atomic_t threads_active;
269 wait_queue_head_t wait_for_threads;
4a733ee1 270#ifdef CONFIG_PROC_FS
a460e745 271 struct proc_dir_entry *dir;
4a733ee1 272#endif
a460e745 273 const char *name;
e729aa16 274} ____cacheline_internodealigned_in_smp;
1da177e4 275
0b8f1efa 276extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
85ac16d0 277 struct irq_desc *desc, int node);
0b8f1efa 278extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc);
9059d8fa 279
0b8f1efa 280#ifndef CONFIG_SPARSE_IRQ
34ffdb72 281extern struct irq_desc irq_desc[NR_IRQS];
15e957d0
YL
282#endif
283
284#ifdef CONFIG_NUMA_IRQ_DESC
85ac16d0 285extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int node);
15e957d0
YL
286#else
287static inline struct irq_desc *move_irq_desc(struct irq_desc *desc, int node)
288{
289 return desc;
290}
291#endif
0b8f1efa 292
85ac16d0 293extern struct irq_desc *irq_to_desc_alloc_node(unsigned int irq, int node);
0b8f1efa 294
34ffdb72
IM
295/*
296 * Pick up the arch-dependent methods:
297 */
298#include <asm/hw_irq.h>
1da177e4 299
06fcb0c6 300extern int setup_irq(unsigned int irq, struct irqaction *new);
cbf94f06 301extern void remove_irq(unsigned int irq, struct irqaction *act);
1da177e4
LT
302
303#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6 304
54d5d424
AR
305#ifdef CONFIG_SMP
306
8b8e8c1b 307#ifdef CONFIG_GENERIC_PENDING_IRQ
54d5d424 308
c777ac55 309void move_native_irq(int irq);
e7b946e9 310void move_masked_irq(int irq);
54d5d424 311
8b8e8c1b 312#else /* CONFIG_GENERIC_PENDING_IRQ */
06fcb0c6
IM
313
314static inline void move_irq(int irq)
315{
316}
317
318static inline void move_native_irq(int irq)
319{
320}
321
e7b946e9
EB
322static inline void move_masked_irq(int irq)
323{
324}
325
06fcb0c6 326#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424 327
06fcb0c6 328#else /* CONFIG_SMP */
54d5d424 329
54d5d424 330#define move_native_irq(x)
e7b946e9 331#define move_masked_irq(x)
54d5d424 332
06fcb0c6 333#endif /* CONFIG_SMP */
54d5d424 334
1da177e4 335extern int no_irq_affinity;
1da177e4 336
950f4427
TG
337static inline int irq_balancing_disabled(unsigned int irq)
338{
08678b08
YL
339 struct irq_desc *desc;
340
341 desc = irq_to_desc(irq);
342 return desc->status & IRQ_NO_BALANCING_MASK;
950f4427
TG
343}
344
6a6de9ef 345/* Handle irq action chains: */
bedd30d9 346extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);
6a6de9ef
TG
347
348/*
349 * Built-in IRQ handlers for various IRQ types,
bebd04cc 350 * callable via desc->handle_irq()
6a6de9ef 351 */
ec701584
HH
352extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
353extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
354extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
355extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
356extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
357extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
31b47cf7 358extern void handle_nested_irq(unsigned int irq);
6a6de9ef 359
2e60bbb6 360/*
6a6de9ef 361 * Monolithic do_IRQ implementation.
2e60bbb6 362 */
af8c65b5 363#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
ec701584 364extern unsigned int __do_IRQ(unsigned int irq);
af8c65b5 365#endif
2e60bbb6 366
dae86204
IM
367/*
368 * Architectures call this to let the generic IRQ layer
369 * handle an interrupt. If the descriptor is attached to an
370 * irqchip-style controller then we call the ->handle_irq() handler,
371 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
372 */
46926b67 373static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
dae86204 374{
af8c65b5 375#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
7d12e780 376 desc->handle_irq(irq, desc);
af8c65b5 377#else
dae86204 378 if (likely(desc->handle_irq))
7d12e780 379 desc->handle_irq(irq, desc);
dae86204 380 else
7d12e780 381 __do_IRQ(irq);
af8c65b5 382#endif
dae86204
IM
383}
384
46926b67
YL
385static inline void generic_handle_irq(unsigned int irq)
386{
387 generic_handle_irq_desc(irq, irq_to_desc(irq));
388}
389
6a6de9ef 390/* Handling of unhandled and spurious interrupts: */
34ffdb72 391extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
bedd30d9 392 irqreturn_t action_ret);
1da177e4 393
a4633adc
TG
394/* Resending of interrupts :*/
395void check_irq_resend(struct irq_desc *desc, unsigned int irq);
396
6a6de9ef
TG
397/* Enable/disable irq debugging output: */
398extern int noirqdebug_setup(char *str);
399
400/* Checks whether the interrupt can be requested by request_irq(): */
401extern int can_request_irq(unsigned int irq, unsigned long irqflags);
402
f8b5473f 403/* Dummy irq-chip implementations: */
6a6de9ef 404extern struct irq_chip no_irq_chip;
f8b5473f 405extern struct irq_chip dummy_irq_chip;
6a6de9ef 406
145fc655
IM
407extern void
408set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
409 irq_flow_handler_t handle);
6a6de9ef 410extern void
a460e745
IM
411set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
412 irq_flow_handler_t handle, const char *name);
413
6a6de9ef 414extern void
a460e745
IM
415__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
416 const char *name);
1da177e4 417
b019e573
KH
418/* caller has locked the irq_desc and both params are valid */
419static inline void __set_irq_handler_unlocked(int irq,
420 irq_flow_handler_t handler)
421{
08678b08
YL
422 struct irq_desc *desc;
423
424 desc = irq_to_desc(irq);
425 desc->handle_irq = handler;
b019e573
KH
426}
427
6a6de9ef
TG
428/*
429 * Set a highlevel flow handler for a given IRQ:
430 */
431static inline void
57a58a94 432set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef 433{
a460e745 434 __set_irq_handler(irq, handle, 0, NULL);
6a6de9ef
TG
435}
436
437/*
438 * Set a highlevel chained flow handler for a given IRQ.
439 * (a chained handler is automatically enabled and set to
440 * IRQ_NOREQUEST and IRQ_NOPROBE)
441 */
442static inline void
443set_irq_chained_handler(unsigned int irq,
57a58a94 444 irq_flow_handler_t handle)
6a6de9ef 445{
a460e745 446 __set_irq_handler(irq, handle, 1, NULL);
6a6de9ef
TG
447}
448
399b5da2
TG
449extern void set_irq_nested_thread(unsigned int irq, int nest);
450
46f4f8f6
RB
451extern void set_irq_noprobe(unsigned int irq);
452extern void set_irq_probe(unsigned int irq);
453
3a16d713 454/* Handle dynamic irq creation and destruction */
d047f53a 455extern unsigned int create_irq_nr(unsigned int irq_want, int node);
3a16d713
EB
456extern int create_irq(void);
457extern void destroy_irq(unsigned int irq);
458
1f80025e
EB
459/* Test to see if a driver has successfully requested an irq */
460static inline int irq_has_action(unsigned int irq)
461{
08678b08 462 struct irq_desc *desc = irq_to_desc(irq);
1f80025e
EB
463 return desc->action != NULL;
464}
465
3a16d713
EB
466/* Dynamic irq helper functions */
467extern void dynamic_irq_init(unsigned int irq);
ced5b697 468void dynamic_irq_init_keep_chip_data(unsigned int irq);
3a16d713 469extern void dynamic_irq_cleanup(unsigned int irq);
ced5b697 470void dynamic_irq_cleanup_keep_chip_data(unsigned int irq);
dd87eb3a 471
3a16d713 472/* Set/get chip/data for an IRQ: */
dd87eb3a
TG
473extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
474extern int set_irq_data(unsigned int irq, void *data);
475extern int set_irq_chip_data(unsigned int irq, void *data);
476extern int set_irq_type(unsigned int irq, unsigned int type);
5b912c10 477extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);
dd87eb3a 478
ff7dcd44
TG
479#define get_irq_chip(irq) (irq_to_desc(irq)->irq_data.chip)
480#define get_irq_chip_data(irq) (irq_to_desc(irq)->irq_data.chip_data)
481#define get_irq_data(irq) (irq_to_desc(irq)->irq_data.handler_data)
482#define get_irq_msi(irq) (irq_to_desc(irq)->irq_data.msi_desc)
dd87eb3a 483
ff7dcd44
TG
484#define get_irq_desc_chip(desc) ((desc)->irq_data.chip)
485#define get_irq_desc_chip_data(desc) ((desc)->irq_data.chip_data)
486#define get_irq_desc_data(desc) ((desc)->irq_data.handler_data)
487#define get_irq_desc_msi(desc) ((desc)->irq_data.msi_desc)
0b8f1efa 488
6a6de9ef 489#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4 490
06fcb0c6 491#endif /* !CONFIG_S390 */
1da177e4 492
7f7ace0c
MT
493#ifdef CONFIG_SMP
494/**
9ec4fa27 495 * alloc_desc_masks - allocate cpumasks for irq_desc
7f7ace0c 496 * @desc: pointer to irq_desc struct
ab33dcff 497 * @node: node which will be handling the cpumasks
7f7ace0c
MT
498 * @boot: true if need bootmem
499 *
500 * Allocates affinity and pending_mask cpumask if required.
501 * Returns true if successful (or not required).
7f7ace0c 502 */
85ac16d0 503static inline bool alloc_desc_masks(struct irq_desc *desc, int node,
38c7fed2 504 bool boot)
7f7ace0c 505{
38c7fed2 506 gfp_t gfp = GFP_ATOMIC;
7f7ace0c 507
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508 if (boot)
509 gfp = GFP_NOWAIT;
7f7ace0c 510
38c7fed2 511#ifdef CONFIG_CPUMASK_OFFSTACK
6b8ff312 512 if (!alloc_cpumask_var_node(&desc->irq_data.affinity, gfp, node))
7f7ace0c 513 return false;
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514
515#ifdef CONFIG_GENERIC_PENDING_IRQ
38c7fed2 516 if (!alloc_cpumask_var_node(&desc->pending_mask, gfp, node)) {
6b8ff312 517 free_cpumask_var(desc->irq_data.affinity);
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518 return false;
519 }
9ec4fa27 520#endif
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521#endif
522 return true;
523}
524
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525static inline void init_desc_masks(struct irq_desc *desc)
526{
6b8ff312 527 cpumask_setall(desc->irq_data.affinity);
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528#ifdef CONFIG_GENERIC_PENDING_IRQ
529 cpumask_clear(desc->pending_mask);
530#endif
531}
532
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533/**
534 * init_copy_desc_masks - copy cpumasks for irq_desc
535 * @old_desc: pointer to old irq_desc struct
536 * @new_desc: pointer to new irq_desc struct
537 *
538 * Insures affinity and pending_masks are copied to new irq_desc.
539 * If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
540 * irq_desc struct so the copy is redundant.
541 */
542
543static inline void init_copy_desc_masks(struct irq_desc *old_desc,
544 struct irq_desc *new_desc)
545{
9ec4fa27 546#ifdef CONFIG_CPUMASK_OFFSTACK
6b8ff312 547 cpumask_copy(new_desc->irq_data.affinity, old_desc->irq_data.affinity);
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548
549#ifdef CONFIG_GENERIC_PENDING_IRQ
550 cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
551#endif
552#endif
553}
554
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555static inline void free_desc_masks(struct irq_desc *old_desc,
556 struct irq_desc *new_desc)
557{
6b8ff312 558 free_cpumask_var(old_desc->irq_data.affinity);
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559
560#ifdef CONFIG_GENERIC_PENDING_IRQ
561 free_cpumask_var(old_desc->pending_mask);
562#endif
563}
564
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565#else /* !CONFIG_SMP */
566
85ac16d0 567static inline bool alloc_desc_masks(struct irq_desc *desc, int node,
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568 bool boot)
569{
570 return true;
571}
572
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573static inline void init_desc_masks(struct irq_desc *desc)
574{
575}
576
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577static inline void init_copy_desc_masks(struct irq_desc *old_desc,
578 struct irq_desc *new_desc)
579{
580}
581
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582static inline void free_desc_masks(struct irq_desc *old_desc,
583 struct irq_desc *new_desc)
584{
585}
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586#endif /* CONFIG_SMP */
587
06fcb0c6 588#endif /* _LINUX_IRQ_H */