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10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> | |
18 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
19 | */ | |
20 | ||
21 | #ifndef __DMAR_H__ | |
22 | #define __DMAR_H__ | |
23 | ||
24 | #include <linux/acpi.h> | |
25 | #include <linux/types.h> | |
ba395927 | 26 | #include <linux/msi.h> |
1531a6a6 | 27 | #include <linux/irqreturn.h> |
10e5247f | 28 | |
ba395927 | 29 | struct intel_iommu; |
29b61be6 | 30 | #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP) |
2ae21010 SS |
31 | struct dmar_drhd_unit { |
32 | struct list_head list; /* list of drhd units */ | |
33 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
34 | u64 reg_base_addr; /* register base address*/ | |
35 | struct pci_dev **devices; /* target device array */ | |
36 | int devices_cnt; /* target device count */ | |
37 | u8 ignored:1; /* ignore drhd */ | |
38 | u8 include_all:1; | |
39 | struct intel_iommu *iommu; | |
40 | }; | |
41 | ||
42 | extern struct list_head dmar_drhd_units; | |
43 | ||
44 | #define for_each_drhd_unit(drhd) \ | |
45 | list_for_each_entry(drhd, &dmar_drhd_units, list) | |
46 | ||
8f912ba4 DW |
47 | #define for_each_active_iommu(i, drhd) \ |
48 | list_for_each_entry(drhd, &dmar_drhd_units, list) \ | |
49 | if (i=drhd->iommu, drhd->ignored) {} else | |
50 | ||
51 | #define for_each_iommu(i, drhd) \ | |
52 | list_for_each_entry(drhd, &dmar_drhd_units, list) \ | |
53 | if (i=drhd->iommu, 0) {} else | |
54 | ||
2ae21010 | 55 | extern int dmar_table_init(void); |
2ae21010 SS |
56 | extern int dmar_dev_scope_init(void); |
57 | ||
58 | /* Intel IOMMU detection */ | |
59 | extern void detect_intel_iommu(void); | |
9d783ba0 | 60 | extern int enable_drhd_fault_handling(void); |
2ae21010 | 61 | |
2ae21010 SS |
62 | extern int parse_ioapics_under_ir(void); |
63 | extern int alloc_iommu(struct dmar_drhd_unit *); | |
64 | #else | |
65 | static inline void detect_intel_iommu(void) | |
66 | { | |
67 | return; | |
68 | } | |
69 | ||
70 | static inline int dmar_table_init(void) | |
71 | { | |
72 | return -ENODEV; | |
73 | } | |
29b61be6 SS |
74 | static inline int enable_drhd_fault_handling(void) |
75 | { | |
76 | return -1; | |
77 | } | |
2ae21010 SS |
78 | #endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */ |
79 | ||
2ae21010 SS |
80 | struct irte { |
81 | union { | |
82 | struct { | |
83 | __u64 present : 1, | |
84 | fpd : 1, | |
85 | dst_mode : 1, | |
86 | redir_hint : 1, | |
87 | trigger_mode : 1, | |
88 | dlvry_mode : 3, | |
89 | avail : 4, | |
90 | __reserved_1 : 4, | |
91 | vector : 8, | |
92 | __reserved_2 : 8, | |
93 | dest_id : 32; | |
94 | }; | |
95 | __u64 low; | |
96 | }; | |
97 | ||
98 | union { | |
99 | struct { | |
100 | __u64 sid : 16, | |
101 | sq : 2, | |
102 | svt : 2, | |
103 | __reserved_3 : 44; | |
104 | }; | |
105 | __u64 high; | |
106 | }; | |
107 | }; | |
29b61be6 SS |
108 | #ifdef CONFIG_INTR_REMAP |
109 | extern int intr_remapping_enabled; | |
110 | extern int enable_intr_remapping(int); | |
111 | ||
b6fcb33a SS |
112 | extern int get_irte(int irq, struct irte *entry); |
113 | extern int modify_irte(int irq, struct irte *irte_modified); | |
114 | extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count); | |
115 | extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, | |
116 | u16 sub_handle); | |
117 | extern int map_irq_to_irte_handle(int irq, u16 *sub_handle); | |
118 | extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index); | |
119 | extern int flush_irte(int irq); | |
120 | extern int free_irte(int irq); | |
121 | ||
122 | extern int irq_remapped(int irq); | |
75c46fa6 | 123 | extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev); |
89027d35 | 124 | extern struct intel_iommu *map_ioapic_to_ir(int apic); |
2ae21010 | 125 | #else |
29b61be6 SS |
126 | static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
127 | { | |
128 | return -1; | |
129 | } | |
130 | static inline int modify_irte(int irq, struct irte *irte_modified) | |
131 | { | |
132 | return -1; | |
133 | } | |
134 | static inline int free_irte(int irq) | |
135 | { | |
136 | return -1; | |
137 | } | |
138 | static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
139 | { | |
140 | return -1; | |
141 | } | |
142 | static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, | |
143 | u16 sub_handle) | |
144 | { | |
145 | return -1; | |
146 | } | |
147 | static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) | |
148 | { | |
149 | return NULL; | |
150 | } | |
151 | static inline struct intel_iommu *map_ioapic_to_ir(int apic) | |
152 | { | |
153 | return NULL; | |
154 | } | |
b6fcb33a | 155 | #define irq_remapped(irq) (0) |
2ae21010 SS |
156 | #define enable_intr_remapping(mode) (-1) |
157 | #define intr_remapping_enabled (0) | |
158 | #endif | |
159 | ||
3460a6d9 KA |
160 | /* Can't use the common MSI interrupt functions |
161 | * since DMAR is not a pci device | |
162 | */ | |
163 | extern void dmar_msi_unmask(unsigned int irq); | |
164 | extern void dmar_msi_mask(unsigned int irq); | |
165 | extern void dmar_msi_read(int irq, struct msi_msg *msg); | |
166 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
167 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
1531a6a6 | 168 | extern irqreturn_t dmar_fault(int irq, void *dev_id); |
3460a6d9 KA |
169 | extern int arch_setup_dmar_msi(unsigned int irq); |
170 | ||
9d783ba0 | 171 | #ifdef CONFIG_DMAR |
2ae21010 | 172 | extern int iommu_detected, no_iommu; |
10e5247f | 173 | extern struct list_head dmar_rmrr_units; |
10e5247f KA |
174 | struct dmar_rmrr_unit { |
175 | struct list_head list; /* list of rmrr units */ | |
1886e8a9 | 176 | struct acpi_dmar_header *hdr; /* ACPI header */ |
10e5247f KA |
177 | u64 base_address; /* reserved base address*/ |
178 | u64 end_address; /* reserved end address */ | |
179 | struct pci_dev **devices; /* target devices */ | |
180 | int devices_cnt; /* target device count */ | |
181 | }; | |
182 | ||
ba395927 KA |
183 | #define for_each_rmrr_units(rmrr) \ |
184 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
2ae21010 SS |
185 | /* Intel DMAR initialization functions */ |
186 | extern int intel_iommu_init(void); | |
ba395927 | 187 | #else |
ba395927 KA |
188 | static inline int intel_iommu_init(void) |
189 | { | |
2ae21010 SS |
190 | #ifdef CONFIG_INTR_REMAP |
191 | return dmar_dev_scope_init(); | |
192 | #else | |
ba395927 | 193 | return -ENODEV; |
2ae21010 | 194 | #endif |
1886e8a9 | 195 | } |
ba395927 | 196 | #endif /* !CONFIG_DMAR */ |
10e5247f | 197 | #endif /* __DMAR_H__ */ |