[net-next-2.6.git] / include / linux / dmar.h

/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
 */

#ifndef __DMAR_H__
#define __DMAR_H__

#include <linux/acpi.h>
#include <linux/types.h>
#include <linux/msi.h>

#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
struct intel_iommu;

struct dmar_drhd_unit {
	struct list_head list;		/* list of drhd units	*/
	struct  acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	reg_base_addr;		/* register base address*/
	struct	pci_dev **devices; 	/* target device array	*/
	int	devices_cnt;		/* target device count	*/
	u8	ignored:1; 		/* ignore drhd		*/
	u8	include_all:1;
	struct intel_iommu *iommu;
};

extern struct list_head dmar_drhd_units;

#define for_each_drhd_unit(drhd) \
	list_for_each_entry(drhd, &dmar_drhd_units, list)

extern int dmar_table_init(void);
extern int early_dmar_detect(void);
extern int dmar_dev_scope_init(void);

/* Intel IOMMU detection */
extern void detect_intel_iommu(void);


extern int parse_ioapics_under_ir(void);
extern int alloc_iommu(struct dmar_drhd_unit *);
#else
static inline void detect_intel_iommu(void)
{
	return;
}

static inline int dmar_table_init(void)
{
	return -ENODEV;
}
#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */

#ifdef CONFIG_INTR_REMAP
extern int intr_remapping_enabled;
extern int enable_intr_remapping(int);

struct irte {
	union {
		struct {
			__u64	present 	: 1,
				fpd		: 1,
				dst_mode	: 1,
				redir_hint	: 1,
				trigger_mode	: 1,
				dlvry_mode	: 3,
				avail		: 4,
				__reserved_1	: 4,
				vector		: 8,
				__reserved_2	: 8,
				dest_id		: 32;
		};
		__u64 low;
	};

	union {
		struct {
			__u64	sid		: 16,
				sq		: 2,
				svt		: 2,
				__reserved_3	: 44;
		};
		__u64 high;
	};
};
extern int get_irte(int irq, struct irte *entry);
extern int modify_irte(int irq, struct irte *irte_modified);
extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
   			u16 sub_handle);
extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
extern int flush_irte(int irq);
extern int free_irte(int irq);

extern int irq_remapped(int irq);
extern struct intel_iommu *map_ioapic_to_ir(int apic);
#else
#define irq_remapped(irq)		(0)
#define enable_intr_remapping(mode)	(-1)
#define intr_remapping_enabled		(0)
#endif

#ifdef CONFIG_DMAR
extern const char *dmar_get_fault_reason(u8 fault_reason);

/* Can't use the common MSI interrupt functions
 * since DMAR is not a pci device
 */
extern void dmar_msi_unmask(unsigned int irq);
extern void dmar_msi_mask(unsigned int irq);
extern void dmar_msi_read(int irq, struct msi_msg *msg);
extern void dmar_msi_write(int irq, struct msi_msg *msg);
extern int dmar_set_interrupt(struct intel_iommu *iommu);
extern int arch_setup_dmar_msi(unsigned int irq);

extern int iommu_detected, no_iommu;
extern struct list_head dmar_rmrr_units;
struct dmar_rmrr_unit {
	struct list_head list;		/* list of rmrr units	*/
	struct acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	base_address;		/* reserved base address*/
	u64	end_address;		/* reserved end address */
	struct pci_dev **devices;	/* target devices */
	int	devices_cnt;		/* target device count */
};

#define for_each_rmrr_units(rmrr) \
	list_for_each_entry(rmrr, &dmar_rmrr_units, list)
/* Intel DMAR  initialization functions */
extern int intel_iommu_init(void);
extern int dmar_disabled;
#else
static inline int intel_iommu_init(void)
{
#ifdef CONFIG_INTR_REMAP
	return dmar_dev_scope_init();
#else
	return -ENODEV;
#endif
}
#endif /* !CONFIG_DMAR */
#endif /* __DMAR_H__ */
Commit	Line	Data
10e5247f KA	1	/*
	2	* Copyright (c) 2006, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	15	* Place - Suite 330, Boston, MA 02111-1307 USA.
	16	*
	17	* Copyright (C) Ashok Raj <ashok.raj@intel.com>
	18	* Copyright (C) Shaohua Li <shaohua.li@intel.com>
	19	*/
	20
	21	#ifndef __DMAR_H__
	22	#define __DMAR_H__
	23
	24	#include <linux/acpi.h>
	25	#include <linux/types.h>
ba395927	26	#include <linux/msi.h>
10e5247f	27
2ae21010	28	#if defined(CONFIG_DMAR) \|\| defined(CONFIG_INTR_REMAP)
ba395927 KA	29	struct intel_iommu;
ba395927 KA	30
2ae21010 SS	31	struct dmar_drhd_unit {
	32	struct list_head list; /* list of drhd units */
	33	struct acpi_dmar_header hdr; / ACPI header */
	34	u64 reg_base_addr; /* register base address*/
	35	struct pci_dev *devices; / target device array */
	36	int devices_cnt; /* target device count */
	37	u8 ignored:1; /* ignore drhd */
	38	u8 include_all:1;
	39	struct intel_iommu *iommu;
	40	};
	41
	42	extern struct list_head dmar_drhd_units;
	43
	44	#define for_each_drhd_unit(drhd) \
	45	list_for_each_entry(drhd, &dmar_drhd_units, list)
	46
	47	extern int dmar_table_init(void);
	48	extern int early_dmar_detect(void);
	49	extern int dmar_dev_scope_init(void);
	50
	51	/* Intel IOMMU detection */
	52	extern void detect_intel_iommu(void);
	53
	54
	55	extern int parse_ioapics_under_ir(void);
	56	extern int alloc_iommu(struct dmar_drhd_unit *);
	57	#else
	58	static inline void detect_intel_iommu(void)
	59	{
	60	return;
	61	}
	62
	63	static inline int dmar_table_init(void)
	64	{
	65	return -ENODEV;
	66	}
	67	#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
	68
	69	#ifdef CONFIG_INTR_REMAP
	70	extern int intr_remapping_enabled;
	71	extern int enable_intr_remapping(int);
	72
	73	struct irte {
	74	union {
	75	struct {
	76	__u64 present : 1,
	77	fpd : 1,
	78	dst_mode : 1,
	79	redir_hint : 1,
	80	trigger_mode : 1,
	81	dlvry_mode : 3,
	82	avail : 4,
	83	__reserved_1 : 4,
	84	vector : 8,
	85	__reserved_2 : 8,
	86	dest_id : 32;
	87	};
	88	__u64 low;
	89	};
	90
	91	union {
	92	struct {
	93	__u64 sid : 16,
	94	sq : 2,
95	svt : 2,
96	__reserved_3 : 44;
97	};
98	__u64 high;
99	};
100	};
b6fcb33a SS	101	extern int get_irte(int irq, struct irte *entry);
	102	extern int modify_irte(int irq, struct irte *irte_modified);
	103	extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
	104	extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
	105	u16 sub_handle);
	106	extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
	107	extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
	108	extern int flush_irte(int irq);
	109	extern int free_irte(int irq);
	110
	111	extern int irq_remapped(int irq);
89027d35	112	extern struct intel_iommu *map_ioapic_to_ir(int apic);
2ae21010	113	#else
b6fcb33a	114	#define irq_remapped(irq) (0)
2ae21010 SS	115	#define enable_intr_remapping(mode) (-1)
	116	#define intr_remapping_enabled (0)
	117	#endif
	118
	119	#ifdef CONFIG_DMAR
d94afc6c	120	extern const char *dmar_get_fault_reason(u8 fault_reason);
3460a6d9 KA	121
	122	/* Can't use the common MSI interrupt functions
	123	* since DMAR is not a pci device
	124	*/
	125	extern void dmar_msi_unmask(unsigned int irq);
	126	extern void dmar_msi_mask(unsigned int irq);
	127	extern void dmar_msi_read(int irq, struct msi_msg *msg);
	128	extern void dmar_msi_write(int irq, struct msi_msg *msg);
	129	extern int dmar_set_interrupt(struct intel_iommu *iommu);
	130	extern int arch_setup_dmar_msi(unsigned int irq);
	131
2ae21010	132	extern int iommu_detected, no_iommu;
10e5247f	133	extern struct list_head dmar_rmrr_units;
10e5247f KA	134	struct dmar_rmrr_unit {
10e5247f KA	135	struct list_head list; /* list of rmrr units */
1886e8a9	136	struct acpi_dmar_header hdr; / ACPI header */
10e5247f KA	137	u64 base_address; /* reserved base address*/
	138	u64 end_address; /* reserved end address */
	139	struct pci_dev *devices; / target devices */
	140	int devices_cnt; /* target device count */
	141	};
	142
ba395927 KA	143	#define for_each_rmrr_units(rmrr) \
ba395927 KA	144	list_for_each_entry(rmrr, &dmar_rmrr_units, list)
2ae21010 SS	145	/* Intel DMAR initialization functions */
	146	extern int intel_iommu_init(void);
	147	extern int dmar_disabled;
ba395927	148	#else
ba395927 KA	149	static inline int intel_iommu_init(void)
ba395927 KA	150	{
2ae21010 SS	151	#ifdef CONFIG_INTR_REMAP
	152	return dmar_dev_scope_init();
	153	#else
ba395927	154	return -ENODEV;
2ae21010	155	#endif
1886e8a9	156	}
ba395927	157	#endif /* !CONFIG_DMAR */
10e5247f	158	#endif /* __DMAR_H__ */