[net-next-2.6.git] / include / linux / dmaengine.h

/*
 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef DMAENGINE_H
#define DMAENGINE_H

#include <linux/device.h>
#include <linux/uio.h>
#include <linux/dma-mapping.h>

/**
 * typedef dma_cookie_t - an opaque DMA cookie
 *
 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 */
typedef s32 dma_cookie_t;

#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)

/**
 * enum dma_status - DMA transaction status
 * @DMA_SUCCESS: transaction completed successfully
 * @DMA_IN_PROGRESS: transaction not yet processed
 * @DMA_ERROR: transaction failed
 */
enum dma_status {
	DMA_SUCCESS,
	DMA_IN_PROGRESS,
	DMA_ERROR,
};

/**
 * enum dma_transaction_type - DMA transaction types/indexes
 */
enum dma_transaction_type {
	DMA_MEMCPY,
	DMA_XOR,
	DMA_PQ_XOR,
	DMA_DUAL_XOR,
	DMA_PQ_UPDATE,
	DMA_XOR_VAL,
	DMA_PQ_VAL,
	DMA_MEMSET,
	DMA_MEMCPY_CRC32C,
	DMA_INTERRUPT,
	DMA_PRIVATE,
	DMA_SLAVE,
};

/* last transaction type for creation of the capabilities mask */
#define DMA_TX_TYPE_END (DMA_SLAVE + 1)


/**
 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
 * 	control completion, and communicate status.
 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
 * 	this transaction
 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
 * 	acknowledges receipt, i.e. has has a chance to establish any
 * 	dependency chains
 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
 */
enum dma_ctrl_flags {
	DMA_PREP_INTERRUPT = (1 << 0),
	DMA_CTRL_ACK = (1 << 1),
	DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
	DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
};

/**
 * enum sum_check_bits - bit position of pq_check_flags
 */
enum sum_check_bits {
	SUM_CHECK_P = 0,
	SUM_CHECK_Q = 1,
};

/**
 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
 */
enum sum_check_flags {
	SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
	SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
};


/**
 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 * See linux/cpumask.h
 */
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;

/**
 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 * @memcpy_count: transaction counter
 * @bytes_transferred: byte counter
 */

struct dma_chan_percpu {
	/* stats */
	unsigned long memcpy_count;
	unsigned long bytes_transferred;
};

/**
 * struct dma_chan - devices supply DMA channels, clients use them
 * @device: ptr to the dma device who supplies this channel, always !%NULL
 * @cookie: last cookie value returned to client
 * @chan_id: channel ID for sysfs
 * @dev: class device for sysfs
 * @device_node: used to add this to the device chan list
 * @local: per-cpu pointer to a struct dma_chan_percpu
 * @client-count: how many clients are using this channel
 * @table_count: number of appearances in the mem-to-mem allocation table
 * @private: private data for certain client-channel associations
 */
struct dma_chan {
	struct dma_device *device;
	dma_cookie_t cookie;

	/* sysfs */
	int chan_id;
	struct dma_chan_dev *dev;

	struct list_head device_node;
	struct dma_chan_percpu *local;
	int client_count;
	int table_count;
	void *private;
};

/**
 * struct dma_chan_dev - relate sysfs device node to backing channel device
 * @chan - driver channel device
 * @device - sysfs device
 * @dev_id - parent dma_device dev_id
 * @idr_ref - reference count to gate release of dma_device dev_id
 */
struct dma_chan_dev {
	struct dma_chan *chan;
	struct device device;
	int dev_id;
	atomic_t *idr_ref;
};

static inline const char *dma_chan_name(struct dma_chan *chan)
{
	return dev_name(&chan->dev->device);
}

void dma_chan_cleanup(struct kref *kref);

/**
 * typedef dma_filter_fn - callback filter for dma_request_channel
 * @chan: channel to be reviewed
 * @filter_param: opaque parameter passed through dma_request_channel
 *
 * When this optional parameter is specified in a call to dma_request_channel a
 * suitable channel is passed to this routine for further dispositioning before
 * being returned.  Where 'suitable' indicates a non-busy channel that
 * satisfies the given capability mask.  It returns 'true' to indicate that the
 * channel is suitable.
 */
typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);

typedef void (*dma_async_tx_callback)(void *dma_async_param);
/**
 * struct dma_async_tx_descriptor - async transaction descriptor
 * ---dma generic offload fields---
 * @cookie: tracking cookie for this transaction, set to -EBUSY if
 *	this tx is sitting on a dependency list
 * @flags: flags to augment operation preparation, control completion, and
 * 	communicate status
 * @phys: physical address of the descriptor
 * @tx_list: driver common field for operations that require multiple
 *	descriptors
 * @chan: target channel for this operation
 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
 * @callback: routine to call after this operation is complete
 * @callback_param: general parameter to pass to the callback routine
 * ---async_tx api specific fields---
 * @next: at completion submit this descriptor
 * @parent: pointer to the next level up in the dependency chain
 * @lock: protect the parent and next pointers
 */
struct dma_async_tx_descriptor {
	dma_cookie_t cookie;
	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
	dma_addr_t phys;
	struct list_head tx_list;
	struct dma_chan *chan;
	dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
	dma_async_tx_callback callback;
	void *callback_param;
	struct dma_async_tx_descriptor *next;
	struct dma_async_tx_descriptor *parent;
	spinlock_t lock;
};

/**
 * struct dma_device - info on the entity supplying DMA services
 * @chancnt: how many DMA channels are supported
 * @privatecnt: how many DMA channels are requested by dma_request_channel
 * @channels: the list of struct dma_chan
 * @global_node: list_head for global dma_device_list
 * @cap_mask: one or more dma_capability flags
 * @max_xor: maximum number of xor sources, 0 if no capability
 * @dev_id: unique device ID
 * @dev: struct device reference for dma mapping api
 * @device_alloc_chan_resources: allocate resources and return the
 *	number of allocated descriptors
 * @device_free_chan_resources: release DMA channel's resources
 * @device_prep_dma_memcpy: prepares a memcpy operation
 * @device_prep_dma_xor: prepares a xor operation
 * @device_prep_dma_xor_val: prepares a xor validation operation
 * @device_prep_dma_memset: prepares a memset operation
 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 * @device_prep_slave_sg: prepares a slave dma operation
 * @device_terminate_all: terminate all pending operations
 * @device_is_tx_complete: poll for transaction completion
 * @device_issue_pending: push pending transactions to hardware
 */
struct dma_device {

	unsigned int chancnt;
	unsigned int privatecnt;
	struct list_head channels;
	struct list_head global_node;
	dma_cap_mask_t  cap_mask;
	int max_xor;

	int dev_id;
	struct device *dev;

	int (*device_alloc_chan_resources)(struct dma_chan *chan);
	void (*device_free_chan_resources)(struct dma_chan *chan);

	struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
		size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
		unsigned int src_cnt, size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
		struct dma_chan *chan, dma_addr_t *src,	unsigned int src_cnt,
		size_t len, enum sum_check_flags *result, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
		unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
		struct dma_chan *chan, unsigned long flags);

	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_data_direction direction,
		unsigned long flags);
	void (*device_terminate_all)(struct dma_chan *chan);

	enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
			dma_cookie_t cookie, dma_cookie_t *last,
			dma_cookie_t *used);
	void (*device_issue_pending)(struct dma_chan *chan);
};

/* --- public DMA engine API --- */

#ifdef CONFIG_DMA_ENGINE
void dmaengine_get(void);
void dmaengine_put(void);
#else
static inline void dmaengine_get(void)
{
}
static inline void dmaengine_put(void)
{
}
#endif

#ifdef CONFIG_NET_DMA
#define net_dmaengine_get()	dmaengine_get()
#define net_dmaengine_put()	dmaengine_put()
#else
static inline void net_dmaengine_get(void)
{
}
static inline void net_dmaengine_put(void)
{
}
#endif

#ifdef CONFIG_ASYNC_TX_DMA
#define async_dmaengine_get()	dmaengine_get()
#define async_dmaengine_put()	dmaengine_put()
#define async_dma_find_channel(type) dma_find_channel(type)
#else
static inline void async_dmaengine_get(void)
{
}
static inline void async_dmaengine_put(void)
{
}
static inline struct dma_chan *
async_dma_find_channel(enum dma_transaction_type type)
{
	return NULL;
}
#endif

dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
	void *dest, void *src, size_t len);
dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
	struct page *page, unsigned int offset, void *kdata, size_t len);
dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
	struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
	unsigned int src_off, size_t len);
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
	struct dma_chan *chan);

static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
{
	tx->flags |= DMA_CTRL_ACK;
}

static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
{
	tx->flags &= ~DMA_CTRL_ACK;
}

static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
{
	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
}

#define first_dma_cap(mask) __first_dma_cap(&(mask))
static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
{
	return min_t(int, DMA_TX_TYPE_END,
		find_first_bit(srcp->bits, DMA_TX_TYPE_END));
}

#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
{
	return min_t(int, DMA_TX_TYPE_END,
		find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
}

#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
static inline void
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
{
	set_bit(tx_type, dstp->bits);
}

#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
static inline void
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
{
	clear_bit(tx_type, dstp->bits);
}

#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
{
	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
}

#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
static inline int
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
{
	return test_bit(tx_type, srcp->bits);
}

#define for_each_dma_cap_mask(cap, mask) \
	for ((cap) = first_dma_cap(mask);	\
		(cap) < DMA_TX_TYPE_END;	\
		(cap) = next_dma_cap((cap), (mask)))

/**
 * dma_async_issue_pending - flush pending transactions to HW
 * @chan: target DMA channel
 *
 * This allows drivers to push copies to HW in batches,
 * reducing MMIO writes where possible.
 */
static inline void dma_async_issue_pending(struct dma_chan *chan)
{
	chan->device->device_issue_pending(chan);
}

#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)

/**
 * dma_async_is_tx_complete - poll for transaction completion
 * @chan: DMA channel
 * @cookie: transaction identifier to check status of
 * @last: returns last completed cookie, can be NULL
 * @used: returns last issued cookie, can be NULL
 *
 * If @last and @used are passed in, upon return they reflect the driver
 * internal state and can be used with dma_async_is_complete() to check
 * the status of multiple cookies without re-checking hardware state.
 */
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
	dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
{
	return chan->device->device_is_tx_complete(chan, cookie, last, used);
}

#define dma_async_memcpy_complete(chan, cookie, last, used)\
	dma_async_is_tx_complete(chan, cookie, last, used)

/**
 * dma_async_is_complete - test a cookie against chan state
 * @cookie: transaction identifier to test status of
 * @last_complete: last know completed transaction
 * @last_used: last cookie value handed out
 *
 * dma_async_is_complete() is used in dma_async_memcpy_complete()
 * the test logic is separated for lightweight testing of multiple cookies
 */
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
			dma_cookie_t last_complete, dma_cookie_t last_used)
{
	if (last_complete <= last_used) {
		if ((cookie <= last_complete) || (cookie > last_used))
			return DMA_SUCCESS;
	} else {
		if ((cookie <= last_complete) && (cookie > last_used))
			return DMA_SUCCESS;
	}
	return DMA_IN_PROGRESS;
}

enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
#ifdef CONFIG_DMA_ENGINE
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
void dma_issue_pending_all(void);
#else
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
{
	return DMA_SUCCESS;
}
static inline void dma_issue_pending_all(void)
{
	do { } while (0);
}
#endif

/* --- DMA device --- */

int dma_async_device_register(struct dma_device *device);
void dma_async_device_unregister(struct dma_device *device);
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
void dma_release_channel(struct dma_chan *chan);

/* --- Helper iov-locking functions --- */

struct dma_page_list {
	char __user *base_address;
	int nr_pages;
	struct page **pages;
};

struct dma_pinned_list {
	int nr_iovecs;
	struct dma_page_list page_list[0];
};

struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);

dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
	struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
	struct dma_pinned_list *pinned_list, struct page *page,
	unsigned int offset, size_t len);

#endif /* DMAENGINE_H */
Commit	Line	Data
c13c8260 CL	1	/*
	2	* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59
	16	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called COPYING.
	20	*/
	21	#ifndef DMAENGINE_H
	22	#define DMAENGINE_H
1c0f16e5	23
c13c8260 CL	24	#include <linux/device.h>
c13c8260 CL	25	#include <linux/uio.h>
7405f74b	26	#include <linux/dma-mapping.h>
c13c8260	27
c13c8260	28	/**
fe4ada2d	29	* typedef dma_cookie_t - an opaque DMA cookie
c13c8260 CL	30	*
	31	* if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
	32	*/
	33	typedef s32 dma_cookie_t;
	34
	35	#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
	36
	37	/**
	38	* enum dma_status - DMA transaction status
	39	* @DMA_SUCCESS: transaction completed successfully
	40	* @DMA_IN_PROGRESS: transaction not yet processed
	41	* @DMA_ERROR: transaction failed
	42	*/
	43	enum dma_status {
	44	DMA_SUCCESS,
	45	DMA_IN_PROGRESS,
	46	DMA_ERROR,
	47	};
	48
7405f74b DW	49	/**
	50	* enum dma_transaction_type - DMA transaction types/indexes
	51	*/
	52	enum dma_transaction_type {
	53	DMA_MEMCPY,
	54	DMA_XOR,
	55	DMA_PQ_XOR,
	56	DMA_DUAL_XOR,
	57	DMA_PQ_UPDATE,
099f53cb DW	58	DMA_XOR_VAL,
099f53cb DW	59	DMA_PQ_VAL,
7405f74b DW	60	DMA_MEMSET,
	61	DMA_MEMCPY_CRC32C,
	62	DMA_INTERRUPT,
59b5ec21	63	DMA_PRIVATE,
dc0ee643	64	DMA_SLAVE,
7405f74b DW	65	};
	66
	67	/* last transaction type for creation of the capabilities mask */
dc0ee643 HS	68	#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
dc0ee643 HS	69
7405f74b	70
d4c56f97	71	/**
636bdeaa DW	72	* enum dma_ctrl_flags - DMA flags to augment operation preparation,
636bdeaa DW	73	* control completion, and communicate status.
d4c56f97 DW	74	* @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
d4c56f97 DW	75	* this transaction
636bdeaa DW	76	* @DMA_CTRL_ACK - the descriptor cannot be reused until the client
	77	* acknowledges receipt, i.e. has has a chance to establish any
	78	* dependency chains
e1d181ef DW	79	* @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
e1d181ef DW	80	* @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
d4c56f97	81	*/
636bdeaa	82	enum dma_ctrl_flags {
d4c56f97	83	DMA_PREP_INTERRUPT = (1 << 0),
636bdeaa	84	DMA_CTRL_ACK = (1 << 1),
e1d181ef DW	85	DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
e1d181ef DW	86	DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
d4c56f97 DW	87	};
d4c56f97 DW	88
ad283ea4 DW	89	/**
	90	* enum sum_check_bits - bit position of pq_check_flags
	91	*/
	92	enum sum_check_bits {
	93	SUM_CHECK_P = 0,
	94	SUM_CHECK_Q = 1,
	95	};
	96
	97	/**
	98	* enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
	99	* @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
	100	* @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
	101	*/
	102	enum sum_check_flags {
	103	SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
	104	SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
	105	};
	106
	107
7405f74b DW	108	/**
	109	* dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
	110	* See linux/cpumask.h
	111	*/
	112	typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
	113
c13c8260 CL	114	/**
c13c8260 CL	115	* struct dma_chan_percpu - the per-CPU part of struct dma_chan
c13c8260 CL	116	* @memcpy_count: transaction counter
	117	* @bytes_transferred: byte counter
	118	*/
	119
	120	struct dma_chan_percpu {
c13c8260 CL	121	/* stats */
	122	unsigned long memcpy_count;
	123	unsigned long bytes_transferred;
	124	};
	125
	126	/**
	127	* struct dma_chan - devices supply DMA channels, clients use them
fe4ada2d	128	* @device: ptr to the dma device who supplies this channel, always !%NULL
c13c8260	129	* @cookie: last cookie value returned to client
fe4ada2d	130	* @chan_id: channel ID for sysfs
41d5e59c	131	* @dev: class device for sysfs
c13c8260 CL	132	* @device_node: used to add this to the device chan list
c13c8260 CL	133	* @local: per-cpu pointer to a struct dma_chan_percpu
7cc5bf9a	134	* @client-count: how many clients are using this channel
bec08513	135	* @table_count: number of appearances in the mem-to-mem allocation table
287d8592	136	* @private: private data for certain client-channel associations
c13c8260 CL	137	*/
c13c8260 CL	138	struct dma_chan {
c13c8260 CL	139	struct dma_device *device;
	140	dma_cookie_t cookie;
	141
	142	/* sysfs */
	143	int chan_id;
41d5e59c	144	struct dma_chan_dev *dev;
c13c8260	145
c13c8260 CL	146	struct list_head device_node;
c13c8260 CL	147	struct dma_chan_percpu *local;
7cc5bf9a	148	int client_count;
bec08513	149	int table_count;
287d8592	150	void *private;
c13c8260 CL	151	};
c13c8260 CL	152
41d5e59c DW	153	/**
	154	* struct dma_chan_dev - relate sysfs device node to backing channel device
	155	* @chan - driver channel device
	156	* @device - sysfs device
864498aa DW	157	* @dev_id - parent dma_device dev_id
864498aa DW	158	* @idr_ref - reference count to gate release of dma_device dev_id
41d5e59c DW	159	*/
	160	struct dma_chan_dev {
	161	struct dma_chan *chan;
	162	struct device device;
864498aa DW	163	int dev_id;
864498aa DW	164	atomic_t *idr_ref;
41d5e59c DW	165	};
	166
	167	static inline const char dma_chan_name(struct dma_chan chan)
	168	{
	169	return dev_name(&chan->dev->device);
	170	}
d379b01e	171
c13c8260 CL	172	void dma_chan_cleanup(struct kref *kref);
c13c8260 CL	173
59b5ec21 DW	174	/**
	175	* typedef dma_filter_fn - callback filter for dma_request_channel
	176	* @chan: channel to be reviewed
	177	* @filter_param: opaque parameter passed through dma_request_channel
	178	*
	179	* When this optional parameter is specified in a call to dma_request_channel a
	180	* suitable channel is passed to this routine for further dispositioning before
	181	* being returned. Where 'suitable' indicates a non-busy channel that
7dd60251 DW	182	* satisfies the given capability mask. It returns 'true' to indicate that the
7dd60251 DW	183	* channel is suitable.
59b5ec21	184	*/
7dd60251	185	typedef bool (dma_filter_fn)(struct dma_chan chan, void *filter_param);
59b5ec21	186
7405f74b DW	187	typedef void (dma_async_tx_callback)(void dma_async_param);
	188	/**
	189	* struct dma_async_tx_descriptor - async transaction descriptor
	190	* ---dma generic offload fields---
	191	* @cookie: tracking cookie for this transaction, set to -EBUSY if
	192	* this tx is sitting on a dependency list
636bdeaa DW	193	* @flags: flags to augment operation preparation, control completion, and
636bdeaa DW	194	* communicate status
7405f74b DW	195	* @phys: physical address of the descriptor
	196	* @tx_list: driver common field for operations that require multiple
	197	* descriptors
	198	* @chan: target channel for this operation
	199	* @tx_submit: set the prepared descriptor(s) to be executed by the engine
7405f74b DW	200	* @callback: routine to call after this operation is complete
	201	* @callback_param: general parameter to pass to the callback routine
	202	* ---async_tx api specific fields---
19242d72	203	* @next: at completion submit this descriptor
7405f74b	204	* @parent: pointer to the next level up in the dependency chain
19242d72	205	* @lock: protect the parent and next pointers
7405f74b DW	206	*/
	207	struct dma_async_tx_descriptor {
	208	dma_cookie_t cookie;
636bdeaa	209	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
7405f74b DW	210	dma_addr_t phys;
	211	struct list_head tx_list;
	212	struct dma_chan *chan;
	213	dma_cookie_t (tx_submit)(struct dma_async_tx_descriptor tx);
7405f74b DW	214	dma_async_tx_callback callback;
7405f74b DW	215	void *callback_param;
19242d72	216	struct dma_async_tx_descriptor *next;
7405f74b DW	217	struct dma_async_tx_descriptor *parent;
	218	spinlock_t lock;
	219	};
	220
c13c8260 CL	221	/**
	222	* struct dma_device - info on the entity supplying DMA services
	223	* @chancnt: how many DMA channels are supported
0f571515	224	* @privatecnt: how many DMA channels are requested by dma_request_channel
c13c8260 CL	225	* @channels: the list of struct dma_chan
c13c8260 CL	226	* @global_node: list_head for global dma_device_list
7405f74b DW	227	* @cap_mask: one or more dma_capability flags
7405f74b DW	228	* @max_xor: maximum number of xor sources, 0 if no capability
fe4ada2d	229	* @dev_id: unique device ID
7405f74b	230	* @dev: struct device reference for dma mapping api
fe4ada2d RD	231	* @device_alloc_chan_resources: allocate resources and return the
	232	* number of allocated descriptors
	233	* @device_free_chan_resources: release DMA channel's resources
7405f74b DW	234	* @device_prep_dma_memcpy: prepares a memcpy operation
7405f74b DW	235	* @device_prep_dma_xor: prepares a xor operation
099f53cb	236	* @device_prep_dma_xor_val: prepares a xor validation operation
7405f74b DW	237	* @device_prep_dma_memset: prepares a memset operation
7405f74b DW	238	* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
dc0ee643 HS	239	* @device_prep_slave_sg: prepares a slave dma operation
dc0ee643 HS	240	* @device_terminate_all: terminate all pending operations
1d93e52e	241	* @device_is_tx_complete: poll for transaction completion
7405f74b	242	* @device_issue_pending: push pending transactions to hardware
c13c8260 CL	243	*/
	244	struct dma_device {
	245
	246	unsigned int chancnt;
0f571515	247	unsigned int privatecnt;
c13c8260 CL	248	struct list_head channels;
c13c8260 CL	249	struct list_head global_node;
7405f74b DW	250	dma_cap_mask_t cap_mask;
7405f74b DW	251	int max_xor;
c13c8260	252
c13c8260	253	int dev_id;
7405f74b	254	struct device *dev;
c13c8260	255
aa1e6f1a	256	int (device_alloc_chan_resources)(struct dma_chan chan);
c13c8260	257	void (device_free_chan_resources)(struct dma_chan chan);
7405f74b DW	258
7405f74b DW	259	struct dma_async_tx_descriptor (device_prep_dma_memcpy)(
0036731c	260	struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
d4c56f97	261	size_t len, unsigned long flags);
7405f74b	262	struct dma_async_tx_descriptor (device_prep_dma_xor)(
0036731c	263	struct dma_chan chan, dma_addr_t dest, dma_addr_t src,
d4c56f97	264	unsigned int src_cnt, size_t len, unsigned long flags);
099f53cb	265	struct dma_async_tx_descriptor (device_prep_dma_xor_val)(
0036731c	266	struct dma_chan chan, dma_addr_t src, unsigned int src_cnt,
ad283ea4	267	size_t len, enum sum_check_flags *result, unsigned long flags);
7405f74b	268	struct dma_async_tx_descriptor (device_prep_dma_memset)(
0036731c	269	struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
d4c56f97	270	unsigned long flags);
7405f74b	271	struct dma_async_tx_descriptor (device_prep_dma_interrupt)(
636bdeaa	272	struct dma_chan *chan, unsigned long flags);
7405f74b	273
dc0ee643 HS	274	struct dma_async_tx_descriptor (device_prep_slave_sg)(
	275	struct dma_chan chan, struct scatterlist sgl,
	276	unsigned int sg_len, enum dma_data_direction direction,
	277	unsigned long flags);
	278	void (device_terminate_all)(struct dma_chan chan);
	279
7405f74b	280	enum dma_status (device_is_tx_complete)(struct dma_chan chan,
c13c8260 CL	281	dma_cookie_t cookie, dma_cookie_t *last,
c13c8260 CL	282	dma_cookie_t *used);
7405f74b	283	void (device_issue_pending)(struct dma_chan chan);
c13c8260 CL	284	};
	285
	286	/* --- public DMA engine API --- */
	287
649274d9	288	#ifdef CONFIG_DMA_ENGINE
209b84a8 DW	289	void dmaengine_get(void);
209b84a8 DW	290	void dmaengine_put(void);
649274d9 DW	291	#else
	292	static inline void dmaengine_get(void)
	293	{
	294	}
	295	static inline void dmaengine_put(void)
	296	{
	297	}
	298	#endif
	299
b4bd07c2 DM	300	#ifdef CONFIG_NET_DMA
	301	#define net_dmaengine_get() dmaengine_get()
	302	#define net_dmaengine_put() dmaengine_put()
	303	#else
	304	static inline void net_dmaengine_get(void)
	305	{
	306	}
	307	static inline void net_dmaengine_put(void)
	308	{
	309	}
	310	#endif
	311
729b5d1b DW	312	#ifdef CONFIG_ASYNC_TX_DMA
	313	#define async_dmaengine_get() dmaengine_get()
	314	#define async_dmaengine_put() dmaengine_put()
	315	#define async_dma_find_channel(type) dma_find_channel(type)
	316	#else
	317	static inline void async_dmaengine_get(void)
	318	{
	319	}
	320	static inline void async_dmaengine_put(void)
	321	{
	322	}
	323	static inline struct dma_chan *
	324	async_dma_find_channel(enum dma_transaction_type type)
	325	{
	326	return NULL;
	327	}
	328	#endif
	329
7405f74b DW	330	dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
	331	void dest, void src, size_t len);
	332	dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
	333	struct page page, unsigned int offset, void kdata, size_t len);
	334	dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
	335	struct page dest_pg, unsigned int dest_off, struct page src_pg,
	336	unsigned int src_off, size_t len);
	337	void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
	338	struct dma_chan *chan);
c13c8260	339
0839875e	340	static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
7405f74b	341	{
636bdeaa DW	342	tx->flags \|= DMA_CTRL_ACK;
	343	}
	344
ef560682 GL	345	static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
	346	{
	347	tx->flags &= ~DMA_CTRL_ACK;
	348	}
	349
0839875e	350	static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
636bdeaa	351	{
0839875e	352	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
c13c8260 CL	353	}
c13c8260 CL	354
7405f74b DW	355	#define first_dma_cap(mask) __first_dma_cap(&(mask))
7405f74b DW	356	static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
c13c8260	357	{
7405f74b DW	358	return min_t(int, DMA_TX_TYPE_END,
	359	find_first_bit(srcp->bits, DMA_TX_TYPE_END));
	360	}
c13c8260	361
7405f74b DW	362	#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
	363	static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
	364	{
	365	return min_t(int, DMA_TX_TYPE_END,
	366	find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
c13c8260 CL	367	}
c13c8260 CL	368
7405f74b DW	369	#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
	370	static inline void
	371	__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
c13c8260	372	{
7405f74b DW	373	set_bit(tx_type, dstp->bits);
7405f74b DW	374	}
c13c8260	375
0f571515 AN	376	#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
	377	static inline void
	378	__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
	379	{
	380	clear_bit(tx_type, dstp->bits);
	381	}
	382
33df8ca0 DW	383	#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
	384	static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
	385	{
	386	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
	387	}
	388
7405f74b DW	389	#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
	390	static inline int
	391	__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
	392	{
	393	return test_bit(tx_type, srcp->bits);
c13c8260 CL	394	}
c13c8260 CL	395
7405f74b DW	396	#define for_each_dma_cap_mask(cap, mask) \
	397	for ((cap) = first_dma_cap(mask); \
	398	(cap) < DMA_TX_TYPE_END; \
	399	(cap) = next_dma_cap((cap), (mask)))
	400
c13c8260	401	/**
7405f74b	402	* dma_async_issue_pending - flush pending transactions to HW
fe4ada2d	403	* @chan: target DMA channel
c13c8260 CL	404	*
	405	* This allows drivers to push copies to HW in batches,
	406	* reducing MMIO writes where possible.
	407	*/
7405f74b	408	static inline void dma_async_issue_pending(struct dma_chan *chan)
c13c8260	409	{
ec8670f1	410	chan->device->device_issue_pending(chan);
c13c8260 CL	411	}
c13c8260 CL	412
7405f74b DW	413	#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
7405f74b DW	414
c13c8260	415	/**
7405f74b	416	* dma_async_is_tx_complete - poll for transaction completion
c13c8260 CL	417	* @chan: DMA channel
	418	* @cookie: transaction identifier to check status of
	419	* @last: returns last completed cookie, can be NULL
	420	* @used: returns last issued cookie, can be NULL
	421	*
	422	* If @last and @used are passed in, upon return they reflect the driver
	423	* internal state and can be used with dma_async_is_complete() to check
	424	* the status of multiple cookies without re-checking hardware state.
	425	*/
7405f74b	426	static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
c13c8260 CL	427	dma_cookie_t cookie, dma_cookie_t last, dma_cookie_t used)
c13c8260 CL	428	{
7405f74b	429	return chan->device->device_is_tx_complete(chan, cookie, last, used);
c13c8260 CL	430	}
c13c8260 CL	431
7405f74b DW	432	#define dma_async_memcpy_complete(chan, cookie, last, used)\
	433	dma_async_is_tx_complete(chan, cookie, last, used)
	434
c13c8260 CL	435	/**
	436	* dma_async_is_complete - test a cookie against chan state
	437	* @cookie: transaction identifier to test status of
	438	* @last_complete: last know completed transaction
	439	* @last_used: last cookie value handed out
	440	*
	441	* dma_async_is_complete() is used in dma_async_memcpy_complete()
8a5703f8	442	* the test logic is separated for lightweight testing of multiple cookies
c13c8260 CL	443	*/
	444	static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
	445	dma_cookie_t last_complete, dma_cookie_t last_used)
	446	{
	447	if (last_complete <= last_used) {
	448	if ((cookie <= last_complete) \|\| (cookie > last_used))
	449	return DMA_SUCCESS;
	450	} else {
	451	if ((cookie <= last_complete) && (cookie > last_used))
	452	return DMA_SUCCESS;
	453	}
	454	return DMA_IN_PROGRESS;
	455	}
	456
7405f74b	457	enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
07f2211e DW	458	#ifdef CONFIG_DMA_ENGINE
07f2211e DW	459	enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
c50331e8	460	void dma_issue_pending_all(void);
07f2211e DW	461	#else
	462	static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
	463	{
	464	return DMA_SUCCESS;
	465	}
c50331e8 DW	466	static inline void dma_issue_pending_all(void)
	467	{
	468	do { } while (0);
	469	}
07f2211e	470	#endif
c13c8260 CL	471
	472	/* --- DMA device --- */
	473
	474	int dma_async_device_register(struct dma_device *device);
	475	void dma_async_device_unregister(struct dma_device *device);
07f2211e	476	void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
bec08513	477	struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
59b5ec21 DW	478	#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
	479	struct dma_chan __dma_request_channel(dma_cap_mask_t mask, dma_filter_fn fn, void *fn_param);
	480	void dma_release_channel(struct dma_chan *chan);
c13c8260	481
de5506e1 CL	482	/* --- Helper iov-locking functions --- */
	483
	484	struct dma_page_list {
b2ddb901	485	char __user *base_address;
de5506e1 CL	486	int nr_pages;
	487	struct page **pages;
	488	};
	489
	490	struct dma_pinned_list {
	491	int nr_iovecs;
	492	struct dma_page_list page_list[0];
	493	};
	494
	495	struct dma_pinned_list dma_pin_iovec_pages(struct iovec iov, size_t len);
	496	void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
	497
	498	dma_cookie_t dma_memcpy_to_iovec(struct dma_chan chan, struct iovec iov,
	499	struct dma_pinned_list pinned_list, unsigned char kdata, size_t len);
	500	dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan chan, struct iovec iov,
	501	struct dma_pinned_list pinned_list, struct page page,
	502	unsigned int offset, size_t len);
	503
c13c8260	504	#endif /* DMAENGINE_H */