[net-next-2.6.git] / include / linux / dma-mapping.h

#ifndef _LINUX_DMA_MAPPING_H
#define _LINUX_DMA_MAPPING_H

#include <linux/device.h>
#include <linux/err.h>
#include <linux/dma-attrs.h>
#include <linux/scatterlist.h>

/* These definitions mirror those in pci.h, so they can be used
 * interchangeably with their PCI_ counterparts */
enum dma_data_direction {
	DMA_BIDIRECTIONAL = 0,
	DMA_TO_DEVICE = 1,
	DMA_FROM_DEVICE = 2,
	DMA_NONE = 3,
};

struct dma_map_ops {
	void* (*alloc_coherent)(struct device *dev, size_t size,
				dma_addr_t *dma_handle, gfp_t gfp);
	void (*free_coherent)(struct device *dev, size_t size,
			      void *vaddr, dma_addr_t dma_handle);
	dma_addr_t (*map_page)(struct device *dev, struct page *page,
			       unsigned long offset, size_t size,
			       enum dma_data_direction dir,
			       struct dma_attrs *attrs);
	void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
			   size_t size, enum dma_data_direction dir,
			   struct dma_attrs *attrs);
	int (*map_sg)(struct device *dev, struct scatterlist *sg,
		      int nents, enum dma_data_direction dir,
		      struct dma_attrs *attrs);
	void (*unmap_sg)(struct device *dev,
			 struct scatterlist *sg, int nents,
			 enum dma_data_direction dir,
			 struct dma_attrs *attrs);
	void (*sync_single_for_cpu)(struct device *dev,
				    dma_addr_t dma_handle, size_t size,
				    enum dma_data_direction dir);
	void (*sync_single_for_device)(struct device *dev,
				       dma_addr_t dma_handle, size_t size,
				       enum dma_data_direction dir);
	void (*sync_sg_for_cpu)(struct device *dev,
				struct scatterlist *sg, int nents,
				enum dma_data_direction dir);
	void (*sync_sg_for_device)(struct device *dev,
				   struct scatterlist *sg, int nents,
				   enum dma_data_direction dir);
	int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
	int (*dma_supported)(struct device *dev, u64 mask);
	int (*set_dma_mask)(struct device *dev, u64 mask);
	int is_phys;
};

#define DMA_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))

typedef u64 DMA_nnBIT_MASK __deprecated;

/*
 * NOTE: do not use the below macros in new code and do not add new definitions
 * here.
 *
 * Instead, just open-code DMA_BIT_MASK(n) within your driver
 */
#define DMA_64BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(64)
#define DMA_48BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(48)
#define DMA_47BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(47)
#define DMA_40BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(40)
#define DMA_39BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(39)
#define DMA_35BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(35)
#define DMA_32BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(32)
#define DMA_31BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(31)
#define DMA_30BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(30)
#define DMA_29BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(29)
#define DMA_28BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(28)
#define DMA_24BIT_MASK	(DMA_nnBIT_MASK)DMA_BIT_MASK(24)

#define DMA_MASK_NONE	0x0ULL

static inline int valid_dma_direction(int dma_direction)
{
	return ((dma_direction == DMA_BIDIRECTIONAL) ||
		(dma_direction == DMA_TO_DEVICE) ||
		(dma_direction == DMA_FROM_DEVICE));
}

static inline int is_device_dma_capable(struct device *dev)
{
	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
}

#ifdef CONFIG_HAS_DMA
#include <asm/dma-mapping.h>
#else
#include <asm-generic/dma-mapping-broken.h>
#endif

static inline u64 dma_get_mask(struct device *dev)
{
	if (dev && dev->dma_mask && *dev->dma_mask)
		return *dev->dma_mask;
	return DMA_BIT_MASK(32);
}

static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
{
	if (!dma_supported(dev, mask))
		return -EIO;
	dev->coherent_dma_mask = mask;
	return 0;
}

extern u64 dma_get_required_mask(struct device *dev);

static inline unsigned int dma_get_max_seg_size(struct device *dev)
{
	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
}

static inline unsigned int dma_set_max_seg_size(struct device *dev,
						unsigned int size)
{
	if (dev->dma_parms) {
		dev->dma_parms->max_segment_size = size;
		return 0;
	} else
		return -EIO;
}

static inline unsigned long dma_get_seg_boundary(struct device *dev)
{
	return dev->dma_parms ?
		dev->dma_parms->segment_boundary_mask : 0xffffffff;
}

static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
{
	if (dev->dma_parms) {
		dev->dma_parms->segment_boundary_mask = mask;
		return 0;
	} else
		return -EIO;
}

#ifdef CONFIG_HAS_DMA
static inline int dma_get_cache_alignment(void)
{
#ifdef ARCH_DMA_MINALIGN
	return ARCH_DMA_MINALIGN;
#endif
	return 1;
}
#endif

/* flags for the coherent memory api */
#define	DMA_MEMORY_MAP			0x01
#define DMA_MEMORY_IO			0x02
#define DMA_MEMORY_INCLUDES_CHILDREN	0x04
#define DMA_MEMORY_EXCLUSIVE		0x08

#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
static inline int
dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
			    dma_addr_t device_addr, size_t size, int flags)
{
	return 0;
}

static inline void
dma_release_declared_memory(struct device *dev)
{
}

static inline void *
dma_mark_declared_memory_occupied(struct device *dev,
				  dma_addr_t device_addr, size_t size)
{
	return ERR_PTR(-EBUSY);
}
#endif

/*
 * Managed DMA API
 */
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
			       dma_addr_t dma_handle);
extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
				    dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
				  dma_addr_t dma_handle);
#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
					dma_addr_t device_addr, size_t size,
					int flags);
extern void dmam_release_declared_memory(struct device *dev);
#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
static inline int dmam_declare_coherent_memory(struct device *dev,
				dma_addr_t bus_addr, dma_addr_t device_addr,
				size_t size, gfp_t gfp)
{
	return 0;
}

static inline void dmam_release_declared_memory(struct device *dev)
{
}
#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */

#ifndef CONFIG_HAVE_DMA_ATTRS
struct dma_attrs;

#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	dma_map_single(dev, cpu_addr, size, dir)

#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	dma_unmap_single(dev, dma_addr, size, dir)

#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_map_sg(dev, sgl, nents, dir)

#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_unmap_sg(dev, sgl, nents, dir)

#endif /* CONFIG_HAVE_DMA_ATTRS */

#ifdef CONFIG_NEED_DMA_MAP_STATE
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)        dma_addr_t ADDR_NAME
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)          __u32 LEN_NAME
#define dma_unmap_addr(PTR, ADDR_NAME)           ((PTR)->ADDR_NAME)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  (((PTR)->ADDR_NAME) = (VAL))
#define dma_unmap_len(PTR, LEN_NAME)             ((PTR)->LEN_NAME)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    (((PTR)->LEN_NAME) = (VAL))
#else
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
#define dma_unmap_addr(PTR, ADDR_NAME)           (0)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  do { } while (0)
#define dma_unmap_len(PTR, LEN_NAME)             (0)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    do { } while (0)
#endif

#endif
Commit	Line	Data
96532bab RD	1	#ifndef _LINUX_DMA_MAPPING_H
96532bab RD	2	#define _LINUX_DMA_MAPPING_H
1da177e4 LT	3
	4	#include <linux/device.h>
	5	#include <linux/err.h>
f0402a26 FT	6	#include <linux/dma-attrs.h>
f0402a26 FT	7	#include <linux/scatterlist.h>
1da177e4 LT	8
	9	/* These definitions mirror those in pci.h, so they can be used
	10	* interchangeably with their PCI_ counterparts */
	11	enum dma_data_direction {
	12	DMA_BIDIRECTIONAL = 0,
	13	DMA_TO_DEVICE = 1,
	14	DMA_FROM_DEVICE = 2,
	15	DMA_NONE = 3,
	16	};
	17
f0402a26 FT	18	struct dma_map_ops {
	19	void* (alloc_coherent)(struct device dev, size_t size,
	20	dma_addr_t *dma_handle, gfp_t gfp);
	21	void (free_coherent)(struct device dev, size_t size,
	22	void *vaddr, dma_addr_t dma_handle);
	23	dma_addr_t (map_page)(struct device dev, struct page *page,
	24	unsigned long offset, size_t size,
	25	enum dma_data_direction dir,
	26	struct dma_attrs *attrs);
	27	void (unmap_page)(struct device dev, dma_addr_t dma_handle,
	28	size_t size, enum dma_data_direction dir,
	29	struct dma_attrs *attrs);
	30	int (map_sg)(struct device dev, struct scatterlist *sg,
	31	int nents, enum dma_data_direction dir,
	32	struct dma_attrs *attrs);
	33	void (unmap_sg)(struct device dev,
	34	struct scatterlist *sg, int nents,
	35	enum dma_data_direction dir,
	36	struct dma_attrs *attrs);
	37	void (sync_single_for_cpu)(struct device dev,
	38	dma_addr_t dma_handle, size_t size,
	39	enum dma_data_direction dir);
	40	void (sync_single_for_device)(struct device dev,
	41	dma_addr_t dma_handle, size_t size,
	42	enum dma_data_direction dir);
f0402a26 FT	43	void (sync_sg_for_cpu)(struct device dev,
	44	struct scatterlist *sg, int nents,
	45	enum dma_data_direction dir);
	46	void (sync_sg_for_device)(struct device dev,
	47	struct scatterlist *sg, int nents,
	48	enum dma_data_direction dir);
	49	int (mapping_error)(struct device dev, dma_addr_t dma_addr);
	50	int (dma_supported)(struct device dev, u64 mask);
f726f30e	51	int (set_dma_mask)(struct device dev, u64 mask);
f0402a26 FT	52	int is_phys;
	53	};
	54
8f286c33	55	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
34c65384	56
d68412b6 JS	57	typedef u64 DMA_nnBIT_MASK __deprecated;
d68412b6 JS	58
8f286c33 AM	59	/*
	60	* NOTE: do not use the below macros in new code and do not add new definitions
	61	* here.
	62	*
	63	* Instead, just open-code DMA_BIT_MASK(n) within your driver
	64	*/
d68412b6 JS	65	#define DMA_64BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(64)
	66	#define DMA_48BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(48)
	67	#define DMA_47BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(47)
	68	#define DMA_40BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(40)
	69	#define DMA_39BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(39)
	70	#define DMA_35BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(35)
	71	#define DMA_32BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(32)
	72	#define DMA_31BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(31)
	73	#define DMA_30BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(30)
	74	#define DMA_29BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(29)
	75	#define DMA_28BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(28)
	76	#define DMA_24BIT_MASK (DMA_nnBIT_MASK)DMA_BIT_MASK(24)
1da177e4	77
32e8f702 JB	78	#define DMA_MASK_NONE 0x0ULL
32e8f702 JB	79
d6bd3a39 REB	80	static inline int valid_dma_direction(int dma_direction)
	81	{
	82	return ((dma_direction == DMA_BIDIRECTIONAL) \|\|
	83	(dma_direction == DMA_TO_DEVICE) \|\|
	84	(dma_direction == DMA_FROM_DEVICE));
	85	}
	86
32e8f702 JB	87	static inline int is_device_dma_capable(struct device *dev)
	88	{
	89	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
	90	}
	91
1b0fac45	92	#ifdef CONFIG_HAS_DMA
1da177e4	93	#include <asm/dma-mapping.h>
1b0fac45 DW	94	#else
	95	#include <asm-generic/dma-mapping-broken.h>
	96	#endif
1da177e4	97
589fc9a6 FT	98	static inline u64 dma_get_mask(struct device *dev)
589fc9a6 FT	99	{
07a2c01a	100	if (dev && dev->dma_mask && *dev->dma_mask)
589fc9a6	101	return *dev->dma_mask;
284901a9	102	return DMA_BIT_MASK(32);
589fc9a6 FT	103	}
589fc9a6 FT	104
6a1961f4 FT	105	static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
	106	{
	107	if (!dma_supported(dev, mask))
	108	return -EIO;
	109	dev->coherent_dma_mask = mask;
	110	return 0;
	111	}
	112
1da177e4 LT	113	extern u64 dma_get_required_mask(struct device *dev);
1da177e4 LT	114
6b7b6510 FT	115	static inline unsigned int dma_get_max_seg_size(struct device *dev)
	116	{
	117	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
	118	}
	119
	120	static inline unsigned int dma_set_max_seg_size(struct device *dev,
	121	unsigned int size)
	122	{
	123	if (dev->dma_parms) {
	124	dev->dma_parms->max_segment_size = size;
	125	return 0;
	126	} else
	127	return -EIO;
	128	}
	129
d22a6966 FT	130	static inline unsigned long dma_get_seg_boundary(struct device *dev)
	131	{
	132	return dev->dma_parms ?
	133	dev->dma_parms->segment_boundary_mask : 0xffffffff;
	134	}
	135
	136	static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
	137	{
	138	if (dev->dma_parms) {
	139	dev->dma_parms->segment_boundary_mask = mask;
	140	return 0;
	141	} else
	142	return -EIO;
	143	}
	144
e259f191	145	#ifdef CONFIG_HAS_DMA
4565f017 FT	146	static inline int dma_get_cache_alignment(void)
	147	{
	148	#ifdef ARCH_DMA_MINALIGN
	149	return ARCH_DMA_MINALIGN;
	150	#endif
	151	return 1;
	152	}
e259f191	153	#endif
4565f017	154
1da177e4 LT	155	/* flags for the coherent memory api */
	156	#define DMA_MEMORY_MAP 0x01
	157	#define DMA_MEMORY_IO 0x02
	158	#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
	159	#define DMA_MEMORY_EXCLUSIVE 0x08
	160
	161	#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	162	static inline int
	163	dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	164	dma_addr_t device_addr, size_t size, int flags)
	165	{
	166	return 0;
	167	}
	168
	169	static inline void
	170	dma_release_declared_memory(struct device *dev)
	171	{
	172	}
	173
	174	static inline void *
	175	dma_mark_declared_memory_occupied(struct device *dev,
	176	dma_addr_t device_addr, size_t size)
	177	{
	178	return ERR_PTR(-EBUSY);
	179	}
	180	#endif
	181
9ac7849e TH	182	/*
	183	* Managed DMA API
	184	*/
	185	extern void dmam_alloc_coherent(struct device dev, size_t size,
	186	dma_addr_t *dma_handle, gfp_t gfp);
	187	extern void dmam_free_coherent(struct device dev, size_t size, void vaddr,
	188	dma_addr_t dma_handle);
	189	extern void dmam_alloc_noncoherent(struct device dev, size_t size,
	190	dma_addr_t *dma_handle, gfp_t gfp);
	191	extern void dmam_free_noncoherent(struct device dev, size_t size, void vaddr,
	192	dma_addr_t dma_handle);
	193	#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	194	extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	195	dma_addr_t device_addr, size_t size,
	196	int flags);
	197	extern void dmam_release_declared_memory(struct device *dev);
	198	#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
	199	static inline int dmam_declare_coherent_memory(struct device *dev,
	200	dma_addr_t bus_addr, dma_addr_t device_addr,
	201	size_t size, gfp_t gfp)
	202	{
	203	return 0;
	204	}
1da177e4	205
9ac7849e TH	206	static inline void dmam_release_declared_memory(struct device *dev)
	207	{
	208	}
	209	#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
1da177e4	210
74bc7cee AK	211	#ifndef CONFIG_HAVE_DMA_ATTRS
	212	struct dma_attrs;
	213
	214	#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	215	dma_map_single(dev, cpu_addr, size, dir)
	216
	217	#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	218	dma_unmap_single(dev, dma_addr, size, dir)
	219
	220	#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	221	dma_map_sg(dev, sgl, nents, dir)
	222
	223	#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	224	dma_unmap_sg(dev, sgl, nents, dir)
	225
	226	#endif /* CONFIG_HAVE_DMA_ATTRS */
	227
0acedc12 FT	228	#ifdef CONFIG_NEED_DMA_MAP_STATE
	229	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
	230	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
	231	#define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
	232	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
	233	#define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
	234	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
	235	#else
	236	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
	237	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
	238	#define dma_unmap_addr(PTR, ADDR_NAME) (0)
	239	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
	240	#define dma_unmap_len(PTR, LEN_NAME) (0)
	241	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
	242	#endif
	243
9ac7849e	244	#endif