[net-next-2.6.git] / include / linux / cs5535.h

/*
 * AMD CS5535/CS5536 definitions
 * Copyright (C) 2006  Advanced Micro Devices, Inc.
 * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 */

#ifndef _CS5535_H
#define _CS5535_H

/* MSRs */
#define MSR_LBAR_SMB		0x5140000B
#define MSR_LBAR_GPIO		0x5140000C
#define MSR_LBAR_MFGPT		0x5140000D
#define MSR_LBAR_ACPI		0x5140000E
#define MSR_LBAR_PMS		0x5140000F

#define MSR_DIVIL_SOFT_RESET	0x51400017

#define MSR_PIC_YSEL_LOW	0x51400020
#define MSR_PIC_YSEL_HIGH	0x51400021
#define MSR_PIC_ZSEL_LOW	0x51400022
#define MSR_PIC_ZSEL_HIGH	0x51400023
#define MSR_PIC_IRQM_LPC	0x51400025

#define MSR_MFGPT_IRQ		0x51400028
#define MSR_MFGPT_NR		0x51400029
#define MSR_MFGPT_SETUP		0x5140002B

/* resource sizes */
#define LBAR_GPIO_SIZE		0xFF
#define LBAR_MFGPT_SIZE		0x40
#define LBAR_ACPI_SIZE		0x40
#define LBAR_PMS_SIZE		0x80

/* VSA2 magic values */
#define VSA_VRC_INDEX		0xAC1C
#define VSA_VRC_DATA		0xAC1E
#define VSA_VR_UNLOCK		0xFC53  /* unlock virtual register */
#define VSA_VR_SIGNATURE	0x0003
#define VSA_VR_MEM_SIZE		0x0200
#define AMD_VSA_SIG		0x4132  /* signature is ascii 'VSA2' */
#define GSW_VSA_SIG		0x534d  /* General Software signature */

#include <linux/io.h>

static inline int cs5535_has_vsa2(void)
{
	static int has_vsa2 = -1;

	if (has_vsa2 == -1) {
		uint16_t val;

		/*
		 * The VSA has virtual registers that we can query for a
		 * signature.
		 */
		outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
		outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);

		val = inw(VSA_VRC_DATA);
		has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
	}

	return has_vsa2;
}

/* GPIOs */
#define GPIO_OUTPUT_VAL		0x00
#define GPIO_OUTPUT_ENABLE	0x04
#define GPIO_OUTPUT_OPEN_DRAIN	0x08
#define GPIO_OUTPUT_INVERT	0x0C
#define GPIO_OUTPUT_AUX1	0x10
#define GPIO_OUTPUT_AUX2	0x14
#define GPIO_PULL_UP		0x18
#define GPIO_PULL_DOWN		0x1C
#define GPIO_INPUT_ENABLE	0x20
#define GPIO_INPUT_INVERT	0x24
#define GPIO_INPUT_FILTER	0x28
#define GPIO_INPUT_EVENT_COUNT	0x2C
#define GPIO_READ_BACK		0x30
#define GPIO_INPUT_AUX1		0x34
#define GPIO_EVENTS_ENABLE	0x38
#define GPIO_LOCK_ENABLE	0x3C
#define GPIO_POSITIVE_EDGE_EN	0x40
#define GPIO_NEGATIVE_EDGE_EN	0x44
#define GPIO_POSITIVE_EDGE_STS	0x48
#define GPIO_NEGATIVE_EDGE_STS	0x4C

#define GPIO_MAP_X		0xE0
#define GPIO_MAP_Y		0xE4
#define GPIO_MAP_Z		0xE8
#define GPIO_MAP_W		0xEC

void cs5535_gpio_set(unsigned offset, unsigned int reg);
void cs5535_gpio_clear(unsigned offset, unsigned int reg);
int cs5535_gpio_isset(unsigned offset, unsigned int reg);

/* MFGPTs */

#define MFGPT_MAX_TIMERS	8
#define MFGPT_TIMER_ANY		(-1)

#define MFGPT_DOMAIN_WORKING	1
#define MFGPT_DOMAIN_STANDBY	2
#define MFGPT_DOMAIN_ANY	(MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)

#define MFGPT_CMP1		0
#define MFGPT_CMP2		1

#define MFGPT_EVENT_IRQ		0
#define MFGPT_EVENT_NMI		1
#define MFGPT_EVENT_RESET	3

#define MFGPT_REG_CMP1		0
#define MFGPT_REG_CMP2		2
#define MFGPT_REG_COUNTER	4
#define MFGPT_REG_SETUP		6

#define MFGPT_SETUP_CNTEN	(1 << 15)
#define MFGPT_SETUP_CMP2	(1 << 14)
#define MFGPT_SETUP_CMP1	(1 << 13)
#define MFGPT_SETUP_SETUP	(1 << 12)
#define MFGPT_SETUP_STOPEN	(1 << 11)
#define MFGPT_SETUP_EXTEN	(1 << 10)
#define MFGPT_SETUP_REVEN	(1 << 5)
#define MFGPT_SETUP_CLKSEL	(1 << 4)

struct cs5535_mfgpt_timer;

extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
		uint16_t reg);
extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
		uint16_t value);

extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
		int event, int enable);
extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
		int *irq, int enable);
extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
		int domain);
extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);

static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
		int cmp, int *irq)
{
	return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
}

static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
		int cmp, int *irq)
{
	return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
}

#endif
Commit	Line	Data
5f0a96b0 AS	1	/*
	2	* AMD CS5535/CS5536 definitions
	3	* Copyright (C) 2006 Advanced Micro Devices, Inc.
	4	* Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of version 2 of the GNU General Public License
	8	* as published by the Free Software Foundation.
	9	*/
	10
	11	#ifndef _CS5535_H
	12	#define _CS5535_H
	13
	14	/* MSRs */
	15	#define MSR_LBAR_SMB 0x5140000B
	16	#define MSR_LBAR_GPIO 0x5140000C
	17	#define MSR_LBAR_MFGPT 0x5140000D
	18	#define MSR_LBAR_ACPI 0x5140000E
	19	#define MSR_LBAR_PMS 0x5140000F
	20
2e8c1243 AS	21	#define MSR_DIVIL_SOFT_RESET 0x51400017
2e8c1243 AS	22
82dca611 AS	23	#define MSR_PIC_YSEL_LOW 0x51400020
	24	#define MSR_PIC_YSEL_HIGH 0x51400021
	25	#define MSR_PIC_ZSEL_LOW 0x51400022
	26	#define MSR_PIC_ZSEL_HIGH 0x51400023
	27	#define MSR_PIC_IRQM_LPC 0x51400025
	28
	29	#define MSR_MFGPT_IRQ 0x51400028
	30	#define MSR_MFGPT_NR 0x51400029
	31	#define MSR_MFGPT_SETUP 0x5140002B
	32
5f0a96b0 AS	33	/* resource sizes */
	34	#define LBAR_GPIO_SIZE 0xFF
	35	#define LBAR_MFGPT_SIZE 0x40
	36	#define LBAR_ACPI_SIZE 0x40
	37	#define LBAR_PMS_SIZE 0x80
	38
f060f270 AS	39	/* VSA2 magic values */
	40	#define VSA_VRC_INDEX 0xAC1C
	41	#define VSA_VRC_DATA 0xAC1E
	42	#define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
	43	#define VSA_VR_SIGNATURE 0x0003
	44	#define VSA_VR_MEM_SIZE 0x0200
	45	#define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
	46	#define GSW_VSA_SIG 0x534d /* General Software signature */
	47
	48	#include <linux/io.h>
	49
	50	static inline int cs5535_has_vsa2(void)
	51	{
	52	static int has_vsa2 = -1;
	53
	54	if (has_vsa2 == -1) {
	55	uint16_t val;
	56
	57	/*
	58	* The VSA has virtual registers that we can query for a
	59	* signature.
	60	*/
	61	outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
	62	outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
	63
	64	val = inw(VSA_VRC_DATA);
	65	has_vsa2 = (val == AMD_VSA_SIG \|\| val == GSW_VSA_SIG);
	66	}
	67
	68	return has_vsa2;
	69	}
	70
5f0a96b0 AS	71	/* GPIOs */
	72	#define GPIO_OUTPUT_VAL 0x00
	73	#define GPIO_OUTPUT_ENABLE 0x04
	74	#define GPIO_OUTPUT_OPEN_DRAIN 0x08
	75	#define GPIO_OUTPUT_INVERT 0x0C
	76	#define GPIO_OUTPUT_AUX1 0x10
	77	#define GPIO_OUTPUT_AUX2 0x14
	78	#define GPIO_PULL_UP 0x18
	79	#define GPIO_PULL_DOWN 0x1C
	80	#define GPIO_INPUT_ENABLE 0x20
	81	#define GPIO_INPUT_INVERT 0x24
	82	#define GPIO_INPUT_FILTER 0x28
	83	#define GPIO_INPUT_EVENT_COUNT 0x2C
	84	#define GPIO_READ_BACK 0x30
	85	#define GPIO_INPUT_AUX1 0x34
	86	#define GPIO_EVENTS_ENABLE 0x38
	87	#define GPIO_LOCK_ENABLE 0x3C
	88	#define GPIO_POSITIVE_EDGE_EN 0x40
	89	#define GPIO_NEGATIVE_EDGE_EN 0x44
	90	#define GPIO_POSITIVE_EDGE_STS 0x48
	91	#define GPIO_NEGATIVE_EDGE_STS 0x4C
	92
	93	#define GPIO_MAP_X 0xE0
	94	#define GPIO_MAP_Y 0xE4
	95	#define GPIO_MAP_Z 0xE8
	96	#define GPIO_MAP_W 0xEC
	97
	98	void cs5535_gpio_set(unsigned offset, unsigned int reg);
	99	void cs5535_gpio_clear(unsigned offset, unsigned int reg);
	100	int cs5535_gpio_isset(unsigned offset, unsigned int reg);
	101
82dca611 AS	102	/* MFGPTs */
	103
	104	#define MFGPT_MAX_TIMERS 8
	105	#define MFGPT_TIMER_ANY (-1)
	106
	107	#define MFGPT_DOMAIN_WORKING 1
	108	#define MFGPT_DOMAIN_STANDBY 2
	109	#define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING \| MFGPT_DOMAIN_STANDBY)
	110
	111	#define MFGPT_CMP1 0
	112	#define MFGPT_CMP2 1
	113
	114	#define MFGPT_EVENT_IRQ 0
	115	#define MFGPT_EVENT_NMI 1
	116	#define MFGPT_EVENT_RESET 3
	117
	118	#define MFGPT_REG_CMP1 0
	119	#define MFGPT_REG_CMP2 2
	120	#define MFGPT_REG_COUNTER 4
	121	#define MFGPT_REG_SETUP 6
	122
	123	#define MFGPT_SETUP_CNTEN (1 << 15)
	124	#define MFGPT_SETUP_CMP2 (1 << 14)
	125	#define MFGPT_SETUP_CMP1 (1 << 13)
	126	#define MFGPT_SETUP_SETUP (1 << 12)
	127	#define MFGPT_SETUP_STOPEN (1 << 11)
	128	#define MFGPT_SETUP_EXTEN (1 << 10)
	129	#define MFGPT_SETUP_REVEN (1 << 5)
	130	#define MFGPT_SETUP_CLKSEL (1 << 4)
	131
	132	struct cs5535_mfgpt_timer;
	133
	134	extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
	135	uint16_t reg);
	136	extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
	137	uint16_t value);
	138
	139	extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
	140	int event, int enable);
	141	extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
	142	int *irq, int enable);
	143	extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
	144	int domain);
	145	extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
	146
	147	static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
	148	int cmp, int *irq)
	149	{
	150	return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
	151	}
	152
	153	static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
	154	int cmp, int *irq)
	155	{
	156	return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
	157	}
	158
5f0a96b0	159	#endif