[net-next-2.6.git] / include / drm / mga_drm.h

/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jeff Hartmann <jhartmann@valinux.com>
 *    Keith Whitwell <keith@tungstengraphics.com>
 *
 * Rewritten by:
 *    Gareth Hughes <gareth@valinux.com>
 */

#ifndef __MGA_DRM_H__
#define __MGA_DRM_H__

#include "drm.h"

/* WARNING: If you change any of these defines, make sure to change the
 * defines in the Xserver file (mga_sarea.h)
 */

#ifndef __MGA_SAREA_DEFINES__
#define __MGA_SAREA_DEFINES__

/* WARP pipe flags
 */
#define MGA_F			0x1	/* fog */
#define MGA_A			0x2	/* alpha */
#define MGA_S			0x4	/* specular */
#define MGA_T2			0x8	/* multitexture */

#define MGA_WARP_TGZ		0
#define MGA_WARP_TGZF		(MGA_F)
#define MGA_WARP_TGZA		(MGA_A)
#define MGA_WARP_TGZAF		(MGA_F|MGA_A)
#define MGA_WARP_TGZS		(MGA_S)
#define MGA_WARP_TGZSF		(MGA_S|MGA_F)
#define MGA_WARP_TGZSA		(MGA_S|MGA_A)
#define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
#define MGA_WARP_T2GZ		(MGA_T2)
#define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
#define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
#define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
#define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
#define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
#define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
#define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)

#define MGA_MAX_G200_PIPES	8	/* no multitex */
#define MGA_MAX_G400_PIPES	16
#define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
#define MGA_WARP_UCODE_SIZE	32768	/* in bytes */

#define MGA_CARD_TYPE_G200	1
#define MGA_CARD_TYPE_G400	2
#define MGA_CARD_TYPE_G450	3	/* not currently used */
#define MGA_CARD_TYPE_G550	4

#define MGA_FRONT		0x1
#define MGA_BACK		0x2
#define MGA_DEPTH		0x4

/* What needs to be changed for the current vertex dma buffer?
 */
#define MGA_UPLOAD_CONTEXT	0x1
#define MGA_UPLOAD_TEX0		0x2
#define MGA_UPLOAD_TEX1		0x4
#define MGA_UPLOAD_PIPE		0x8
#define MGA_UPLOAD_TEX0IMAGE	0x10	/* handled client-side */
#define MGA_UPLOAD_TEX1IMAGE	0x20	/* handled client-side */
#define MGA_UPLOAD_2D		0x40
#define MGA_WAIT_AGE		0x80	/* handled client-side */
#define MGA_UPLOAD_CLIPRECTS	0x100	/* handled client-side */
#if 0
#define MGA_DMA_FLUSH		0x200	/* set when someone gets the lock
					   quiescent */
#endif

/* 32 buffers of 64k each, total 2 meg.
 */
#define MGA_BUFFER_SIZE		(1 << 16)
#define MGA_NUM_BUFFERS		128

/* Keep these small for testing.
 */
#define MGA_NR_SAREA_CLIPRECTS	8

/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
 * regions, subject to a minimum region size of (1<<16) == 64k.
 *
 * Clients may subdivide regions internally, but when sharing between
 * clients, the region size is the minimum granularity.
 */

#define MGA_CARD_HEAP			0
#define MGA_AGP_HEAP			1
#define MGA_NR_TEX_HEAPS		2
#define MGA_NR_TEX_REGIONS		16
#define MGA_LOG_MIN_TEX_REGION_SIZE	16

#define  DRM_MGA_IDLE_RETRY          2048

#endif				/* __MGA_SAREA_DEFINES__ */

/* Setup registers for 3D context
 */
typedef struct {
	unsigned int dstorg;
	unsigned int maccess;
	unsigned int plnwt;
	unsigned int dwgctl;
	unsigned int alphactrl;
	unsigned int fogcolor;
	unsigned int wflag;
	unsigned int tdualstage0;
	unsigned int tdualstage1;
	unsigned int fcol;
	unsigned int stencil;
	unsigned int stencilctl;
} drm_mga_context_regs_t;

/* Setup registers for 2D, X server
 */
typedef struct {
	unsigned int pitch;
} drm_mga_server_regs_t;

/* Setup registers for each texture unit
 */
typedef struct {
	unsigned int texctl;
	unsigned int texctl2;
	unsigned int texfilter;
	unsigned int texbordercol;
	unsigned int texorg;
	unsigned int texwidth;
	unsigned int texheight;
	unsigned int texorg1;
	unsigned int texorg2;
	unsigned int texorg3;
	unsigned int texorg4;
} drm_mga_texture_regs_t;

/* General aging mechanism
 */
typedef struct {
	unsigned int head;	/* Position of head pointer          */
	unsigned int wrap;	/* Primary DMA wrap count            */
} drm_mga_age_t;

typedef struct _drm_mga_sarea {
	/* The channel for communication of state information to the kernel
	 * on firing a vertex dma buffer.
	 */
	drm_mga_context_regs_t context_state;
	drm_mga_server_regs_t server_state;
	drm_mga_texture_regs_t tex_state[2];
	unsigned int warp_pipe;
	unsigned int dirty;
	unsigned int vertsize;

	/* The current cliprects, or a subset thereof.
	 */
	struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
	unsigned int nbox;

	/* Information about the most recently used 3d drawable.  The
	 * client fills in the req_* fields, the server fills in the
	 * exported_ fields and puts the cliprects into boxes, above.
	 *
	 * The client clears the exported_drawable field before
	 * clobbering the boxes data.
	 */
	unsigned int req_drawable;	/* the X drawable id */
	unsigned int req_draw_buffer;	/* MGA_FRONT or MGA_BACK */

	unsigned int exported_drawable;
	unsigned int exported_index;
	unsigned int exported_stamp;
	unsigned int exported_buffers;
	unsigned int exported_nfront;
	unsigned int exported_nback;
	int exported_back_x, exported_front_x, exported_w;
	int exported_back_y, exported_front_y, exported_h;
	struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];

	/* Counters for aging textures and for client-side throttling.
	 */
	unsigned int status[4];
	unsigned int last_wrap;

	drm_mga_age_t last_frame;
	unsigned int last_enqueue;	/* last time a buffer was enqueued */
	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
	unsigned int last_quiescent;	/*  */

	/* LRU lists for texture memory in agp space and on the card.
	 */
	struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
	unsigned int texAge[MGA_NR_TEX_HEAPS];

	/* Mechanism to validate card state.
	 */
	int ctxOwner;
} drm_mga_sarea_t;

/* MGA specific ioctls
 * The device specific ioctl range is 0x40 to 0x79.
 */
#define DRM_MGA_INIT     0x00
#define DRM_MGA_FLUSH    0x01
#define DRM_MGA_RESET    0x02
#define DRM_MGA_SWAP     0x03
#define DRM_MGA_CLEAR    0x04
#define DRM_MGA_VERTEX   0x05
#define DRM_MGA_INDICES  0x06
#define DRM_MGA_ILOAD    0x07
#define DRM_MGA_BLIT     0x08
#define DRM_MGA_GETPARAM 0x09

/* 3.2:
 * ioctls for operating on fences.
 */
#define DRM_MGA_SET_FENCE      0x0a
#define DRM_MGA_WAIT_FENCE     0x0b
#define DRM_MGA_DMA_BOOTSTRAP  0x0c

#define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
#define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
#define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
#define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
#define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
#define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
#define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
#define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
#define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)

typedef struct _drm_mga_warp_index {
	int installed;
	unsigned long phys_addr;
	int size;
} drm_mga_warp_index_t;

typedef struct drm_mga_init {
	enum {
		MGA_INIT_DMA = 0x01,
		MGA_CLEANUP_DMA = 0x02
	} func;

	unsigned long sarea_priv_offset;

	int chipset;
	int sgram;

	unsigned int maccess;

	unsigned int fb_cpp;
	unsigned int front_offset, front_pitch;
	unsigned int back_offset, back_pitch;

	unsigned int depth_cpp;
	unsigned int depth_offset, depth_pitch;

	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
	unsigned int texture_size[MGA_NR_TEX_HEAPS];

	unsigned long fb_offset;
	unsigned long mmio_offset;
	unsigned long status_offset;
	unsigned long warp_offset;
	unsigned long primary_offset;
	unsigned long buffers_offset;
} drm_mga_init_t;

typedef struct drm_mga_dma_bootstrap {
	/**
	 * \name AGP texture region
	 *
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
	 * be filled in with the actual AGP texture settings.
	 *
	 * \warning
	 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
	 * is zero, it means that PCI memory (most likely through the use of
	 * an IOMMU) is being used for "AGP" textures.
	 */
	/*@{ */
	unsigned long texture_handle; /**< Handle used to map AGP textures. */
	__u32 texture_size;	      /**< Size of the AGP texture region. */
	/*@} */

	/**
	 * Requested size of the primary DMA region.
	 *
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	 * filled in with the actual AGP mode.  If AGP was not available
	 */
	__u32 primary_size;

	/**
	 * Requested number of secondary DMA buffers.
	 *
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	 * filled in with the actual number of secondary DMA buffers
	 * allocated.  Particularly when PCI DMA is used, this may be
	 * (subtantially) less than the number requested.
	 */
	__u32 secondary_bin_count;

	/**
	 * Requested size of each secondary DMA buffer.
	 *
	 * While the kernel \b is free to reduce
	 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
	 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
	 */
	__u32 secondary_bin_size;

	/**
	 * Bit-wise mask of AGPSTAT2_* values.  Currently only \c AGPSTAT2_1X,
	 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported.  If this value is
	 * zero, it means that PCI DMA should be used, even if AGP is
	 * possible.
	 *
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	 * filled in with the actual AGP mode.  If AGP was not available
	 * (i.e., PCI DMA was used), this value will be zero.
	 */
	__u32 agp_mode;

	/**
	 * Desired AGP GART size, measured in megabytes.
	 */
	__u8 agp_size;
} drm_mga_dma_bootstrap_t;

typedef struct drm_mga_clear {
	unsigned int flags;
	unsigned int clear_color;
	unsigned int clear_depth;
	unsigned int color_mask;
	unsigned int depth_mask;
} drm_mga_clear_t;

typedef struct drm_mga_vertex {
	int idx;		/* buffer to queue */
	int used;		/* bytes in use */
	int discard;		/* client finished with buffer?  */
} drm_mga_vertex_t;

typedef struct drm_mga_indices {
	int idx;		/* buffer to queue */
	unsigned int start;
	unsigned int end;
	int discard;		/* client finished with buffer?  */
} drm_mga_indices_t;

typedef struct drm_mga_iload {
	int idx;
	unsigned int dstorg;
	unsigned int length;
} drm_mga_iload_t;

typedef struct _drm_mga_blit {
	unsigned int planemask;
	unsigned int srcorg;
	unsigned int dstorg;
	int src_pitch, dst_pitch;
	int delta_sx, delta_sy;
	int delta_dx, delta_dy;
	int height, ydir;	/* flip image vertically */
	int source_pitch, dest_pitch;
} drm_mga_blit_t;

/* 3.1: An ioctl to get parameters that aren't available to the 3d
 * client any other way.
 */
#define MGA_PARAM_IRQ_NR            1

/* 3.2: Query the actual card type.  The DDX only distinguishes between
 * G200 chips and non-G200 chips, which it calls G400.  It turns out that
 * there are some very sublte differences between the G4x0 chips and the G550
 * chips.  Using this parameter query, a client-side driver can detect the
 * difference between a G4x0 and a G550.
 */
#define MGA_PARAM_CARD_TYPE         2

typedef struct drm_mga_getparam {
	int param;
	void __user *value;
} drm_mga_getparam_t;

#endif
Commit	Line	Data
1da177e4 LT	1	/* mga_drm.h -- Public header for the Matrox g200/g400 driver -- linux-c --
	2	* Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
	3	*
	4	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
	5	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
	6	* All rights reserved.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice (including the next
	16	* paragraph) shall be included in all copies or substantial portions of the
	17	* Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	23	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	24	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	25	* OTHER DEALINGS IN THE SOFTWARE.
	26	*
	27	* Authors:
	28	* Jeff Hartmann <jhartmann@valinux.com>
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	*
	31	* Rewritten by:
	32	* Gareth Hughes <gareth@valinux.com>
	33	*/
	34
	35	#ifndef __MGA_DRM_H__
	36	#define __MGA_DRM_H__
	37
1a95916f	38	#include "drm.h"
1d7f83d5	39
1da177e4 LT	40	/* WARNING: If you change any of these defines, make sure to change the
	41	* defines in the Xserver file (mga_sarea.h)
	42	*/
	43
	44	#ifndef __MGA_SAREA_DEFINES__
	45	#define __MGA_SAREA_DEFINES__
	46
	47	/* WARP pipe flags
	48	*/
b5e89ed5 DA	49	#define MGA_F 0x1 /* fog */
	50	#define MGA_A 0x2 /* alpha */
	51	#define MGA_S 0x4 /* specular */
	52	#define MGA_T2 0x8 /* multitexture */
1da177e4 LT	53
	54	#define MGA_WARP_TGZ 0
	55	#define MGA_WARP_TGZF (MGA_F)
	56	#define MGA_WARP_TGZA (MGA_A)
	57	#define MGA_WARP_TGZAF (MGA_F\|MGA_A)
	58	#define MGA_WARP_TGZS (MGA_S)
	59	#define MGA_WARP_TGZSF (MGA_S\|MGA_F)
	60	#define MGA_WARP_TGZSA (MGA_S\|MGA_A)
	61	#define MGA_WARP_TGZSAF (MGA_S\|MGA_F\|MGA_A)
	62	#define MGA_WARP_T2GZ (MGA_T2)
	63	#define MGA_WARP_T2GZF (MGA_T2\|MGA_F)
	64	#define MGA_WARP_T2GZA (MGA_T2\|MGA_A)
	65	#define MGA_WARP_T2GZAF (MGA_T2\|MGA_A\|MGA_F)
	66	#define MGA_WARP_T2GZS (MGA_T2\|MGA_S)
	67	#define MGA_WARP_T2GZSF (MGA_T2\|MGA_S\|MGA_F)
	68	#define MGA_WARP_T2GZSA (MGA_T2\|MGA_S\|MGA_A)
	69	#define MGA_WARP_T2GZSAF (MGA_T2\|MGA_S\|MGA_F\|MGA_A)
	70
b5e89ed5	71	#define MGA_MAX_G200_PIPES 8 /* no multitex */
1da177e4 LT	72	#define MGA_MAX_G400_PIPES 16
1da177e4 LT	73	#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
b5e89ed5	74	#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
1da177e4 LT	75
	76	#define MGA_CARD_TYPE_G200 1
	77	#define MGA_CARD_TYPE_G400 2
b5e89ed5	78	#define MGA_CARD_TYPE_G450 3 /* not currently used */
93f453f3	79	#define MGA_CARD_TYPE_G550 4
1da177e4 LT	80
	81	#define MGA_FRONT 0x1
	82	#define MGA_BACK 0x2
	83	#define MGA_DEPTH 0x4
	84
	85	/* What needs to be changed for the current vertex dma buffer?
	86	*/
	87	#define MGA_UPLOAD_CONTEXT 0x1
	88	#define MGA_UPLOAD_TEX0 0x2
	89	#define MGA_UPLOAD_TEX1 0x4
	90	#define MGA_UPLOAD_PIPE 0x8
b5e89ed5 DA	91	#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
b5e89ed5 DA	92	#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
1da177e4	93	#define MGA_UPLOAD_2D 0x40
b5e89ed5 DA	94	#define MGA_WAIT_AGE 0x80 /* handled client-side */
b5e89ed5 DA	95	#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
1da177e4	96	#if 0
b5e89ed5 DA	97	#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
b5e89ed5 DA	98	quiescent */
1da177e4 LT	99	#endif
	100
	101	/* 32 buffers of 64k each, total 2 meg.
	102	*/
	103	#define MGA_BUFFER_SIZE (1 << 16)
	104	#define MGA_NUM_BUFFERS 128
	105
	106	/* Keep these small for testing.
	107	*/
	108	#define MGA_NR_SAREA_CLIPRECTS 8
	109
	110	/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
	111	* regions, subject to a minimum region size of (1<<16) == 64k.
	112	*
	113	* Clients may subdivide regions internally, but when sharing between
	114	* clients, the region size is the minimum granularity.
	115	*/
	116
	117	#define MGA_CARD_HEAP 0
	118	#define MGA_AGP_HEAP 1
	119	#define MGA_NR_TEX_HEAPS 2
	120	#define MGA_NR_TEX_REGIONS 16
	121	#define MGA_LOG_MIN_TEX_REGION_SIZE 16
	122
	123	#define DRM_MGA_IDLE_RETRY 2048
	124
b5e89ed5	125	#endif /* __MGA_SAREA_DEFINES__ */
1da177e4 LT	126
	127	/* Setup registers for 3D context
	128	*/
	129	typedef struct {
	130	unsigned int dstorg;
	131	unsigned int maccess;
	132	unsigned int plnwt;
	133	unsigned int dwgctl;
	134	unsigned int alphactrl;
	135	unsigned int fogcolor;
	136	unsigned int wflag;
	137	unsigned int tdualstage0;
	138	unsigned int tdualstage1;
	139	unsigned int fcol;
	140	unsigned int stencil;
	141	unsigned int stencilctl;
	142	} drm_mga_context_regs_t;
	143
	144	/* Setup registers for 2D, X server
	145	*/
	146	typedef struct {
	147	unsigned int pitch;
	148	} drm_mga_server_regs_t;
	149
	150	/* Setup registers for each texture unit
	151	*/
	152	typedef struct {
	153	unsigned int texctl;
	154	unsigned int texctl2;
	155	unsigned int texfilter;
	156	unsigned int texbordercol;
	157	unsigned int texorg;
	158	unsigned int texwidth;
	159	unsigned int texheight;
	160	unsigned int texorg1;
	161	unsigned int texorg2;
	162	unsigned int texorg3;
	163	unsigned int texorg4;
	164	} drm_mga_texture_regs_t;
	165
	166	/* General aging mechanism
	167	*/
	168	typedef struct {
b5e89ed5 DA	169	unsigned int head; /* Position of head pointer */
b5e89ed5 DA	170	unsigned int wrap; /* Primary DMA wrap count */
1da177e4 LT	171	} drm_mga_age_t;
	172
	173	typedef struct _drm_mga_sarea {
	174	/* The channel for communication of state information to the kernel
	175	* on firing a vertex dma buffer.
	176	*/
b5e89ed5 DA	177	drm_mga_context_regs_t context_state;
	178	drm_mga_server_regs_t server_state;
	179	drm_mga_texture_regs_t tex_state[2];
	180	unsigned int warp_pipe;
	181	unsigned int dirty;
	182	unsigned int vertsize;
1da177e4 LT	183
	184	/* The current cliprects, or a subset thereof.
	185	*/
eddca551	186	struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
b5e89ed5	187	unsigned int nbox;
1da177e4 LT	188
	189	/* Information about the most recently used 3d drawable. The
	190	* client fills in the req_* fields, the server fills in the
	191	* exported_ fields and puts the cliprects into boxes, above.
	192	*
	193	* The client clears the exported_drawable field before
	194	* clobbering the boxes data.
	195	*/
b5e89ed5 DA	196	unsigned int req_drawable; /* the X drawable id */
b5e89ed5 DA	197	unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
1da177e4	198
b5e89ed5	199	unsigned int exported_drawable;
1da177e4	200	unsigned int exported_index;
b5e89ed5 DA	201	unsigned int exported_stamp;
	202	unsigned int exported_buffers;
	203	unsigned int exported_nfront;
	204	unsigned int exported_nback;
1da177e4 LT	205	int exported_back_x, exported_front_x, exported_w;
1da177e4 LT	206	int exported_back_y, exported_front_y, exported_h;
eddca551	207	struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
1da177e4 LT	208
	209	/* Counters for aging textures and for client-side throttling.
	210	*/
	211	unsigned int status[4];
	212	unsigned int last_wrap;
	213
	214	drm_mga_age_t last_frame;
b5e89ed5	215	unsigned int last_enqueue; /* last time a buffer was enqueued */
1da177e4	216	unsigned int last_dispatch; /* age of the most recently dispatched buffer */
b5e89ed5	217	unsigned int last_quiescent; /* */
1da177e4 LT	218
	219	/* LRU lists for texture memory in agp space and on the card.
	220	*/
eddca551	221	struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
1da177e4 LT	222	unsigned int texAge[MGA_NR_TEX_HEAPS];
	223
	224	/* Mechanism to validate card state.
	225	*/
b5e89ed5	226	int ctxOwner;
1da177e4 LT	227	} drm_mga_sarea_t;
1da177e4 LT	228
1da177e4 LT	229	/* MGA specific ioctls
	230	* The device specific ioctl range is 0x40 to 0x79.
	231	*/
	232	#define DRM_MGA_INIT 0x00
	233	#define DRM_MGA_FLUSH 0x01
	234	#define DRM_MGA_RESET 0x02
	235	#define DRM_MGA_SWAP 0x03
	236	#define DRM_MGA_CLEAR 0x04
	237	#define DRM_MGA_VERTEX 0x05
	238	#define DRM_MGA_INDICES 0x06
	239	#define DRM_MGA_ILOAD 0x07
	240	#define DRM_MGA_BLIT 0x08
	241	#define DRM_MGA_GETPARAM 0x09
	242
6795c985 DA	243	/* 3.2:
	244	* ioctls for operating on fences.
	245	*/
	246	#define DRM_MGA_SET_FENCE 0x0a
	247	#define DRM_MGA_WAIT_FENCE 0x0b
	248	#define DRM_MGA_DMA_BOOTSTRAP 0x0c
	249
1da177e4	250	#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
1b2f1489	251	#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
1da177e4 LT	252	#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
	253	#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
	254	#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
	255	#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
	256	#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
	257	#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
	258	#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
	259	#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
1d7f83d5 AB	260	#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
1d7f83d5 AB	261	#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
6795c985	262	#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
1da177e4 LT	263
1da177e4 LT	264	typedef struct _drm_mga_warp_index {
b5e89ed5 DA	265	int installed;
	266	unsigned long phys_addr;
	267	int size;
1da177e4 LT	268	} drm_mga_warp_index_t;
	269
	270	typedef struct drm_mga_init {
b5e89ed5 DA	271	enum {
	272	MGA_INIT_DMA = 0x01,
	273	MGA_CLEANUP_DMA = 0x02
1da177e4 LT	274	} func;
1da177e4 LT	275
b5e89ed5	276	unsigned long sarea_priv_offset;
1da177e4 LT	277
1da177e4 LT	278	int chipset;
b5e89ed5	279	int sgram;
1da177e4 LT	280
	281	unsigned int maccess;
	282
b5e89ed5	283	unsigned int fb_cpp;
1da177e4	284	unsigned int front_offset, front_pitch;
b5e89ed5	285	unsigned int back_offset, back_pitch;
1da177e4	286
b5e89ed5 DA	287	unsigned int depth_cpp;
b5e89ed5 DA	288	unsigned int depth_offset, depth_pitch;
1da177e4	289
b5e89ed5 DA	290	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
b5e89ed5 DA	291	unsigned int texture_size[MGA_NR_TEX_HEAPS];
1da177e4 LT	292
	293	unsigned long fb_offset;
	294	unsigned long mmio_offset;
	295	unsigned long status_offset;
	296	unsigned long warp_offset;
	297	unsigned long primary_offset;
	298	unsigned long buffers_offset;
	299	} drm_mga_init_t;
	300
6795c985 DA	301	typedef struct drm_mga_dma_bootstrap {
	302	/**
	303	* \name AGP texture region
b5e89ed5	304	*
6795c985 DA	305	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
6795c985 DA	306	* be filled in with the actual AGP texture settings.
b5e89ed5	307	*
6795c985 DA	308	* \warning
	309	* If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
	310	* is zero, it means that PCI memory (most likely through the use of
	311	* an IOMMU) is being used for "AGP" textures.
	312	*/
b5e89ed5	313	/@{ /
d1f2b55a	314	unsigned long texture_handle; /*< Handle used to map AGP textures. /
1d7f83d5	315	__u32 texture_size; /*< Size of the AGP texture region. /
b5e89ed5	316	/@} /
6795c985 DA	317
	318	/**
	319	* Requested size of the primary DMA region.
b5e89ed5	320	*
6795c985 DA	321	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	322	* filled in with the actual AGP mode. If AGP was not available
	323	*/
1d7f83d5	324	__u32 primary_size;
6795c985	325
6795c985 DA	326	/**
6795c985 DA	327	* Requested number of secondary DMA buffers.
b5e89ed5	328	*
6795c985 DA	329	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	330	* filled in with the actual number of secondary DMA buffers
	331	* allocated. Particularly when PCI DMA is used, this may be
	332	* (subtantially) less than the number requested.
	333	*/
1d7f83d5	334	__u32 secondary_bin_count;
b5e89ed5	335
6795c985 DA	336	/**
6795c985 DA	337	* Requested size of each secondary DMA buffer.
b5e89ed5	338	*
6795c985 DA	339	* While the kernel \b is free to reduce
	340	* dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
	341	* to reduce dma_mga_dma_bootstrap::secondary_bin_size.
	342	*/
1d7f83d5	343	__u32 secondary_bin_size;
6795c985	344
6795c985 DA	345	/**
	346	* Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
	347	* \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
	348	* zero, it means that PCI DMA should be used, even if AGP is
	349	* possible.
b5e89ed5	350	*
6795c985 DA	351	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	352	* filled in with the actual AGP mode. If AGP was not available
	353	* (i.e., PCI DMA was used), this value will be zero.
	354	*/
1d7f83d5	355	__u32 agp_mode;
6795c985	356
6795c985 DA	357	/**
	358	* Desired AGP GART size, measured in megabytes.
	359	*/
1d7f83d5	360	__u8 agp_size;
6795c985	361	} drm_mga_dma_bootstrap_t;
1da177e4 LT	362
	363	typedef struct drm_mga_clear {
	364	unsigned int flags;
	365	unsigned int clear_color;
	366	unsigned int clear_depth;
	367	unsigned int color_mask;
	368	unsigned int depth_mask;
	369	} drm_mga_clear_t;
	370
	371	typedef struct drm_mga_vertex {
b5e89ed5 DA	372	int idx; /* buffer to queue */
	373	int used; /* bytes in use */
	374	int discard; /* client finished with buffer? */
1da177e4 LT	375	} drm_mga_vertex_t;
	376
	377	typedef struct drm_mga_indices {
b5e89ed5	378	int idx; /* buffer to queue */
1da177e4 LT	379	unsigned int start;
1da177e4 LT	380	unsigned int end;
b5e89ed5	381	int discard; /* client finished with buffer? */
1da177e4 LT	382	} drm_mga_indices_t;
	383
	384	typedef struct drm_mga_iload {
	385	int idx;
	386	unsigned int dstorg;
	387	unsigned int length;
	388	} drm_mga_iload_t;
	389
	390	typedef struct _drm_mga_blit {
	391	unsigned int planemask;
	392	unsigned int srcorg;
	393	unsigned int dstorg;
	394	int src_pitch, dst_pitch;
	395	int delta_sx, delta_sy;
	396	int delta_dx, delta_dy;
b5e89ed5	397	int height, ydir; /* flip image vertically */
1da177e4 LT	398	int source_pitch, dest_pitch;
	399	} drm_mga_blit_t;
	400
	401	/* 3.1: An ioctl to get parameters that aren't available to the 3d
b5e89ed5	402	* client any other way.
1da177e4 LT	403	*/
	404	#define MGA_PARAM_IRQ_NR 1
	405
6795c985 DA	406	/* 3.2: Query the actual card type. The DDX only distinguishes between
	407	* G200 chips and non-G200 chips, which it calls G400. It turns out that
	408	* there are some very sublte differences between the G4x0 chips and the G550
	409	* chips. Using this parameter query, a client-side driver can detect the
	410	* difference between a G4x0 and a G550.
	411	*/
	412	#define MGA_PARAM_CARD_TYPE 2
	413
1da177e4 LT	414	typedef struct drm_mga_getparam {
	415	int param;
	416	void __user *value;
	417	} drm_mga_getparam_t;
	418
	419	#endif