[net-next-2.6.git] / include / asm-mips / processor.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 Waldorf GMBH
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 */
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H

#include <linux/cpumask.h>
#include <linux/threads.h>

#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/mipsregs.h>
#include <asm/prefetch.h>
#include <asm/system.h>

/*
 * Return current * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/*
 * System setup and hardware flags..
 */
extern void (*cpu_wait)(void);

extern unsigned int vced_count, vcei_count;

#ifdef CONFIG_32BIT
/*
 * User space process size: 2GB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.
 */
#define TASK_SIZE	0x7fff8000UL

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 3))
#endif

#ifdef CONFIG_64BIT
/*
 * User space process size: 1TB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.  TASK_SIZE
 * is limited to 1TB by the R4000 architecture; R10000 and better can
 * support 16TB; the architectural reserve for future expansion is
 * 8192EB ...
 */
#define TASK_SIZE32	0x7fff8000UL
#define TASK_SIZE	0x10000000000UL

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE						\
	(test_thread_flag(TIF_32BIT_ADDR) ?				\
		PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
#define TASK_SIZE_OF(tsk)						\
	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
#endif

#define NUM_FPU_REGS	32

typedef __u64 fpureg_t;

/*
 * It would be nice to add some more fields for emulator statistics, but there
 * are a number of fixed offsets in offset.h and elsewhere that would have to
 * be recalculated by hand.  So the additional information will be private to
 * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 */

struct mips_fpu_struct {
	fpureg_t	fpr[NUM_FPU_REGS];
	unsigned int	fcr31;
};

#define NUM_DSP_REGS   6

typedef __u32 dspreg_t;

struct mips_dsp_state {
	dspreg_t        dspr[NUM_DSP_REGS];
	unsigned int    dspcontrol;
};

#define INIT_CPUMASK { \
	{0,} \
}

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define ARCH_MIN_TASKALIGN	8

struct mips_abi;

/*
 * If you change thread_struct remember to change the #defines below too!
 */
struct thread_struct {
	/* Saved main processor registers. */
	unsigned long reg16;
	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
	unsigned long reg29, reg30, reg31;

	/* Saved cp0 stuff. */
	unsigned long cp0_status;

	/* Saved fpu/fpu emulator stuff. */
	struct mips_fpu_struct fpu;
#ifdef CONFIG_MIPS_MT_FPAFF
	/* Emulated instruction count */
	unsigned long emulated_fp;
	/* Saved per-thread scheduler affinity mask */
	cpumask_t user_cpus_allowed;
#endif /* CONFIG_MIPS_MT_FPAFF */

	/* Saved state of the DSP ASE, if available. */
	struct mips_dsp_state dsp;

	/* Other stuff associated with the thread. */
	unsigned long cp0_badvaddr;	/* Last user fault */
	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
	unsigned long error_code;
	unsigned long trap_no;
	unsigned long irix_trampoline;  /* Wheee... */
	unsigned long irix_oldctx;
	struct mips_abi *abi;
};

#ifdef CONFIG_MIPS_MT_FPAFF
#define FPAFF_INIT						\
	.emulated_fp			= 0,			\
	.user_cpus_allowed		= INIT_CPUMASK,
#else
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */

#define INIT_THREAD  {						\
        /*							\
         * Saved main processor registers			\
         */							\
	.reg16			= 0,				\
	.reg17			= 0,				\
	.reg18			= 0,				\
	.reg19			= 0,				\
	.reg20			= 0,				\
	.reg21			= 0,				\
	.reg22			= 0,				\
	.reg23			= 0,				\
	.reg29			= 0,				\
	.reg30			= 0,				\
	.reg31			= 0,				\
	/*							\
	 * Saved cp0 stuff					\
	 */							\
	.cp0_status		= 0,				\
	/*							\
	 * Saved FPU/FPU emulator stuff				\
	 */							\
	.fpu			= {				\
		.fpr		= {0,},				\
		.fcr31		= 0,				\
	},							\
	/*							\
	 * FPU affinity state (null if not FPAFF)		\
	 */							\
	FPAFF_INIT						\
	/*							\
	 * Saved DSP stuff					\
	 */							\
	.dsp			= {				\
		.dspr		= {0, },			\
		.dspcontrol	= 0,				\
	},							\
	/*							\
	 * Other stuff associated with the process		\
	 */							\
	.cp0_badvaddr		= 0,				\
	.cp0_baduaddr		= 0,				\
	.error_code		= 0,				\
	.trap_no		= 0,				\
	.irix_trampoline	= 0,				\
	.irix_oldctx		= 0,				\
}

struct task_struct;

/* Free all resources held by a thread. */
#define release_thread(thread) do { } while(0)

/* Prepare to copy thread state - unlazy all lazy status */
#define prepare_to_copy(tsk)	do { } while (0)

extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);

extern unsigned long thread_saved_pc(struct task_struct *tsk);

/*
 * Do necessary setup to start up a newly executed thread.
 */
extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);

unsigned long get_wchan(struct task_struct *p);

#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32)
#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1)
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)

#define cpu_relax()	barrier()

/*
 * Return_address is a replacement for __builtin_return_address(count)
 * which on certain architectures cannot reasonably be implemented in GCC
 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 * aborts compilation on some CPUs.  It's simply not possible to unwind
 * some CPU's stackframes.
 *
 * __builtin_return_address works only for non-leaf functions.  We avoid the
 * overhead of a function call by forcing the compiler to save the return
 * address register on the stack.
 */
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})

#ifdef CONFIG_CPU_HAS_PREFETCH

#define ARCH_HAS_PREFETCH

static inline void prefetch(const void *addr)
{
	__asm__ __volatile__(
	"	.set	mips4		\n"
	"	pref	%0, (%1)	\n"
	"	.set	mips0		\n"
	:
	: "i" (Pref_Load), "r" (addr));
}

#endif

#endif /* _ASM_PROCESSOR_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 Waldorf GMBH
	7	* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
	8	* Copyright (C) 1996 Paul M. Antoine
	9	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	10	*/
	11	#ifndef _ASM_PROCESSOR_H
	12	#define _ASM_PROCESSOR_H
	13
41c594ab	14	#include <linux/cpumask.h>
1da177e4 LT	15	#include <linux/threads.h>
	16
	17	#include <asm/cachectl.h>
	18	#include <asm/cpu.h>
	19	#include <asm/cpu-info.h>
	20	#include <asm/mipsregs.h>
	21	#include <asm/prefetch.h>
	22	#include <asm/system.h>
	23
	24	/*
	25	* Return current * instruction pointer ("program counter").
	26	*/
	27	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	28
	29	/*
	30	* System setup and hardware flags..
	31	*/
	32	extern void (*cpu_wait)(void);
	33
	34	extern unsigned int vced_count, vcei_count;
	35
875d43e7	36	#ifdef CONFIG_32BIT
1da177e4 LT	37	/*
	38	* User space process size: 2GB. This is hardcoded into a few places,
	39	* so don't change it unless you know what you are doing.
	40	*/
	41	#define TASK_SIZE 0x7fff8000UL
	42
	43	/*
	44	* This decides where the kernel will search for a free chunk of vm
	45	* space during mmap's.
	46	*/
	47	#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
	48	#endif
	49
875d43e7	50	#ifdef CONFIG_64BIT
1da177e4 LT	51	/*
	52	* User space process size: 1TB. This is hardcoded into a few places,
	53	* so don't change it unless you know what you are doing. TASK_SIZE
	54	* is limited to 1TB by the R4000 architecture; R10000 and better can
	55	* support 16TB; the architectural reserve for future expansion is
	56	* 8192EB ...
	57	*/
	58	#define TASK_SIZE32 0x7fff8000UL
	59	#define TASK_SIZE 0x10000000000UL
	60
	61	/*
	62	* This decides where the kernel will search for a free chunk of vm
	63	* space during mmap's.
	64	*/
293c5bd1 RB	65	#define TASK_UNMAPPED_BASE \
	66	(test_thread_flag(TIF_32BIT_ADDR) ? \
	67	PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
82455257 DH	68	#define TASK_SIZE_OF(tsk) \
82455257 DH	69	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
1da177e4 LT	70	#endif
	71
	72	#define NUM_FPU_REGS 32
	73
	74	typedef __u64 fpureg_t;
	75
1da177e4 LT	76	/*
	77	* It would be nice to add some more fields for emulator statistics, but there
	78	* are a number of fixed offsets in offset.h and elsewhere that would have to
	79	* be recalculated by hand. So the additional information will be private to
	80	* the FPU emulator for now. See asm-mips/fpu_emulator.h.
	81	*/
	82
eae89076	83	struct mips_fpu_struct {
1da177e4 LT	84	fpureg_t fpr[NUM_FPU_REGS];
	85	unsigned int fcr31;
	86	};
	87
e50c0a8f RB	88	#define NUM_DSP_REGS 6
	89
	90	typedef __u32 dspreg_t;
	91
	92	struct mips_dsp_state {
	93	dspreg_t dspr[NUM_DSP_REGS];
	94	unsigned int dspcontrol;
e50c0a8f RB	95	};
e50c0a8f RB	96
41c594ab RB	97	#define INIT_CPUMASK { \
	98	{0,} \
	99	}
	100
1da177e4 LT	101	typedef struct {
	102	unsigned long seg;
	103	} mm_segment_t;
	104
	105	#define ARCH_MIN_TASKALIGN 8
	106
e50c0a8f RB	107	struct mips_abi;
e50c0a8f RB	108
1da177e4 LT	109	/*
	110	* If you change thread_struct remember to change the #defines below too!
	111	*/
	112	struct thread_struct {
	113	/* Saved main processor registers. */
	114	unsigned long reg16;
	115	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
	116	unsigned long reg29, reg30, reg31;
	117
	118	/* Saved cp0 stuff. */
	119	unsigned long cp0_status;
	120
	121	/* Saved fpu/fpu emulator stuff. */
eae89076	122	struct mips_fpu_struct fpu;
f088fc84 RB	123	#ifdef CONFIG_MIPS_MT_FPAFF
	124	/* Emulated instruction count */
	125	unsigned long emulated_fp;
	126	/* Saved per-thread scheduler affinity mask */
	127	cpumask_t user_cpus_allowed;
	128	#endif /* CONFIG_MIPS_MT_FPAFF */
1da177e4	129
e50c0a8f RB	130	/* Saved state of the DSP ASE, if available. */
	131	struct mips_dsp_state dsp;
	132
1da177e4 LT	133	/* Other stuff associated with the thread. */
	134	unsigned long cp0_badvaddr; /* Last user fault */
	135	unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
	136	unsigned long error_code;
	137	unsigned long trap_no;
1da177e4 LT	138	unsigned long irix_trampoline; /* Wheee... */
1da177e4 LT	139	unsigned long irix_oldctx;
e50c0a8f	140	struct mips_abi *abi;
1da177e4 LT	141	};
1da177e4 LT	142
f088fc84	143	#ifdef CONFIG_MIPS_MT_FPAFF
fee578fa RB	144	#define FPAFF_INIT \
	145	.emulated_fp = 0, \
	146	.user_cpus_allowed = INIT_CPUMASK,
f088fc84 RB	147	#else
	148	#define FPAFF_INIT
	149	#endif /* CONFIG_MIPS_MT_FPAFF */
	150
fee578fa RB	151	#define INIT_THREAD { \
	152	/* \
	153	* Saved main processor registers \
	154	*/ \
	155	.reg16 = 0, \
	156	.reg17 = 0, \
	157	.reg18 = 0, \
	158	.reg19 = 0, \
	159	.reg20 = 0, \
	160	.reg21 = 0, \
	161	.reg22 = 0, \
	162	.reg23 = 0, \
	163	.reg29 = 0, \
	164	.reg30 = 0, \
	165	.reg31 = 0, \
	166	/* \
	167	* Saved cp0 stuff \
	168	*/ \
	169	.cp0_status = 0, \
	170	/* \
	171	* Saved FPU/FPU emulator stuff \
	172	*/ \
	173	.fpu = { \
	174	.fpr = {0,}, \
	175	.fcr31 = 0, \
	176	}, \
	177	/* \
	178	* FPU affinity state (null if not FPAFF) \
	179	*/ \
	180	FPAFF_INIT \
	181	/* \
	182	* Saved DSP stuff \
	183	*/ \
	184	.dsp = { \
	185	.dspr = {0, }, \
	186	.dspcontrol = 0, \
	187	}, \
	188	/* \
	189	* Other stuff associated with the process \
	190	*/ \
	191	.cp0_badvaddr = 0, \
	192	.cp0_baduaddr = 0, \
	193	.error_code = 0, \
	194	.trap_no = 0, \
fee578fa RB	195	.irix_trampoline = 0, \
fee578fa RB	196	.irix_oldctx = 0, \
1da177e4 LT	197	}
	198
	199	struct task_struct;
	200
	201	/* Free all resources held by a thread. */
	202	#define release_thread(thread) do { } while(0)
	203
	204	/* Prepare to copy thread state - unlazy all lazy status */
	205	#define prepare_to_copy(tsk) do { } while (0)
	206
	207	extern long kernel_thread(int (fn)(void ), void * arg, unsigned long flags);
	208
	209	extern unsigned long thread_saved_pc(struct task_struct *tsk);
	210
	211	/*
	212	* Do necessary setup to start up a newly executed thread.
	213	*/
	214	extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
	215
	216	unsigned long get_wchan(struct task_struct *p);
	217
75bb07e7	218	#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32)
40bc9c67 AV	219	#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1)
	220	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
	221	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
	222	#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
1da177e4 LT	223
	224	#define cpu_relax() barrier()
	225
	226	/*
	227	* Return_address is a replacement for __builtin_return_address(count)
	228	* which on certain architectures cannot reasonably be implemented in GCC
	229	* (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
	230	* Note that __builtin_return_address(x>=1) is forbidden because GCC
	231	* aborts compilation on some CPUs. It's simply not possible to unwind
	232	* some CPU's stackframes.
	233	*
	234	* __builtin_return_address works only for non-leaf functions. We avoid the
	235	* overhead of a function call by forcing the compiler to save the return
	236	* address register on the stack.
	237	*/
	238	#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
	239
	240	#ifdef CONFIG_CPU_HAS_PREFETCH
	241
	242	#define ARCH_HAS_PREFETCH
	243
9797cae3	244	static inline void prefetch(const void *addr)
1da177e4 LT	245	{
	246	__asm__ __volatile__(
	247	" .set mips4 \n"
	248	" pref %0, (%1) \n"
	249	" .set mips0 \n"
	250	:
	251	: "i" (Pref_Load), "r" (addr));
	252	}
	253
	254	#endif
	255
	256	#endif /* _ASM_PROCESSOR_H */