[net-next-2.6.git] / include / asm-arm / arch-at91 / debug-macro.S

/*
 * include/asm-arm/arch-at91/debug-macro.S
 *
 *  Copyright (C) 2003-2005 SAN People
 *
 * Debugging macro include header
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <asm/arch/hardware.h>
#include <asm/arch/at91_dbgu.h>

	.macro	addruart,rx
	mrc	p15, 0, \rx, c1, c0
	tst	\rx, #1						@ MMU enabled?
	ldreq	\rx, =(AT91_BASE_SYS + AT91_DBGU)		@ System peripherals (phys address)
	ldrne	\rx, =(AT91_VA_BASE_SYS	+ AT91_DBGU)		@ System peripherals (virt address)
	.endm

	.macro	senduart,rd,rx
	strb	\rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)]	@ Write to Transmitter Holding Register
	.endm

	.macro	waituart,rd,rx
1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)]		@ Read Status Register
	tst	\rd, #AT91_DBGU_TXRDY				@ DBGU_TXRDY = 1 when ready to transmit
	beq	1001b
	.endm

	.macro	busyuart,rd,rx
1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)]		@ Read Status Register
	tst	\rd, #AT91_DBGU_TXEMPTY				@ DBGU_TXEMPTY = 1 when transmission complete
	beq	1001b
	.endm
Commit	Line	Data
73a59c1c	1	/*
9d041268	2	* include/asm-arm/arch-at91/debug-macro.S
73a59c1c SP	3	*
	4	* Copyright (C) 2003-2005 SAN People
	5	*
	6	* Debugging macro include header
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	*/
	13
be509729	14	#include <asm/arch/hardware.h>
55d8baee	15	#include <asm/arch/at91_dbgu.h>
73a59c1c SP	16
	17	.macro addruart,rx
	18	mrc p15, 0, \rx, c1, c0
d0760b3b AV	19	tst \rx, #1 @ MMU enabled?
	20	ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
	21	ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
73a59c1c SP	22	.endm
	23
	24	.macro senduart,rd,rx
d0760b3b	25	strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register
73a59c1c SP	26	.endm
	27
	28	.macro waituart,rd,rx
d0760b3b AV	29	1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
d0760b3b AV	30	tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
73a59c1c SP	31	beq 1001b
	32	.endm
	33
	34	.macro busyuart,rd,rx
d0760b3b AV	35	1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
d0760b3b AV	36	tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
73a59c1c SP	37	beq 1001b
	38	.endm
	39