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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
19 | * 4. Hardware interrupts. Not supported at present. | |
20 | * | |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
e46cdb66 | 31 | |
38e20b07 | 32 | #include <asm/desc.h> |
e46cdb66 JF |
33 | #include <asm/ptrace.h> |
34 | #include <asm/irq.h> | |
792dc4f6 | 35 | #include <asm/idle.h> |
e46cdb66 JF |
36 | #include <asm/sync_bitops.h> |
37 | #include <asm/xen/hypercall.h> | |
8d1b8753 | 38 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 39 | |
38e20b07 SY |
40 | #include <xen/xen.h> |
41 | #include <xen/hvm.h> | |
e04d0d07 | 42 | #include <xen/xen-ops.h> |
e46cdb66 JF |
43 | #include <xen/events.h> |
44 | #include <xen/interface/xen.h> | |
45 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
46 | #include <xen/interface/hvm/hvm_op.h> |
47 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 48 | |
e46cdb66 JF |
49 | /* |
50 | * This lock protects updates to the following mapping and reference-count | |
51 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
52 | */ | |
53 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
54 | ||
55 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 56 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 57 | |
f87e4cac | 58 | /* IRQ <-> IPI mapping */ |
204fba4a | 59 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 60 | |
ced40d0f JF |
61 | /* Interrupt types. */ |
62 | enum xen_irq_type { | |
d77bbd4d | 63 | IRQT_UNBOUND = 0, |
f87e4cac JF |
64 | IRQT_PIRQ, |
65 | IRQT_VIRQ, | |
66 | IRQT_IPI, | |
67 | IRQT_EVTCHN | |
68 | }; | |
e46cdb66 | 69 | |
ced40d0f JF |
70 | /* |
71 | * Packed IRQ information: | |
72 | * type - enum xen_irq_type | |
73 | * event channel - irq->event channel mapping | |
74 | * cpu - cpu this event channel is bound to | |
75 | * index - type-specific information: | |
76 | * PIRQ - vector, with MSB being "needs EIO" | |
77 | * VIRQ - virq number | |
78 | * IPI - IPI vector | |
79 | * EVTCHN - | |
80 | */ | |
81 | struct irq_info | |
82 | { | |
83 | enum xen_irq_type type; /* type */ | |
84 | unsigned short evtchn; /* event channel */ | |
85 | unsigned short cpu; /* cpu bound */ | |
86 | ||
87 | union { | |
88 | unsigned short virq; | |
89 | enum ipi_vector ipi; | |
90 | struct { | |
91 | unsigned short gsi; | |
92 | unsigned short vector; | |
93 | } pirq; | |
94 | } u; | |
95 | }; | |
96 | ||
97 | static struct irq_info irq_info[NR_IRQS]; | |
e46cdb66 JF |
98 | |
99 | static int evtchn_to_irq[NR_EVENT_CHANNELS] = { | |
100 | [0 ... NR_EVENT_CHANNELS-1] = -1 | |
101 | }; | |
c7a3589e MT |
102 | struct cpu_evtchn_s { |
103 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
104 | }; | |
105 | static struct cpu_evtchn_s *cpu_evtchn_mask_p; | |
106 | static inline unsigned long *cpu_evtchn_mask(int cpu) | |
107 | { | |
108 | return cpu_evtchn_mask_p[cpu].bits; | |
109 | } | |
e46cdb66 | 110 | |
e46cdb66 JF |
111 | /* Xen will never allocate port zero for any purpose. */ |
112 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
113 | ||
e46cdb66 JF |
114 | static struct irq_chip xen_dynamic_chip; |
115 | ||
116 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
117 | static struct irq_info mk_unbound_info(void) |
118 | { | |
119 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
120 | } | |
121 | ||
122 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
123 | { | |
90af9514 IC |
124 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn, |
125 | .cpu = 0 }; | |
ced40d0f JF |
126 | } |
127 | ||
128 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 129 | { |
ced40d0f | 130 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
90af9514 | 131 | .cpu = 0, .u.ipi = ipi }; |
ced40d0f JF |
132 | } |
133 | ||
134 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
135 | { | |
136 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
90af9514 | 137 | .cpu = 0, .u.virq = virq }; |
ced40d0f JF |
138 | } |
139 | ||
140 | static struct irq_info mk_pirq_info(unsigned short evtchn, | |
141 | unsigned short gsi, unsigned short vector) | |
142 | { | |
143 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
90af9514 | 144 | .cpu = 0, .u.pirq = { .gsi = gsi, .vector = vector } }; |
e46cdb66 JF |
145 | } |
146 | ||
147 | /* | |
148 | * Accessors for packed IRQ information. | |
149 | */ | |
ced40d0f | 150 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 151 | { |
ced40d0f | 152 | return &irq_info[irq]; |
e46cdb66 JF |
153 | } |
154 | ||
ced40d0f | 155 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 156 | { |
ced40d0f | 157 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
158 | } |
159 | ||
d4c04536 IC |
160 | unsigned irq_from_evtchn(unsigned int evtchn) |
161 | { | |
162 | return evtchn_to_irq[evtchn]; | |
163 | } | |
164 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
165 | ||
ced40d0f | 166 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 167 | { |
ced40d0f JF |
168 | struct irq_info *info = info_for_irq(irq); |
169 | ||
170 | BUG_ON(info == NULL); | |
171 | BUG_ON(info->type != IRQT_IPI); | |
172 | ||
173 | return info->u.ipi; | |
174 | } | |
175 | ||
176 | static unsigned virq_from_irq(unsigned irq) | |
177 | { | |
178 | struct irq_info *info = info_for_irq(irq); | |
179 | ||
180 | BUG_ON(info == NULL); | |
181 | BUG_ON(info->type != IRQT_VIRQ); | |
182 | ||
183 | return info->u.virq; | |
184 | } | |
185 | ||
186 | static unsigned gsi_from_irq(unsigned irq) | |
187 | { | |
188 | struct irq_info *info = info_for_irq(irq); | |
189 | ||
190 | BUG_ON(info == NULL); | |
191 | BUG_ON(info->type != IRQT_PIRQ); | |
192 | ||
193 | return info->u.pirq.gsi; | |
194 | } | |
195 | ||
196 | static unsigned vector_from_irq(unsigned irq) | |
197 | { | |
198 | struct irq_info *info = info_for_irq(irq); | |
199 | ||
200 | BUG_ON(info == NULL); | |
201 | BUG_ON(info->type != IRQT_PIRQ); | |
202 | ||
203 | return info->u.pirq.vector; | |
204 | } | |
205 | ||
206 | static enum xen_irq_type type_from_irq(unsigned irq) | |
207 | { | |
208 | return info_for_irq(irq)->type; | |
209 | } | |
210 | ||
211 | static unsigned cpu_from_irq(unsigned irq) | |
212 | { | |
213 | return info_for_irq(irq)->cpu; | |
214 | } | |
215 | ||
216 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
217 | { | |
218 | int irq = evtchn_to_irq[evtchn]; | |
219 | unsigned ret = 0; | |
220 | ||
221 | if (irq != -1) | |
222 | ret = cpu_from_irq(irq); | |
223 | ||
224 | return ret; | |
e46cdb66 JF |
225 | } |
226 | ||
227 | static inline unsigned long active_evtchns(unsigned int cpu, | |
228 | struct shared_info *sh, | |
229 | unsigned int idx) | |
230 | { | |
231 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 232 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
233 | ~sh->evtchn_mask[idx]); |
234 | } | |
235 | ||
236 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
237 | { | |
238 | int irq = evtchn_to_irq[chn]; | |
239 | ||
240 | BUG_ON(irq == -1); | |
241 | #ifdef CONFIG_SMP | |
7f7ace0c | 242 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
243 | #endif |
244 | ||
ced40d0f | 245 | __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
c7a3589e | 246 | __set_bit(chn, cpu_evtchn_mask(cpu)); |
e46cdb66 | 247 | |
ced40d0f | 248 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
249 | } |
250 | ||
251 | static void init_evtchn_cpu_bindings(void) | |
252 | { | |
253 | #ifdef CONFIG_SMP | |
10e58084 | 254 | struct irq_desc *desc; |
e46cdb66 | 255 | int i; |
10e58084 | 256 | |
e46cdb66 | 257 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 258 | for_each_irq_desc(i, desc) { |
7f7ace0c | 259 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 260 | } |
e46cdb66 JF |
261 | #endif |
262 | ||
c7a3589e | 263 | memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0))); |
e46cdb66 JF |
264 | } |
265 | ||
e46cdb66 JF |
266 | static inline void clear_evtchn(int port) |
267 | { | |
268 | struct shared_info *s = HYPERVISOR_shared_info; | |
269 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
270 | } | |
271 | ||
272 | static inline void set_evtchn(int port) | |
273 | { | |
274 | struct shared_info *s = HYPERVISOR_shared_info; | |
275 | sync_set_bit(port, &s->evtchn_pending[0]); | |
276 | } | |
277 | ||
168d2f46 JF |
278 | static inline int test_evtchn(int port) |
279 | { | |
280 | struct shared_info *s = HYPERVISOR_shared_info; | |
281 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
282 | } | |
283 | ||
e46cdb66 JF |
284 | |
285 | /** | |
286 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
287 | * @irq: irq of event channel to send event to | |
288 | * | |
289 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
290 | * save/restore. Notifications on a broken connection are silently | |
291 | * dropped. | |
292 | */ | |
293 | void notify_remote_via_irq(int irq) | |
294 | { | |
295 | int evtchn = evtchn_from_irq(irq); | |
296 | ||
297 | if (VALID_EVTCHN(evtchn)) | |
298 | notify_remote_via_evtchn(evtchn); | |
299 | } | |
300 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
301 | ||
302 | static void mask_evtchn(int port) | |
303 | { | |
304 | struct shared_info *s = HYPERVISOR_shared_info; | |
305 | sync_set_bit(port, &s->evtchn_mask[0]); | |
306 | } | |
307 | ||
308 | static void unmask_evtchn(int port) | |
309 | { | |
310 | struct shared_info *s = HYPERVISOR_shared_info; | |
311 | unsigned int cpu = get_cpu(); | |
312 | ||
313 | BUG_ON(!irqs_disabled()); | |
314 | ||
315 | /* Slow path (hypercall) if this is a non-local port. */ | |
316 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
317 | struct evtchn_unmask unmask = { .port = port }; | |
318 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
319 | } else { | |
320 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
321 | ||
322 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
323 | ||
324 | /* | |
325 | * The following is basically the equivalent of | |
326 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
327 | * the interrupt edge' if the channel is masked. | |
328 | */ | |
329 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
330 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
331 | &vcpu_info->evtchn_pending_sel)) | |
332 | vcpu_info->evtchn_upcall_pending = 1; | |
333 | } | |
334 | ||
335 | put_cpu(); | |
336 | } | |
337 | ||
338 | static int find_unbound_irq(void) | |
339 | { | |
340 | int irq; | |
6f8a0ed4 | 341 | struct irq_desc *desc; |
e46cdb66 | 342 | |
99ad198c SS |
343 | for (irq = 0; irq < nr_irqs; irq++) { |
344 | desc = irq_to_desc(irq); | |
345 | /* only 0->15 have init'd desc; handle irq > 16 */ | |
346 | if (desc == NULL) | |
347 | break; | |
348 | if (desc->chip == &no_irq_chip) | |
349 | break; | |
350 | if (desc->chip != &xen_dynamic_chip) | |
351 | continue; | |
d77bbd4d | 352 | if (irq_info[irq].type == IRQT_UNBOUND) |
e46cdb66 | 353 | break; |
99ad198c | 354 | } |
e46cdb66 | 355 | |
5a15d7e8 YL |
356 | if (irq == nr_irqs) |
357 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 | 358 | |
85ac16d0 | 359 | desc = irq_to_desc_alloc_node(irq, 0); |
6f8a0ed4 JF |
360 | if (WARN_ON(desc == NULL)) |
361 | return -1; | |
362 | ||
99ad198c | 363 | dynamic_irq_init_keep_chip_data(irq); |
ced40d0f | 364 | |
e46cdb66 JF |
365 | return irq; |
366 | } | |
367 | ||
b536b4b9 | 368 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
369 | { |
370 | int irq; | |
371 | ||
372 | spin_lock(&irq_mapping_update_lock); | |
373 | ||
374 | irq = evtchn_to_irq[evtchn]; | |
375 | ||
376 | if (irq == -1) { | |
377 | irq = find_unbound_irq(); | |
378 | ||
e46cdb66 JF |
379 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
380 | handle_level_irq, "event"); | |
381 | ||
382 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 383 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
384 | } |
385 | ||
e46cdb66 JF |
386 | spin_unlock(&irq_mapping_update_lock); |
387 | ||
388 | return irq; | |
389 | } | |
b536b4b9 | 390 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 391 | |
f87e4cac JF |
392 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
393 | { | |
394 | struct evtchn_bind_ipi bind_ipi; | |
395 | int evtchn, irq; | |
396 | ||
397 | spin_lock(&irq_mapping_update_lock); | |
398 | ||
399 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 400 | |
f87e4cac JF |
401 | if (irq == -1) { |
402 | irq = find_unbound_irq(); | |
403 | if (irq < 0) | |
404 | goto out; | |
405 | ||
f87e4cac JF |
406 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
407 | handle_level_irq, "ipi"); | |
408 | ||
409 | bind_ipi.vcpu = cpu; | |
410 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
411 | &bind_ipi) != 0) | |
412 | BUG(); | |
413 | evtchn = bind_ipi.port; | |
414 | ||
415 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 416 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
417 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
418 | ||
419 | bind_evtchn_to_cpu(evtchn, cpu); | |
420 | } | |
421 | ||
f87e4cac JF |
422 | out: |
423 | spin_unlock(&irq_mapping_update_lock); | |
424 | return irq; | |
425 | } | |
426 | ||
427 | ||
e46cdb66 JF |
428 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
429 | { | |
430 | struct evtchn_bind_virq bind_virq; | |
431 | int evtchn, irq; | |
432 | ||
433 | spin_lock(&irq_mapping_update_lock); | |
434 | ||
435 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
436 | ||
437 | if (irq == -1) { | |
438 | bind_virq.virq = virq; | |
439 | bind_virq.vcpu = cpu; | |
440 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
441 | &bind_virq) != 0) | |
442 | BUG(); | |
443 | evtchn = bind_virq.port; | |
444 | ||
445 | irq = find_unbound_irq(); | |
446 | ||
e46cdb66 JF |
447 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
448 | handle_level_irq, "virq"); | |
449 | ||
450 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 451 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
452 | |
453 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
454 | ||
455 | bind_evtchn_to_cpu(evtchn, cpu); | |
456 | } | |
457 | ||
e46cdb66 JF |
458 | spin_unlock(&irq_mapping_update_lock); |
459 | ||
460 | return irq; | |
461 | } | |
462 | ||
463 | static void unbind_from_irq(unsigned int irq) | |
464 | { | |
465 | struct evtchn_close close; | |
466 | int evtchn = evtchn_from_irq(irq); | |
467 | ||
468 | spin_lock(&irq_mapping_update_lock); | |
469 | ||
d77bbd4d | 470 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
471 | close.port = evtchn; |
472 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
473 | BUG(); | |
474 | ||
475 | switch (type_from_irq(irq)) { | |
476 | case IRQT_VIRQ: | |
477 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 478 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 479 | break; |
d68d82af AN |
480 | case IRQT_IPI: |
481 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 482 | [ipi_from_irq(irq)] = -1; |
d68d82af | 483 | break; |
e46cdb66 JF |
484 | default: |
485 | break; | |
486 | } | |
487 | ||
488 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
489 | bind_evtchn_to_cpu(evtchn, 0); | |
490 | ||
491 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
492 | } |
493 | ||
494 | if (irq_info[irq].type != IRQT_UNBOUND) { | |
ced40d0f | 495 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 496 | |
0f2287ad | 497 | dynamic_irq_cleanup(irq); |
e46cdb66 JF |
498 | } |
499 | ||
500 | spin_unlock(&irq_mapping_update_lock); | |
501 | } | |
502 | ||
503 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 504 | irq_handler_t handler, |
e46cdb66 JF |
505 | unsigned long irqflags, |
506 | const char *devname, void *dev_id) | |
507 | { | |
508 | unsigned int irq; | |
509 | int retval; | |
510 | ||
511 | irq = bind_evtchn_to_irq(evtchn); | |
512 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
513 | if (retval != 0) { | |
514 | unbind_from_irq(irq); | |
515 | return retval; | |
516 | } | |
517 | ||
518 | return irq; | |
519 | } | |
520 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
521 | ||
522 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 523 | irq_handler_t handler, |
e46cdb66 JF |
524 | unsigned long irqflags, const char *devname, void *dev_id) |
525 | { | |
526 | unsigned int irq; | |
527 | int retval; | |
528 | ||
529 | irq = bind_virq_to_irq(virq, cpu); | |
530 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
531 | if (retval != 0) { | |
532 | unbind_from_irq(irq); | |
533 | return retval; | |
534 | } | |
535 | ||
536 | return irq; | |
537 | } | |
538 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
539 | ||
f87e4cac JF |
540 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
541 | unsigned int cpu, | |
542 | irq_handler_t handler, | |
543 | unsigned long irqflags, | |
544 | const char *devname, | |
545 | void *dev_id) | |
546 | { | |
547 | int irq, retval; | |
548 | ||
549 | irq = bind_ipi_to_irq(ipi, cpu); | |
550 | if (irq < 0) | |
551 | return irq; | |
552 | ||
553 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
554 | if (retval != 0) { | |
555 | unbind_from_irq(irq); | |
556 | return retval; | |
557 | } | |
558 | ||
559 | return irq; | |
560 | } | |
561 | ||
e46cdb66 JF |
562 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
563 | { | |
564 | free_irq(irq, dev_id); | |
565 | unbind_from_irq(irq); | |
566 | } | |
567 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
568 | ||
f87e4cac JF |
569 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
570 | { | |
571 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
572 | BUG_ON(irq < 0); | |
573 | notify_remote_via_irq(irq); | |
574 | } | |
575 | ||
ee523ca1 JF |
576 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
577 | { | |
578 | struct shared_info *sh = HYPERVISOR_shared_info; | |
579 | int cpu = smp_processor_id(); | |
580 | int i; | |
581 | unsigned long flags; | |
582 | static DEFINE_SPINLOCK(debug_lock); | |
583 | ||
584 | spin_lock_irqsave(&debug_lock, flags); | |
585 | ||
586 | printk("vcpu %d\n ", cpu); | |
587 | ||
588 | for_each_online_cpu(i) { | |
589 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
590 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 591 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
592 | v->evtchn_upcall_pending, |
593 | v->evtchn_pending_sel); | |
594 | } | |
595 | printk("pending:\n "); | |
596 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
597 | printk("%08lx%s", sh->evtchn_pending[i], | |
598 | i % 8 == 0 ? "\n " : " "); | |
599 | printk("\nmasks:\n "); | |
600 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
601 | printk("%08lx%s", sh->evtchn_mask[i], | |
602 | i % 8 == 0 ? "\n " : " "); | |
603 | ||
604 | printk("\nunmasked:\n "); | |
605 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
606 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
607 | i % 8 == 0 ? "\n " : " "); | |
608 | ||
609 | printk("\npending list:\n"); | |
610 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
611 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
612 | printk(" %d: event %d -> irq %d\n", | |
ced40d0f JF |
613 | cpu_from_evtchn(i), i, |
614 | evtchn_to_irq[i]); | |
ee523ca1 JF |
615 | } |
616 | } | |
617 | ||
618 | spin_unlock_irqrestore(&debug_lock, flags); | |
619 | ||
620 | return IRQ_HANDLED; | |
621 | } | |
622 | ||
245b2e70 TH |
623 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
624 | ||
e46cdb66 JF |
625 | /* |
626 | * Search the CPUs pending events bitmasks. For each one found, map | |
627 | * the event number to an irq, and feed it into do_IRQ() for | |
628 | * handling. | |
629 | * | |
630 | * Xen uses a two-level bitmap to speed searching. The first level is | |
631 | * a bitset of words which contain pending event bits. The second | |
632 | * level is a bitset of pending events themselves. | |
633 | */ | |
38e20b07 | 634 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
635 | { |
636 | int cpu = get_cpu(); | |
637 | struct shared_info *s = HYPERVISOR_shared_info; | |
638 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be | 639 | unsigned count; |
e46cdb66 | 640 | |
229664be JF |
641 | do { |
642 | unsigned long pending_words; | |
e46cdb66 | 643 | |
229664be | 644 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 645 | |
245b2e70 | 646 | if (__get_cpu_var(xed_nesting_count)++) |
229664be | 647 | goto out; |
e46cdb66 | 648 | |
e849c3e9 IY |
649 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
650 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 651 | wmb(); |
e849c3e9 | 652 | #endif |
229664be JF |
653 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
654 | while (pending_words != 0) { | |
655 | unsigned long pending_bits; | |
656 | int word_idx = __ffs(pending_words); | |
657 | pending_words &= ~(1UL << word_idx); | |
658 | ||
659 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
660 | int bit_idx = __ffs(pending_bits); | |
661 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
662 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 663 | struct irq_desc *desc; |
229664be | 664 | |
ca4dbc66 EB |
665 | if (irq != -1) { |
666 | desc = irq_to_desc(irq); | |
667 | if (desc) | |
668 | generic_handle_irq_desc(irq, desc); | |
669 | } | |
e46cdb66 JF |
670 | } |
671 | } | |
e46cdb66 | 672 | |
229664be JF |
673 | BUG_ON(!irqs_disabled()); |
674 | ||
245b2e70 TH |
675 | count = __get_cpu_var(xed_nesting_count); |
676 | __get_cpu_var(xed_nesting_count) = 0; | |
183d03cc | 677 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
678 | |
679 | out: | |
38e20b07 SY |
680 | |
681 | put_cpu(); | |
682 | } | |
683 | ||
684 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
685 | { | |
686 | struct pt_regs *old_regs = set_irq_regs(regs); | |
687 | ||
688 | exit_idle(); | |
689 | irq_enter(); | |
690 | ||
691 | __xen_evtchn_do_upcall(); | |
692 | ||
3445a8fd JF |
693 | irq_exit(); |
694 | set_irq_regs(old_regs); | |
38e20b07 | 695 | } |
3445a8fd | 696 | |
38e20b07 SY |
697 | void xen_hvm_evtchn_do_upcall(void) |
698 | { | |
699 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 700 | } |
183d03cc | 701 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 702 | |
eb1e305f JF |
703 | /* Rebind a new event channel to an existing irq. */ |
704 | void rebind_evtchn_irq(int evtchn, int irq) | |
705 | { | |
d77bbd4d JF |
706 | struct irq_info *info = info_for_irq(irq); |
707 | ||
eb1e305f JF |
708 | /* Make sure the irq is masked, since the new event channel |
709 | will also be masked. */ | |
710 | disable_irq(irq); | |
711 | ||
712 | spin_lock(&irq_mapping_update_lock); | |
713 | ||
714 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
715 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
716 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
717 | so there should be a proper type */ |
718 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
719 | |
720 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 721 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
722 | |
723 | spin_unlock(&irq_mapping_update_lock); | |
724 | ||
725 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 726 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
727 | |
728 | /* Unmask the event channel. */ | |
729 | enable_irq(irq); | |
730 | } | |
731 | ||
e46cdb66 | 732 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 733 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
734 | { |
735 | struct evtchn_bind_vcpu bind_vcpu; | |
736 | int evtchn = evtchn_from_irq(irq); | |
737 | ||
183d03cc SS |
738 | /* events delivered via platform PCI interrupts are always |
739 | * routed to vcpu 0 */ | |
740 | if (!VALID_EVTCHN(evtchn) || | |
741 | (xen_hvm_domain() && !xen_have_vector_callback)) | |
d5dedd45 | 742 | return -1; |
e46cdb66 JF |
743 | |
744 | /* Send future instances of this interrupt to other vcpu. */ | |
745 | bind_vcpu.port = evtchn; | |
746 | bind_vcpu.vcpu = tcpu; | |
747 | ||
748 | /* | |
749 | * If this fails, it usually just indicates that we're dealing with a | |
750 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
751 | * it, but don't do the xenlinux-level rebind in that case. | |
752 | */ | |
753 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
754 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 755 | |
d5dedd45 YL |
756 | return 0; |
757 | } | |
e46cdb66 | 758 | |
d5dedd45 | 759 | static int set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 760 | { |
0de26520 | 761 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 YL |
762 | |
763 | return rebind_irq_to_cpu(irq, tcpu); | |
e46cdb66 JF |
764 | } |
765 | ||
642e0c88 IY |
766 | int resend_irq_on_evtchn(unsigned int irq) |
767 | { | |
768 | int masked, evtchn = evtchn_from_irq(irq); | |
769 | struct shared_info *s = HYPERVISOR_shared_info; | |
770 | ||
771 | if (!VALID_EVTCHN(evtchn)) | |
772 | return 1; | |
773 | ||
774 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
775 | sync_set_bit(evtchn, s->evtchn_pending); | |
776 | if (!masked) | |
777 | unmask_evtchn(evtchn); | |
778 | ||
779 | return 1; | |
780 | } | |
781 | ||
e46cdb66 JF |
782 | static void enable_dynirq(unsigned int irq) |
783 | { | |
784 | int evtchn = evtchn_from_irq(irq); | |
785 | ||
786 | if (VALID_EVTCHN(evtchn)) | |
787 | unmask_evtchn(evtchn); | |
788 | } | |
789 | ||
790 | static void disable_dynirq(unsigned int irq) | |
791 | { | |
792 | int evtchn = evtchn_from_irq(irq); | |
793 | ||
794 | if (VALID_EVTCHN(evtchn)) | |
795 | mask_evtchn(evtchn); | |
796 | } | |
797 | ||
798 | static void ack_dynirq(unsigned int irq) | |
799 | { | |
800 | int evtchn = evtchn_from_irq(irq); | |
801 | ||
802 | move_native_irq(irq); | |
803 | ||
804 | if (VALID_EVTCHN(evtchn)) | |
805 | clear_evtchn(evtchn); | |
806 | } | |
807 | ||
808 | static int retrigger_dynirq(unsigned int irq) | |
809 | { | |
810 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 811 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
812 | int ret = 0; |
813 | ||
814 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
815 | int masked; |
816 | ||
817 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
818 | sync_set_bit(evtchn, sh->evtchn_pending); | |
819 | if (!masked) | |
820 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
821 | ret = 1; |
822 | } | |
823 | ||
824 | return ret; | |
825 | } | |
826 | ||
0e91398f JF |
827 | static void restore_cpu_virqs(unsigned int cpu) |
828 | { | |
829 | struct evtchn_bind_virq bind_virq; | |
830 | int virq, irq, evtchn; | |
831 | ||
832 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
833 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
834 | continue; | |
835 | ||
ced40d0f | 836 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
837 | |
838 | /* Get a new binding from Xen. */ | |
839 | bind_virq.virq = virq; | |
840 | bind_virq.vcpu = cpu; | |
841 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
842 | &bind_virq) != 0) | |
843 | BUG(); | |
844 | evtchn = bind_virq.port; | |
845 | ||
846 | /* Record the new mapping. */ | |
847 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 848 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f JF |
849 | bind_evtchn_to_cpu(evtchn, cpu); |
850 | ||
851 | /* Ready for use. */ | |
852 | unmask_evtchn(evtchn); | |
853 | } | |
854 | } | |
855 | ||
856 | static void restore_cpu_ipis(unsigned int cpu) | |
857 | { | |
858 | struct evtchn_bind_ipi bind_ipi; | |
859 | int ipi, irq, evtchn; | |
860 | ||
861 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
862 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
863 | continue; | |
864 | ||
ced40d0f | 865 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
866 | |
867 | /* Get a new binding from Xen. */ | |
868 | bind_ipi.vcpu = cpu; | |
869 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
870 | &bind_ipi) != 0) | |
871 | BUG(); | |
872 | evtchn = bind_ipi.port; | |
873 | ||
874 | /* Record the new mapping. */ | |
875 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 876 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f JF |
877 | bind_evtchn_to_cpu(evtchn, cpu); |
878 | ||
879 | /* Ready for use. */ | |
880 | unmask_evtchn(evtchn); | |
881 | ||
882 | } | |
883 | } | |
884 | ||
2d9e1e2f JF |
885 | /* Clear an irq's pending state, in preparation for polling on it */ |
886 | void xen_clear_irq_pending(int irq) | |
887 | { | |
888 | int evtchn = evtchn_from_irq(irq); | |
889 | ||
890 | if (VALID_EVTCHN(evtchn)) | |
891 | clear_evtchn(evtchn); | |
892 | } | |
893 | ||
168d2f46 JF |
894 | void xen_set_irq_pending(int irq) |
895 | { | |
896 | int evtchn = evtchn_from_irq(irq); | |
897 | ||
898 | if (VALID_EVTCHN(evtchn)) | |
899 | set_evtchn(evtchn); | |
900 | } | |
901 | ||
902 | bool xen_test_irq_pending(int irq) | |
903 | { | |
904 | int evtchn = evtchn_from_irq(irq); | |
905 | bool ret = false; | |
906 | ||
907 | if (VALID_EVTCHN(evtchn)) | |
908 | ret = test_evtchn(evtchn); | |
909 | ||
910 | return ret; | |
911 | } | |
912 | ||
2d9e1e2f JF |
913 | /* Poll waiting for an irq to become pending. In the usual case, the |
914 | irq will be disabled so it won't deliver an interrupt. */ | |
915 | void xen_poll_irq(int irq) | |
916 | { | |
917 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
918 | ||
919 | if (VALID_EVTCHN(evtchn)) { | |
920 | struct sched_poll poll; | |
921 | ||
922 | poll.nr_ports = 1; | |
923 | poll.timeout = 0; | |
ff3c5362 | 924 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
925 | |
926 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
927 | BUG(); | |
928 | } | |
929 | } | |
930 | ||
0e91398f JF |
931 | void xen_irq_resume(void) |
932 | { | |
933 | unsigned int cpu, irq, evtchn; | |
934 | ||
935 | init_evtchn_cpu_bindings(); | |
936 | ||
937 | /* New event-channel space is not 'live' yet. */ | |
938 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
939 | mask_evtchn(evtchn); | |
940 | ||
941 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 942 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
943 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
944 | ||
945 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
946 | evtchn_to_irq[evtchn] = -1; | |
947 | ||
948 | for_each_possible_cpu(cpu) { | |
949 | restore_cpu_virqs(cpu); | |
950 | restore_cpu_ipis(cpu); | |
951 | } | |
952 | } | |
953 | ||
e46cdb66 JF |
954 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
955 | .name = "xen-dyn", | |
54a353a0 JF |
956 | |
957 | .disable = disable_dynirq, | |
e46cdb66 JF |
958 | .mask = disable_dynirq, |
959 | .unmask = enable_dynirq, | |
54a353a0 | 960 | |
e46cdb66 JF |
961 | .ack = ack_dynirq, |
962 | .set_affinity = set_affinity_irq, | |
963 | .retrigger = retrigger_dynirq, | |
964 | }; | |
965 | ||
38e20b07 SY |
966 | int xen_set_callback_via(uint64_t via) |
967 | { | |
968 | struct xen_hvm_param a; | |
969 | a.domid = DOMID_SELF; | |
970 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
971 | a.value = via; | |
972 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
973 | } | |
974 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
975 | ||
976 | /* Vector callbacks are better than PCI interrupts to receive event | |
977 | * channel notifications because we can receive vector callbacks on any | |
978 | * vcpu and we don't need PCI support or APIC interactions. */ | |
979 | void xen_callback_vector(void) | |
980 | { | |
981 | int rc; | |
982 | uint64_t callback_via; | |
983 | if (xen_have_vector_callback) { | |
984 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
985 | rc = xen_set_callback_via(callback_via); | |
986 | if (rc) { | |
987 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
988 | " failed.\n"); | |
989 | xen_have_vector_callback = 0; | |
990 | return; | |
991 | } | |
992 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
993 | "enabled\n"); | |
994 | /* in the restore case the vector has already been allocated */ | |
995 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
996 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
997 | } | |
998 | } | |
999 | ||
e46cdb66 JF |
1000 | void __init xen_init_IRQ(void) |
1001 | { | |
1002 | int i; | |
c7a3589e | 1003 | |
a70c352a PE |
1004 | cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s), |
1005 | GFP_KERNEL); | |
28e08861 | 1006 | BUG_ON(cpu_evtchn_mask_p == NULL); |
e46cdb66 JF |
1007 | |
1008 | init_evtchn_cpu_bindings(); | |
1009 | ||
1010 | /* No event channels are 'live' right now. */ | |
1011 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1012 | mask_evtchn(i); | |
1013 | ||
38e20b07 SY |
1014 | if (xen_hvm_domain()) { |
1015 | xen_callback_vector(); | |
1016 | native_init_IRQ(); | |
1017 | } else { | |
1018 | irq_ctx_init(smp_processor_id()); | |
1019 | } | |
e46cdb66 | 1020 | } |