[net-next-2.6.git] / drivers / watchdog / omap_wdt.c

/*
 * omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <gdavis@mvista.com> or <source@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * History:
 *
 * 20030527: George G. Davis <gdavis@mvista.com>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
 *	Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/clk.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include <mach/hardware.h>
#include <plat/prcm.h>

#include "omap_wdt.h"

static struct platform_device *omap_wdt_dev;

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

static unsigned int wdt_trgr_pattern = 0x1234;
static spinlock_t wdt_lock;

struct omap_wdt_dev {
	void __iomem    *base;          /* physical */
	struct device   *dev;
	int             omap_wdt_users;
	struct clk      *ick;
	struct clk      *fck;
	struct resource *mem;
	struct miscdevice omap_wdt_miscdev;
};

static void omap_wdt_ping(struct omap_wdt_dev *wdev)
{
	void __iomem    *base = wdev->base;

	/* wait for posted write to complete */
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();

	wdt_trgr_pattern = ~wdt_trgr_pattern;
	__raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));

	/* wait for posted write to complete */
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* Sequence to enable the watchdog */
	__raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();

	__raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* sequence required to disable watchdog */
	__raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();

	__raw_writel(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_adjust_timeout(unsigned new_timeout)
{
	if (new_timeout < TIMER_MARGIN_MIN)
		new_timeout = TIMER_MARGIN_DEFAULT;
	if (new_timeout > TIMER_MARGIN_MAX)
		new_timeout = TIMER_MARGIN_MAX;
	timer_margin = new_timeout;
}

static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
{
	u32 pre_margin = GET_WLDR_VAL(timer_margin);
	void __iomem *base = wdev->base;

	/* just count up at 32 KHz */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();

	__raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

/*
 *	Allow only one task to hold it open
 */
static int omap_wdt_open(struct inode *inode, struct file *file)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
	void __iomem *base = wdev->base;

	if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
		return -EBUSY;

	clk_enable(wdev->ick);    /* Enable the interface clock */
	clk_enable(wdev->fck);    /* Enable the functional clock */

	/* initialize prescaler */
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	__raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	file->private_data = (void *) wdev;

	omap_wdt_set_timeout(wdev);
	omap_wdt_ping(wdev); /* trigger loading of new timeout value */
	omap_wdt_enable(wdev);

	return nonseekable_open(inode, file);
}

static int omap_wdt_release(struct inode *inode, struct file *file)
{
	struct omap_wdt_dev *wdev = file->private_data;

	/*
	 *      Shut off the timer unless NOWAYOUT is defined.
	 */
#ifndef CONFIG_WATCHDOG_NOWAYOUT

	omap_wdt_disable(wdev);

	clk_disable(wdev->ick);
	clk_disable(wdev->fck);
#else
	printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
#endif
	wdev->omap_wdt_users = 0;

	return 0;
}

static ssize_t omap_wdt_write(struct file *file, const char __user *data,
		size_t len, loff_t *ppos)
{
	struct omap_wdt_dev *wdev = file->private_data;

	/* Refresh LOAD_TIME. */
	if (len) {
		spin_lock(&wdt_lock);
		omap_wdt_ping(wdev);
		spin_unlock(&wdt_lock);
	}
	return len;
}

static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
						unsigned long arg)
{
	struct omap_wdt_dev *wdev;
	int new_margin;
	static const struct watchdog_info ident = {
		.identity = "OMAP Watchdog",
		.options = WDIOF_SETTIMEOUT,
		.firmware_version = 0,
	};

	wdev = file->private_data;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		return copy_to_user((struct watchdog_info __user *)arg, &ident,
				sizeof(ident));
	case WDIOC_GETSTATUS:
		return put_user(0, (int __user *)arg);
	case WDIOC_GETBOOTSTATUS:
		if (cpu_is_omap16xx())
			return put_user(__raw_readw(ARM_SYSST),
					(int __user *)arg);
		if (cpu_is_omap24xx())
			return put_user(omap_prcm_get_reset_sources(),
					(int __user *)arg);
	case WDIOC_KEEPALIVE:
		spin_lock(&wdt_lock);
		omap_wdt_ping(wdev);
		spin_unlock(&wdt_lock);
		return 0;
	case WDIOC_SETTIMEOUT:
		if (get_user(new_margin, (int __user *)arg))
			return -EFAULT;
		omap_wdt_adjust_timeout(new_margin);

		spin_lock(&wdt_lock);
		omap_wdt_disable(wdev);
		omap_wdt_set_timeout(wdev);
		omap_wdt_enable(wdev);

		omap_wdt_ping(wdev);
		spin_unlock(&wdt_lock);
		/* Fall */
	case WDIOC_GETTIMEOUT:
		return put_user(timer_margin, (int __user *)arg);
	default:
		return -ENOTTY;
	}
}

static const struct file_operations omap_wdt_fops = {
	.owner = THIS_MODULE,
	.write = omap_wdt_write,
	.unlocked_ioctl = omap_wdt_ioctl,
	.open = omap_wdt_open,
	.release = omap_wdt_release,
};

static int __devinit omap_wdt_probe(struct platform_device *pdev)
{
	struct resource *res, *mem;
	struct omap_wdt_dev *wdev;
	int ret;

	/* reserve static register mappings */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENOENT;
		goto err_get_resource;
	}

	if (omap_wdt_dev) {
		ret = -EBUSY;
		goto err_busy;
	}

	mem = request_mem_region(res->start, resource_size(res), pdev->name);
	if (!mem) {
		ret = -EBUSY;
		goto err_busy;
	}

	wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
	if (!wdev) {
		ret = -ENOMEM;
		goto err_kzalloc;
	}

	wdev->omap_wdt_users = 0;
	wdev->mem = mem;

	wdev->ick = clk_get(&pdev->dev, "ick");
	if (IS_ERR(wdev->ick)) {
		ret = PTR_ERR(wdev->ick);
		wdev->ick = NULL;
		goto err_clk;
	}
	wdev->fck = clk_get(&pdev->dev, "fck");
	if (IS_ERR(wdev->fck)) {
		ret = PTR_ERR(wdev->fck);
		wdev->fck = NULL;
		goto err_clk;
	}

	wdev->base = ioremap(res->start, resource_size(res));
	if (!wdev->base) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	platform_set_drvdata(pdev, wdev);

	clk_enable(wdev->ick);
	clk_enable(wdev->fck);

	omap_wdt_disable(wdev);
	omap_wdt_adjust_timeout(timer_margin);

	wdev->omap_wdt_miscdev.parent = &pdev->dev;
	wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
	wdev->omap_wdt_miscdev.name = "watchdog";
	wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;

	ret = misc_register(&(wdev->omap_wdt_miscdev));
	if (ret)
		goto err_misc;

	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
		__raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
		timer_margin);

	/* autogate OCP interface clock */
	__raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);

	clk_disable(wdev->ick);
	clk_disable(wdev->fck);

	omap_wdt_dev = pdev;

	return 0;

err_misc:
	platform_set_drvdata(pdev, NULL);
	iounmap(wdev->base);

err_ioremap:
	wdev->base = NULL;

err_clk:
	if (wdev->ick)
		clk_put(wdev->ick);
	if (wdev->fck)
		clk_put(wdev->fck);
	kfree(wdev);

err_kzalloc:
	release_mem_region(res->start, resource_size(res));

err_busy:
err_get_resource:

	return ret;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	if (wdev->omap_wdt_users)
		omap_wdt_disable(wdev);
}

static int __devexit omap_wdt_remove(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!res)
		return -ENOENT;

	misc_deregister(&(wdev->omap_wdt_miscdev));
	release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);

	clk_put(wdev->ick);
	clk_put(wdev->fck);
	iounmap(wdev->base);

	kfree(wdev);
	omap_wdt_dev = NULL;

	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	if (wdev->omap_wdt_users)
		omap_wdt_disable(wdev);

	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	if (wdev->omap_wdt_users) {
		omap_wdt_enable(wdev);
		omap_wdt_ping(wdev);
	}

	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= __devexit_p(omap_wdt_remove),
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "omap_wdt",
	},
};

static int __init omap_wdt_init(void)
{
	spin_lock_init(&wdt_lock);
	return platform_driver_register(&omap_wdt_driver);
}

static void __exit omap_wdt_exit(void)
{
	platform_driver_unregister(&omap_wdt_driver);
}

module_init(omap_wdt_init);
module_exit(omap_wdt_exit);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
7768a13c	1	/*
2817142f	2	* omap_wdt.c
7768a13c	3	*
2817142f	4	* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c KS	5	*
	6	* Author: MontaVista Software, Inc.
	7	* <gdavis@mvista.com> or <source@mvista.com>
	8	*
	9	* 2003 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is
	11	* licensed "as is" without any warranty of any kind, whether express
	12	* or implied.
	13	*
	14	* History:
	15	*
	16	* 20030527: George G. Davis <gdavis@mvista.com>
	17	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	18	* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586	19	* Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
7768a13c KS	20	*
	21	* Copyright (c) 2004 Texas Instruments.
	22	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	23	* 2. Ported to 2.6 kernel
	24	*
	25	* Copyright (c) 2005 David Brownell
	26	* Use the driver model and standard identifiers; handle bigger timeouts.
	27	*/
	28
	29	#include <linux/module.h>
7768a13c KS	30	#include <linux/types.h>
	31	#include <linux/kernel.h>
	32	#include <linux/fs.h>
	33	#include <linux/mm.h>
	34	#include <linux/miscdevice.h>
	35	#include <linux/watchdog.h>
	36	#include <linux/reboot.h>
7768a13c KS	37	#include <linux/init.h>
	38	#include <linux/err.h>
	39	#include <linux/platform_device.h>
	40	#include <linux/moduleparam.h>
	41	#include <linux/clk.h>
1977f032	42	#include <linux/bitops.h>
089ab079	43	#include <linux/io.h>
12b9df7d	44	#include <linux/uaccess.h>
5a0e3ad6	45	#include <linux/slab.h>
a09e64fb	46	#include <mach/hardware.h>
ce491cf8	47	#include <plat/prcm.h>
7768a13c KS	48
	49	#include "omap_wdt.h"
	50
2817142f FB	51	static struct platform_device *omap_wdt_dev;
2817142f FB	52
7768a13c KS	53	static unsigned timer_margin;
	54	module_param(timer_margin, uint, 0);
	55	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	56
7768a13c	57	static unsigned int wdt_trgr_pattern = 0x1234;
12b9df7d	58	static spinlock_t wdt_lock;
7768a13c	59
2817142f FB	60	struct omap_wdt_dev {
	61	void __iomem base; / physical */
	62	struct device *dev;
	63	int omap_wdt_users;
39a80c7f RK	64	struct clk *ick;
39a80c7f RK	65	struct clk *fck;
2817142f FB	66	struct resource *mem;
	67	struct miscdevice omap_wdt_miscdev;
	68	};
	69
	70	static void omap_wdt_ping(struct omap_wdt_dev *wdev)
7768a13c	71	{
2817142f	72	void __iomem *base = wdev->base;
b3112180	73
7768a13c	74	/* wait for posted write to complete */
9f69e3b0	75	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c	76	cpu_relax();
b3112180	77
7768a13c	78	wdt_trgr_pattern = ~wdt_trgr_pattern;
9f69e3b0	79	__raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180	80
7768a13c	81	/* wait for posted write to complete */
9f69e3b0	82	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	83	cpu_relax();
	84	/* reloaded WCRR from WLDR */
	85	}
	86
2817142f	87	static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c	88	{
b3112180 FB	89	void __iomem *base = wdev->base;
b3112180 FB	90
7768a13c	91	/* Sequence to enable the watchdog */
9f69e3b0 FB	92	__raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
9f69e3b0 FB	93	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c	94	cpu_relax();
b3112180	95
9f69e3b0 FB	96	__raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
9f69e3b0 FB	97	while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c KS	98	cpu_relax();
	99	}
	100
2817142f	101	static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c	102	{
b3112180 FB	103	void __iomem *base = wdev->base;
b3112180 FB	104
7768a13c	105	/* sequence required to disable watchdog */
9f69e3b0 FB	106	__raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
9f69e3b0 FB	107	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c	108	cpu_relax();
b3112180	109
9f69e3b0 FB	110	__raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
9f69e3b0 FB	111	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c KS	112	cpu_relax();
	113	}
	114
	115	static void omap_wdt_adjust_timeout(unsigned new_timeout)
	116	{
	117	if (new_timeout < TIMER_MARGIN_MIN)
	118	new_timeout = TIMER_MARGIN_DEFAULT;
	119	if (new_timeout > TIMER_MARGIN_MAX)
	120	new_timeout = TIMER_MARGIN_MAX;
	121	timer_margin = new_timeout;
	122	}
	123
2817142f	124	static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
7768a13c KS	125	{
7768a13c KS	126	u32 pre_margin = GET_WLDR_VAL(timer_margin);
b3112180	127	void __iomem *base = wdev->base;
7768a13c KS	128
7768a13c KS	129	/* just count up at 32 KHz */
9f69e3b0	130	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c	131	cpu_relax();
b3112180	132
9f69e3b0 FB	133	__raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
9f69e3b0 FB	134	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c KS	135	cpu_relax();
	136	}
	137
	138	/*
	139	* Allow only one task to hold it open
	140	*/
7768a13c KS	141	static int omap_wdt_open(struct inode inode, struct file file)
7768a13c KS	142	{
b3112180 FB	143	struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
	144	void __iomem *base = wdev->base;
	145
2817142f	146	if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
7768a13c KS	147	return -EBUSY;
7768a13c KS	148
4c5e1946	149	clk_enable(wdev->ick); /* Enable the interface clock */
39a80c7f	150	clk_enable(wdev->fck); /* Enable the functional clock */
7768a13c KS	151
7768a13c KS	152	/* initialize prescaler */
9f69e3b0	153	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c	154	cpu_relax();
b3112180	155
9f69e3b0 FB	156	__raw_writel((1 << 5) \| (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
9f69e3b0 FB	157	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c KS	158	cpu_relax();
7768a13c KS	159
2817142f FB	160	file->private_data = (void *) wdev;
	161
	162	omap_wdt_set_timeout(wdev);
789cd470	163	omap_wdt_ping(wdev); /* trigger loading of new timeout value */
2817142f	164	omap_wdt_enable(wdev);
b3112180	165
ec9505a7	166	return nonseekable_open(inode, file);
7768a13c KS	167	}
	168
	169	static int omap_wdt_release(struct inode inode, struct file file)
	170	{
b3112180 FB	171	struct omap_wdt_dev *wdev = file->private_data;
b3112180 FB	172
7768a13c KS	173	/*
	174	* Shut off the timer unless NOWAYOUT is defined.
	175	*/
	176	#ifndef CONFIG_WATCHDOG_NOWAYOUT
7768a13c	177
2817142f	178	omap_wdt_disable(wdev);
7768a13c	179
4c5e1946	180	clk_disable(wdev->ick);
39a80c7f	181	clk_disable(wdev->fck);
7768a13c KS	182	#else
	183	printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
	184	#endif
2817142f	185	wdev->omap_wdt_users = 0;
b3112180	186
7768a13c KS	187	return 0;
	188	}
	189
12b9df7d	190	static ssize_t omap_wdt_write(struct file file, const char __user data,
7768a13c KS	191	size_t len, loff_t *ppos)
7768a13c KS	192	{
b3112180 FB	193	struct omap_wdt_dev *wdev = file->private_data;
b3112180 FB	194
7768a13c	195	/* Refresh LOAD_TIME. */
12b9df7d AC	196	if (len) {
12b9df7d AC	197	spin_lock(&wdt_lock);
2817142f	198	omap_wdt_ping(wdev);
12b9df7d AC	199	spin_unlock(&wdt_lock);
12b9df7d AC	200	}
7768a13c KS	201	return len;
	202	}
	203
12b9df7d AC	204	static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
12b9df7d AC	205	unsigned long arg)
7768a13c	206	{
2817142f	207	struct omap_wdt_dev *wdev;
7768a13c	208	int new_margin;
12b9df7d	209	static const struct watchdog_info ident = {
7768a13c KS	210	.identity = "OMAP Watchdog",
	211	.options = WDIOF_SETTIMEOUT,
	212	.firmware_version = 0,
	213	};
b3112180	214
2817142f	215	wdev = file->private_data;
7768a13c KS	216
7768a13c KS	217	switch (cmd) {
7768a13c KS	218	case WDIOC_GETSUPPORT:
	219	return copy_to_user((struct watchdog_info __user *)arg, &ident,
	220	sizeof(ident));
	221	case WDIOC_GETSTATUS:
	222	return put_user(0, (int __user *)arg);
	223	case WDIOC_GETBOOTSTATUS:
	224	if (cpu_is_omap16xx())
9f69e3b0	225	return put_user(__raw_readw(ARM_SYSST),
7768a13c KS	226	(int __user *)arg);
	227	if (cpu_is_omap24xx())
	228	return put_user(omap_prcm_get_reset_sources(),
	229	(int __user *)arg);
	230	case WDIOC_KEEPALIVE:
12b9df7d	231	spin_lock(&wdt_lock);
2817142f	232	omap_wdt_ping(wdev);
12b9df7d	233	spin_unlock(&wdt_lock);
7768a13c KS	234	return 0;
	235	case WDIOC_SETTIMEOUT:
	236	if (get_user(new_margin, (int __user *)arg))
	237	return -EFAULT;
	238	omap_wdt_adjust_timeout(new_margin);
	239
12b9df7d	240	spin_lock(&wdt_lock);
2817142f FB	241	omap_wdt_disable(wdev);
	242	omap_wdt_set_timeout(wdev);
	243	omap_wdt_enable(wdev);
7768a13c	244
2817142f	245	omap_wdt_ping(wdev);
12b9df7d	246	spin_unlock(&wdt_lock);
7768a13c KS	247	/* Fall */
	248	case WDIOC_GETTIMEOUT:
	249	return put_user(timer_margin, (int __user *)arg);
0c06090c WVS	250	default:
0c06090c WVS	251	return -ENOTTY;
7768a13c KS	252	}
	253	}
	254
2b8693c0	255	static const struct file_operations omap_wdt_fops = {
7768a13c KS	256	.owner = THIS_MODULE,
7768a13c KS	257	.write = omap_wdt_write,
12b9df7d	258	.unlocked_ioctl = omap_wdt_ioctl,
7768a13c KS	259	.open = omap_wdt_open,
	260	.release = omap_wdt_release,
	261	};
	262
0e3912c7	263	static int __devinit omap_wdt_probe(struct platform_device *pdev)
7768a13c KS	264	{
7768a13c KS	265	struct resource res, mem;
2817142f	266	struct omap_wdt_dev *wdev;
b3112180	267	int ret;
7768a13c KS	268
	269	/* reserve static register mappings */
	270	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b3112180 FB	271	if (!res) {
	272	ret = -ENOENT;
	273	goto err_get_resource;
	274	}
7768a13c	275
b3112180 FB	276	if (omap_wdt_dev) {
	277	ret = -EBUSY;
	278	goto err_busy;
	279	}
2817142f	280
b782a563	281	mem = request_mem_region(res->start, resource_size(res), pdev->name);
b3112180 FB	282	if (!mem) {
	283	ret = -EBUSY;
	284	goto err_busy;
	285	}
7768a13c	286
2817142f FB	287	wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
	288	if (!wdev) {
	289	ret = -ENOMEM;
b3112180	290	goto err_kzalloc;
2817142f	291	}
b3112180	292
2817142f FB	293	wdev->omap_wdt_users = 0;
2817142f FB	294	wdev->mem = mem;
7768a13c	295
4c5e1946 RK	296	wdev->ick = clk_get(&pdev->dev, "ick");
	297	if (IS_ERR(wdev->ick)) {
	298	ret = PTR_ERR(wdev->ick);
	299	wdev->ick = NULL;
	300	goto err_clk;
7768a13c	301	}
39a80c7f RK	302	wdev->fck = clk_get(&pdev->dev, "fck");
	303	if (IS_ERR(wdev->fck)) {
	304	ret = PTR_ERR(wdev->fck);
	305	wdev->fck = NULL;
	306	goto err_clk;
2817142f FB	307	}
2817142f FB	308
b782a563	309	wdev->base = ioremap(res->start, resource_size(res));
9f69e3b0 FB	310	if (!wdev->base) {
9f69e3b0 FB	311	ret = -ENOMEM;
b3112180	312	goto err_ioremap;
9f69e3b0 FB	313	}
9f69e3b0 FB	314
2817142f	315	platform_set_drvdata(pdev, wdev);
7768a13c	316
789cd470 UBH	317	clk_enable(wdev->ick);
	318	clk_enable(wdev->fck);
	319
2817142f	320	omap_wdt_disable(wdev);
7768a13c KS	321	omap_wdt_adjust_timeout(timer_margin);
7768a13c KS	322
2817142f FB	323	wdev->omap_wdt_miscdev.parent = &pdev->dev;
	324	wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
	325	wdev->omap_wdt_miscdev.name = "watchdog";
	326	wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
	327
	328	ret = misc_register(&(wdev->omap_wdt_miscdev));
7768a13c	329	if (ret)
b3112180	330	goto err_misc;
7768a13c	331
2817142f	332	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
9f69e3b0	333	__raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
2817142f	334	timer_margin);
7768a13c KS	335
7768a13c KS	336	/* autogate OCP interface clock */
9f69e3b0	337	__raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
2817142f	338
789cd470 UBH	339	clk_disable(wdev->ick);
	340	clk_disable(wdev->fck);
	341
2817142f FB	342	omap_wdt_dev = pdev;
2817142f FB	343
7768a13c KS	344	return 0;
7768a13c KS	345
b3112180 FB	346	err_misc:
	347	platform_set_drvdata(pdev, NULL);
	348	iounmap(wdev->base);
	349
	350	err_ioremap:
	351	wdev->base = NULL;
	352
	353	err_clk:
39a80c7f RK	354	if (wdev->ick)
	355	clk_put(wdev->ick);
	356	if (wdev->fck)
	357	clk_put(wdev->fck);
b3112180 FB	358	kfree(wdev);
	359
	360	err_kzalloc:
b782a563	361	release_mem_region(res->start, resource_size(res));
b3112180 FB	362
	363	err_busy:
	364	err_get_resource:
	365
7768a13c KS	366	return ret;
	367	}
	368
	369	static void omap_wdt_shutdown(struct platform_device *pdev)
	370	{
b3112180	371	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f FB	372
	373	if (wdev->omap_wdt_users)
	374	omap_wdt_disable(wdev);
7768a13c KS	375	}
7768a13c KS	376
0e3912c7	377	static int __devexit omap_wdt_remove(struct platform_device *pdev)
7768a13c	378	{
b3112180	379	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f FB	380	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	381
	382	if (!res)
	383	return -ENOENT;
	384
	385	misc_deregister(&(wdev->omap_wdt_miscdev));
b782a563	386	release_mem_region(res->start, resource_size(res));
2817142f	387	platform_set_drvdata(pdev, NULL);
b3112180	388
4c5e1946	389	clk_put(wdev->ick);
39a80c7f	390	clk_put(wdev->fck);
9f69e3b0 FB	391	iounmap(wdev->base);
9f69e3b0 FB	392
2817142f FB	393	kfree(wdev);
2817142f FB	394	omap_wdt_dev = NULL;
b3112180	395
7768a13c KS	396	return 0;
	397	}
	398
	399	#ifdef CONFIG_PM
	400
	401	/* REVISIT ... not clear this is the best way to handle system suspend; and
	402	* it's very inappropriate for selective device suspend (e.g. suspending this
	403	* through sysfs rather than by stopping the watchdog daemon). Also, this
	404	* may not play well enough with NOWAYOUT...
	405	*/
	406
	407	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	408	{
b3112180 FB	409	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180 FB	410
2817142f FB	411	if (wdev->omap_wdt_users)
2817142f FB	412	omap_wdt_disable(wdev);
b3112180	413
7768a13c KS	414	return 0;
	415	}
	416
	417	static int omap_wdt_resume(struct platform_device *pdev)
	418	{
b3112180 FB	419	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180 FB	420
2817142f FB	421	if (wdev->omap_wdt_users) {
	422	omap_wdt_enable(wdev);
	423	omap_wdt_ping(wdev);
7768a13c	424	}
b3112180	425
7768a13c KS	426	return 0;
	427	}
	428
	429	#else
	430	#define omap_wdt_suspend NULL
	431	#define omap_wdt_resume NULL
	432	#endif
	433
	434	static struct platform_driver omap_wdt_driver = {
	435	.probe = omap_wdt_probe,
0e3912c7	436	.remove = __devexit_p(omap_wdt_remove),
7768a13c KS	437	.shutdown = omap_wdt_shutdown,
	438	.suspend = omap_wdt_suspend,
	439	.resume = omap_wdt_resume,
	440	.driver = {
	441	.owner = THIS_MODULE,
	442	.name = "omap_wdt",
	443	},
	444	};
	445
	446	static int __init omap_wdt_init(void)
	447	{
12b9df7d	448	spin_lock_init(&wdt_lock);
7768a13c KS	449	return platform_driver_register(&omap_wdt_driver);
	450	}
	451
	452	static void __exit omap_wdt_exit(void)
	453	{
	454	platform_driver_unregister(&omap_wdt_driver);
	455	}
	456
	457	module_init(omap_wdt_init);
	458	module_exit(omap_wdt_exit);
	459
	460	MODULE_AUTHOR("George G. Davis");
	461	MODULE_LICENSE("GPL");
	462	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c	463	MODULE_ALIAS("platform:omap_wdt");