]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/video/mx3fb.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
stmmac: update the driver version
[net-next-2.6.git] / drivers / video / mx3fb.c
CommitLineData
86528da2
GL		 1/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/sched.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20#include <linux/fb.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/console.h>
27#include <linux/clk.h>
28#include <linux/mutex.h>
29
30#include <mach/hardware.h>
31#include <mach/ipu.h>
32#include <mach/mx3fb.h>
33
34#include <asm/io.h>
35#include <asm/uaccess.h>
36
6e1588cb 37#define MX3FB_NAME "mx3_sdc_fb"
86528da2 38
6e1588cb 39#define MX3FB_REG_OFFSET 0xB4
86528da2
GL		 40
41/* SDC Registers */
6e1588cb
GL		 42#define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
43#define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
44#define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
45#define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
46#define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
47#define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
48#define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
49#define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
50#define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
51#define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
52#define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
86528da2
GL		 53
54/* Register bits */
6e1588cb
GL		 55#define SDC_COM_TFT_COLOR 0x00000001UL
56#define SDC_COM_FG_EN 0x00000010UL
57#define SDC_COM_GWSEL 0x00000020UL
58#define SDC_COM_GLB_A 0x00000040UL
59#define SDC_COM_KEY_COLOR_G 0x00000080UL
60#define SDC_COM_BG_EN 0x00000200UL
61#define SDC_COM_SHARP 0x00001000UL
86528da2 62
6e1588cb 63#define SDC_V_SYNC_WIDTH_L 0x00000001UL
86528da2
GL		 64
65/* Display Interface registers */
6e1588cb
GL		 66#define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
67#define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
68#define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
69#define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
70#define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
71#define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
72#define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
73#define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
74#define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
75#define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
76#define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
77#define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
78#define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
79#define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
80#define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
81#define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
82#define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
83#define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
84#define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
85#define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
86#define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
87#define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
88#define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
89#define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
90#define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
91#define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
92#define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
93#define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
94#define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
95#define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
96#define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
97#define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
98#define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
99#define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
100#define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
101#define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
102#define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
103#define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
104#define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
86528da2
GL		 105
106/* DI_DISP_SIG_POL bits */
6e1588cb
GL		 107#define DI_D3_VSYNC_POL_SHIFT 28
108#define DI_D3_HSYNC_POL_SHIFT 27
109#define DI_D3_DRDY_SHARP_POL_SHIFT 26
110#define DI_D3_CLK_POL_SHIFT 25
111#define DI_D3_DATA_POL_SHIFT 24
86528da2
GL		 112
113/* DI_DISP_IF_CONF bits */
6e1588cb
GL		 114#define DI_D3_CLK_IDLE_SHIFT 26
115#define DI_D3_CLK_SEL_SHIFT 25
116#define DI_D3_DATAMSK_SHIFT 24
86528da2
GL		 117
118enum ipu_panel {
6e1588cb
GL		 119 IPU_PANEL_SHARP_TFT,
120 IPU_PANEL_TFT,
86528da2
GL		 121};
122
123struct ipu_di_signal_cfg {
6e1588cb
GL		 124 unsigned datamask_en:1;
125 unsigned clksel_en:1;
126 unsigned clkidle_en:1;
127 unsigned data_pol:1; /* true = inverted */
128 unsigned clk_pol:1; /* true = rising edge */
129 unsigned enable_pol:1;
130 unsigned Hsync_pol:1; /* true = active high */
131 unsigned Vsync_pol:1;
86528da2
GL		 132};
133
134static const struct fb_videomode mx3fb_modedb[] = {
6e1588cb
GL		 135 {
136 /* 240x320 @ 60 Hz */
137 .name = "Sharp-QVGA",
138 .refresh = 60,
139 .xres = 240,
140 .yres = 320,
141 .pixclock = 185925,
142 .left_margin = 9,
143 .right_margin = 16,
144 .upper_margin = 7,
145 .lower_margin = 9,
146 .hsync_len = 1,
147 .vsync_len = 1,
148 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
149 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
150 FB_SYNC_CLK_IDLE_EN,
151 .vmode = FB_VMODE_NONINTERLACED,
152 .flag = 0,
153 }, {
154 /* 240x33 @ 60 Hz */
155 .name = "Sharp-CLI",
156 .refresh = 60,
157 .xres = 240,
158 .yres = 33,
159 .pixclock = 185925,
160 .left_margin = 9,
161 .right_margin = 16,
162 .upper_margin = 7,
163 .lower_margin = 9 + 287,
164 .hsync_len = 1,
165 .vsync_len = 1,
166 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
167 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
168 FB_SYNC_CLK_IDLE_EN,
169 .vmode = FB_VMODE_NONINTERLACED,
170 .flag = 0,
171 }, {
172 /* 640x480 @ 60 Hz */
173 .name = "NEC-VGA",
174 .refresh = 60,
175 .xres = 640,
176 .yres = 480,
177 .pixclock = 38255,
178 .left_margin = 144,
179 .right_margin = 0,
180 .upper_margin = 34,
181 .lower_margin = 40,
182 .hsync_len = 1,
183 .vsync_len = 1,
184 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
185 .vmode = FB_VMODE_NONINTERLACED,
186 .flag = 0,
187 }, {
188 /* NTSC TV output */
189 .name = "TV-NTSC",
190 .refresh = 60,
191 .xres = 640,
192 .yres = 480,
193 .pixclock = 37538,
194 .left_margin = 38,
195 .right_margin = 858 - 640 - 38 - 3,
196 .upper_margin = 36,
197 .lower_margin = 518 - 480 - 36 - 1,
198 .hsync_len = 3,
199 .vsync_len = 1,
200 .sync = 0,
201 .vmode = FB_VMODE_NONINTERLACED,
202 .flag = 0,
203 }, {
204 /* PAL TV output */
205 .name = "TV-PAL",
206 .refresh = 50,
207 .xres = 640,
208 .yres = 480,
209 .pixclock = 37538,
210 .left_margin = 38,
211 .right_margin = 960 - 640 - 38 - 32,
212 .upper_margin = 32,
213 .lower_margin = 555 - 480 - 32 - 3,
214 .hsync_len = 32,
215 .vsync_len = 3,
216 .sync = 0,
217 .vmode = FB_VMODE_NONINTERLACED,
218 .flag = 0,
219 }, {
220 /* TV output VGA mode, 640x480 @ 65 Hz */
221 .name = "TV-VGA",
222 .refresh = 60,
223 .xres = 640,
224 .yres = 480,
225 .pixclock = 40574,
226 .left_margin = 35,
227 .right_margin = 45,
228 .upper_margin = 9,
229 .lower_margin = 1,
230 .hsync_len = 46,
231 .vsync_len = 5,
232 .sync = 0,
233 .vmode = FB_VMODE_NONINTERLACED,
234 .flag = 0,
235 },
86528da2
GL		 236};
237
238struct mx3fb_data {
6e1588cb
GL		 239 struct fb_info *fbi;
240 int backlight_level;
241 void __iomem *reg_base;
242 spinlock_t lock;
243 struct device *dev;
244
245 uint32_t h_start_width;
246 uint32_t v_start_width;
86528da2
GL		 247};
248
249struct dma_chan_request {
6e1588cb
GL		 250 struct mx3fb_data *mx3fb;
251 enum ipu_channel id;
86528da2
GL		 252};
253
254/* MX3 specific framebuffer information. */
255struct mx3fb_info {
6e1588cb
GL		 256 int blank;
257 enum ipu_channel ipu_ch;
258 uint32_t cur_ipu_buf;
86528da2 259
6e1588cb 260 u32 pseudo_palette[16];
86528da2 261
6e1588cb
GL		 262 struct completion flip_cmpl;
263 struct mutex mutex; /* Protects fb-ops */
264 struct mx3fb_data *mx3fb;
265 struct idmac_channel *idmac_channel;
266 struct dma_async_tx_descriptor *txd;
267 dma_cookie_t cookie;
268 struct scatterlist sg[2];
86528da2 269
6e1588cb 270 u32 sync; /* preserve var->sync flags */
86528da2
GL		 271};
272
273static void mx3fb_dma_done(void *);
274
275/* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
276static const char *fb_mode;
277static unsigned long default_bpp = 16;
278
279static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
280{
6e1588cb 281 return __raw_readl(mx3fb->reg_base + reg);
86528da2
GL		 282}
283
284static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
285{
6e1588cb 286 __raw_writel(value, mx3fb->reg_base + reg);
86528da2
GL		 287}
288
289static const uint32_t di_mappings[] = {
6e1588cb
GL		 290 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */
291 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */
292 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */
293 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */
86528da2
GL		 294};
295
296static void sdc_fb_init(struct mx3fb_info *fbi)
297{
6e1588cb
GL		 298 struct mx3fb_data *mx3fb = fbi->mx3fb;
299 uint32_t reg;
86528da2 300
6e1588cb 301 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
86528da2 302
6e1588cb 303 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
86528da2
GL		 304}
305
306/* Returns enabled flag before uninit */
307static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
308{
6e1588cb
GL		 309 struct mx3fb_data *mx3fb = fbi->mx3fb;
310 uint32_t reg;
86528da2 311
6e1588cb 312 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
86528da2 313
6e1588cb 314 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
86528da2 315
6e1588cb 316 return reg & SDC_COM_BG_EN;
86528da2
GL		 317}
318
319static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
320{
6e1588cb
GL		 321 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
322 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
323 struct dma_chan *dma_chan = &ichan->dma_chan;
324 unsigned long flags;
325 dma_cookie_t cookie;
326
b3cb5372
AP		 327 if (mx3_fbi->txd)
328 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
329 to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
330 else
331 dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
6e1588cb
GL		 332
333 /* This enables the channel */
334 if (mx3_fbi->cookie < 0) {
335 mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan,
336 &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
337 if (!mx3_fbi->txd) {
338 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
339 dma_chan->chan_id);
340 return;
341 }
342
343 mx3_fbi->txd->callback_param = mx3_fbi->txd;
344 mx3_fbi->txd->callback = mx3fb_dma_done;
345
346 cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
347 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
348 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
349 } else {
350 if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
351 dev_err(mx3fb->dev, "Cannot enable channel %d\n",
352 dma_chan->chan_id);
353 return;
354 }
355
356 /* Just re-activate the same buffer */
357 dma_async_issue_pending(dma_chan);
358 cookie = mx3_fbi->cookie;
359 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
360 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
361 }
362
363 if (cookie >= 0) {
364 spin_lock_irqsave(&mx3fb->lock, flags);
365 sdc_fb_init(mx3_fbi);
366 mx3_fbi->cookie = cookie;
367 spin_unlock_irqrestore(&mx3fb->lock, flags);
368 }
369
370 /*
371 * Attention! Without this msleep the channel keeps generating
372 * interrupts. Next sdc_set_brightness() is going to be called
373 * from mx3fb_blank().
374 */
375 msleep(2);
86528da2
GL		 376}
377
378static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
379{
6e1588cb
GL		 380 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
381 uint32_t enabled;
382 unsigned long flags;
86528da2 383
6e1588cb 384 spin_lock_irqsave(&mx3fb->lock, flags);
86528da2 385
6e1588cb 386 enabled = sdc_fb_uninit(mx3_fbi);
86528da2 387
6e1588cb 388 spin_unlock_irqrestore(&mx3fb->lock, flags);
86528da2 389
c3635c78 390 mx3_fbi->txd->chan->device->device_control(mx3_fbi->txd->chan,
05827630 391 DMA_TERMINATE_ALL, 0);
6e1588cb
GL		 392 mx3_fbi->txd = NULL;
393 mx3_fbi->cookie = -EINVAL;
86528da2
GL		 394}
395
396/**
397 * sdc_set_window_pos() - set window position of the respective plane.
6e1588cb
GL		 398 * @mx3fb: mx3fb context.
399 * @channel: IPU DMAC channel ID.
400 * @x_pos: X coordinate relative to the top left corner to place window at.
401 * @y_pos: Y coordinate relative to the top left corner to place window at.
402 * @return: 0 on success or negative error code on failure.
86528da2
GL		 403 */
404static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
6e1588cb 405 int16_t x_pos, int16_t y_pos)
86528da2 406{
6e1588cb
GL		 407 if (channel != IDMAC_SDC_0)
408 return -EINVAL;
86528da2 409
d88ca815
GL		 410 x_pos += mx3fb->h_start_width;
411 y_pos += mx3fb->v_start_width;
412
6e1588cb
GL		 413 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
414 return 0;
86528da2
GL		 415}
416
417/**
418 * sdc_init_panel() - initialize a synchronous LCD panel.
6e1588cb
GL		 419 * @mx3fb: mx3fb context.
420 * @panel: panel type.
421 * @pixel_clk: desired pixel clock frequency in Hz.
422 * @width: width of panel in pixels.
423 * @height: height of panel in pixels.
424 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code.
425 * @h_start_width: number of pixel clocks between the HSYNC signal pulse
426 * and the start of valid data.
427 * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
428 * @h_end_width: number of pixel clocks between the end of valid data
429 * and the HSYNC signal for next line.
430 * @v_start_width: number of lines between the VSYNC signal pulse and the
431 * start of valid data.
432 * @v_sync_width: width of the VSYNC signal in units of lines
433 * @v_end_width: number of lines between the end of valid data and the
434 * VSYNC signal for next frame.
435 * @sig: bitfield of signal polarities for LCD interface.
436 * @return: 0 on success or negative error code on failure.
86528da2
GL		 437 */
438static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
6e1588cb
GL		 439 uint32_t pixel_clk,
440 uint16_t width, uint16_t height,
441 enum pixel_fmt pixel_fmt,
442 uint16_t h_start_width, uint16_t h_sync_width,
443 uint16_t h_end_width, uint16_t v_start_width,
444 uint16_t v_sync_width, uint16_t v_end_width,
445 struct ipu_di_signal_cfg sig)
86528da2 446{
6e1588cb
GL		 447 unsigned long lock_flags;
448 uint32_t reg;
449 uint32_t old_conf;
450 uint32_t div;
451 struct clk *ipu_clk;
86528da2 452
6e1588cb 453 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
86528da2 454
6e1588cb
GL		 455 if (v_sync_width == 0 || h_sync_width == 0)
456 return -EINVAL;
86528da2 457
6e1588cb
GL		 458 /* Init panel size and blanking periods */
459 reg = ((uint32_t) (h_sync_width - 1) << 26) |
460 ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
461 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
86528da2
GL		 462
463#ifdef DEBUG
6e1588cb 464 printk(KERN_CONT " hor_conf %x,", reg);
86528da2
GL		 465#endif
466
6e1588cb
GL		 467 reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
468 ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
469 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
86528da2
GL		 470
471#ifdef DEBUG
6e1588cb 472 printk(KERN_CONT " ver_conf %x\n", reg);
86528da2
GL		 473#endif
474
6e1588cb
GL		 475 mx3fb->h_start_width = h_start_width;
476 mx3fb->v_start_width = v_start_width;
477
478 switch (panel) {
479 case IPU_PANEL_SHARP_TFT:
480 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
481 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
482 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
483 break;
484 case IPU_PANEL_TFT:
485 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
486 break;
487 default:
488 return -EINVAL;
489 }
490
491 /* Init clocking */
492
493 /*
494 * Calculate divider: fractional part is 4 bits so simply multiple by
495 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
496 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
497 */
3879f5d6 498 ipu_clk = clk_get(mx3fb->dev, NULL);
d88ca815
GL		 499 if (!IS_ERR(ipu_clk)) {
500 div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
501 clk_put(ipu_clk);
502 } else {
503 div = 0;
504 }
6e1588cb
GL		 505
506 if (div < 0x40) { /* Divider less than 4 */
507 dev_dbg(mx3fb->dev,
508 "InitPanel() - Pixel clock divider less than 4\n");
509 div = 0x40;
510 }
511
d88ca815
GL		 512 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
513 pixel_clk, div >> 4, (div & 7) * 125);
514
6e1588cb
GL		 515 spin_lock_irqsave(&mx3fb->lock, lock_flags);
516
517 /*
518 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
519 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
520 * debug. DISP3_IF_CLK_UP_WR is 0
521 */
522 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
523
524 /* DI settings */
525 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
526 old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
d88ca815
GL		 527 sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
528 sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
6e1588cb
GL		 529 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
530
531 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
532 old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
d88ca815
GL		 533 sig.clk_pol << DI_D3_CLK_POL_SHIFT |
534 sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
535 sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
536 sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
6e1588cb
GL		 537 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
538
539 switch (pixel_fmt) {
540 case IPU_PIX_FMT_RGB24:
541 mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
542 mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
543 mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
544 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
545 ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
546 break;
547 case IPU_PIX_FMT_RGB666:
548 mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
549 mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
550 mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
551 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
552 ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
553 break;
554 case IPU_PIX_FMT_BGR666:
555 mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
556 mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
557 mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
558 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
559 ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
560 break;
561 default:
562 mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
563 mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
564 mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
565 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
566 ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
567 break;
568 }
569
570 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
571
572 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
573 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
574 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
575 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
576 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
577 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
578
579 return 0;
86528da2
GL		 580}
581
582/**
583 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
6e1588cb
GL		 584 * @mx3fb: mx3fb context.
585 * @channel: IPU DMAC channel ID.
586 * @enable: boolean to enable or disable color keyl.
587 * @color_key: 24-bit RGB color to use as transparent color key.
588 * @return: 0 on success or negative error code on failure.
86528da2
GL		 589 */
590static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
6e1588cb 591 bool enable, uint32_t color_key)
86528da2 592{
6e1588cb
GL		 593 uint32_t reg, sdc_conf;
594 unsigned long lock_flags;
86528da2 595
6e1588cb 596 spin_lock_irqsave(&mx3fb->lock, lock_flags);
86528da2 597
6e1588cb
GL		 598 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
599 if (channel == IDMAC_SDC_0)
600 sdc_conf &= ~SDC_COM_GWSEL;
601 else
602 sdc_conf |= SDC_COM_GWSEL;
86528da2 603
6e1588cb
GL		 604 if (enable) {
605 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
606 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
607 SDC_GW_CTRL);
86528da2 608
6e1588cb
GL		 609 sdc_conf |= SDC_COM_KEY_COLOR_G;
610 } else {
611 sdc_conf &= ~SDC_COM_KEY_COLOR_G;
612 }
613 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
86528da2 614
6e1588cb 615 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
86528da2 616
6e1588cb 617 return 0;
86528da2
GL		 618}
619
620/**
621 * sdc_set_global_alpha() - set global alpha blending modes.
6e1588cb
GL		 622 * @mx3fb: mx3fb context.
623 * @enable: boolean to enable or disable global alpha blending. If disabled,
624 * per pixel blending is used.
625 * @alpha: global alpha value.
626 * @return: 0 on success or negative error code on failure.
86528da2
GL		 627 */
628static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
629{
6e1588cb
GL		 630 uint32_t reg;
631 unsigned long lock_flags;
86528da2 632
6e1588cb 633 spin_lock_irqsave(&mx3fb->lock, lock_flags);
86528da2 634
6e1588cb
GL		 635 if (enable) {
636 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
637 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
86528da2 638
6e1588cb
GL		 639 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
640 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
641 } else {
642 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
643 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
644 }
86528da2 645
6e1588cb 646 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
86528da2 647
6e1588cb 648 return 0;
86528da2
GL		 649}
650
651static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
652{
b3cb5372 653 dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
6e1588cb
GL		 654 /* This might be board-specific */
655 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
656 return;
86528da2
GL		 657}
658
659static uint32_t bpp_to_pixfmt(int bpp)
660{
6e1588cb
GL		 661 uint32_t pixfmt = 0;
662 switch (bpp) {
663 case 24:
664 pixfmt = IPU_PIX_FMT_BGR24;
665 break;
666 case 32:
667 pixfmt = IPU_PIX_FMT_BGR32;
668 break;
669 case 16:
670 pixfmt = IPU_PIX_FMT_RGB565;
671 break;
672 }
673 return pixfmt;
86528da2
GL		 674}
675
676static int mx3fb_blank(int blank, struct fb_info *fbi);
20de03da
GL		 677static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
678 bool lock);
86528da2
GL		 679static int mx3fb_unmap_video_memory(struct fb_info *fbi);
680
681/**
682 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
6e1588cb
GL		 683 * @info: framebuffer information pointer
684 * @return: 0 on success or negative error code on failure.
86528da2
GL		 685 */
686static int mx3fb_set_fix(struct fb_info *fbi)
687{
6e1588cb
GL		 688 struct fb_fix_screeninfo *fix = &fbi->fix;
689 struct fb_var_screeninfo *var = &fbi->var;
86528da2 690
6e1588cb 691 strncpy(fix->id, "DISP3 BG", 8);
86528da2 692
6e1588cb 693 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
86528da2 694
6e1588cb
GL		 695 fix->type = FB_TYPE_PACKED_PIXELS;
696 fix->accel = FB_ACCEL_NONE;
697 fix->visual = FB_VISUAL_TRUECOLOR;
698 fix->xpanstep = 1;
699 fix->ypanstep = 1;
86528da2 700
6e1588cb 701 return 0;
86528da2
GL		 702}
703
704static void mx3fb_dma_done(void *arg)
705{
6e1588cb
GL		 706 struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
707 struct dma_chan *chan = tx_desc->txd.chan;
708 struct idmac_channel *ichannel = to_idmac_chan(chan);
709 struct mx3fb_data *mx3fb = ichannel->client;
710 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 711
6e1588cb 712 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
86528da2 713
6e1588cb 714 /* We only need one interrupt, it will be re-enabled as needed */
c8a4fb47 715 disable_irq_nosync(ichannel->eof_irq);
86528da2 716
6e1588cb 717 complete(&mx3_fbi->flip_cmpl);
86528da2
GL		 718}
719
20de03da 720static int __set_par(struct fb_info *fbi, bool lock)
86528da2 721{
6e1588cb
GL		 722 u32 mem_len;
723 struct ipu_di_signal_cfg sig_cfg;
724 enum ipu_panel mode = IPU_PANEL_TFT;
725 struct mx3fb_info *mx3_fbi = fbi->par;
726 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
727 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
728 struct idmac_video_param *video = &ichan->params.video;
729 struct scatterlist *sg = mx3_fbi->sg;
6e1588cb 730
6e1588cb
GL		 731 /* Total cleanup */
732 if (mx3_fbi->txd)
733 sdc_disable_channel(mx3_fbi);
734
735 mx3fb_set_fix(fbi);
736
737 mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
738 if (mem_len > fbi->fix.smem_len) {
739 if (fbi->fix.smem_start)
740 mx3fb_unmap_video_memory(fbi);
741
20de03da 742 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
6e1588cb 743 return -ENOMEM;
6e1588cb
GL		 744 }
745
6e1588cb
GL		 746 sg_init_table(&sg[0], 1);
747 sg_init_table(&sg[1], 1);
748
d88ca815 749 sg_dma_address(&sg[0]) = fbi->fix.smem_start;
6e1588cb
GL		 750 sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
751 fbi->fix.smem_len,
752 offset_in_page(fbi->screen_base));
753
754 if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
755 memset(&sig_cfg, 0, sizeof(sig_cfg));
756 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
757 sig_cfg.Hsync_pol = true;
758 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
759 sig_cfg.Vsync_pol = true;
760 if (fbi->var.sync & FB_SYNC_CLK_INVERT)
761 sig_cfg.clk_pol = true;
762 if (fbi->var.sync & FB_SYNC_DATA_INVERT)
763 sig_cfg.data_pol = true;
764 if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
765 sig_cfg.enable_pol = true;
766 if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
767 sig_cfg.clkidle_en = true;
768 if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
769 sig_cfg.clksel_en = true;
770 if (fbi->var.sync & FB_SYNC_SHARP_MODE)
771 mode = IPU_PANEL_SHARP_TFT;
772
773 dev_dbg(fbi->device, "pixclock = %ul Hz\n",
774 (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
775
776 if (sdc_init_panel(mx3fb, mode,
777 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
778 fbi->var.xres, fbi->var.yres,
779 (fbi->var.sync & FB_SYNC_SWAP_RGB) ?
780 IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666,
781 fbi->var.left_margin,
782 fbi->var.hsync_len,
783 fbi->var.right_margin +
784 fbi->var.hsync_len,
785 fbi->var.upper_margin,
786 fbi->var.vsync_len,
787 fbi->var.lower_margin +
788 fbi->var.vsync_len, sig_cfg) != 0) {
6e1588cb
GL		 789 dev_err(fbi->device,
790 "mx3fb: Error initializing panel.\n");
791 return -EINVAL;
792 }
793 }
794
795 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
796
797 mx3_fbi->cur_ipu_buf = 0;
798
799 video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel);
800 video->out_width = fbi->var.xres;
801 video->out_height = fbi->var.yres;
802 video->out_stride = fbi->var.xres_virtual;
803
804 if (mx3_fbi->blank == FB_BLANK_UNBLANK)
805 sdc_enable_channel(mx3_fbi);
806
20de03da
GL		 807 return 0;
808}
809
810/**
811 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
812 * @fbi: framebuffer information pointer.
813 * @return: 0 on success or negative error code on failure.
814 */
815static int mx3fb_set_par(struct fb_info *fbi)
816{
817 struct mx3fb_info *mx3_fbi = fbi->par;
818 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
819 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
820 int ret;
821
822 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
823
824 mutex_lock(&mx3_fbi->mutex);
825
826 ret = __set_par(fbi, true);
827
6e1588cb
GL		 828 mutex_unlock(&mx3_fbi->mutex);
829
20de03da 830 return ret;
86528da2
GL		 831}
832
833/**
834 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
6e1588cb
GL		 835 * @var: framebuffer variable parameters
836 * @fbi: framebuffer information pointer
86528da2
GL		 837 */
838static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
839{
6e1588cb
GL		 840 struct mx3fb_info *mx3_fbi = fbi->par;
841 u32 vtotal;
842 u32 htotal;
843
844 dev_dbg(fbi->device, "%s\n", __func__);
845
846 if (var->xres_virtual < var->xres)
847 var->xres_virtual = var->xres;
848 if (var->yres_virtual < var->yres)
849 var->yres_virtual = var->yres;
850
851 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
852 (var->bits_per_pixel != 16))
853 var->bits_per_pixel = default_bpp;
854
855 switch (var->bits_per_pixel) {
856 case 16:
857 var->red.length = 5;
858 var->red.offset = 11;
859 var->red.msb_right = 0;
860
861 var->green.length = 6;
862 var->green.offset = 5;
863 var->green.msb_right = 0;
864
865 var->blue.length = 5;
866 var->blue.offset = 0;
867 var->blue.msb_right = 0;
868
869 var->transp.length = 0;
870 var->transp.offset = 0;
871 var->transp.msb_right = 0;
872 break;
873 case 24:
874 var->red.length = 8;
875 var->red.offset = 16;
876 var->red.msb_right = 0;
877
878 var->green.length = 8;
879 var->green.offset = 8;
880 var->green.msb_right = 0;
881
882 var->blue.length = 8;
883 var->blue.offset = 0;
884 var->blue.msb_right = 0;
885
886 var->transp.length = 0;
887 var->transp.offset = 0;
888 var->transp.msb_right = 0;
889 break;
890 case 32:
891 var->red.length = 8;
892 var->red.offset = 16;
893 var->red.msb_right = 0;
894
895 var->green.length = 8;
896 var->green.offset = 8;
897 var->green.msb_right = 0;
898
899 var->blue.length = 8;
900 var->blue.offset = 0;
901 var->blue.msb_right = 0;
902
903 var->transp.length = 8;
904 var->transp.offset = 24;
905 var->transp.msb_right = 0;
906 break;
907 }
908
909 if (var->pixclock < 1000) {
910 htotal = var->xres + var->right_margin + var->hsync_len +
911 var->left_margin;
912 vtotal = var->yres + var->lower_margin + var->vsync_len +
913 var->upper_margin;
914 var->pixclock = (vtotal * htotal * 6UL) / 100UL;
915 var->pixclock = KHZ2PICOS(var->pixclock);
916 dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
917 var->pixclock);
918 }
919
920 var->height = -1;
921 var->width = -1;
922 var->grayscale = 0;
923
924 /* Preserve sync flags */
925 var->sync |= mx3_fbi->sync;
926 mx3_fbi->sync |= var->sync;
927
928 return 0;
86528da2
GL		 929}
930
931static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
932{
6e1588cb
GL		 933 chan &= 0xffff;
934 chan >>= 16 - bf->length;
935 return chan << bf->offset;
86528da2
GL		 936}
937
938static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
6e1588cb
GL		 939 unsigned int green, unsigned int blue,
940 unsigned int trans, struct fb_info *fbi)
86528da2 941{
6e1588cb
GL		 942 struct mx3fb_info *mx3_fbi = fbi->par;
943 u32 val;
944 int ret = 1;
945
d88ca815 946 dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
6e1588cb
GL		 947
948 mutex_lock(&mx3_fbi->mutex);
949 /*
950 * If greyscale is true, then we convert the RGB value
951 * to greyscale no matter what visual we are using.
952 */
953 if (fbi->var.grayscale)
954 red = green = blue = (19595 * red + 38470 * green +
955 7471 * blue) >> 16;
956 switch (fbi->fix.visual) {
957 case FB_VISUAL_TRUECOLOR:
958 /*
959 * 16-bit True Colour. We encode the RGB value
960 * according to the RGB bitfield information.
961 */
962 if (regno < 16) {
963 u32 *pal = fbi->pseudo_palette;
964
965 val = chan_to_field(red, &fbi->var.red);
966 val |= chan_to_field(green, &fbi->var.green);
967 val |= chan_to_field(blue, &fbi->var.blue);
968
969 pal[regno] = val;
970
971 ret = 0;
972 }
973 break;
974
975 case FB_VISUAL_STATIC_PSEUDOCOLOR:
976 case FB_VISUAL_PSEUDOCOLOR:
977 break;
978 }
979 mutex_unlock(&mx3_fbi->mutex);
980
981 return ret;
86528da2
GL		 982}
983
20de03da 984static void __blank(int blank, struct fb_info *fbi)
86528da2 985{
6e1588cb
GL		 986 struct mx3fb_info *mx3_fbi = fbi->par;
987 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
988
6e1588cb
GL		 989 mx3_fbi->blank = blank;
990
991 switch (blank) {
992 case FB_BLANK_POWERDOWN:
993 case FB_BLANK_VSYNC_SUSPEND:
994 case FB_BLANK_HSYNC_SUSPEND:
995 case FB_BLANK_NORMAL:
6e1588cb 996 sdc_set_brightness(mx3fb, 0);
d88ca815
GL		 997 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
998 /* Give LCD time to update - enough for 50 and 60 Hz */
999 msleep(25);
1000 sdc_disable_channel(mx3_fbi);
6e1588cb
GL		 1001 break;
1002 case FB_BLANK_UNBLANK:
1003 sdc_enable_channel(mx3_fbi);
1004 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1005 break;
1006 }
20de03da
GL		 1007}
1008
1009/**
1010 * mx3fb_blank() - blank the display.
1011 */
1012static int mx3fb_blank(int blank, struct fb_info *fbi)
1013{
1014 struct mx3fb_info *mx3_fbi = fbi->par;
1015
1016 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1017 blank, fbi->screen_base, fbi->fix.smem_len);
1018
1019 if (mx3_fbi->blank == blank)
1020 return 0;
1021
1022 mutex_lock(&mx3_fbi->mutex);
1023 __blank(blank, fbi);
6e1588cb
GL		 1024 mutex_unlock(&mx3_fbi->mutex);
1025
1026 return 0;
86528da2
GL		 1027}
1028
1029/**
1030 * mx3fb_pan_display() - pan or wrap the display
6e1588cb
GL		 1031 * @var: variable screen buffer information.
1032 * @info: framebuffer information pointer.
86528da2
GL		 1033 *
1034 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1035 */
1036static int mx3fb_pan_display(struct fb_var_screeninfo *var,
6e1588cb 1037 struct fb_info *fbi)
86528da2 1038{
6e1588cb
GL		 1039 struct mx3fb_info *mx3_fbi = fbi->par;
1040 u32 y_bottom;
1041 unsigned long base;
1042 off_t offset;
1043 dma_cookie_t cookie;
1044 struct scatterlist *sg = mx3_fbi->sg;
1045 struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1046 struct dma_async_tx_descriptor *txd;
1047 int ret;
1048
1049 dev_dbg(fbi->device, "%s [%c]\n", __func__,
1050 list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1051
1052 if (var->xoffset > 0) {
1053 dev_dbg(fbi->device, "x panning not supported\n");
1054 return -EINVAL;
1055 }
1056
1057 if (fbi->var.xoffset == var->xoffset &&
1058 fbi->var.yoffset == var->yoffset)
1059 return 0; /* No change, do nothing */
1060
1061 y_bottom = var->yoffset;
1062
1063 if (!(var->vmode & FB_VMODE_YWRAP))
1064 y_bottom += var->yres;
1065
1066 if (y_bottom > fbi->var.yres_virtual)
1067 return -EINVAL;
1068
1069 mutex_lock(&mx3_fbi->mutex);
1070
1071 offset = (var->yoffset * var->xres_virtual + var->xoffset) *
1072 (var->bits_per_pixel / 8);
1073 base = fbi->fix.smem_start + offset;
1074
1075 dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1076 mx3_fbi->cur_ipu_buf, base);
1077
1078 /*
1079 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1080 * which we will need for the next device_prep_slave_sg(). The
1081 * IRQ-handler will disable the IRQ again.
1082 */
1083 init_completion(&mx3_fbi->flip_cmpl);
1084 enable_irq(mx3_fbi->idmac_channel->eof_irq);
1085
1086 ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1087 if (ret <= 0) {
1088 mutex_unlock(&mx3_fbi->mutex);
1089 dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1090 "user interrupt" : "timeout");
d88ca815 1091 disable_irq(mx3_fbi->idmac_channel->eof_irq);
6e1588cb
GL		 1092 return ret ? : -ETIMEDOUT;
1093 }
1094
1095 mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1096
1097 sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1098 sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1099 virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1100 offset_in_page(fbi->screen_base + offset));
1101
d88ca815
GL		 1102 if (mx3_fbi->txd)
1103 async_tx_ack(mx3_fbi->txd);
1104
6e1588cb
GL		 1105 txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg +
1106 mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
1107 if (!txd) {
1108 dev_err(fbi->device,
1109 "Error preparing a DMA transaction descriptor.\n");
1110 mutex_unlock(&mx3_fbi->mutex);
1111 return -EIO;
1112 }
1113
1114 txd->callback_param = txd;
1115 txd->callback = mx3fb_dma_done;
1116
1117 /*
1118 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1119 * should switch to another buffer
1120 */
1121 cookie = txd->tx_submit(txd);
1122 dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1123 if (cookie < 0) {
1124 dev_err(fbi->device,
1125 "Error updating SDC buf %d to address=0x%08lX\n",
1126 mx3_fbi->cur_ipu_buf, base);
1127 mutex_unlock(&mx3_fbi->mutex);
1128 return -EIO;
1129 }
1130
6e1588cb
GL		 1131 mx3_fbi->txd = txd;
1132
1133 fbi->var.xoffset = var->xoffset;
1134 fbi->var.yoffset = var->yoffset;
1135
1136 if (var->vmode & FB_VMODE_YWRAP)
1137 fbi->var.vmode |= FB_VMODE_YWRAP;
1138 else
1139 fbi->var.vmode &= ~FB_VMODE_YWRAP;
1140
1141 mutex_unlock(&mx3_fbi->mutex);
1142
1143 dev_dbg(fbi->device, "Update complete\n");
1144
1145 return 0;
86528da2
GL		 1146}
1147
1148/*
1149 * This structure contains the pointers to the control functions that are
1150 * invoked by the core framebuffer driver to perform operations like
1151 * blitting, rectangle filling, copy regions and cursor definition.
1152 */
1153static struct fb_ops mx3fb_ops = {
6e1588cb
GL		 1154 .owner = THIS_MODULE,
1155 .fb_set_par = mx3fb_set_par,
1156 .fb_check_var = mx3fb_check_var,
1157 .fb_setcolreg = mx3fb_setcolreg,
1158 .fb_pan_display = mx3fb_pan_display,
1159 .fb_fillrect = cfb_fillrect,
1160 .fb_copyarea = cfb_copyarea,
1161 .fb_imageblit = cfb_imageblit,
1162 .fb_blank = mx3fb_blank,
86528da2
GL		 1163};
1164
1165#ifdef CONFIG_PM
1166/*
1167 * Power management hooks. Note that we won't be called from IRQ context,
1168 * unlike the blank functions above, so we may sleep.
1169 */
1170
1171/*
1172 * Suspends the framebuffer and blanks the screen. Power management support
1173 */
1174static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1175{
b09de420
SH		 1176 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1177 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 1178
6e1588cb 1179 acquire_console_sem();
b09de420 1180 fb_set_suspend(mx3fb->fbi, 1);
6e1588cb 1181 release_console_sem();
86528da2 1182
6e1588cb
GL		 1183 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1184 sdc_disable_channel(mx3_fbi);
1185 sdc_set_brightness(mx3fb, 0);
86528da2 1186
6e1588cb
GL		 1187 }
1188 return 0;
86528da2
GL		 1189}
1190
1191/*
1192 * Resumes the framebuffer and unblanks the screen. Power management support
1193 */
1194static int mx3fb_resume(struct platform_device *pdev)
1195{
b09de420
SH		 1196 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1197 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 1198
6e1588cb
GL		 1199 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1200 sdc_enable_channel(mx3_fbi);
b09de420 1201 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
6e1588cb 1202 }
86528da2 1203
6e1588cb 1204 acquire_console_sem();
b09de420 1205 fb_set_suspend(mx3fb->fbi, 0);
6e1588cb 1206 release_console_sem();
86528da2 1207
6e1588cb 1208 return 0;
86528da2
GL		 1209}
1210#else
1211#define mx3fb_suspend NULL
1212#define mx3fb_resume NULL
1213#endif
1214
1215/*
1216 * Main framebuffer functions
1217 */
1218
1219/**
1220 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
6e1588cb 1221 * @fbi: framebuffer information pointer
537a1bf0 1222 * @mem_len: length of mapped memory
20de03da 1223 * @lock: do not lock during initialisation
6e1588cb 1224 * @return: Error code indicating success or failure
86528da2
GL		 1225 *
1226 * This buffer is remapped into a non-cached, non-buffered, memory region to
1227 * allow palette and pixel writes to occur without flushing the cache. Once this
1228 * area is remapped, all virtual memory access to the video memory should occur
1229 * at the new region.
1230 */
20de03da
GL		 1231static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1232 bool lock)
86528da2 1233{
6e1588cb
GL		 1234 int retval = 0;
1235 dma_addr_t addr;
86528da2 1236
6e1588cb 1237 fbi->screen_base = dma_alloc_writecombine(fbi->device,
537a1bf0 1238 mem_len,
6e1588cb 1239 &addr, GFP_DMA);
86528da2 1240
6e1588cb
GL		 1241 if (!fbi->screen_base) {
1242 dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
537a1bf0 1243 mem_len);
6e1588cb
GL		 1244 retval = -EBUSY;
1245 goto err0;
1246 }
86528da2 1247
20de03da
GL		 1248 if (lock)
1249 mutex_lock(&fbi->mm_lock);
6e1588cb 1250 fbi->fix.smem_start = addr;
537a1bf0 1251 fbi->fix.smem_len = mem_len;
20de03da
GL		 1252 if (lock)
1253 mutex_unlock(&fbi->mm_lock);
86528da2 1254
6e1588cb
GL		 1255 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1256 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
86528da2 1257
6e1588cb 1258 fbi->screen_size = fbi->fix.smem_len;
86528da2 1259
6e1588cb
GL		 1260 /* Clear the screen */
1261 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
86528da2 1262
6e1588cb 1263 return 0;
86528da2
GL		 1264
1265err0:
6e1588cb
GL		 1266 fbi->fix.smem_len = 0;
1267 fbi->fix.smem_start = 0;
1268 fbi->screen_base = NULL;
1269 return retval;
86528da2
GL		 1270}
1271
1272/**
1273 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
6e1588cb
GL		 1274 * @fbi: framebuffer information pointer
1275 * @return: error code indicating success or failure
86528da2
GL		 1276 */
1277static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1278{
6e1588cb
GL		 1279 dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1280 fbi->screen_base, fbi->fix.smem_start);
86528da2 1281
6e1588cb 1282 fbi->screen_base = 0;
537a1bf0 1283 mutex_lock(&fbi->mm_lock);
6e1588cb
GL		 1284 fbi->fix.smem_start = 0;
1285 fbi->fix.smem_len = 0;
537a1bf0 1286 mutex_unlock(&fbi->mm_lock);
6e1588cb 1287 return 0;
86528da2
GL		 1288}
1289
1290/**
1291 * mx3fb_init_fbinfo() - initialize framebuffer information object.
6e1588cb 1292 * @return: initialized framebuffer structure.
86528da2
GL		 1293 */
1294static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1295{
6e1588cb
GL		 1296 struct fb_info *fbi;
1297 struct mx3fb_info *mx3fbi;
1298 int ret;
86528da2 1299
6e1588cb
GL		 1300 /* Allocate sufficient memory for the fb structure */
1301 fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1302 if (!fbi)
1303 return NULL;
86528da2 1304
6e1588cb
GL		 1305 mx3fbi = fbi->par;
1306 mx3fbi->cookie = -EINVAL;
1307 mx3fbi->cur_ipu_buf = 0;
86528da2 1308
6e1588cb 1309 fbi->var.activate = FB_ACTIVATE_NOW;
86528da2 1310
6e1588cb
GL		 1311 fbi->fbops = ops;
1312 fbi->flags = FBINFO_FLAG_DEFAULT;
1313 fbi->pseudo_palette = mx3fbi->pseudo_palette;
86528da2 1314
6e1588cb 1315 mutex_init(&mx3fbi->mutex);
86528da2 1316
6e1588cb
GL		 1317 /* Allocate colormap */
1318 ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1319 if (ret < 0) {
1320 framebuffer_release(fbi);
1321 return NULL;
1322 }
86528da2 1323
6e1588cb 1324 return fbi;
86528da2
GL		 1325}
1326
1327static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1328{
6e1588cb
GL		 1329 struct device *dev = mx3fb->dev;
1330 struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data;
1331 const char *name = mx3fb_pdata->name;
1332 unsigned int irq;
1333 struct fb_info *fbi;
1334 struct mx3fb_info *mx3fbi;
1335 const struct fb_videomode *mode;
1336 int ret, num_modes;
86528da2 1337
6e1588cb
GL		 1338 ichan->client = mx3fb;
1339 irq = ichan->eof_irq;
86528da2 1340
6e1588cb
GL		 1341 if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1342 return -EINVAL;
86528da2 1343
6e1588cb
GL		 1344 fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1345 if (!fbi)
1346 return -ENOMEM;
86528da2 1347
6e1588cb
GL		 1348 if (!fb_mode)
1349 fb_mode = name;
86528da2 1350
6e1588cb
GL		 1351 if (!fb_mode) {
1352 ret = -EINVAL;
1353 goto emode;
1354 }
86528da2 1355
6e1588cb
GL		 1356 if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1357 mode = mx3fb_pdata->mode;
1358 num_modes = mx3fb_pdata->num_modes;
1359 } else {
1360 mode = mx3fb_modedb;
1361 num_modes = ARRAY_SIZE(mx3fb_modedb);
1362 }
86528da2 1363
6e1588cb
GL		 1364 if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1365 num_modes, NULL, default_bpp)) {
1366 ret = -EBUSY;
1367 goto emode;
1368 }
86528da2 1369
6e1588cb 1370 fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
86528da2 1371
6e1588cb
GL		 1372 /* Default Y virtual size is 2x panel size */
1373 fbi->var.yres_virtual = fbi->var.yres * 2;
86528da2 1374
6e1588cb 1375 mx3fb->fbi = fbi;
86528da2 1376
6e1588cb
GL		 1377 /* set Display Interface clock period */
1378 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1379 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
86528da2 1380
6e1588cb
GL		 1381 sdc_set_brightness(mx3fb, 255);
1382 sdc_set_global_alpha(mx3fb, true, 0xFF);
1383 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
86528da2 1384
6e1588cb
GL		 1385 mx3fbi = fbi->par;
1386 mx3fbi->idmac_channel = ichan;
1387 mx3fbi->ipu_ch = ichan->dma_chan.chan_id;
1388 mx3fbi->mx3fb = mx3fb;
1389 mx3fbi->blank = FB_BLANK_NORMAL;
86528da2 1390
6e1588cb
GL		 1391 init_completion(&mx3fbi->flip_cmpl);
1392 disable_irq(ichan->eof_irq);
1393 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
20de03da
GL		 1394 ret = __set_par(fbi, false);
1395 if (ret < 0)
1396 goto esetpar;
1397
1398 __blank(FB_BLANK_UNBLANK, fbi);
86528da2 1399
2eec8c31 1400 dev_info(dev, "registered, using mode %s\n", fb_mode);
86528da2 1401
6e1588cb
GL		 1402 ret = register_framebuffer(fbi);
1403 if (ret < 0)
1404 goto erfb;
86528da2 1405
6e1588cb 1406 return 0;
86528da2
GL		 1407
1408erfb:
1409esetpar:
1410emode:
6e1588cb
GL		 1411 fb_dealloc_cmap(&fbi->cmap);
1412 framebuffer_release(fbi);
86528da2 1413
6e1588cb 1414 return ret;
86528da2
GL		 1415}
1416
1417static bool chan_filter(struct dma_chan *chan, void *arg)
1418{
6e1588cb
GL		 1419 struct dma_chan_request *rq = arg;
1420 struct device *dev;
1421 struct mx3fb_platform_data *mx3fb_pdata;
86528da2 1422
6e1588cb
GL		 1423 if (!rq)
1424 return false;
86528da2 1425
6e1588cb
GL		 1426 dev = rq->mx3fb->dev;
1427 mx3fb_pdata = dev->platform_data;
86528da2 1428
6e1588cb
GL		 1429 return rq->id == chan->chan_id &&
1430 mx3fb_pdata->dma_dev == chan->device->dev;
86528da2
GL		 1431}
1432
1433static void release_fbi(struct fb_info *fbi)
1434{
6e1588cb 1435 mx3fb_unmap_video_memory(fbi);
86528da2 1436
6e1588cb 1437 fb_dealloc_cmap(&fbi->cmap);
86528da2 1438
6e1588cb
GL		 1439 unregister_framebuffer(fbi);
1440 framebuffer_release(fbi);
86528da2
GL		 1441}
1442
1443static int mx3fb_probe(struct platform_device *pdev)
1444{
6e1588cb
GL		 1445 struct device *dev = &pdev->dev;
1446 int ret;
1447 struct resource *sdc_reg;
1448 struct mx3fb_data *mx3fb;
1449 dma_cap_mask_t mask;
1450 struct dma_chan *chan;
1451 struct dma_chan_request rq;
1452
1453 /*
1454 * Display Interface (DI) and Synchronous Display Controller (SDC)
1455 * registers
1456 */
1457 sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1458 if (!sdc_reg)
1459 return -EINVAL;
1460
1461 mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1462 if (!mx3fb)
1463 return -ENOMEM;
1464
1465 spin_lock_init(&mx3fb->lock);
1466
1467 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1468 if (!mx3fb->reg_base) {
1469 ret = -ENOMEM;
1470 goto eremap;
1471 }
1472
1473 pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end,
1474 mx3fb->reg_base);
1475
1476 /* IDMAC interface */
1477 dmaengine_get();
1478
1479 mx3fb->dev = dev;
1480 platform_set_drvdata(pdev, mx3fb);
1481
1482 rq.mx3fb = mx3fb;
1483
1484 dma_cap_zero(mask);
1485 dma_cap_set(DMA_SLAVE, mask);
1486 dma_cap_set(DMA_PRIVATE, mask);
1487 rq.id = IDMAC_SDC_0;
1488 chan = dma_request_channel(mask, chan_filter, &rq);
1489 if (!chan) {
1490 ret = -EBUSY;
1491 goto ersdc0;
1492 }
1493
b3cb5372
AP		 1494 mx3fb->backlight_level = 255;
1495
6e1588cb
GL		 1496 ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1497 if (ret < 0)
1498 goto eisdc0;
1499
6e1588cb 1500 return 0;
86528da2
GL		 1501
1502eisdc0:
6e1588cb 1503 dma_release_channel(chan);
86528da2 1504ersdc0:
6e1588cb
GL		 1505 dmaengine_put();
1506 iounmap(mx3fb->reg_base);
86528da2 1507eremap:
6e1588cb
GL		 1508 kfree(mx3fb);
1509 dev_err(dev, "mx3fb: failed to register fb\n");
1510 return ret;
86528da2
GL		 1511}
1512
1513static int mx3fb_remove(struct platform_device *dev)
1514{
6e1588cb
GL		 1515 struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1516 struct fb_info *fbi = mx3fb->fbi;
1517 struct mx3fb_info *mx3_fbi = fbi->par;
1518 struct dma_chan *chan;
86528da2 1519
6e1588cb
GL		 1520 chan = &mx3_fbi->idmac_channel->dma_chan;
1521 release_fbi(fbi);
86528da2 1522
6e1588cb
GL		 1523 dma_release_channel(chan);
1524 dmaengine_put();
86528da2 1525
6e1588cb
GL		 1526 iounmap(mx3fb->reg_base);
1527 kfree(mx3fb);
1528 return 0;
86528da2
GL		 1529}
1530
1531static struct platform_driver mx3fb_driver = {
6e1588cb
GL		 1532 .driver = {
1533 .name = MX3FB_NAME,
1534 },
1535 .probe = mx3fb_probe,
1536 .remove = mx3fb_remove,
1537 .suspend = mx3fb_suspend,
1538 .resume = mx3fb_resume,
86528da2
GL		 1539};
1540
1541/*
1542 * Parse user specified options (`video=mx3fb:')
1543 * example:
6e1588cb 1544 * video=mx3fb:bpp=16
86528da2 1545 */
d88ca815 1546static int __init mx3fb_setup(void)
86528da2
GL		 1547{
1548#ifndef MODULE
6e1588cb
GL		 1549 char *opt, *options = NULL;
1550
1551 if (fb_get_options("mx3fb", &options))
1552 return -ENODEV;
1553
1554 if (!options || !*options)
1555 return 0;
1556
1557 while ((opt = strsep(&options, ",")) != NULL) {
1558 if (!*opt)
1559 continue;
1560 if (!strncmp(opt, "bpp=", 4))
1561 default_bpp = simple_strtoul(opt + 4, NULL, 0);
1562 else
1563 fb_mode = opt;
1564 }
86528da2
GL		 1565#endif
1566
6e1588cb 1567 return 0;
86528da2
GL		 1568}
1569
1570static int __init mx3fb_init(void)
1571{
6e1588cb 1572 int ret = mx3fb_setup();
86528da2 1573
6e1588cb
GL		 1574 if (ret < 0)
1575 return ret;
86528da2 1576
6e1588cb
GL		 1577 ret = platform_driver_register(&mx3fb_driver);
1578 return ret;
86528da2
GL		 1579}
1580
1581static void __exit mx3fb_exit(void)
1582{
6e1588cb 1583 platform_driver_unregister(&mx3fb_driver);
86528da2
GL		 1584}
1585
1586module_init(mx3fb_init);
1587module_exit(mx3fb_exit);
1588
1589MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1590MODULE_DESCRIPTION("MX3 framebuffer driver");
1591MODULE_ALIAS("platform:" MX3FB_NAME);
1592MODULE_LICENSE("GPL v2");
Clone of davem's net-next-2.6 tree