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[PATCH] NFS: fix error handling on access_ok in compat_sys_nfsservctl
[net-next-2.6.git] / drivers / video / matrox / matroxfb_base.h
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1da177e4
LT		 1/*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 */
8#ifndef __MATROXFB_H__
9#define __MATROXFB_H__
10
11/* general, but fairly heavy, debugging */
12#undef MATROXFB_DEBUG
13
14/* heavy debugging: */
15/* -- logs putc[s], so everytime a char is displayed, it's logged */
16#undef MATROXFB_DEBUG_HEAVY
17
18/* This one _could_ cause infinite loops */
19/* It _does_ cause lots and lots of messages during idle loops */
20#undef MATROXFB_DEBUG_LOOP
21
22/* Debug register calls, too? */
23#undef MATROXFB_DEBUG_REG
24
25/* Guard accelerator accesses with spin_lock_irqsave... */
26#undef MATROXFB_USE_SPINLOCKS
27
28#include <linux/config.h>
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/errno.h>
32#include <linux/string.h>
33#include <linux/mm.h>
34#include <linux/tty.h>
35#include <linux/slab.h>
36#include <linux/delay.h>
37#include <linux/fb.h>
38#include <linux/console.h>
39#include <linux/selection.h>
40#include <linux/ioport.h>
41#include <linux/init.h>
42#include <linux/timer.h>
43#include <linux/pci.h>
44#include <linux/spinlock.h>
45#include <linux/kd.h>
46
47#include <asm/io.h>
48#include <asm/unaligned.h>
49#ifdef CONFIG_MTRR
50#include <asm/mtrr.h>
51#endif
52
1da177e4
LT		 53#if defined(CONFIG_PPC_PMAC)
54#include <asm/prom.h>
55#include <asm/pci-bridge.h>
56#include "../macmodes.h"
57#endif
58
59/* always compile support for 32MB... It cost almost nothing */
60#define CONFIG_FB_MATROX_32MB
61
62#ifdef MATROXFB_DEBUG
63
64#define DEBUG
65#define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
66
67#ifdef MATROXFB_DEBUG_HEAVY
68#define DBG_HEAVY(x) DBG(x)
69#else /* MATROXFB_DEBUG_HEAVY */
70#define DBG_HEAVY(x) /* DBG_HEAVY */
71#endif /* MATROXFB_DEBUG_HEAVY */
72
73#ifdef MATROXFB_DEBUG_LOOP
74#define DBG_LOOP(x) DBG(x)
75#else /* MATROXFB_DEBUG_LOOP */
76#define DBG_LOOP(x) /* DBG_LOOP */
77#endif /* MATROXFB_DEBUG_LOOP */
78
79#ifdef MATROXFB_DEBUG_REG
80#define DBG_REG(x) DBG(x)
81#else /* MATROXFB_DEBUG_REG */
82#define DBG_REG(x) /* DBG_REG */
83#endif /* MATROXFB_DEBUG_REG */
84
85#else /* MATROXFB_DEBUG */
86
87#define DBG(x) /* DBG */
88#define DBG_HEAVY(x) /* DBG_HEAVY */
89#define DBG_REG(x) /* DBG_REG */
90#define DBG_LOOP(x) /* DBG_LOOP */
91
92#endif /* MATROXFB_DEBUG */
93
94#ifdef DEBUG
95#define dprintk(X...) printk(X)
96#else
97#define dprintk(X...)
98#endif
99
100#ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
101#define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
102#endif
103#ifndef PCI_SS_VENDOR_ID_MATROX
104#define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
105#endif
106
107#ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
108#define PCI_SS_ID_MATROX_GENERIC 0xFF00
109#define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
110#define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
111#define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
112#define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
113#define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
114#define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
115#define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
116#define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
117#define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
118#endif
119
120#define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
121#define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
122#define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
123
124#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
125
126/* G-series and Mystique have (almost) same DAC */
127#undef NEED_DAC1064
128#if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
129#define NEED_DAC1064 1
130#endif
131
132typedef struct {
133 void __iomem* vaddr;
134} vaddr_t;
135
136static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
137 return readb(va.vaddr + offs);
138}
139
140static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
141 writeb(value, va.vaddr + offs);
142}
143
144static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
145 writew(value, va.vaddr + offs);
146}
147
148static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
149 return readl(va.vaddr + offs);
150}
151
152static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
153 writel(value, va.vaddr + offs);
154}
155
156static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
157#if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
158 /*
159 * memcpy_toio works for us if:
160 * (1) Copies data as 32bit quantities, not byte after byte,
161 * (2) Performs LE ordered stores, and
162 * (3) It copes with unaligned source (destination is guaranteed to be page
163 * aligned and length is guaranteed to be multiple of 4).
164 */
165 memcpy_toio(va.vaddr, src, len);
166#else
167 u_int32_t __iomem* addr = va.vaddr;
168
169 if ((unsigned long)src & 3) {
170 while (len >= 4) {
171 fb_writel(get_unaligned((u32 *)src), addr);
172 addr++;
173 len -= 4;
174 src += 4;
175 }
176 } else {
177 while (len >= 4) {
178 fb_writel(*(u32 *)src, addr);
179 addr++;
180 len -= 4;
181 src += 4;
182 }
183 }
184#endif
185}
186
187static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
188 va->vaddr += offs;
189}
190
191static inline void __iomem* vaddr_va(vaddr_t va) {
192 return va.vaddr;
193}
194
195#define MGA_IOREMAP_NORMAL 0
196#define MGA_IOREMAP_NOCACHE 1
197
198#define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
199#define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
200static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
201 if (flags & MGA_IOREMAP_NOCACHE)
202 virt->vaddr = ioremap_nocache(phys, size);
203 else
204 virt->vaddr = ioremap(phys, size);
205 return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
206}
207
208static inline void mga_iounmap(vaddr_t va) {
209 iounmap(va.vaddr);
210}
211
212struct my_timming {
213 unsigned int pixclock;
214 int mnp;
215 unsigned int crtc;
216 unsigned int HDisplay;
217 unsigned int HSyncStart;
218 unsigned int HSyncEnd;
219 unsigned int HTotal;
220 unsigned int VDisplay;
221 unsigned int VSyncStart;
222 unsigned int VSyncEnd;
223 unsigned int VTotal;
224 unsigned int sync;
225 int dblscan;
226 int interlaced;
227 unsigned int delay; /* CRTC delay */
228};
229
230enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
231
232struct matrox_pll_cache {
233 unsigned int valid;
234 struct {
235 unsigned int mnp_key;
236 unsigned int mnp_value;
237 } data[4];
238};
239
240struct matrox_pll_limits {
241 unsigned int vcomin;
242 unsigned int vcomax;
243};
244
245struct matrox_pll_features {
246 unsigned int vco_freq_min;
247 unsigned int ref_freq;
248 unsigned int feed_div_min;
249 unsigned int feed_div_max;
250 unsigned int in_div_min;
251 unsigned int in_div_max;
252 unsigned int post_shift_max;
253};
254
255struct matroxfb_par
256{
257 unsigned int final_bppShift;
258 unsigned int cmap_len;
259 struct {
260 unsigned int bytes;
261 unsigned int pixels;
262 unsigned int chunks;
263 } ydstorg;
264};
265
266struct matrox_fb_info;
267
268struct matrox_DAC1064_features {
269 u_int8_t xvrefctrl;
270 u_int8_t xmiscctrl;
271};
272
1da177e4
LT		 273/* current hardware status */
274struct mavenregs {
275 u_int8_t regs[256];
276 int mode;
277 int vlines;
278 int xtal;
279 int fv;
280
281 u_int16_t htotal;
282 u_int16_t hcorr;
283};
284
285struct matrox_crtc2 {
286 u_int32_t ctl;
287};
288
289struct matrox_hw_state {
290 u_int32_t MXoptionReg;
291 unsigned char DACclk[6];
292 unsigned char DACreg[80];
293 unsigned char MiscOutReg;
294 unsigned char DACpal[768];
295 unsigned char CRTC[25];
296 unsigned char CRTCEXT[9];
297 unsigned char SEQ[5];
298 /* unused for MGA mode, but who knows... */
299 unsigned char GCTL[9];
300 /* unused for MGA mode, but who knows... */
301 unsigned char ATTR[21];
302
303 /* TVOut only */
304 struct mavenregs maven;
305
306 struct matrox_crtc2 crtc2;
307};
308
309struct matrox_accel_data {
310#ifdef CONFIG_FB_MATROX_MILLENIUM
311 unsigned char ramdac_rev;
312#endif
313 u_int32_t m_dwg_rect;
314 u_int32_t m_opmode;
315};
316
317struct v4l2_queryctrl;
318struct v4l2_control;
319
320struct matrox_altout {
321 const char *name;
322 int (*compute)(void* altout_dev, struct my_timming* input);
323 int (*program)(void* altout_dev);
324 int (*start)(void* altout_dev);
325 int (*verifymode)(void* altout_dev, u_int32_t mode);
326 int (*getqueryctrl)(void* altout_dev,
327 struct v4l2_queryctrl* ctrl);
328 int (*getctrl)(void* altout_dev,
329 struct v4l2_control* ctrl);
330 int (*setctrl)(void* altout_dev,
331 struct v4l2_control* ctrl);
332};
333
334#define MATROXFB_SRC_NONE 0
335#define MATROXFB_SRC_CRTC1 1
336#define MATROXFB_SRC_CRTC2 2
337
338enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
339
340struct matrox_bios {
341 unsigned int bios_valid : 1;
342 unsigned int pins_len;
343 unsigned char pins[128];
344 struct {
345 unsigned char vMaj, vMin, vRev;
346 } version;
347 struct {
348 unsigned char state, tvout;
349 } output;
350};
351
1da177e4
LT		 352struct matrox_switch;
353struct matroxfb_driver;
354struct matroxfb_dh_fb_info;
355
356struct matrox_vsync {
357 wait_queue_head_t wait;
358 unsigned int cnt;
359};
360
361struct matrox_fb_info {
362 struct fb_info fbcon;
363
364 struct list_head next_fb;
365
366 int dead;
367 int initialized;
368 unsigned int usecount;
369
370 unsigned int userusecount;
371 unsigned long irq_flags;
372
373 struct matroxfb_par curr;
374 struct matrox_hw_state hw;
375
376 struct matrox_accel_data accel;
377
378 struct pci_dev* pcidev;
379
380 struct {
381 struct matrox_vsync vsync;
382 unsigned int pixclock;
383 int mnp;
384 int panpos;
385 } crtc1;
386 struct {
387 struct matrox_vsync vsync;
388 unsigned int pixclock;
389 int mnp;
390 struct matroxfb_dh_fb_info* info;
391 struct rw_semaphore lock;
392 } crtc2;
393 struct {
394 struct rw_semaphore lock;
395 struct {
396 int brightness, contrast, saturation, hue, gamma;
397 int testout, deflicker;
398 } tvo_params;
399 } altout;
400#define MATROXFB_MAX_OUTPUTS 3
401 struct {
402 unsigned int src;
403 struct matrox_altout* output;
404 void* data;
405 unsigned int mode;
406 unsigned int default_src;
407 } outputs[MATROXFB_MAX_OUTPUTS];
408
409#define MATROXFB_MAX_FB_DRIVERS 5
410 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
411 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
412 unsigned int drivers_count;
413
414 struct {
415 unsigned long base; /* physical */
416 vaddr_t vbase; /* CPU view */
417 unsigned int len;
418 unsigned int len_usable;
419 unsigned int len_maximum;
420 } video;
421
422 struct {
423 unsigned long base; /* physical */
424 vaddr_t vbase; /* CPU view */
425 unsigned int len;
426 } mmio;
427
428 unsigned int max_pixel_clock;
429
430 struct matrox_switch* hw_switch;
431
432 struct {
433 struct matrox_pll_features pll;
434 struct matrox_DAC1064_features DAC1064;
1da177e4
LT		 435 } features;
436 struct {
437 spinlock_t DAC;
438 spinlock_t accel;
439 } lock;
440
441 enum mga_chip chip;
442
443 int interleave;
444 int millenium;
445 int milleniumII;
446 struct {
447 int cfb4;
448 const int* vxres;
449 int cross4MB;
450 int text;
451 int plnwt;
452 int srcorg;
453 } capable;
454#ifdef CONFIG_MTRR
455 struct {
456 int vram;
457 int vram_valid;
458 } mtrr;
459#endif
460 struct {
461 int precise_width;
462 int mga_24bpp_fix;
463 int novga;
464 int nobios;
465 int nopciretry;
466 int noinit;
467 int sgram;
468#ifdef CONFIG_FB_MATROX_32MB
469 int support32MB;
470#endif
471
472 int accelerator;
473 int text_type_aux;
474 int video64bits;
475 int crtc2;
476 int maven_capable;
477 unsigned int vgastep;
478 unsigned int textmode;
479 unsigned int textstep;
480 unsigned int textvram; /* character cells */
481 unsigned int ydstorg; /* offset in bytes from video start to usable memory */
482 /* 0 except for 6MB Millenium */
483 int memtype;
484 int g450dac;
485 int dfp_type;
486 int panellink; /* G400 DFP possible (not G450/G550) */
487 int dualhead;
488 unsigned int fbResource;
489 } devflags;
490 struct fb_ops fbops;
491 struct matrox_bios bios;
492 struct {
493 struct matrox_pll_limits pixel;
494 struct matrox_pll_limits system;
495 struct matrox_pll_limits video;
496 } limits;
497 struct {
498 struct matrox_pll_cache pixel;
499 struct matrox_pll_cache system;
500 struct matrox_pll_cache video;
501 } cache;
502 struct {
503 struct {
504 unsigned int video;
505 unsigned int system;
506 } pll;
507 struct {
508 u_int32_t opt;
509 u_int32_t opt2;
510 u_int32_t opt3;
511 u_int32_t mctlwtst;
512 u_int32_t mctlwtst_core;
513 u_int32_t memmisc;
514 u_int32_t memrdbk;
515 u_int32_t maccess;
516 } reg;
517 struct {
518 unsigned int ddr:1,
519 emrswen:1,
520 dll:1;
521 } memory;
522 } values;
523 u_int32_t cmap[17];
524};
525
526#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
527
528#ifdef CONFIG_FB_MATROX_MULTIHEAD
529#define ACCESS_FBINFO2(info, x) (info->x)
530#define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
531
532#define MINFO minfo
533
534#define WPMINFO2 struct matrox_fb_info* minfo
535#define WPMINFO WPMINFO2 ,
536#define CPMINFO2 const struct matrox_fb_info* minfo
537#define CPMINFO CPMINFO2 ,
538#define PMINFO2 minfo
539#define PMINFO PMINFO2 ,
540
541#define MINFO_FROM(x) struct matrox_fb_info* minfo = x
542#else
543
544extern struct matrox_fb_info matroxfb_global_mxinfo;
545
546#define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
547#define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
548
549#define MINFO (&matroxfb_global_mxinfo)
550
551#define WPMINFO2 void
552#define WPMINFO
553#define CPMINFO2 void
554#define CPMINFO
555#define PMINFO2
556#define PMINFO
557
558#define MINFO_FROM(x)
559
560#endif
561
562#define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
563
564struct matrox_switch {
565 int (*preinit)(WPMINFO2);
566 void (*reset)(WPMINFO2);
567 int (*init)(WPMINFO struct my_timming*);
568 void (*restore)(WPMINFO2);
569};
570
571struct matroxfb_driver {
572 struct list_head node;
573 char* name;
574 void* (*probe)(struct matrox_fb_info* info);
575 void (*remove)(struct matrox_fb_info* info, void* data);
576};
577
578int matroxfb_register_driver(struct matroxfb_driver* drv);
579void matroxfb_unregister_driver(struct matroxfb_driver* drv);
580
581#define PCI_OPTION_REG 0x40
582#define PCI_OPTION_ENABLE_ROM 0x40000000
583
584#define PCI_MGA_INDEX 0x44
585#define PCI_MGA_DATA 0x48
586#define PCI_OPTION2_REG 0x50
587#define PCI_OPTION3_REG 0x54
588#define PCI_MEMMISC_REG 0x58
589
590#define M_DWGCTL 0x1C00
591#define M_MACCESS 0x1C04
592#define M_CTLWTST 0x1C08
593
594#define M_PLNWT 0x1C1C
595
596#define M_BCOL 0x1C20
597#define M_FCOL 0x1C24
598
599#define M_SGN 0x1C58
600#define M_LEN 0x1C5C
601#define M_AR0 0x1C60
602#define M_AR1 0x1C64
603#define M_AR2 0x1C68
604#define M_AR3 0x1C6C
605#define M_AR4 0x1C70
606#define M_AR5 0x1C74
607#define M_AR6 0x1C78
608
609#define M_CXBNDRY 0x1C80
610#define M_FXBNDRY 0x1C84
611#define M_YDSTLEN 0x1C88
612#define M_PITCH 0x1C8C
613#define M_YDST 0x1C90
614#define M_YDSTORG 0x1C94
615#define M_YTOP 0x1C98
616#define M_YBOT 0x1C9C
617
618/* mystique only */
619#define M_CACHEFLUSH 0x1FFF
620
621#define M_EXEC 0x0100
622
623#define M_DWG_TRAP 0x04
624#define M_DWG_BITBLT 0x08
625#define M_DWG_ILOAD 0x09
626
627#define M_DWG_LINEAR 0x0080
628#define M_DWG_SOLID 0x0800
629#define M_DWG_ARZERO 0x1000
630#define M_DWG_SGNZERO 0x2000
631#define M_DWG_SHIFTZERO 0x4000
632
633#define M_DWG_REPLACE 0x000C0000
634#define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
635#define M_DWG_XOR 0x00060010
636
637#define M_DWG_BFCOL 0x04000000
638#define M_DWG_BMONOWF 0x08000000
639
640#define M_DWG_TRANSC 0x40000000
641
642#define M_FIFOSTATUS 0x1E10
643#define M_STATUS 0x1E14
644#define M_ICLEAR 0x1E18
645#define M_IEN 0x1E1C
646
647#define M_VCOUNT 0x1E20
648
649#define M_RESET 0x1E40
650#define M_MEMRDBK 0x1E44
651
652#define M_AGP2PLL 0x1E4C
653
654#define M_OPMODE 0x1E54
655#define M_OPMODE_DMA_GEN_WRITE 0x00
656#define M_OPMODE_DMA_BLIT 0x04
657#define M_OPMODE_DMA_VECTOR_WRITE 0x08
658#define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
659#define M_OPMODE_DMA_BE_8BPP 0x0000
660#define M_OPMODE_DMA_BE_16BPP 0x0100
661#define M_OPMODE_DMA_BE_32BPP 0x0200
662#define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
663#define M_OPMODE_DIR_BE_8BPP 0x000000
664#define M_OPMODE_DIR_BE_16BPP 0x010000
665#define M_OPMODE_DIR_BE_32BPP 0x020000
666
667#define M_ATTR_INDEX 0x1FC0
668#define M_ATTR_DATA 0x1FC1
669
670#define M_MISC_REG 0x1FC2
671#define M_3C2_RD 0x1FC2
672
673#define M_SEQ_INDEX 0x1FC4
674#define M_SEQ_DATA 0x1FC5
675
676#define M_MISC_REG_READ 0x1FCC
677
678#define M_GRAPHICS_INDEX 0x1FCE
679#define M_GRAPHICS_DATA 0x1FCF
680
681#define M_CRTC_INDEX 0x1FD4
682
683#define M_ATTR_RESET 0x1FDA
684#define M_3DA_WR 0x1FDA
685#define M_INSTS1 0x1FDA
686
687#define M_EXTVGA_INDEX 0x1FDE
688#define M_EXTVGA_DATA 0x1FDF
689
690/* G200 only */
691#define M_SRCORG 0x2CB4
692#define M_DSTORG 0x2CB8
693
694#define M_RAMDAC_BASE 0x3C00
695
696/* fortunately, same on TVP3026 and MGA1064 */
697#define M_DAC_REG (M_RAMDAC_BASE+0)
698#define M_DAC_VAL (M_RAMDAC_BASE+1)
699#define M_PALETTE_MASK (M_RAMDAC_BASE+2)
700
701#define M_X_INDEX 0x00
702#define M_X_DATAREG 0x0A
703
704#define DAC_XGENIOCTRL 0x2A
705#define DAC_XGENIODATA 0x2B
706
707#define M_C2CTL 0x3C10
708
709#define MX_OPTION_BSWAP 0x00000000
710
711#ifdef __LITTLE_ENDIAN
712#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
713#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
714#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
715#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
716#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
717#else
718#ifdef __BIG_ENDIAN
719#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
720#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
721#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
722#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
723#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
724#else
725#error "Byte ordering have to be defined. Cannot continue."
726#endif
727#endif
728
729#define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
730#define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
731#define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
732#define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
733#define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
734#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
735#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
736
737#define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
738
739#define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
740
741/* code speedup */
742#ifdef CONFIG_FB_MATROX_MILLENIUM
743#define isInterleave(x) (x->interleave)
744#define isMillenium(x) (x->millenium)
745#define isMilleniumII(x) (x->milleniumII)
746#else
747#define isInterleave(x) (0)
748#define isMillenium(x) (0)
749#define isMilleniumII(x) (0)
750#endif
751
752#define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
753#define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
754#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
755#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
756extern void matroxfb_DAC_out(CPMINFO int reg, int val);
757extern int matroxfb_DAC_in(CPMINFO int reg);
758extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
759extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
760extern int matroxfb_enable_irq(WPMINFO int reenable);
761
762#ifdef MATROXFB_USE_SPINLOCKS
763#define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
764#define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
765#define CRITFLAGS unsigned long critflags;
766#else
767#define CRITBEGIN
768#define CRITEND
769#define CRITFLAGS
770#endif
771
772#endif /* __MATROXFB_H__ */
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