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gxfb/lxfb: use VSA definitions when fetching framebuffer size
[net-next-2.6.git] / drivers / video / geode / lxfb_ops.c
CommitLineData
3968cb49
JC		 1/* Geode LX framebuffer driver
2 *
3 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/fb.h>
14#include <linux/uaccess.h>
15#include <linux/delay.h>
32bf87e3 16#include <asm/geode.h>
3968cb49
JC		 17
18#include "lxfb.h"
19
20/* TODO
21 * Support panel scaling
22 * Add acceleration
23 * Add support for interlacing (TV out)
24 * Support compression
25 */
26
27/* This is the complete list of PLL frequencies that we can set -
28 * we will choose the closest match to the incoming clock.
29 * freq is the frequency of the dotclock * 1000 (for example,
30 * 24823 = 24.983 Mhz).
31 * pllval is the corresponding PLL value
32*/
33
34static const struct {
35 unsigned int pllval;
36 unsigned int freq;
37} pll_table[] = {
3888d463
JR		 38 { 0x000131AC, 6231 },
39 { 0x0001215D, 6294 },
40 { 0x00011087, 6750 },
41 { 0x0001216C, 7081 },
42 { 0x0001218D, 7140 },
43 { 0x000110C9, 7800 },
44 { 0x00013147, 7875 },
45 { 0x000110A7, 8258 },
46 { 0x00012159, 8778 },
47 { 0x00014249, 8875 },
48 { 0x00010057, 9000 },
49 { 0x0001219A, 9472 },
50 { 0x00012158, 9792 },
51 { 0x00010045, 10000 },
52 { 0x00010089, 10791 },
53 { 0x000110E7, 11225 },
54 { 0x00012136, 11430 },
55 { 0x00013207, 12375 },
56 { 0x00012187, 12500 },
57 { 0x00014286, 14063 },
58 { 0x000110E5, 15016 },
59 { 0x00014214, 16250 },
60 { 0x00011105, 17045 },
61 { 0x000131E4, 18563 },
62 { 0x00013183, 18750 },
63 { 0x00014284, 19688 },
64 { 0x00011104, 20400 },
65 { 0x00016363, 23625 },
66 { 0x00015303, 24380 },
67 { 0x000031AC, 24923 },
68 { 0x0000215D, 25175 },
69 { 0x00001087, 27000 },
70 { 0x0000216C, 28322 },
71 { 0x0000218D, 28560 },
72 { 0x00010041, 29913 },
73 { 0x000010C9, 31200 },
74 { 0x00003147, 31500 },
75 { 0x000141A1, 32400 },
76 { 0x000010A7, 33032 },
77 { 0x00012182, 33375 },
78 { 0x000141B1, 33750 },
79 { 0x00002159, 35112 },
80 { 0x00004249, 35500 },
81 { 0x00000057, 36000 },
82 { 0x000141E1, 37125 },
83 { 0x0000219A, 37889 },
84 { 0x00002158, 39168 },
85 { 0x00000045, 40000 },
86 { 0x000131A1, 40500 },
87 { 0x00010061, 42301 },
88 { 0x00000089, 43163 },
89 { 0x00012151, 43875 },
90 { 0x000010E7, 44900 },
91 { 0x00002136, 45720 },
92 { 0x000152E1, 47250 },
93 { 0x00010071, 48000 },
94 { 0x00003207, 49500 },
95 { 0x00002187, 50000 },
96 { 0x00014291, 50625 },
97 { 0x00011101, 51188 },
98 { 0x00017481, 54563 },
99 { 0x00004286, 56250 },
100 { 0x00014170, 57375 },
101 { 0x00016210, 58500 },
102 { 0x000010E5, 60065 },
103 { 0x00013140, 62796 },
104 { 0x00004214, 65000 },
105 { 0x00016250, 65250 },
106 { 0x00001105, 68179 },
107 { 0x000141C0, 69600 },
108 { 0x00015220, 70160 },
109 { 0x00010050, 72000 },
110 { 0x000031E4, 74250 },
111 { 0x00003183, 75000 },
112 { 0x00004284, 78750 },
113 { 0x00012130, 80052 },
114 { 0x00001104, 81600 },
115 { 0x00006363, 94500 },
116 { 0x00005303, 97520 },
3968cb49
JC		 117 { 0x00002183, 100187 },
118 { 0x00002122, 101420 },
119 { 0x00001081, 108000 },
120 { 0x00006201, 113310 },
121 { 0x00000041, 119650 },
122 { 0x000041A1, 129600 },
123 { 0x00002182, 133500 },
124 { 0x000041B1, 135000 },
125 { 0x00000051, 144000 },
126 { 0x000041E1, 148500 },
127 { 0x000062D1, 157500 },
128 { 0x000031A1, 162000 },
129 { 0x00000061, 169203 },
130 { 0x00004231, 172800 },
131 { 0x00002151, 175500 },
132 { 0x000052E1, 189000 },
133 { 0x00000071, 192000 },
134 { 0x00003201, 198000 },
135 { 0x00004291, 202500 },
136 { 0x00001101, 204750 },
137 { 0x00007481, 218250 },
138 { 0x00004170, 229500 },
139 { 0x00006210, 234000 },
140 { 0x00003140, 251182 },
141 { 0x00006250, 261000 },
142 { 0x000041C0, 278400 },
143 { 0x00005220, 280640 },
144 { 0x00000050, 288000 },
145 { 0x000041E0, 297000 },
146 { 0x00002130, 320207 }
147};
148
149
150static void lx_set_dotpll(u32 pllval)
151{
152 u32 dotpll_lo, dotpll_hi;
153 int i;
154
32bf87e3 155 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
3968cb49 156
aec40532 157 if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
3968cb49
JC		 158 return;
159
160 dotpll_hi = pllval;
aec40532
AS		 161 dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
162 dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
3968cb49 163
32bf87e3 164 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
3968cb49
JC		 165
166 /* Wait 100us for the PLL to lock */
167
168 udelay(100);
169
170 /* Now, loop for the lock bit */
171
172 for (i = 0; i < 1000; i++) {
32bf87e3 173 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
aec40532 174 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
3968cb49
JC		 175 break;
176 }
177
178 /* Clear the reset bit */
179
aec40532 180 dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
32bf87e3 181 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
3968cb49
JC		 182}
183
184/* Set the clock based on the frequency specified by the current mode */
185
186static void lx_set_clock(struct fb_info *info)
187{
188 unsigned int diff, min, best = 0;
189 unsigned int freq, i;
190
3888d463 191 freq = (unsigned int) (1000000000 / info->var.pixclock);
3968cb49
JC		 192
193 min = abs(pll_table[0].freq - freq);
194
195 for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
196 diff = abs(pll_table[i].freq - freq);
197 if (diff < min) {
198 min = diff;
199 best = i;
200 }
201 }
202
3888d463 203 lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
3968cb49
JC		 204}
205
206static void lx_graphics_disable(struct fb_info *info)
207{
208 struct lxfb_par *par = info->par;
209 unsigned int val, gcfg;
210
211 /* Note: This assumes that the video is in a quitet state */
212
f5c90e85
AS		 213 write_vp(par, VP_A1T, 0);
214 write_vp(par, VP_A2T, 0);
215 write_vp(par, VP_A3T, 0);
3968cb49
JC		 216
217 /* Turn off the VGA and video enable */
f5c90e85
AS		 218 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
219 DC_GENERAL_CFG_VIDE);
3968cb49 220
9286361b 221 write_dc(par, DC_GENERAL_CFG, val);
3968cb49 222
f5c90e85
AS		 223 val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
224 write_vp(par, VP_VCFG, val);
3968cb49 225
f5c90e85
AS		 226 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
227 DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
3968cb49 228
f5c90e85
AS		 229 val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
230 write_dc(par, DC_GENLK_CTL, val);
3968cb49 231
f5c90e85
AS		 232 val = read_dc(par, DC_CLR_KEY);
233 write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
3968cb49 234
f694e53b
AS		 235 /* turn off the panel */
236 write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P);
3968cb49 237
f5c90e85
AS		 238 val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
239 write_vp(par, VP_MISC, val);
3968cb49
JC		 240
241 /* Turn off the display */
242
f5c90e85
AS		 243 val = read_vp(par, VP_DCFG);
244 write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
245 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
3968cb49 246
9286361b 247 gcfg = read_dc(par, DC_GENERAL_CFG);
f5c90e85 248 gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
9286361b 249 write_dc(par, DC_GENERAL_CFG, gcfg);
3968cb49
JC		 250
251 /* Turn off the TGEN */
9286361b 252 val = read_dc(par, DC_DISPLAY_CFG);
f5c90e85 253 val &= ~DC_DISPLAY_CFG_TGEN;
9286361b 254 write_dc(par, DC_DISPLAY_CFG, val);
3968cb49
JC		 255
256 /* Wait 1000 usecs to ensure that the TGEN is clear */
257 udelay(1000);
258
259 /* Turn off the FIFO loader */
260
f5c90e85 261 gcfg &= ~DC_GENERAL_CFG_DFLE;
9286361b 262 write_dc(par, DC_GENERAL_CFG, gcfg);
3968cb49
JC		 263
264 /* Lastly, wait for the GP to go idle */
265
266 do {
9286361b 267 val = read_gp(par, GP_BLT_STATUS);
f5c90e85 268 } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
3968cb49
JC		 269}
270
271static void lx_graphics_enable(struct fb_info *info)
272{
273 struct lxfb_par *par = info->par;
274 u32 temp, config;
275
276 /* Set the video request register */
f5c90e85 277 write_vp(par, VP_VRR, 0);
3968cb49
JC		 278
279 /* Set up the polarities */
280
f5c90e85 281 config = read_vp(par, VP_DCFG);
3968cb49 282
f5c90e85
AS		 283 config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
284 VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
3968cb49 285
f5c90e85
AS		 286 config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
287 | VP_DCFG_GV_GAM);
3968cb49
JC		 288
289 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
f5c90e85 290 config |= VP_DCFG_CRT_HSYNC_POL;
3968cb49
JC		 291
292 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
f5c90e85 293 config |= VP_DCFG_CRT_VSYNC_POL;
3968cb49
JC		 294
295 if (par->output & OUTPUT_PANEL) {
296 u32 msrlo, msrhi;
297
f5c90e85
AS		 298 write_fp(par, FP_PT1, 0);
299 write_fp(par, FP_PT2, FP_PT2_SCRC);
300 write_fp(par, FP_DFC, FP_DFC_BC);
3968cb49 301
aec40532
AS		 302 msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
303 msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
3968cb49 304
32bf87e3 305 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
3968cb49
JC		 306 }
307
308 if (par->output & OUTPUT_CRT) {
f5c90e85
AS		 309 config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
310 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
3968cb49
JC		 311 }
312
f5c90e85 313 write_vp(par, VP_DCFG, config);
3968cb49
JC		 314
315 /* Turn the CRT dacs back on */
316
317 if (par->output & OUTPUT_CRT) {
f5c90e85
AS		 318 temp = read_vp(par, VP_MISC);
319 temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
320 write_vp(par, VP_MISC, temp);
3968cb49
JC		 321 }
322
323 /* Turn the panel on (if it isn't already) */
f694e53b
AS		 324 if (par->output & OUTPUT_PANEL)
325 write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P);
3968cb49
JC		 326}
327
328unsigned int lx_framebuffer_size(void)
329{
330 unsigned int val;
331
332 /* The frame buffer size is reported by a VSM in VSA II */
333 /* Virtual Register Class = 0x02 */
334 /* VG_MEM_SIZE (1MB units) = 0x00 */
335
61a517a0
AS		 336 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
337 outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
3968cb49 338
61a517a0 339 val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE;
3968cb49
JC		 340 return (val << 20);
341}
342
343void lx_set_mode(struct fb_info *info)
344{
345 struct lxfb_par *par = info->par;
346 u64 msrval;
347
348 unsigned int max, dv, val, size;
349
350 unsigned int gcfg, dcfg;
351 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
352 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
353
354 /* Unlock the DC registers */
f5c90e85 355 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
3968cb49
JC		 356
357 lx_graphics_disable(info);
358
359 lx_set_clock(info);
360
361 /* Set output mode */
362
32bf87e3 363 rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
aec40532 364 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
3968cb49
JC		 365
366 if (par->output & OUTPUT_PANEL) {
aec40532 367 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
3968cb49
JC		 368
369 if (par->output & OUTPUT_CRT)
aec40532 370 msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
3968cb49 371 else
aec40532
AS		 372 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
373 } else
374 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
3968cb49 375
32bf87e3 376 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
3968cb49
JC		 377
378 /* Clear the various buffers */
379 /* FIXME: Adjust for panning here */
380
f5c90e85
AS		 381 write_dc(par, DC_FB_ST_OFFSET, 0);
382 write_dc(par, DC_CB_ST_OFFSET, 0);
383 write_dc(par, DC_CURS_ST_OFFSET, 0);
3968cb49
JC		 384
385 /* FIXME: Add support for interlacing */
386 /* FIXME: Add support for scaling */
387
f5c90e85
AS		 388 val = read_dc(par, DC_GENLK_CTL);
389 val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
390 DC_GENLK_CTL_FLICK_SEL_MASK);
3968cb49
JC		 391
392 /* Default scaling params */
393
9286361b
AS		 394 write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
395 write_dc(par, DC_IRQ_FILT_CTL, 0);
f5c90e85 396 write_dc(par, DC_GENLK_CTL, val);
3968cb49
JC		 397
398 /* FIXME: Support compression */
399
400 if (info->fix.line_length > 4096)
f5c90e85 401 dv = DC_DV_CTL_DV_LINE_SIZE_8K;
3968cb49 402 else if (info->fix.line_length > 2048)
f5c90e85 403 dv = DC_DV_CTL_DV_LINE_SIZE_4K;
3968cb49 404 else if (info->fix.line_length > 1024)
f5c90e85 405 dv = DC_DV_CTL_DV_LINE_SIZE_2K;
3968cb49 406 else
f5c90e85 407 dv = DC_DV_CTL_DV_LINE_SIZE_1K;
3968cb49
JC		 408
409 max = info->fix.line_length * info->var.yres;
410 max = (max + 0x3FF) & 0xFFFFFC00;
411
f5c90e85 412 write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
3968cb49 413
f5c90e85 414 val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
9286361b 415 write_dc(par, DC_DV_CTL, val | dv);
3968cb49
JC		 416
417 size = info->var.xres * (info->var.bits_per_pixel >> 3);
418
f5c90e85 419 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
9286361b 420 write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
3968cb49
JC		 421
422 /* Set default watermark values */
423
32bf87e3 424 rdmsrl(MSR_LX_SPARE_MSR, msrval);
3968cb49 425
aec40532
AS		 426 msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
427 | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
428 | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
429 | MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
430 msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
431 MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
32bf87e3 432 wrmsrl(MSR_LX_SPARE_MSR, msrval);
3968cb49 433
f5c90e85
AS		 434 gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */
435 gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
436 (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
437 gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */
3968cb49 438
f5c90e85
AS		 439 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */
440 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */
441 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */
442 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */
443 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */
444 dcfg |= DC_DISPLAY_CFG_VISL;
445 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */
3968cb49
JC		 446
447 /* Set the current BPP mode */
448
449 switch (info->var.bits_per_pixel) {
450 case 8:
f5c90e85 451 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
3968cb49
JC		 452 break;
453
454 case 16:
f5c90e85 455 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
3968cb49
JC		 456 break;
457
458 case 32:
459 case 24:
f5c90e85 460 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
3968cb49
JC		 461 break;
462 }
463
464 /* Now - set up the timings */
465
466 hactive = info->var.xres;
467 hblankstart = hactive;
468 hsyncstart = hblankstart + info->var.right_margin;
469 hsyncend = hsyncstart + info->var.hsync_len;
470 hblankend = hsyncend + info->var.left_margin;
471 htotal = hblankend;
472
473 vactive = info->var.yres;
474 vblankstart = vactive;
475 vsyncstart = vblankstart + info->var.lower_margin;
476 vsyncend = vsyncstart + info->var.vsync_len;
477 vblankend = vsyncend + info->var.upper_margin;
478 vtotal = vblankend;
479
9286361b
AS		 480 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
481 write_dc(par, DC_H_BLANK_TIMING,
482 (hblankstart - 1) | ((hblankend - 1) << 16));
483 write_dc(par, DC_H_SYNC_TIMING,
484 (hsyncstart - 1) | ((hsyncend - 1) << 16));
3968cb49 485
9286361b
AS		 486 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
487 write_dc(par, DC_V_BLANK_TIMING,
488 (vblankstart - 1) | ((vblankend - 1) << 16));
489 write_dc(par, DC_V_SYNC_TIMING,
490 (vsyncstart - 1) | ((vsyncend - 1) << 16));
3968cb49 491
9286361b
AS		 492 write_dc(par, DC_FB_ACTIVE,
493 (info->var.xres - 1) << 16 | (info->var.yres - 1));
3968cb49
JC		 494
495 /* And re-enable the graphics output */
496 lx_graphics_enable(info);
497
498 /* Write the two main configuration registers */
9286361b
AS		 499 write_dc(par, DC_DISPLAY_CFG, dcfg);
500 write_dc(par, DC_ARB_CFG, 0);
501 write_dc(par, DC_GENERAL_CFG, gcfg);
3968cb49
JC		 502
503 /* Lock the DC registers */
f5c90e85 504 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
3968cb49
JC		 505}
506
507void lx_set_palette_reg(struct fb_info *info, unsigned regno,
508 unsigned red, unsigned green, unsigned blue)
509{
510 struct lxfb_par *par = info->par;
511 int val;
512
513 /* Hardware palette is in RGB 8-8-8 format. */
514
515 val = (red << 8) & 0xff0000;
516 val |= (green) & 0x00ff00;
517 val |= (blue >> 8) & 0x0000ff;
518
9286361b
AS		 519 write_dc(par, DC_PAL_ADDRESS, regno);
520 write_dc(par, DC_PAL_DATA, val);
3968cb49
JC		 521}
522
523int lx_blank_display(struct fb_info *info, int blank_mode)
524{
525 struct lxfb_par *par = info->par;
526 u32 dcfg, fp_pm;
4537f93a 527 int blank, hsync, vsync, crt;
3968cb49
JC		 528
529 /* CRT power saving modes. */
530 switch (blank_mode) {
531 case FB_BLANK_UNBLANK:
4537f93a 532 blank = 0; hsync = 1; vsync = 1; crt = 1;
3968cb49
JC		 533 break;
534 case FB_BLANK_NORMAL:
4537f93a 535 blank = 1; hsync = 1; vsync = 1; crt = 1;
3968cb49
JC		 536 break;
537 case FB_BLANK_VSYNC_SUSPEND:
4537f93a 538 blank = 1; hsync = 1; vsync = 0; crt = 1;
3968cb49
JC		 539 break;
540 case FB_BLANK_HSYNC_SUSPEND:
4537f93a 541 blank = 1; hsync = 0; vsync = 1; crt = 1;
3968cb49
JC		 542 break;
543 case FB_BLANK_POWERDOWN:
4537f93a 544 blank = 1; hsync = 0; vsync = 0; crt = 0;
3968cb49
JC		 545 break;
546 default:
547 return -EINVAL;
548 }
549
f5c90e85 550 dcfg = read_vp(par, VP_DCFG);
4537f93a
AS		 551 dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
552 VP_DCFG_CRT_EN);
3968cb49 553 if (!blank)
f5c90e85 554 dcfg |= VP_DCFG_DAC_BL_EN;
3968cb49 555 if (hsync)
f5c90e85 556 dcfg |= VP_DCFG_HSYNC_EN;
3968cb49 557 if (vsync)
f5c90e85 558 dcfg |= VP_DCFG_VSYNC_EN;
4537f93a
AS		 559 if (crt)
560 dcfg |= VP_DCFG_CRT_EN;
f5c90e85 561 write_vp(par, VP_DCFG, dcfg);
3968cb49
JC		 562
563 /* Power on/off flat panel */
564
565 if (par->output & OUTPUT_PANEL) {
f5c90e85 566 fp_pm = read_fp(par, FP_PM);
3968cb49 567 if (blank_mode == FB_BLANK_POWERDOWN)
f5c90e85 568 fp_pm &= ~FP_PM_P;
3968cb49 569 else
f5c90e85
AS		 570 fp_pm |= FP_PM_P;
571 write_fp(par, FP_PM, fp_pm);
3968cb49
JC		 572 }
573
574 return 0;
575}
f694e53b
AS		 576
577#ifdef CONFIG_PM
578
579static void lx_save_regs(struct lxfb_par *par)
580{
581 uint32_t filt;
582 int i;
583
584 /* wait for the BLT engine to stop being busy */
585 do {
586 i = read_gp(par, GP_BLT_STATUS);
587 } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
588
589 /* save MSRs */
590 rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
591 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
592 rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
593 rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
594
595 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
596
597 /* save registers */
598 memcpy(par->gp, par->gp_regs, sizeof(par->gp));
599 memcpy(par->dc, par->dc_regs, sizeof(par->dc));
600 memcpy(par->vp, par->vp_regs, sizeof(par->vp));
601 memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp));
602
603 /* save the palette */
604 write_dc(par, DC_PAL_ADDRESS, 0);
605 for (i = 0; i < ARRAY_SIZE(par->pal); i++)
606 par->pal[i] = read_dc(par, DC_PAL_DATA);
607
608 /* save the horizontal filter coefficients */
609 filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
610 for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
611 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
612 par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1);
613 par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2);
614 }
615
616 /* save the vertical filter coefficients */
617 filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
618 for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
619 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
620 par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1);
621 }
622
623 /* save video coeff ram */
624 memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff));
625}
626
627static void lx_restore_gfx_proc(struct lxfb_par *par)
628{
629 int i;
630
631 /* a bunch of registers require GP_RASTER_MODE to be set first */
632 write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]);
633
634 for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
635 switch (i) {
636 case GP_RASTER_MODE:
637 case GP_VECTOR_MODE:
638 case GP_BLT_MODE:
639 case GP_BLT_STATUS:
640 case GP_HST_SRC:
641 /* FIXME: restore LUT data */
642 case GP_LUT_INDEX:
643 case GP_LUT_DATA:
644 /* don't restore these registers */
645 break;
646
647 default:
648 write_gp(par, i, par->gp[i]);
649 }
650 }
651}
652
653static void lx_restore_display_ctlr(struct lxfb_par *par)
654{
655 uint32_t filt;
656 int i;
657
658 wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
659
660 for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
661 switch (i) {
662 case DC_UNLOCK:
663 /* unlock the DC; runs first */
664 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
665 break;
666
667 case DC_GENERAL_CFG:
668 case DC_DISPLAY_CFG:
669 /* disable all while restoring */
670 write_dc(par, i, 0);
671 break;
672
673 case DC_DV_CTL:
674 /* set all ram to dirty */
675 write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
676
677 case DC_RSVD_1:
678 case DC_RSVD_2:
679 case DC_RSVD_3:
680 case DC_LINE_CNT:
681 case DC_PAL_ADDRESS:
682 case DC_PAL_DATA:
683 case DC_DFIFO_DIAG:
684 case DC_CFIFO_DIAG:
685 case DC_FILT_COEFF1:
686 case DC_FILT_COEFF2:
687 case DC_RSVD_4:
688 case DC_RSVD_5:
689 /* don't restore these registers */
690 break;
691
692 default:
693 write_dc(par, i, par->dc[i]);
694 }
695 }
696
697 /* restore the palette */
698 write_dc(par, DC_PAL_ADDRESS, 0);
699 for (i = 0; i < ARRAY_SIZE(par->pal); i++)
700 write_dc(par, DC_PAL_DATA, par->pal[i]);
701
702 /* restore the horizontal filter coefficients */
703 filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
704 for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
705 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
706 write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]);
707 write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]);
708 }
709
710 /* restore the vertical filter coefficients */
711 filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
712 for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
713 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
714 write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]);
715 }
716}
717
718static void lx_restore_video_proc(struct lxfb_par *par)
719{
720 int i;
721
722 wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
723 wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
724
725 for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
726 switch (i) {
727 case VP_VCFG:
728 case VP_DCFG:
729 case VP_PAR:
730 case VP_PDR:
731 case VP_CCS:
732 case VP_RSVD_0:
733 /* case VP_VDC: */ /* why should this not be restored? */
734 case VP_RSVD_1:
735 case VP_CRC32:
736 /* don't restore these registers */
737 break;
738
739 default:
740 write_vp(par, i, par->vp[i]);
741 }
742 }
743
744 /* restore video coeff ram */
745 memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff));
746}
747
748static void lx_restore_regs(struct lxfb_par *par)
749{
750 int i;
751
752 lx_set_dotpll((u32) (par->msr.dotpll >> 32));
753 lx_restore_gfx_proc(par);
754 lx_restore_display_ctlr(par);
755 lx_restore_video_proc(par);
756
757 /* Flat Panel */
758 for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
759 switch (i) {
760 case FP_PM:
761 case FP_RSVD_0:
762 case FP_RSVD_1:
763 case FP_RSVD_2:
764 case FP_RSVD_3:
765 case FP_RSVD_4:
766 /* don't restore these registers */
767 break;
768
769 default:
770 write_fp(par, i, par->fp[i]);
771 }
772 }
773
774 /* control the panel */
775 if (par->fp[FP_PM] & FP_PM_P) {
776 /* power on the panel if not already power{ed,ing} on */
777 if (!(read_fp(par, FP_PM) &
778 (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
779 write_fp(par, FP_PM, par->fp[FP_PM]);
780 } else {
781 /* power down the panel if not already power{ed,ing} down */
782 if (!(read_fp(par, FP_PM) &
783 (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
784 write_fp(par, FP_PM, par->fp[FP_PM]);
785 }
786
787 /* turn everything on */
788 write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
789 write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
790 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
791 /* do this last; it will enable the FIFO load */
792 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
793
794 /* lock the door behind us */
795 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
796}
797
798int lx_powerdown(struct fb_info *info)
799{
800 struct lxfb_par *par = info->par;
801
802 if (par->powered_down)
803 return 0;
804
805 lx_save_regs(par);
806 lx_graphics_disable(info);
807
808 par->powered_down = 1;
809 return 0;
810}
811
812int lx_powerup(struct fb_info *info)
813{
814 struct lxfb_par *par = info->par;
815
816 if (!par->powered_down)
817 return 0;
818
819 lx_restore_regs(par);
820
821 par->powered_down = 0;
822 return 0;
823}
824
825#endif
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