[net-next-2.6.git] / drivers / video / geode / lxfb.h

/* Geode LX framebuffer driver
 *
 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
 * Copyright (c) 2008  Andres Salomon <dilinger@debian.org>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */
#ifndef _LXFB_H_
#define _LXFB_H_

#include <linux/fb.h>

#define GP_REG_COUNT	(0x7c / 4)
#define DC_REG_COUNT	(0xf0 / 4)
#define VP_REG_COUNT	(0x158 / 8)
#define FP_REG_COUNT	(0x60 / 8)

#define DC_PAL_COUNT	0x104
#define DC_HFILT_COUNT	0x100
#define DC_VFILT_COUNT	0x100
#define VP_COEFF_SIZE	0x1000

#define OUTPUT_CRT   0x01
#define OUTPUT_PANEL 0x02

struct lxfb_par {
	int output;

	void __iomem *gp_regs;
	void __iomem *dc_regs;
	void __iomem *vp_regs;
#ifdef CONFIG_PM
	int powered_down;

	/* register state, for power mgmt functionality */
	struct {
		uint64_t padsel;
		uint64_t dotpll;
		uint64_t dfglcfg;
		uint64_t dcspare;
	} msr;

	uint32_t gp[GP_REG_COUNT];
	uint32_t dc[DC_REG_COUNT];
	uint64_t vp[VP_REG_COUNT];
	uint64_t fp[FP_REG_COUNT];

	uint32_t pal[DC_PAL_COUNT];
	uint32_t hcoeff[DC_HFILT_COUNT * 2];
	uint32_t vcoeff[DC_VFILT_COUNT];
	uint32_t vp_coeff[VP_COEFF_SIZE / 4];
#endif
};

static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
{
	return (((xres * (bpp >> 3)) + 7) & ~7);
}

void lx_set_mode(struct fb_info *);
unsigned int lx_framebuffer_size(void);
int lx_blank_display(struct fb_info *, int);
void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
			unsigned int, unsigned int);

#ifdef CONFIG_PM
int lx_powerdown(struct fb_info *info);
int lx_powerup(struct fb_info *info);
#endif


/* Graphics Processor registers (table 6-29 from the data book) */
enum gp_registers {
	GP_DST_OFFSET = 0,
	GP_SRC_OFFSET,
	GP_STRIDE,
	GP_WID_HEIGHT,

	GP_SRC_COLOR_FG,
	GP_SRC_COLOR_BG,
	GP_PAT_COLOR_0,
	GP_PAT_COLOR_1,

	GP_PAT_COLOR_2,
	GP_PAT_COLOR_3,
	GP_PAT_COLOR_4,
	GP_PAT_COLOR_5,

	GP_PAT_DATA_0,
	GP_PAT_DATA_1,
	GP_RASTER_MODE,
	GP_VECTOR_MODE,

	GP_BLT_MODE,
	GP_BLT_STATUS,
	GP_HST_SRC,
	GP_BASE_OFFSET,

	GP_CMD_TOP,
	GP_CMD_BOT,
	GP_CMD_READ,
	GP_CMD_WRITE,

	GP_CH3_OFFSET,
	GP_CH3_MODE_STR,
	GP_CH3_WIDHI,
	GP_CH3_HSRC,

	GP_LUT_INDEX,
	GP_LUT_DATA,
	GP_INT_CNTRL, /* 0x78 */
};

#define GP_BLT_STATUS_CE		(1 << 4)	/* cmd buf empty */
#define GP_BLT_STATUS_PB		(1 << 0)	/* primative busy */


/* Display Controller registers (table 6-47 from the data book) */
enum dc_registers {
	DC_UNLOCK = 0,
	DC_GENERAL_CFG,
	DC_DISPLAY_CFG,
	DC_ARB_CFG,

	DC_FB_ST_OFFSET,
	DC_CB_ST_OFFSET,
	DC_CURS_ST_OFFSET,
	DC_RSVD_0,

	DC_VID_Y_ST_OFFSET,
	DC_VID_U_ST_OFFSET,
	DC_VID_V_ST_OFFSET,
	DC_DV_TOP,

	DC_LINE_SIZE,
	DC_GFX_PITCH,
	DC_VID_YUV_PITCH,
	DC_RSVD_1,

	DC_H_ACTIVE_TIMING,
	DC_H_BLANK_TIMING,
	DC_H_SYNC_TIMING,
	DC_RSVD_2,

	DC_V_ACTIVE_TIMING,
	DC_V_BLANK_TIMING,
	DC_V_SYNC_TIMING,
	DC_FB_ACTIVE,

	DC_CURSOR_X,
	DC_CURSOR_Y,
	DC_RSVD_3,
	DC_LINE_CNT,

	DC_PAL_ADDRESS,
	DC_PAL_DATA,
	DC_DFIFO_DIAG,
	DC_CFIFO_DIAG,

	DC_VID_DS_DELTA,
	DC_GLIU0_MEM_OFFSET,
	DC_DV_CTL,
	DC_DV_ACCESS,

	DC_GFX_SCALE,
	DC_IRQ_FILT_CTL,
	DC_FILT_COEFF1,
	DC_FILT_COEFF2,

	DC_VBI_EVEN_CTL,
	DC_VBI_ODD_CTL,
	DC_VBI_HOR,
	DC_VBI_LN_ODD,

	DC_VBI_LN_EVEN,
	DC_VBI_PITCH,
	DC_CLR_KEY,
	DC_CLR_KEY_MASK,

	DC_CLR_KEY_X,
	DC_CLR_KEY_Y,
	DC_IRQ,
	DC_RSVD_4,

	DC_RSVD_5,
	DC_GENLK_CTL,
	DC_VID_EVEN_Y_ST_OFFSET,
	DC_VID_EVEN_U_ST_OFFSET,

	DC_VID_EVEN_V_ST_OFFSET,
	DC_V_ACTIVE_EVEN_TIMING,
	DC_V_BLANK_EVEN_TIMING,
	DC_V_SYNC_EVEN_TIMING,	/* 0xec */
};

#define DC_UNLOCK_LOCK			0x00000000
#define DC_UNLOCK_UNLOCK		0x00004758	/* magic value */

#define DC_GENERAL_CFG_FDTY		(1 << 17)
#define DC_GENERAL_CFG_DFHPEL_SHIFT	(12)
#define DC_GENERAL_CFG_DFHPSL_SHIFT	(8)
#define DC_GENERAL_CFG_VGAE		(1 << 7)
#define DC_GENERAL_CFG_DECE		(1 << 6)
#define DC_GENERAL_CFG_CMPE		(1 << 5)
#define DC_GENERAL_CFG_VIDE		(1 << 3)
#define DC_GENERAL_CFG_DFLE		(1 << 0)

#define DC_DISPLAY_CFG_VISL		(1 << 27)
#define DC_DISPLAY_CFG_PALB		(1 << 25)
#define DC_DISPLAY_CFG_DCEN		(1 << 24)
#define DC_DISPLAY_CFG_DISP_MODE_24BPP	(1 << 9)
#define DC_DISPLAY_CFG_DISP_MODE_16BPP	(1 << 8)
#define DC_DISPLAY_CFG_DISP_MODE_8BPP	(0)
#define DC_DISPLAY_CFG_TRUP		(1 << 6)
#define DC_DISPLAY_CFG_VDEN		(1 << 4)
#define DC_DISPLAY_CFG_GDEN		(1 << 3)
#define DC_DISPLAY_CFG_TGEN		(1 << 0)

#define DC_DV_TOP_DV_TOP_EN		(1 << 0)

#define DC_DV_CTL_DV_LINE_SIZE		((1 << 10) | (1 << 11))
#define DC_DV_CTL_DV_LINE_SIZE_1K	(0)
#define DC_DV_CTL_DV_LINE_SIZE_2K	(1 << 10)
#define DC_DV_CTL_DV_LINE_SIZE_4K	(1 << 11)
#define DC_DV_CTL_DV_LINE_SIZE_8K	((1 << 10) | (1 << 11))
#define DC_DV_CTL_CLEAR_DV_RAM		(1 << 0)

#define DC_IRQ_FILT_CTL_H_FILT_SEL	(1 << 10)

#define DC_CLR_KEY_CLR_KEY_EN		(1 << 24)

#define DC_IRQ_VIP_VSYNC_IRQ_STATUS	(1 << 21)	/* undocumented? */
#define DC_IRQ_STATUS			(1 << 20)	/* undocumented? */
#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK	(1 << 1)
#define DC_IRQ_MASK			(1 << 0)

#define DC_GENLK_CTL_FLICK_SEL_MASK	(0x0F << 28)
#define DC_GENLK_CTL_ALPHA_FLICK_EN	(1 << 25)
#define DC_GENLK_CTL_FLICK_EN		(1 << 24)
#define DC_GENLK_CTL_GENLK_EN		(1 << 18)


/*
 * Video Processor registers (table 6-71).
 * There is space for 64 bit values, but we never use more than the
 * lower 32 bits.  The actual register save/restore code only bothers
 * to restore those 32 bits.
 */
enum vp_registers {
	VP_VCFG = 0,
	VP_DCFG,

	VP_VX,
	VP_VY,

	VP_SCL,
	VP_VCK,

	VP_VCM,
	VP_PAR,

	VP_PDR,
	VP_SLR,

	VP_MISC,
	VP_CCS,

	VP_VYS,
	VP_VXS,

	VP_RSVD_0,
	VP_VDC,

	VP_RSVD_1,
	VP_CRC,

	VP_CRC32,
	VP_VDE,

	VP_CCK,
	VP_CCM,

	VP_CC1,
	VP_CC2,

	VP_A1X,
	VP_A1Y,

	VP_A1C,
	VP_A1T,

	VP_A2X,
	VP_A2Y,

	VP_A2C,
	VP_A2T,

	VP_A3X,
	VP_A3Y,

	VP_A3C,
	VP_A3T,

	VP_VRR,
	VP_AWT,

	VP_VTM,
	VP_VYE,

	VP_A1YE,
	VP_A2YE,

	VP_A3YE,	/* 0x150 */

	VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
};

#define VP_VCFG_VID_EN			(1 << 0)

#define VP_DCFG_GV_GAM			(1 << 21)
#define VP_DCFG_PWR_SEQ_DELAY		((1 << 17) | (1 << 18) | (1 << 19))
#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT	(1 << 19)	/* undocumented */
#define VP_DCFG_CRT_SYNC_SKW		((1 << 14) | (1 << 15) | (1 << 16))
#define VP_DCFG_CRT_SYNC_SKW_DEFAULT	(1 << 16)
#define VP_DCFG_CRT_VSYNC_POL		(1 << 9)
#define VP_DCFG_CRT_HSYNC_POL		(1 << 8)
#define VP_DCFG_DAC_BL_EN		(1 << 3)
#define VP_DCFG_VSYNC_EN		(1 << 2)
#define VP_DCFG_HSYNC_EN		(1 << 1)
#define VP_DCFG_CRT_EN			(1 << 0)

#define VP_MISC_APWRDN			(1 << 11)
#define VP_MISC_DACPWRDN		(1 << 10)
#define VP_MISC_BYP_BOTH		(1 << 0)


/*
 * Flat Panel registers (table 6-71).
 * Also 64 bit registers; see above note about 32-bit handling.
 */

/* we're actually in the VP register space, starting at address 0x400 */
#define VP_FP_START	0x400

enum fp_registers {
	FP_PT1 = 0,
	FP_PT2,

	FP_PM,
	FP_DFC,

	FP_RSVD_0,
	FP_RSVD_1,

	FP_RSVD_2,
	FP_RSVD_3,

	FP_RSVD_4,
	FP_DCA,

	FP_DMD,
	FP_CRC, /* 0x458 */
};

#define FP_PT2_SCRC			(1 << 27)	/* shfclk free */

#define FP_PM_P				(1 << 24)	/* panel power ctl */
#define FP_PM_PANEL_PWR_UP		(1 << 3)	/* r/o */
#define FP_PM_PANEL_PWR_DOWN		(1 << 2)	/* r/o */
#define FP_PM_PANEL_OFF			(1 << 1)	/* r/o */
#define FP_PM_PANEL_ON			(1 << 0)	/* r/o */

#define FP_DFC_BC			((1 << 4) | (1 << 5) | (1 << 6))


/* register access functions */

static inline uint32_t read_gp(struct lxfb_par *par, int reg)
{
	return readl(par->gp_regs + 4*reg);
}

static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->gp_regs + 4*reg);
}

static inline uint32_t read_dc(struct lxfb_par *par, int reg)
{
	return readl(par->dc_regs + 4*reg);
}

static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->dc_regs + 4*reg);
}

static inline uint32_t read_vp(struct lxfb_par *par, int reg)
{
	return readl(par->vp_regs + 8*reg);
}

static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->vp_regs + 8*reg);
}

static inline uint32_t read_fp(struct lxfb_par *par, int reg)
{
	return readl(par->vp_regs + 8*reg + VP_FP_START);
}

static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->vp_regs + 8*reg + VP_FP_START);
}


/* MSRs are defined in linux/cs5535.h; their bitfields are here */

#define MSR_GLCP_DOTPLL_LOCK		(1 << 25)	/* r/o */
#define MSR_GLCP_DOTPLL_HALFPIX		(1 << 24)
#define MSR_GLCP_DOTPLL_BYPASS		(1 << 15)
#define MSR_GLCP_DOTPLL_DOTRESET	(1 << 0)

/* note: this is actually the VP's GLD_MSR_CONFIG */
#define MSR_LX_GLD_MSR_CONFIG_FMT	((1 << 3) | (1 << 4) | (1 << 5))
#define MSR_LX_GLD_MSR_CONFIG_FMT_FP	(1 << 3)
#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT	(0)
#define MSR_LX_GLD_MSR_CONFIG_FPC	(1 << 15)	/* FP *and* CRT */

#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW	0xDFFFFFFF	/* ??? */
#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH	0x0000003F	/* ??? */

#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO	(1 << 11)	/* undocumented */
#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL	(1 << 10)	/* undocumented */
#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD	(1 << 9)	/* undocumented */
#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M	(1 << 8)	/* undocumented */
#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI	(1 << 7)	/* undocumented */
#define MSR_LX_SPARE_MSR_DIS_VIFO_WM	(1 << 6)
#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK	(1 << 5)	/* undocumented */
#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX	(1 << 4)	/* undocumented */
#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK	(1 << 1)	/* undocumented */

#endif
Commit	Line	Data
8a8e6b9d AS	1	/* Geode LX framebuffer driver
	2	*
	3	* Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
	4	* Copyright (c) 2008 Andres Salomon <dilinger@debian.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
3968cb49 JC	11	#ifndef _LXFB_H_
	12	#define _LXFB_H_
	13
	14	#include <linux/fb.h>
	15
f694e53b AS	16	#define GP_REG_COUNT (0x7c / 4)
	17	#define DC_REG_COUNT (0xf0 / 4)
	18	#define VP_REG_COUNT (0x158 / 8)
	19	#define FP_REG_COUNT (0x60 / 8)
	20
	21	#define DC_PAL_COUNT 0x104
	22	#define DC_HFILT_COUNT 0x100
	23	#define DC_VFILT_COUNT 0x100
	24	#define VP_COEFF_SIZE 0x1000
	25
3968cb49 JC	26	#define OUTPUT_CRT 0x01
	27	#define OUTPUT_PANEL 0x02
	28
	29	struct lxfb_par {
	30	int output;
3968cb49 JC	31
	32	void __iomem *gp_regs;
	33	void __iomem *dc_regs;
31f51fa8	34	void __iomem *vp_regs;
f694e53b AS	35	#ifdef CONFIG_PM
	36	int powered_down;
	37
	38	/* register state, for power mgmt functionality */
	39	struct {
	40	uint64_t padsel;
	41	uint64_t dotpll;
	42	uint64_t dfglcfg;
	43	uint64_t dcspare;
	44	} msr;
	45
	46	uint32_t gp[GP_REG_COUNT];
	47	uint32_t dc[DC_REG_COUNT];
	48	uint64_t vp[VP_REG_COUNT];
	49	uint64_t fp[FP_REG_COUNT];
	50
	51	uint32_t pal[DC_PAL_COUNT];
	52	uint32_t hcoeff[DC_HFILT_COUNT * 2];
	53	uint32_t vcoeff[DC_VFILT_COUNT];
	54	uint32_t vp_coeff[VP_COEFF_SIZE / 4];
	55	#endif
3968cb49 JC	56	};
	57
	58	static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
	59	{
	60	return (((xres * (bpp >> 3)) + 7) & ~7);
	61	}
	62
	63	void lx_set_mode(struct fb_info *);
3968cb49 JC	64	unsigned int lx_framebuffer_size(void);
	65	int lx_blank_display(struct fb_info *, int);
	66	void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
	67	unsigned int, unsigned int);
	68
f694e53b AS	69	#ifdef CONFIG_PM
	70	int lx_powerdown(struct fb_info *info);
	71	int lx_powerup(struct fb_info *info);
	72	#endif
	73
3968cb49	74
f5c90e85 AS	75	/* Graphics Processor registers (table 6-29 from the data book) */
	76	enum gp_registers {
	77	GP_DST_OFFSET = 0,
	78	GP_SRC_OFFSET,
	79	GP_STRIDE,
	80	GP_WID_HEIGHT,
	81
	82	GP_SRC_COLOR_FG,
	83	GP_SRC_COLOR_BG,
	84	GP_PAT_COLOR_0,
	85	GP_PAT_COLOR_1,
	86
	87	GP_PAT_COLOR_2,
	88	GP_PAT_COLOR_3,
	89	GP_PAT_COLOR_4,
	90	GP_PAT_COLOR_5,
	91
	92	GP_PAT_DATA_0,
	93	GP_PAT_DATA_1,
	94	GP_RASTER_MODE,
	95	GP_VECTOR_MODE,
	96
	97	GP_BLT_MODE,
	98	GP_BLT_STATUS,
	99	GP_HST_SRC,
	100	GP_BASE_OFFSET,
	101
	102	GP_CMD_TOP,
	103	GP_CMD_BOT,
	104	GP_CMD_READ,
	105	GP_CMD_WRITE,
	106
	107	GP_CH3_OFFSET,
	108	GP_CH3_MODE_STR,
	109	GP_CH3_WIDHI,
	110	GP_CH3_HSRC,
	111
	112	GP_LUT_INDEX,
	113	GP_LUT_DATA,
	114	GP_INT_CNTRL, /* 0x78 */
	115	};
	116
	117	#define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
	118	#define GP_BLT_STATUS_PB (1 << 0) /* primative busy */
	119
	120
	121	/* Display Controller registers (table 6-47 from the data book) */
	122	enum dc_registers {
	123	DC_UNLOCK = 0,
	124	DC_GENERAL_CFG,
	125	DC_DISPLAY_CFG,
	126	DC_ARB_CFG,
	127
	128	DC_FB_ST_OFFSET,
	129	DC_CB_ST_OFFSET,
	130	DC_CURS_ST_OFFSET,
	131	DC_RSVD_0,
	132
	133	DC_VID_Y_ST_OFFSET,
	134	DC_VID_U_ST_OFFSET,
	135	DC_VID_V_ST_OFFSET,
	136	DC_DV_TOP,
	137
	138	DC_LINE_SIZE,
139	DC_GFX_PITCH,
140	DC_VID_YUV_PITCH,
141	DC_RSVD_1,
142
143	DC_H_ACTIVE_TIMING,
144	DC_H_BLANK_TIMING,
145	DC_H_SYNC_TIMING,
146	DC_RSVD_2,
147
148	DC_V_ACTIVE_TIMING,
149	DC_V_BLANK_TIMING,
150	DC_V_SYNC_TIMING,
151	DC_FB_ACTIVE,
152
153	DC_CURSOR_X,
154	DC_CURSOR_Y,
155	DC_RSVD_3,
156	DC_LINE_CNT,
157
158	DC_PAL_ADDRESS,
159	DC_PAL_DATA,
160	DC_DFIFO_DIAG,
161	DC_CFIFO_DIAG,
162
163	DC_VID_DS_DELTA,
164	DC_GLIU0_MEM_OFFSET,
165	DC_DV_CTL,
166	DC_DV_ACCESS,
167
168	DC_GFX_SCALE,
169	DC_IRQ_FILT_CTL,
170	DC_FILT_COEFF1,
171	DC_FILT_COEFF2,
172
173	DC_VBI_EVEN_CTL,
174	DC_VBI_ODD_CTL,
175	DC_VBI_HOR,
176	DC_VBI_LN_ODD,
177
178	DC_VBI_LN_EVEN,
179	DC_VBI_PITCH,
180	DC_CLR_KEY,
181	DC_CLR_KEY_MASK,
182
183	DC_CLR_KEY_X,
184	DC_CLR_KEY_Y,
185	DC_IRQ,
186	DC_RSVD_4,
187
188	DC_RSVD_5,
189	DC_GENLK_CTL,
190	DC_VID_EVEN_Y_ST_OFFSET,
191	DC_VID_EVEN_U_ST_OFFSET,
192
193	DC_VID_EVEN_V_ST_OFFSET,
194	DC_V_ACTIVE_EVEN_TIMING,
195	DC_V_BLANK_EVEN_TIMING,
196	DC_V_SYNC_EVEN_TIMING, /* 0xec */
197	};
198
199	#define DC_UNLOCK_LOCK 0x00000000
200	#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
201
202	#define DC_GENERAL_CFG_FDTY (1 << 17)
203	#define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
204	#define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
205	#define DC_GENERAL_CFG_VGAE (1 << 7)
206	#define DC_GENERAL_CFG_DECE (1 << 6)
207	#define DC_GENERAL_CFG_CMPE (1 << 5)
208	#define DC_GENERAL_CFG_VIDE (1 << 3)
209	#define DC_GENERAL_CFG_DFLE (1 << 0)
3968cb49	210
f5c90e85 AS	211	#define DC_DISPLAY_CFG_VISL (1 << 27)
	212	#define DC_DISPLAY_CFG_PALB (1 << 25)
	213	#define DC_DISPLAY_CFG_DCEN (1 << 24)
	214	#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
	215	#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
	216	#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
	217	#define DC_DISPLAY_CFG_TRUP (1 << 6)
	218	#define DC_DISPLAY_CFG_VDEN (1 << 4)
	219	#define DC_DISPLAY_CFG_GDEN (1 << 3)
	220	#define DC_DISPLAY_CFG_TGEN (1 << 0)
3968cb49	221
f5c90e85	222	#define DC_DV_TOP_DV_TOP_EN (1 << 0)
3968cb49	223
f5c90e85 AS	224	#define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) \| (1 << 11))
	225	#define DC_DV_CTL_DV_LINE_SIZE_1K (0)
	226	#define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
	227	#define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
	228	#define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) \| (1 << 11))
f694e53b AS	229	#define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
	230
	231	#define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
3968cb49	232
f5c90e85	233	#define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
3968cb49	234
f5c90e85 AS	235	#define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
	236	#define DC_IRQ_STATUS (1 << 20) /* undocumented? */
	237	#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
	238	#define DC_IRQ_MASK (1 << 0)
3968cb49	239
f5c90e85 AS	240	#define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
	241	#define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
	242	#define DC_GENLK_CTL_FLICK_EN (1 << 24)
	243	#define DC_GENLK_CTL_GENLK_EN (1 << 18)
3968cb49	244
3968cb49	245
f5c90e85 AS	246	/*
	247	* Video Processor registers (table 6-71).
	248	* There is space for 64 bit values, but we never use more than the
	249	* lower 32 bits. The actual register save/restore code only bothers
	250	* to restore those 32 bits.
	251	*/
	252	enum vp_registers {
	253	VP_VCFG = 0,
	254	VP_DCFG,
3968cb49	255
f5c90e85 AS	256	VP_VX,
f5c90e85 AS	257	VP_VY,
3968cb49	258
f5c90e85 AS	259	VP_SCL,
f5c90e85 AS	260	VP_VCK,
3968cb49	261
f5c90e85 AS	262	VP_VCM,
f5c90e85 AS	263	VP_PAR,
3968cb49	264
f5c90e85 AS	265	VP_PDR,
f5c90e85 AS	266	VP_SLR,
3968cb49	267
f5c90e85 AS	268	VP_MISC,
f5c90e85 AS	269	VP_CCS,
3968cb49	270
f5c90e85 AS	271	VP_VYS,
f5c90e85 AS	272	VP_VXS,
3968cb49	273
f5c90e85 AS	274	VP_RSVD_0,
f5c90e85 AS	275	VP_VDC,
3968cb49	276
f5c90e85 AS	277	VP_RSVD_1,
f5c90e85 AS	278	VP_CRC,
3968cb49	279
f5c90e85 AS	280	VP_CRC32,
f5c90e85 AS	281	VP_VDE,
3968cb49	282
f5c90e85 AS	283	VP_CCK,
f5c90e85 AS	284	VP_CCM,
3968cb49	285
f5c90e85 AS	286	VP_CC1,
f5c90e85 AS	287	VP_CC2,
3968cb49	288
f5c90e85 AS	289	VP_A1X,
f5c90e85 AS	290	VP_A1Y,
3968cb49	291
f5c90e85 AS	292	VP_A1C,
f5c90e85 AS	293	VP_A1T,
3968cb49	294
f5c90e85 AS	295	VP_A2X,
f5c90e85 AS	296	VP_A2Y,
3968cb49	297
f5c90e85 AS	298	VP_A2C,
f5c90e85 AS	299	VP_A2T,
3968cb49	300
f5c90e85 AS	301	VP_A3X,
f5c90e85 AS	302	VP_A3Y,
3968cb49	303
f5c90e85 AS	304	VP_A3C,
	305	VP_A3T,
	306
	307	VP_VRR,
	308	VP_AWT,
	309
	310	VP_VTM,
	311	VP_VYE,
	312
	313	VP_A1YE,
	314	VP_A2YE,
	315
	316	VP_A3YE, /* 0x150 */
f694e53b AS	317
f694e53b AS	318	VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
f5c90e85	319	};
3968cb49	320
f5c90e85	321	#define VP_VCFG_VID_EN (1 << 0)
3968cb49	322
f5c90e85 AS	323	#define VP_DCFG_GV_GAM (1 << 21)
	324	#define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) \| (1 << 18) \| (1 << 19))
	325	#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
	326	#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) \| (1 << 15) \| (1 << 16))
	327	#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
	328	#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
	329	#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
	330	#define VP_DCFG_DAC_BL_EN (1 << 3)
	331	#define VP_DCFG_VSYNC_EN (1 << 2)
	332	#define VP_DCFG_HSYNC_EN (1 << 1)
	333	#define VP_DCFG_CRT_EN (1 << 0)
3968cb49	334
f5c90e85 AS	335	#define VP_MISC_APWRDN (1 << 11)
	336	#define VP_MISC_DACPWRDN (1 << 10)
	337	#define VP_MISC_BYP_BOTH (1 << 0)
3968cb49	338
3968cb49	339
f5c90e85 AS	340	/*
	341	* Flat Panel registers (table 6-71).
	342	* Also 64 bit registers; see above note about 32-bit handling.
	343	*/
	344
	345	/* we're actually in the VP register space, starting at address 0x400 */
	346	#define VP_FP_START 0x400
	347
	348	enum fp_registers {
	349	FP_PT1 = 0,
	350	FP_PT2,
	351
	352	FP_PM,
	353	FP_DFC,
	354
	355	FP_RSVD_0,
	356	FP_RSVD_1,
	357
	358	FP_RSVD_2,
	359	FP_RSVD_3,
	360
	361	FP_RSVD_4,
	362	FP_DCA,
	363
	364	FP_DMD,
	365	FP_CRC, /* 0x458 */
	366	};
	367
	368	#define FP_PT2_SCRC (1 << 27) /* shfclk free */
3968cb49	369
f5c90e85	370	#define FP_PM_P (1 << 24) /* panel power ctl */
f694e53b AS	371	#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
	372	#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
	373	#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
	374	#define FP_PM_PANEL_ON (1 << 0) /* r/o */
3968cb49	375
f5c90e85	376	#define FP_DFC_BC ((1 << 4) \| (1 << 5) \| (1 << 6))
3968cb49	377
9286361b AS	378
	379	/* register access functions */
	380
	381	static inline uint32_t read_gp(struct lxfb_par *par, int reg)
	382	{
f5c90e85	383	return readl(par->gp_regs + 4*reg);
9286361b AS	384	}
	385
	386	static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
	387	{
f5c90e85	388	writel(val, par->gp_regs + 4*reg);
9286361b AS	389	}
	390
	391	static inline uint32_t read_dc(struct lxfb_par *par, int reg)
	392	{
f5c90e85	393	return readl(par->dc_regs + 4*reg);
9286361b AS	394	}
	395
	396	static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
	397	{
f5c90e85	398	writel(val, par->dc_regs + 4*reg);
9286361b AS	399	}
	400
	401	static inline uint32_t read_vp(struct lxfb_par *par, int reg)
	402	{
31f51fa8	403	return readl(par->vp_regs + 8*reg);
9286361b AS	404	}
	405
	406	static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
	407	{
31f51fa8	408	writel(val, par->vp_regs + 8*reg);
9286361b AS	409	}
	410
	411	static inline uint32_t read_fp(struct lxfb_par *par, int reg)
	412	{
31f51fa8	413	return readl(par->vp_regs + 8*reg + VP_FP_START);
9286361b AS	414	}
	415
	416	static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
	417	{
31f51fa8	418	writel(val, par->vp_regs + 8*reg + VP_FP_START);
9286361b AS	419	}
9286361b AS	420
aec40532	421
f3a57a60	422	/* MSRs are defined in linux/cs5535.h; their bitfields are here */
aec40532 AS	423
	424	#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
	425	#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
	426	#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
	427	#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
	428
	429	/* note: this is actually the VP's GLD_MSR_CONFIG */
	430	#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) \| (1 << 4) \| (1 << 5))
	431	#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
	432	#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
	433	#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP and CRT */
	434
	435	#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
	436	#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
	437
	438	#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
	439	#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
	440	#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
	441	#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
	442	#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
	443	#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
	444	#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
	445	#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
	446	#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
	447
3968cb49	448	#endif