[net-next-2.6.git] / drivers / video / geode / gxfb_core.c

/*
 * Geode GX framebuffer driver.
 *
 *   Copyright (C) 2006 Arcom Control Systems Ltd.
 *
 *   This program is free software; you can redistribute it and/or modify it
 *   under the terms of the GNU General Public License as published by the
 *   Free Software Foundation; either version 2 of the License, or (at your
 *   option) any later version.
 *
 *
 * This driver assumes that the BIOS has created a virtual PCI device header
 * for the video device. The PCI header is assumed to contain the following
 * BARs:
 *
 *    BAR0 - framebuffer memory
 *    BAR1 - graphics processor registers
 *    BAR2 - display controller registers
 *    BAR3 - video processor and flat panel control registers.
 *
 * 16 MiB of framebuffer memory is assumed to be available.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/console.h>
#include <linux/suspend.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/cs5535.h>

#include "gxfb.h"

static char *mode_option;
static int vram;
static int vt_switch;

/* Modes relevant to the GX (taken from modedb.c) */
static struct fb_videomode gx_modedb[] __initdata = {
	/* 640x480-60 VESA */
	{ NULL, 60, 640, 480, 39682,  48, 16, 33, 10, 96, 2,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 640x480-75 VESA */
	{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 640x480-85 VESA */
	{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 800x600-60 VESA */
	{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 800x600-75 VESA */
	{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 800x600-85 VESA */
	{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1024x768-60 VESA */
	{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
	  0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1024x768-75 VESA */
	{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1024x768-85 VESA */
	{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x960-60 VESA */
	{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x960-85 VESA */
	{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x1024-60 VESA */
	{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x1024-75 VESA */
	{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1280x1024-85 VESA */
	{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1600x1200-60 VESA */
	{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1600x1200-75 VESA */
	{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	/* 1600x1200-85 VESA */
	{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};

#ifdef CONFIG_OLPC
#include <asm/olpc.h>

static struct fb_videomode gx_dcon_modedb[] __initdata = {
	/* The only mode the DCON has is 1200x900 */
	{ NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	  FB_VMODE_NONINTERLACED, 0 }
};

static void __init get_modedb(struct fb_videomode **modedb, unsigned int *size)
{
	if (olpc_has_dcon()) {
		*modedb = (struct fb_videomode *) gx_dcon_modedb;
		*size = ARRAY_SIZE(gx_dcon_modedb);
	} else {
		*modedb = (struct fb_videomode *) gx_modedb;
		*size = ARRAY_SIZE(gx_modedb);
	}
}

#else
static void __init get_modedb(struct fb_videomode **modedb, unsigned int *size)
{
	*modedb = (struct fb_videomode *) gx_modedb;
	*size = ARRAY_SIZE(gx_modedb);
}
#endif

static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
	if (var->xres > 1600 || var->yres > 1200)
		return -EINVAL;
	if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
		return -EINVAL;

	if (var->bits_per_pixel == 32) {
		var->red.offset   = 16; var->red.length   = 8;
		var->green.offset =  8; var->green.length = 8;
		var->blue.offset  =  0; var->blue.length  = 8;
	} else if (var->bits_per_pixel == 16) {
		var->red.offset   = 11; var->red.length   = 5;
		var->green.offset =  5; var->green.length = 6;
		var->blue.offset  =  0; var->blue.length  = 5;
	} else if (var->bits_per_pixel == 8) {
		var->red.offset   = 0; var->red.length   = 8;
		var->green.offset = 0; var->green.length = 8;
		var->blue.offset  = 0; var->blue.length  = 8;
	} else
		return -EINVAL;
	var->transp.offset = 0; var->transp.length = 0;

	/* Enough video memory? */
	if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
		return -EINVAL;

	/* FIXME: Check timing parameters here? */

	return 0;
}

static int gxfb_set_par(struct fb_info *info)
{
	if (info->var.bits_per_pixel > 8)
		info->fix.visual = FB_VISUAL_TRUECOLOR;
	else
		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

	info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);

	gx_set_mode(info);

	return 0;
}

static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
	chan &= 0xffff;
	chan >>= 16 - bf->length;
	return chan << bf->offset;
}

static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
			   unsigned blue, unsigned transp,
			   struct fb_info *info)
{
	if (info->var.grayscale) {
		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
	}

	/* Truecolor has hardware independent palette */
	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
		u32 *pal = info->pseudo_palette;
		u32 v;

		if (regno >= 16)
			return -EINVAL;

		v  = chan_to_field(red, &info->var.red);
		v |= chan_to_field(green, &info->var.green);
		v |= chan_to_field(blue, &info->var.blue);

		pal[regno] = v;
	} else {
		if (regno >= 256)
			return -EINVAL;

		gx_set_hw_palette_reg(info, regno, red, green, blue);
	}

	return 0;
}

static int gxfb_blank(int blank_mode, struct fb_info *info)
{
	return gx_blank_display(info, blank_mode);
}

static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
	struct gxfb_par *par = info->par;
	int ret;

	ret = pci_enable_device(dev);
	if (ret < 0)
		return ret;

	ret = pci_request_region(dev, 3, "gxfb (video processor)");
	if (ret < 0)
		return ret;
	par->vid_regs = pci_ioremap_bar(dev, 3);
	if (!par->vid_regs)
		return -ENOMEM;

	ret = pci_request_region(dev, 2, "gxfb (display controller)");
	if (ret < 0)
		return ret;
	par->dc_regs = pci_ioremap_bar(dev, 2);
	if (!par->dc_regs)
		return -ENOMEM;

	ret = pci_request_region(dev, 1, "gxfb (graphics processor)");
	if (ret < 0)
		return ret;
	par->gp_regs = pci_ioremap_bar(dev, 1);

	if (!par->gp_regs)
		return -ENOMEM;

	ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
	if (ret < 0)
		return ret;

	info->fix.smem_start = pci_resource_start(dev, 0);
	info->fix.smem_len = vram ? vram : gx_frame_buffer_size();
	info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
	if (!info->screen_base)
		return -ENOMEM;

	/* Set the 16MiB aligned base address of the graphics memory region
	 * in the display controller */

	write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);

	dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
		 info->fix.smem_len / 1024, info->fix.smem_start);

	return 0;
}

static struct fb_ops gxfb_ops = {
	.owner		= THIS_MODULE,
	.fb_check_var	= gxfb_check_var,
	.fb_set_par	= gxfb_set_par,
	.fb_setcolreg	= gxfb_setcolreg,
	.fb_blank       = gxfb_blank,
	/* No HW acceleration for now. */
	.fb_fillrect	= cfb_fillrect,
	.fb_copyarea	= cfb_copyarea,
	.fb_imageblit	= cfb_imageblit,
};

static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
{
	struct gxfb_par *par;
	struct fb_info *info;

	/* Alloc enough space for the pseudo palette. */
	info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16,
			dev);
	if (!info)
		return NULL;

	par = info->par;

	strcpy(info->fix.id, "Geode GX");

	info->fix.type		= FB_TYPE_PACKED_PIXELS;
	info->fix.type_aux	= 0;
	info->fix.xpanstep	= 0;
	info->fix.ypanstep	= 0;
	info->fix.ywrapstep	= 0;
	info->fix.accel		= FB_ACCEL_NONE;

	info->var.nonstd	= 0;
	info->var.activate	= FB_ACTIVATE_NOW;
	info->var.height	= -1;
	info->var.width	= -1;
	info->var.accel_flags = 0;
	info->var.vmode	= FB_VMODE_NONINTERLACED;

	info->fbops		= &gxfb_ops;
	info->flags		= FBINFO_DEFAULT;
	info->node		= -1;

	info->pseudo_palette	= (void *)par + sizeof(struct gxfb_par);

	info->var.grayscale	= 0;

	if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
		framebuffer_release(info);
		return NULL;
	}

	return info;
}

#ifdef CONFIG_PM
static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct fb_info *info = pci_get_drvdata(pdev);

	if (state.event == PM_EVENT_SUSPEND) {
		acquire_console_sem();
		gx_powerdown(info);
		fb_set_suspend(info, 1);
		release_console_sem();
	}

	/* there's no point in setting PCI states; we emulate PCI, so
	 * we don't end up getting power savings anyways */

	return 0;
}

static int gxfb_resume(struct pci_dev *pdev)
{
	struct fb_info *info = pci_get_drvdata(pdev);
	int ret;

	acquire_console_sem();
	ret = gx_powerup(info);
	if (ret) {
		printk(KERN_ERR "gxfb:  power up failed!\n");
		return ret;
	}

	fb_set_suspend(info, 0);
	release_console_sem();
	return 0;
}
#endif

static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	struct gxfb_par *par;
	struct fb_info *info;
	int ret;
	unsigned long val;

	struct fb_videomode *modedb_ptr;
	unsigned int modedb_size;

	info = gxfb_init_fbinfo(&pdev->dev);
	if (!info)
		return -ENOMEM;
	par = info->par;

	if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
		dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
		goto err;
	}

	/* Figure out if this is a TFT or CRT part */

	rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);

	if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
		par->enable_crt = 0;
	else
		par->enable_crt = 1;

	get_modedb(&modedb_ptr, &modedb_size);
	ret = fb_find_mode(&info->var, info, mode_option,
			   modedb_ptr, modedb_size, NULL, 16);
	if (ret == 0 || ret == 4) {
		dev_err(&pdev->dev, "could not find valid video mode\n");
		ret = -EINVAL;
		goto err;
	}


	/* Clear the frame buffer of garbage. */
        memset_io(info->screen_base, 0, info->fix.smem_len);

	gxfb_check_var(&info->var, info);
	gxfb_set_par(info);

	pm_set_vt_switch(vt_switch);

	if (register_framebuffer(info) < 0) {
		ret = -EINVAL;
		goto err;
	}
	pci_set_drvdata(pdev, info);
	printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
	return 0;

  err:
	if (info->screen_base) {
		iounmap(info->screen_base);
		pci_release_region(pdev, 0);
	}
	if (par->vid_regs) {
		iounmap(par->vid_regs);
		pci_release_region(pdev, 3);
	}
	if (par->dc_regs) {
		iounmap(par->dc_regs);
		pci_release_region(pdev, 2);
	}
	if (par->gp_regs) {
		iounmap(par->gp_regs);
		pci_release_region(pdev, 1);
	}

	if (info) {
		fb_dealloc_cmap(&info->cmap);
		framebuffer_release(info);
	}
	return ret;
}

static void gxfb_remove(struct pci_dev *pdev)
{
	struct fb_info *info = pci_get_drvdata(pdev);
	struct gxfb_par *par = info->par;

	unregister_framebuffer(info);

	iounmap((void __iomem *)info->screen_base);
	pci_release_region(pdev, 0);

	iounmap(par->vid_regs);
	pci_release_region(pdev, 3);

	iounmap(par->dc_regs);
	pci_release_region(pdev, 2);

	iounmap(par->gp_regs);
	pci_release_region(pdev, 1);

	fb_dealloc_cmap(&info->cmap);
	pci_set_drvdata(pdev, NULL);

	framebuffer_release(info);
}

static struct pci_device_id gxfb_id_table[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
	{ 0, }
};

MODULE_DEVICE_TABLE(pci, gxfb_id_table);

static struct pci_driver gxfb_driver = {
	.name		= "gxfb",
	.id_table	= gxfb_id_table,
	.probe		= gxfb_probe,
	.remove		= gxfb_remove,
#ifdef CONFIG_PM
	.suspend	= gxfb_suspend,
	.resume		= gxfb_resume,
#endif
};

#ifndef MODULE
static int __init gxfb_setup(char *options)
{

	char *opt;

	if (!options || !*options)
		return 0;

	while ((opt = strsep(&options, ",")) != NULL) {
		if (!*opt)
			continue;

		mode_option = opt;
	}

	return 0;
}
#endif

static int __init gxfb_init(void)
{
#ifndef MODULE
	char *option = NULL;

	if (fb_get_options("gxfb", &option))
		return -ENODEV;

	gxfb_setup(option);
#endif
	return pci_register_driver(&gxfb_driver);
}

static void __exit gxfb_cleanup(void)
{
	pci_unregister_driver(&gxfb_driver);
}

module_init(gxfb_init);
module_exit(gxfb_cleanup);

module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");

module_param(vram, int, 0);
MODULE_PARM_DESC(vram, "video memory size");

module_param(vt_switch, int, 0);
MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");

MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
MODULE_LICENSE("GPL");
Commit	Line	Data
fc4effc7 DV	1	/*
	2	* Geode GX framebuffer driver.
	3	*
	4	* Copyright (C) 2006 Arcom Control Systems Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	*
	12	* This driver assumes that the BIOS has created a virtual PCI device header
	13	* for the video device. The PCI header is assumed to contain the following
	14	* BARs:
	15	*
	16	* BAR0 - framebuffer memory
	17	* BAR1 - graphics processor registers
	18	* BAR2 - display controller registers
	19	* BAR3 - video processor and flat panel control registers.
	20	*
	21	* 16 MiB of framebuffer memory is assumed to be available.
	22	*/
	23	#include <linux/module.h>
	24	#include <linux/kernel.h>
	25	#include <linux/errno.h>
	26	#include <linux/string.h>
	27	#include <linux/mm.h>
fc4effc7 DV	28	#include <linux/slab.h>
	29	#include <linux/delay.h>
	30	#include <linux/fb.h>
46fb6f11	31	#include <linux/console.h>
b6f448e9	32	#include <linux/suspend.h>
fc4effc7 DV	33	#include <linux/init.h>
fc4effc7 DV	34	#include <linux/pci.h>
f3a57a60	35	#include <linux/cs5535.h>
fc4effc7	36
ab06aaf6	37	#include "gxfb.h"
fc4effc7	38
16ef9870	39	static char *mode_option;
fa20c8a6	40	static int vram;
b6f448e9	41	static int vt_switch;
fc4effc7 DV	42
fc4effc7 DV	43	/* Modes relevant to the GX (taken from modedb.c) */
3553a2fa	44	static struct fb_videomode gx_modedb[] __initdata = {
fc4effc7 DV	45	/* 640x480-60 VESA */
	46	{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
	47	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	48	/* 640x480-75 VESA */
	49	{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
	50	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	51	/* 640x480-85 VESA */
	52	{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
	53	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	54	/* 800x600-60 VESA */
	55	{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
	56	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	57	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	58	/* 800x600-75 VESA */
	59	{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
	60	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	61	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	62	/* 800x600-85 VESA */
	63	{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
	64	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	65	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	66	/* 1024x768-60 VESA */
	67	{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
	68	0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	69	/* 1024x768-75 VESA */
	70	{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
	71	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	72	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	73	/* 1024x768-85 VESA */
	74	{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
	75	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	76	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	77	/* 1280x960-60 VESA */
	78	{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
	79	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	80	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	81	/* 1280x960-85 VESA */
	82	{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
	83	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	84	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	85	/* 1280x1024-60 VESA */
	86	{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
	87	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	88	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	89	/* 1280x1024-75 VESA */
	90	{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
	91	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	92	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	93	/* 1280x1024-85 VESA */
	94	{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
	95	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	96	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	97	/* 1600x1200-60 VESA */
	98	{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
	99	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	100	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	101	/* 1600x1200-75 VESA */
	102	{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
	103	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	104	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
	105	/* 1600x1200-85 VESA */
	106	{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
	107	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	108	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
109	};
110
3553a2fa AS	111	#ifdef CONFIG_OLPC
	112	#include <asm/olpc.h>
	113
	114	static struct fb_videomode gx_dcon_modedb[] __initdata = {
	115	/* The only mode the DCON has is 1200x900 */
	116	{ NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
	117	FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	118	FB_VMODE_NONINTERLACED, 0 }
	119	};
	120
	121	static void __init get_modedb(struct fb_videomode *modedb, unsigned int size)
	122	{
	123	if (olpc_has_dcon()) {
	124	modedb = (struct fb_videomode ) gx_dcon_modedb;
	125	*size = ARRAY_SIZE(gx_dcon_modedb);
	126	} else {
	127	modedb = (struct fb_videomode ) gx_modedb;
	128	*size = ARRAY_SIZE(gx_modedb);
	129	}
	130	}
	131
	132	#else
	133	static void __init get_modedb(struct fb_videomode *modedb, unsigned int size)
	134	{
	135	modedb = (struct fb_videomode ) gx_modedb;
	136	*size = ARRAY_SIZE(gx_modedb);
	137	}
	138	#endif
	139
fc4effc7 DV	140	static int gxfb_check_var(struct fb_var_screeninfo var, struct fb_info info)
	141	{
	142	if (var->xres > 1600 \|\| var->yres > 1200)
	143	return -EINVAL;
	144	if ((var->xres > 1280 \|\| var->yres > 1024) && var->bits_per_pixel > 16)
	145	return -EINVAL;
	146
	147	if (var->bits_per_pixel == 32) {
	148	var->red.offset = 16; var->red.length = 8;
	149	var->green.offset = 8; var->green.length = 8;
	150	var->blue.offset = 0; var->blue.length = 8;
	151	} else if (var->bits_per_pixel == 16) {
	152	var->red.offset = 11; var->red.length = 5;
	153	var->green.offset = 5; var->green.length = 6;
	154	var->blue.offset = 0; var->blue.length = 5;
	155	} else if (var->bits_per_pixel == 8) {
	156	var->red.offset = 0; var->red.length = 8;
	157	var->green.offset = 0; var->green.length = 8;
	158	var->blue.offset = 0; var->blue.length = 8;
	159	} else
	160	return -EINVAL;
	161	var->transp.offset = 0; var->transp.length = 0;
	162
	163	/* Enough video memory? */
	164	if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
	165	return -EINVAL;
	166
	167	/* FIXME: Check timing parameters here? */
	168
	169	return 0;
	170	}
	171
	172	static int gxfb_set_par(struct fb_info *info)
	173	{
b14caecd	174	if (info->var.bits_per_pixel > 8)
fc4effc7	175	info->fix.visual = FB_VISUAL_TRUECOLOR;
b14caecd	176	else
fc4effc7	177	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
fc4effc7 DV	178
	179	info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
	180
d1b4cc3e	181	gx_set_mode(info);
fc4effc7 DV	182
	183	return 0;
	184	}
	185
	186	static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
	187	{
	188	chan &= 0xffff;
	189	chan >>= 16 - bf->length;
	190	return chan << bf->offset;
	191	}
	192
	193	static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
	194	unsigned blue, unsigned transp,
	195	struct fb_info *info)
	196	{
fc4effc7 DV	197	if (info->var.grayscale) {
	198	/* grayscale = 0.30R + 0.59G + 0.11B /
	199	red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
	200	}
	201
	202	/* Truecolor has hardware independent palette */
	203	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
	204	u32 *pal = info->pseudo_palette;
	205	u32 v;
	206
	207	if (regno >= 16)
	208	return -EINVAL;
	209
	210	v = chan_to_field(red, &info->var.red);
	211	v \|= chan_to_field(green, &info->var.green);
	212	v \|= chan_to_field(blue, &info->var.blue);
	213
	214	pal[regno] = v;
	215	} else {
	216	if (regno >= 256)
	217	return -EINVAL;
	218
d1b4cc3e	219	gx_set_hw_palette_reg(info, regno, red, green, blue);
fc4effc7 DV	220	}
	221
	222	return 0;
	223	}
	224
	225	static int gxfb_blank(int blank_mode, struct fb_info *info)
	226	{
d1b4cc3e	227	return gx_blank_display(info, blank_mode);
fc4effc7 DV	228	}
	229
	230	static int __init gxfb_map_video_memory(struct fb_info info, struct pci_dev dev)
	231	{
d1b4cc3e	232	struct gxfb_par *par = info->par;
fc4effc7 DV	233	int ret;
	234
	235	ret = pci_enable_device(dev);
	236	if (ret < 0)
	237	return ret;
	238
	239	ret = pci_request_region(dev, 3, "gxfb (video processor)");
	240	if (ret < 0)
	241	return ret;
3c36aa5c	242	par->vid_regs = pci_ioremap_bar(dev, 3);
fc4effc7 DV	243	if (!par->vid_regs)
	244	return -ENOMEM;
	245
	246	ret = pci_request_region(dev, 2, "gxfb (display controller)");
	247	if (ret < 0)
	248	return ret;
3c36aa5c	249	par->dc_regs = pci_ioremap_bar(dev, 2);
fc4effc7 DV	250	if (!par->dc_regs)
	251	return -ENOMEM;
	252
46fb6f11 AS	253	ret = pci_request_region(dev, 1, "gxfb (graphics processor)");
	254	if (ret < 0)
	255	return ret;
3c36aa5c	256	par->gp_regs = pci_ioremap_bar(dev, 1);
46fb6f11 AS	257
	258	if (!par->gp_regs)
	259	return -ENOMEM;
	260
fc4effc7 DV	261	ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
	262	if (ret < 0)
	263	return ret;
fa20c8a6	264
fc4effc7	265	info->fix.smem_start = pci_resource_start(dev, 0);
fa20c8a6	266	info->fix.smem_len = vram ? vram : gx_frame_buffer_size();
fc4effc7 DV	267	info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
	268	if (!info->screen_base)
	269	return -ENOMEM;
	270
fa20c8a6	271	/* Set the 16MiB aligned base address of the graphics memory region
f378819a JC	272	* in the display controller */
f378819a JC	273
ab06aaf6	274	write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
f378819a	275
fa20c8a6	276	dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
fc4effc7 DV	277	info->fix.smem_len / 1024, info->fix.smem_start);
	278
	279	return 0;
	280	}
	281
	282	static struct fb_ops gxfb_ops = {
	283	.owner = THIS_MODULE,
	284	.fb_check_var = gxfb_check_var,
	285	.fb_set_par = gxfb_set_par,
	286	.fb_setcolreg = gxfb_setcolreg,
	287	.fb_blank = gxfb_blank,
	288	/* No HW acceleration for now. */
	289	.fb_fillrect = cfb_fillrect,
	290	.fb_copyarea = cfb_copyarea,
	291	.fb_imageblit = cfb_imageblit,
	292	};
	293
	294	static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
	295	{
d1b4cc3e	296	struct gxfb_par *par;
fc4effc7 DV	297	struct fb_info *info;
	298
	299	/* Alloc enough space for the pseudo palette. */
d1b4cc3e AS	300	info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16,
d1b4cc3e AS	301	dev);
fc4effc7 DV	302	if (!info)
	303	return NULL;
	304
	305	par = info->par;
	306
	307	strcpy(info->fix.id, "Geode GX");
	308
	309	info->fix.type = FB_TYPE_PACKED_PIXELS;
	310	info->fix.type_aux = 0;
	311	info->fix.xpanstep = 0;
	312	info->fix.ypanstep = 0;
	313	info->fix.ywrapstep = 0;
	314	info->fix.accel = FB_ACCEL_NONE;
	315
	316	info->var.nonstd = 0;
	317	info->var.activate = FB_ACTIVATE_NOW;
	318	info->var.height = -1;
	319	info->var.width = -1;
	320	info->var.accel_flags = 0;
	321	info->var.vmode = FB_VMODE_NONINTERLACED;
	322
	323	info->fbops = &gxfb_ops;
	324	info->flags = FBINFO_DEFAULT;
	325	info->node = -1;
	326
d1b4cc3e	327	info->pseudo_palette = (void *)par + sizeof(struct gxfb_par);
fc4effc7 DV	328
	329	info->var.grayscale = 0;
	330
b14caecd AS	331	if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
	332	framebuffer_release(info);
	333	return NULL;
	334	}
	335
fc4effc7 DV	336	return info;
	337	}
	338
46fb6f11 AS	339	#ifdef CONFIG_PM
	340	static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state)
	341	{
	342	struct fb_info *info = pci_get_drvdata(pdev);
	343
	344	if (state.event == PM_EVENT_SUSPEND) {
	345	acquire_console_sem();
	346	gx_powerdown(info);
	347	fb_set_suspend(info, 1);
	348	release_console_sem();
	349	}
	350
	351	/* there's no point in setting PCI states; we emulate PCI, so
	352	* we don't end up getting power savings anyways */
	353
	354	return 0;
	355	}
	356
	357	static int gxfb_resume(struct pci_dev *pdev)
	358	{
	359	struct fb_info *info = pci_get_drvdata(pdev);
	360	int ret;
	361
	362	acquire_console_sem();
	363	ret = gx_powerup(info);
	364	if (ret) {
	365	printk(KERN_ERR "gxfb: power up failed!\n");
	366	return ret;
	367	}
	368
	369	fb_set_suspend(info, 0);
	370	release_console_sem();
	371	return 0;
	372	}
	373	#endif
	374
fc4effc7 DV	375	static int __init gxfb_probe(struct pci_dev pdev, const struct pci_device_id id)
fc4effc7 DV	376	{
d1b4cc3e	377	struct gxfb_par *par;
fc4effc7 DV	378	struct fb_info *info;
fc4effc7 DV	379	int ret;
ab1db0cf	380	unsigned long val;
fc4effc7	381
3553a2fa AS	382	struct fb_videomode *modedb_ptr;
	383	unsigned int modedb_size;
	384
fc4effc7 DV	385	info = gxfb_init_fbinfo(&pdev->dev);
	386	if (!info)
	387	return -ENOMEM;
	388	par = info->par;
	389
fc4effc7 DV	390	if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
	391	dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
	392	goto err;
	393	}
	394
ab1db0cf JC	395	/* Figure out if this is a TFT or CRT part */
ab1db0cf JC	396
32bf87e3	397	rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);
ab1db0cf	398
9f1277bd	399	if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
ab1db0cf JC	400	par->enable_crt = 0;
	401	else
	402	par->enable_crt = 1;
	403
3553a2fa	404	get_modedb(&modedb_ptr, &modedb_size);
fc4effc7	405	ret = fb_find_mode(&info->var, info, mode_option,
3553a2fa	406	modedb_ptr, modedb_size, NULL, 16);
fc4effc7 DV	407	if (ret == 0 \|\| ret == 4) {
	408	dev_err(&pdev->dev, "could not find valid video mode\n");
	409	ret = -EINVAL;
	410	goto err;
	411	}
	412
16ef9870 JC	413
16ef9870 JC	414	/* Clear the frame buffer of garbage. */
fc4effc7 DV	415	memset_io(info->screen_base, 0, info->fix.smem_len);
	416
	417	gxfb_check_var(&info->var, info);
	418	gxfb_set_par(info);
	419
b6f448e9 AS	420	pm_set_vt_switch(vt_switch);
b6f448e9 AS	421
fc4effc7 DV	422	if (register_framebuffer(info) < 0) {
	423	ret = -EINVAL;
	424	goto err;
	425	}
	426	pci_set_drvdata(pdev, info);
	427	printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
	428	return 0;
	429
	430	err:
	431	if (info->screen_base) {
	432	iounmap(info->screen_base);
	433	pci_release_region(pdev, 0);
	434	}
	435	if (par->vid_regs) {
	436	iounmap(par->vid_regs);
	437	pci_release_region(pdev, 3);
	438	}
	439	if (par->dc_regs) {
	440	iounmap(par->dc_regs);
	441	pci_release_region(pdev, 2);
	442	}
46fb6f11 AS	443	if (par->gp_regs) {
	444	iounmap(par->gp_regs);
	445	pci_release_region(pdev, 1);
	446	}
fc4effc7	447
b14caecd AS	448	if (info) {
b14caecd AS	449	fb_dealloc_cmap(&info->cmap);
fc4effc7	450	framebuffer_release(info);
b14caecd	451	}
fc4effc7 DV	452	return ret;
	453	}
	454
	455	static void gxfb_remove(struct pci_dev *pdev)
	456	{
	457	struct fb_info *info = pci_get_drvdata(pdev);
d1b4cc3e	458	struct gxfb_par *par = info->par;
fc4effc7 DV	459
	460	unregister_framebuffer(info);
	461
	462	iounmap((void __iomem *)info->screen_base);
	463	pci_release_region(pdev, 0);
	464
	465	iounmap(par->vid_regs);
	466	pci_release_region(pdev, 3);
	467
	468	iounmap(par->dc_regs);
	469	pci_release_region(pdev, 2);
	470
46fb6f11 AS	471	iounmap(par->gp_regs);
	472	pci_release_region(pdev, 1);
	473
b14caecd	474	fb_dealloc_cmap(&info->cmap);
fc4effc7 DV	475	pci_set_drvdata(pdev, NULL);
	476
	477	framebuffer_release(info);
	478	}
	479
	480	static struct pci_device_id gxfb_id_table[] = {
0a5e7909	481	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
fc4effc7 DV	482	{ 0, }
	483	};
	484
	485	MODULE_DEVICE_TABLE(pci, gxfb_id_table);
	486
	487	static struct pci_driver gxfb_driver = {
	488	.name = "gxfb",
	489	.id_table = gxfb_id_table,
	490	.probe = gxfb_probe,
	491	.remove = gxfb_remove,
46fb6f11 AS	492	#ifdef CONFIG_PM
	493	.suspend = gxfb_suspend,
	494	.resume = gxfb_resume,
	495	#endif
fc4effc7 DV	496	};
fc4effc7 DV	497
16ef9870 JC	498	#ifndef MODULE
	499	static int __init gxfb_setup(char *options)
	500	{
	501
	502	char *opt;
	503
	504	if (!options \|\| !*options)
	505	return 0;
	506
	507	while ((opt = strsep(&options, ",")) != NULL) {
	508	if (!*opt)
	509	continue;
	510
	511	mode_option = opt;
	512	}
	513
	514	return 0;
	515	}
	516	#endif
	517
fc4effc7 DV	518	static int __init gxfb_init(void)
	519	{
	520	#ifndef MODULE
16ef9870 JC	521	char *option = NULL;
	522
	523	if (fb_get_options("gxfb", &option))
fc4effc7	524	return -ENODEV;
16ef9870 JC	525
16ef9870 JC	526	gxfb_setup(option);
fc4effc7 DV	527	#endif
	528	return pci_register_driver(&gxfb_driver);
	529	}
	530
	531	static void __exit gxfb_cleanup(void)
	532	{
	533	pci_unregister_driver(&gxfb_driver);
	534	}
	535
	536	module_init(gxfb_init);
	537	module_exit(gxfb_cleanup);
	538
16ef9870 JC	539	module_param(mode_option, charp, 0);
16ef9870 JC	540	MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
fc4effc7	541
fa20c8a6 AS	542	module_param(vram, int, 0);
	543	MODULE_PARM_DESC(vram, "video memory size");
	544
b6f448e9 AS	545	module_param(vt_switch, int, 0);
	546	MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
	547
fc4effc7 DV	548	MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
fc4effc7 DV	549	MODULE_LICENSE("GPL");