[net-next-2.6.git] / drivers / usb / musb / omap2430.c

/*
 * Copyright (C) 2005-2007 by Texas Instruments
 * Some code has been taken from tusb6010.c
 * Copyrights for that are attributable to:
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/mux.h>

#include "musb_core.h"
#include "omap2430.h"

#ifdef CONFIG_ARCH_OMAP3430
#define	get_cpu_rev()	2
#endif

#define MUSB_TIMEOUT_A_WAIT_BCON	1100

static struct timer_list musb_idle_timer;

static void musb_do_idle(unsigned long _musb)
{
	struct musb	*musb = (void *)_musb;
	unsigned long	flags;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	u8	power;
#endif
	u8	devctl;

	spin_lock_irqsave(&musb->lock, flags);

	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE) {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		}
		break;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	case OTG_STATE_A_SUSPEND:
		/* finish RESUME signaling? */
		if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
			power = musb_readb(musb->mregs, MUSB_POWER);
			power &= ~MUSB_POWER_RESUME;
			DBG(1, "root port resume stopped, power %02x\n", power);
			musb_writeb(musb->mregs, MUSB_POWER, power);
			musb->is_active = 1;
			musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
						| MUSB_PORT_STAT_RESUME);
			musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
			usb_hcd_poll_rh_status(musb_to_hcd(musb));
			/* NOTE: it might really be A_WAIT_BCON ... */
			musb->xceiv->state = OTG_STATE_A_HOST;
		}
		break;
#endif
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	case OTG_STATE_A_HOST:
		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl &  MUSB_DEVCTL_BDEVICE)
			musb->xceiv->state = OTG_STATE_B_IDLE;
		else
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
#endif
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}


void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
{
	unsigned long		default_timeout = jiffies + msecs_to_jiffies(3);
	static unsigned long	last_timer;

	if (timeout == 0)
		timeout = default_timeout;

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || ((musb->a_wait_bcon == 0)
			&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
		DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
		del_timer(&musb_idle_timer);
		last_timer = jiffies;
		return;
	}

	if (time_after(last_timer, timeout)) {
		if (!timer_pending(&musb_idle_timer))
			last_timer = timeout;
		else {
			DBG(4, "Longer idle timer already pending, ignoring\n");
			return;
		}
	}
	last_timer = timeout;

	DBG(4, "%s inactive, for idle timer for %lu ms\n",
		otg_state_string(musb),
		(unsigned long)jiffies_to_msecs(timeout - jiffies));
	mod_timer(&musb_idle_timer, timeout);
}

void musb_platform_enable(struct musb *musb)
{
}
void musb_platform_disable(struct musb *musb)
{
}
static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
{
}

static void omap_set_vbus(struct musb *musb, int is_on)
{
	u8		devctl;
	/* HDRC controls CPEN, but beware current surges during device
	 * connect.  They can trigger transient overcurrent conditions
	 * that must be ignored.
	 */

	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	if (is_on) {
		musb->is_active = 1;
		musb->xceiv->default_a = 1;
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		devctl |= MUSB_DEVCTL_SESSION;

		MUSB_HST_MODE(musb);
	} else {
		musb->is_active = 0;

		/* NOTE:  we're skipping A_WAIT_VFALL -> A_IDLE and
		 * jumping right to B_IDLE...
		 */

		musb->xceiv->default_a = 0;
		musb->xceiv->state = OTG_STATE_B_IDLE;
		devctl &= ~MUSB_DEVCTL_SESSION;

		MUSB_DEV_MODE(musb);
	}
	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

	DBG(1, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int musb_platform_resume(struct musb *musb);

int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
{
	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	devctl |= MUSB_DEVCTL_SESSION;
	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

	return 0;
}

int __init musb_platform_init(struct musb *musb)
{
	u32 l;

#if defined(CONFIG_ARCH_OMAP2430)
	omap_cfg_reg(AE5_2430_USB0HS_STP);
#endif

	/* We require some kind of external transceiver, hooked
	 * up through ULPI.  TWL4030-family PMICs include one,
	 * which needs a driver, drivers aren't always needed.
	 */
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv) {
		pr_err("HS USB OTG: no transceiver configured\n");
		return -ENODEV;
	}

	musb_platform_resume(musb);

	l = omap_readl(OTG_SYSCONFIG);
	l &= ~ENABLEWAKEUP;	/* disable wakeup */
	l &= ~NOSTDBY;		/* remove possible nostdby */
	l |= SMARTSTDBY;	/* enable smart standby */
	l &= ~AUTOIDLE;		/* disable auto idle */
	l &= ~NOIDLE;		/* remove possible noidle */
	l |= SMARTIDLE;		/* enable smart idle */
	l |= AUTOIDLE;		/* enable auto idle */
	omap_writel(l, OTG_SYSCONFIG);

	l = omap_readl(OTG_INTERFSEL);
	l |= ULPI_12PIN;
	omap_writel(l, OTG_INTERFSEL);

	pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
			"sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
			omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
			omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
			omap_readl(OTG_SIMENABLE));

	omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);

	if (is_host_enabled(musb))
		musb->board_set_vbus = omap_set_vbus;
	musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;

	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);

	return 0;
}

int musb_platform_suspend(struct musb *musb)
{
	u32 l;

	if (!musb->clock)
		return 0;

	/* in any role */
	l = omap_readl(OTG_FORCESTDBY);
	l |= ENABLEFORCE;	/* enable MSTANDBY */
	omap_writel(l, OTG_FORCESTDBY);

	l = omap_readl(OTG_SYSCONFIG);
	l |= ENABLEWAKEUP;	/* enable wakeup */
	omap_writel(l, OTG_SYSCONFIG);

	otg_set_suspend(musb->xceiv, 1);

	if (musb->set_clock)
		musb->set_clock(musb->clock, 0);
	else
		clk_disable(musb->clock);

	return 0;
}

static int musb_platform_resume(struct musb *musb)
{
	u32 l;

	if (!musb->clock)
		return 0;

	otg_set_suspend(musb->xceiv, 0);

	if (musb->set_clock)
		musb->set_clock(musb->clock, 1);
	else
		clk_enable(musb->clock);

	l = omap_readl(OTG_SYSCONFIG);
	l &= ~ENABLEWAKEUP;	/* disable wakeup */
	omap_writel(l, OTG_SYSCONFIG);

	l = omap_readl(OTG_FORCESTDBY);
	l &= ~ENABLEFORCE;	/* disable MSTANDBY */
	omap_writel(l, OTG_FORCESTDBY);

	return 0;
}


int musb_platform_exit(struct musb *musb)
{

	omap_vbus_power(musb, 0 /*off*/, 1);

	musb_platform_suspend(musb);

	clk_put(musb->clock);
	musb->clock = 0;

	return 0;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* Copyright (C) 2005-2007 by Texas Instruments
	3	* Some code has been taken from tusb6010.c
	4	* Copyrights for that are attributable to:
	5	* Copyright (C) 2006 Nokia Corporation
550a7375 FB	6	* Tony Lindgren <tony@atomide.com>
	7	*
	8	* This file is part of the Inventra Controller Driver for Linux.
	9	*
	10	* The Inventra Controller Driver for Linux is free software; you
	11	* can redistribute it and/or modify it under the terms of the GNU
	12	* General Public License version 2 as published by the Free Software
	13	* Foundation.
	14	*
	15	* The Inventra Controller Driver for Linux is distributed in
	16	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	17	* without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	19	* License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with The Inventra Controller Driver for Linux ; if not,
	23	* write to the Free Software Foundation, Inc., 59 Temple Place,
	24	* Suite 330, Boston, MA 02111-1307 USA
	25	*
	26	*/
	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/sched.h>
	30	#include <linux/slab.h>
	31	#include <linux/init.h>
	32	#include <linux/list.h>
	33	#include <linux/clk.h>
	34	#include <linux/io.h>
	35
	36	#include <asm/mach-types.h>
0590d587 FB	37	#include <mach/hardware.h>
0590d587 FB	38	#include <mach/mux.h>
550a7375 FB	39
	40	#include "musb_core.h"
	41	#include "omap2430.h"
	42
	43	#ifdef CONFIG_ARCH_OMAP3430
	44	#define get_cpu_rev() 2
	45	#endif
	46
	47	#define MUSB_TIMEOUT_A_WAIT_BCON 1100
	48
	49	static struct timer_list musb_idle_timer;
	50
	51	static void musb_do_idle(unsigned long _musb)
	52	{
	53	struct musb musb = (void )_musb;
	54	unsigned long flags;
eef767b7	55	#ifdef CONFIG_USB_MUSB_HDRC_HCD
550a7375	56	u8 power;
eef767b7	57	#endif
550a7375 FB	58	u8 devctl;
550a7375 FB	59
550a7375 FB	60	spin_lock_irqsave(&musb->lock, flags);
550a7375 FB	61
71783e0d DB	62	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
71783e0d DB	63
84e250ff	64	switch (musb->xceiv->state) {
550a7375 FB	65	case OTG_STATE_A_WAIT_BCON:
	66	devctl &= ~MUSB_DEVCTL_SESSION;
	67	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	68
	69	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	70	if (devctl & MUSB_DEVCTL_BDEVICE) {
84e250ff	71	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	72	MUSB_DEV_MODE(musb);
550a7375 FB	73	} else {
84e250ff	74	musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 FB	75	MUSB_HST_MODE(musb);
	76	}
	77	break;
	78	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	79	case OTG_STATE_A_SUSPEND:
	80	/* finish RESUME signaling? */
	81	if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
	82	power = musb_readb(musb->mregs, MUSB_POWER);
	83	power &= ~MUSB_POWER_RESUME;
	84	DBG(1, "root port resume stopped, power %02x\n", power);
	85	musb_writeb(musb->mregs, MUSB_POWER, power);
	86	musb->is_active = 1;
	87	musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
	88	\| MUSB_PORT_STAT_RESUME);
	89	musb->port1_status \|= USB_PORT_STAT_C_SUSPEND << 16;
	90	usb_hcd_poll_rh_status(musb_to_hcd(musb));
	91	/* NOTE: it might really be A_WAIT_BCON ... */
84e250ff	92	musb->xceiv->state = OTG_STATE_A_HOST;
550a7375 FB	93	}
	94	break;
	95	#endif
	96	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	97	case OTG_STATE_A_HOST:
	98	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	99	if (devctl & MUSB_DEVCTL_BDEVICE)
84e250ff	100	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375	101	else
84e250ff	102	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
550a7375 FB	103	#endif
	104	default:
	105	break;
	106	}
	107	spin_unlock_irqrestore(&musb->lock, flags);
	108	}
	109
	110
	111	void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
	112	{
	113	unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
	114	static unsigned long last_timer;
	115
	116	if (timeout == 0)
	117	timeout = default_timeout;
	118
	119	/* Never idle if active, or when VBUS timeout is not set as host */
	120	if (musb->is_active \|\| ((musb->a_wait_bcon == 0)
84e250ff	121	&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
550a7375 FB	122	DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
	123	del_timer(&musb_idle_timer);
	124	last_timer = jiffies;
	125	return;
	126	}
	127
	128	if (time_after(last_timer, timeout)) {
	129	if (!timer_pending(&musb_idle_timer))
	130	last_timer = timeout;
	131	else {
	132	DBG(4, "Longer idle timer already pending, ignoring\n");
	133	return;
	134	}
	135	}
	136	last_timer = timeout;
	137
	138	DBG(4, "%s inactive, for idle timer for %lu ms\n",
	139	otg_state_string(musb),
	140	(unsigned long)jiffies_to_msecs(timeout - jiffies));
	141	mod_timer(&musb_idle_timer, timeout);
	142	}
	143
	144	void musb_platform_enable(struct musb *musb)
	145	{
	146	}
	147	void musb_platform_disable(struct musb *musb)
	148	{
	149	}
	150	static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
	151	{
	152	}
	153
	154	static void omap_set_vbus(struct musb *musb, int is_on)
	155	{
	156	u8 devctl;
	157	/* HDRC controls CPEN, but beware current surges during device
	158	* connect. They can trigger transient overcurrent conditions
	159	* that must be ignored.
	160	*/
	161
	162	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	163
	164	if (is_on) {
	165	musb->is_active = 1;
84e250ff DB	166	musb->xceiv->default_a = 1;
84e250ff DB	167	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
550a7375 FB	168	devctl \|= MUSB_DEVCTL_SESSION;
	169
	170	MUSB_HST_MODE(musb);
	171	} else {
	172	musb->is_active = 0;
	173
	174	/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
	175	* jumping right to B_IDLE...
	176	*/
	177
84e250ff DB	178	musb->xceiv->default_a = 0;
84e250ff DB	179	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	180	devctl &= ~MUSB_DEVCTL_SESSION;
	181
	182	MUSB_DEV_MODE(musb);
	183	}
	184	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	185
	186	DBG(1, "VBUS %s, devctl %02x "
	187	/* otg %3x conf %08x prcm %08x */ "\n",
	188	otg_state_string(musb),
	189	musb_readb(musb->mregs, MUSB_DEVCTL));
	190	}
550a7375 FB	191
	192	static int musb_platform_resume(struct musb *musb);
	193
96a274d1	194	int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
550a7375 FB	195	{
	196	u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	197
	198	devctl \|= MUSB_DEVCTL_SESSION;
	199	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	200
96a274d1	201	return 0;
550a7375 FB	202	}
	203
	204	int __init musb_platform_init(struct musb *musb)
	205	{
	206	u32 l;
	207
	208	#if defined(CONFIG_ARCH_OMAP2430)
	209	omap_cfg_reg(AE5_2430_USB0HS_STP);
	210	#endif
	211
84e250ff DB	212	/* We require some kind of external transceiver, hooked
	213	* up through ULPI. TWL4030-family PMICs include one,
	214	* which needs a driver, drivers aren't always needed.
	215	*/
	216	musb->xceiv = otg_get_transceiver();
	217	if (!musb->xceiv) {
	218	pr_err("HS USB OTG: no transceiver configured\n");
	219	return -ENODEV;
	220	}
	221
550a7375 FB	222	musb_platform_resume(musb);
	223
	224	l = omap_readl(OTG_SYSCONFIG);
	225	l &= ~ENABLEWAKEUP; /* disable wakeup */
	226	l &= ~NOSTDBY; /* remove possible nostdby */
	227	l \|= SMARTSTDBY; /* enable smart standby */
	228	l &= ~AUTOIDLE; /* disable auto idle */
	229	l &= ~NOIDLE; /* remove possible noidle */
	230	l \|= SMARTIDLE; /* enable smart idle */
	231	l \|= AUTOIDLE; /* enable auto idle */
	232	omap_writel(l, OTG_SYSCONFIG);
	233
	234	l = omap_readl(OTG_INTERFSEL);
	235	l \|= ULPI_12PIN;
	236	omap_writel(l, OTG_INTERFSEL);
	237
	238	pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
	239	"sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
	240	omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
	241	omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
	242	omap_readl(OTG_SIMENABLE));
	243
	244	omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
	245
	246	if (is_host_enabled(musb))
	247	musb->board_set_vbus = omap_set_vbus;
550a7375 FB	248	musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
	249
	250	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
	251
	252	return 0;
	253	}
	254
	255	int musb_platform_suspend(struct musb *musb)
	256	{
	257	u32 l;
	258
	259	if (!musb->clock)
	260	return 0;
	261
	262	/* in any role */
	263	l = omap_readl(OTG_FORCESTDBY);
	264	l \|= ENABLEFORCE; /* enable MSTANDBY */
	265	omap_writel(l, OTG_FORCESTDBY);
	266
	267	l = omap_readl(OTG_SYSCONFIG);
	268	l \|= ENABLEWAKEUP; /* enable wakeup */
	269	omap_writel(l, OTG_SYSCONFIG);
	270
84e250ff	271	otg_set_suspend(musb->xceiv, 1);
550a7375 FB	272
	273	if (musb->set_clock)
	274	musb->set_clock(musb->clock, 0);
	275	else
	276	clk_disable(musb->clock);
	277
	278	return 0;
	279	}
	280
	281	static int musb_platform_resume(struct musb *musb)
	282	{
	283	u32 l;
	284
	285	if (!musb->clock)
	286	return 0;
	287
84e250ff	288	otg_set_suspend(musb->xceiv, 0);
550a7375 FB	289
	290	if (musb->set_clock)
	291	musb->set_clock(musb->clock, 1);
	292	else
	293	clk_enable(musb->clock);
	294
	295	l = omap_readl(OTG_SYSCONFIG);
	296	l &= ~ENABLEWAKEUP; /* disable wakeup */
	297	omap_writel(l, OTG_SYSCONFIG);
	298
	299	l = omap_readl(OTG_FORCESTDBY);
	300	l &= ~ENABLEFORCE; /* disable MSTANDBY */
	301	omap_writel(l, OTG_FORCESTDBY);
	302
	303	return 0;
	304	}
	305
	306
	307	int musb_platform_exit(struct musb *musb)
	308	{
	309
	310	omap_vbus_power(musb, 0 /off/, 1);
	311
	312	musb_platform_suspend(musb);
	313
	314	clk_put(musb->clock);
	315	musb->clock = 0;
	316
	317	return 0;
	318	}