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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver peripheral support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
cea83241 | 7 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> |
550a7375 FB |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/list.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/smp.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/moduleparam.h> | |
44 | #include <linux/stat.h> | |
45 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 46 | #include <linux/slab.h> |
550a7375 FB |
47 | |
48 | #include "musb_core.h" | |
49 | ||
50 | ||
51 | /* MUSB PERIPHERAL status 3-mar-2006: | |
52 | * | |
53 | * - EP0 seems solid. It passes both USBCV and usbtest control cases. | |
54 | * Minor glitches: | |
55 | * | |
56 | * + remote wakeup to Linux hosts work, but saw USBCV failures; | |
57 | * in one test run (operator error?) | |
58 | * + endpoint halt tests -- in both usbtest and usbcv -- seem | |
59 | * to break when dma is enabled ... is something wrongly | |
60 | * clearing SENDSTALL? | |
61 | * | |
62 | * - Mass storage behaved ok when last tested. Network traffic patterns | |
63 | * (with lots of short transfers etc) need retesting; they turn up the | |
64 | * worst cases of the DMA, since short packets are typical but are not | |
65 | * required. | |
66 | * | |
67 | * - TX/IN | |
68 | * + both pio and dma behave in with network and g_zero tests | |
69 | * + no cppi throughput issues other than no-hw-queueing | |
70 | * + failed with FLAT_REG (DaVinci) | |
71 | * + seems to behave with double buffering, PIO -and- CPPI | |
72 | * + with gadgetfs + AIO, requests got lost? | |
73 | * | |
74 | * - RX/OUT | |
75 | * + both pio and dma behave in with network and g_zero tests | |
76 | * + dma is slow in typical case (short_not_ok is clear) | |
77 | * + double buffering ok with PIO | |
78 | * + double buffering *FAILS* with CPPI, wrong data bytes sometimes | |
79 | * + request lossage observed with gadgetfs | |
80 | * | |
81 | * - ISO not tested ... might work, but only weakly isochronous | |
82 | * | |
83 | * - Gadget driver disabling of softconnect during bind() is ignored; so | |
84 | * drivers can't hold off host requests until userspace is ready. | |
85 | * (Workaround: they can turn it off later.) | |
86 | * | |
87 | * - PORTABILITY (assumes PIO works): | |
88 | * + DaVinci, basically works with cppi dma | |
89 | * + OMAP 2430, ditto with mentor dma | |
90 | * + TUSB 6010, platform-specific dma in the works | |
91 | */ | |
92 | ||
93 | /* ----------------------------------------------------------------------- */ | |
94 | ||
95 | /* | |
96 | * Immediately complete a request. | |
97 | * | |
98 | * @param request the request to complete | |
99 | * @param status the status to complete the request with | |
100 | * Context: controller locked, IRQs blocked. | |
101 | */ | |
102 | void musb_g_giveback( | |
103 | struct musb_ep *ep, | |
104 | struct usb_request *request, | |
105 | int status) | |
106 | __releases(ep->musb->lock) | |
107 | __acquires(ep->musb->lock) | |
108 | { | |
109 | struct musb_request *req; | |
110 | struct musb *musb; | |
111 | int busy = ep->busy; | |
112 | ||
113 | req = to_musb_request(request); | |
114 | ||
115 | list_del(&request->list); | |
116 | if (req->request.status == -EINPROGRESS) | |
117 | req->request.status = status; | |
118 | musb = req->musb; | |
119 | ||
120 | ep->busy = 1; | |
121 | spin_unlock(&musb->lock); | |
122 | if (is_dma_capable()) { | |
123 | if (req->mapped) { | |
124 | dma_unmap_single(musb->controller, | |
125 | req->request.dma, | |
126 | req->request.length, | |
127 | req->tx | |
128 | ? DMA_TO_DEVICE | |
129 | : DMA_FROM_DEVICE); | |
130 | req->request.dma = DMA_ADDR_INVALID; | |
131 | req->mapped = 0; | |
132 | } else if (req->request.dma != DMA_ADDR_INVALID) | |
133 | dma_sync_single_for_cpu(musb->controller, | |
134 | req->request.dma, | |
135 | req->request.length, | |
136 | req->tx | |
137 | ? DMA_TO_DEVICE | |
138 | : DMA_FROM_DEVICE); | |
139 | } | |
140 | if (request->status == 0) | |
141 | DBG(5, "%s done request %p, %d/%d\n", | |
142 | ep->end_point.name, request, | |
143 | req->request.actual, req->request.length); | |
144 | else | |
145 | DBG(2, "%s request %p, %d/%d fault %d\n", | |
146 | ep->end_point.name, request, | |
147 | req->request.actual, req->request.length, | |
148 | request->status); | |
149 | req->request.complete(&req->ep->end_point, &req->request); | |
150 | spin_lock(&musb->lock); | |
151 | ep->busy = busy; | |
152 | } | |
153 | ||
154 | /* ----------------------------------------------------------------------- */ | |
155 | ||
156 | /* | |
157 | * Abort requests queued to an endpoint using the status. Synchronous. | |
158 | * caller locked controller and blocked irqs, and selected this ep. | |
159 | */ | |
160 | static void nuke(struct musb_ep *ep, const int status) | |
161 | { | |
162 | struct musb_request *req = NULL; | |
163 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; | |
164 | ||
165 | ep->busy = 1; | |
166 | ||
167 | if (is_dma_capable() && ep->dma) { | |
168 | struct dma_controller *c = ep->musb->dma_controller; | |
169 | int value; | |
b6e434a5 | 170 | |
550a7375 | 171 | if (ep->is_in) { |
b6e434a5 SS |
172 | /* |
173 | * The programming guide says that we must not clear | |
174 | * the DMAMODE bit before DMAENAB, so we only | |
175 | * clear it in the second write... | |
176 | */ | |
550a7375 | 177 | musb_writew(epio, MUSB_TXCSR, |
b6e434a5 | 178 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); |
550a7375 FB |
179 | musb_writew(epio, MUSB_TXCSR, |
180 | 0 | MUSB_TXCSR_FLUSHFIFO); | |
181 | } else { | |
182 | musb_writew(epio, MUSB_RXCSR, | |
183 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
184 | musb_writew(epio, MUSB_RXCSR, | |
185 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
186 | } | |
187 | ||
188 | value = c->channel_abort(ep->dma); | |
189 | DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); | |
190 | c->channel_release(ep->dma); | |
191 | ep->dma = NULL; | |
192 | } | |
193 | ||
194 | while (!list_empty(&(ep->req_list))) { | |
195 | req = container_of(ep->req_list.next, struct musb_request, | |
196 | request.list); | |
197 | musb_g_giveback(ep, &req->request, status); | |
198 | } | |
199 | } | |
200 | ||
201 | /* ----------------------------------------------------------------------- */ | |
202 | ||
203 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ | |
204 | ||
205 | /* | |
206 | * This assumes the separate CPPI engine is responding to DMA requests | |
207 | * from the usb core ... sequenced a bit differently from mentor dma. | |
208 | */ | |
209 | ||
210 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) | |
211 | { | |
212 | if (can_bulk_split(musb, ep->type)) | |
213 | return ep->hw_ep->max_packet_sz_tx; | |
214 | else | |
215 | return ep->packet_sz; | |
216 | } | |
217 | ||
218 | ||
219 | #ifdef CONFIG_USB_INVENTRA_DMA | |
220 | ||
221 | /* Peripheral tx (IN) using Mentor DMA works as follows: | |
222 | Only mode 0 is used for transfers <= wPktSize, | |
223 | mode 1 is used for larger transfers, | |
224 | ||
225 | One of the following happens: | |
226 | - Host sends IN token which causes an endpoint interrupt | |
227 | -> TxAvail | |
228 | -> if DMA is currently busy, exit. | |
229 | -> if queue is non-empty, txstate(). | |
230 | ||
231 | - Request is queued by the gadget driver. | |
232 | -> if queue was previously empty, txstate() | |
233 | ||
234 | txstate() | |
235 | -> start | |
236 | /\ -> setup DMA | |
237 | | (data is transferred to the FIFO, then sent out when | |
238 | | IN token(s) are recd from Host. | |
239 | | -> DMA interrupt on completion | |
240 | | calls TxAvail. | |
b6e434a5 | 241 | | -> stop DMA, ~DMAENAB, |
550a7375 FB |
242 | | -> set TxPktRdy for last short pkt or zlp |
243 | | -> Complete Request | |
244 | | -> Continue next request (call txstate) | |
245 | |___________________________________| | |
246 | ||
247 | * Non-Mentor DMA engines can of course work differently, such as by | |
248 | * upleveling from irq-per-packet to irq-per-buffer. | |
249 | */ | |
250 | ||
251 | #endif | |
252 | ||
253 | /* | |
254 | * An endpoint is transmitting data. This can be called either from | |
255 | * the IRQ routine or from ep.queue() to kickstart a request on an | |
256 | * endpoint. | |
257 | * | |
258 | * Context: controller locked, IRQs blocked, endpoint selected | |
259 | */ | |
260 | static void txstate(struct musb *musb, struct musb_request *req) | |
261 | { | |
262 | u8 epnum = req->epnum; | |
263 | struct musb_ep *musb_ep; | |
264 | void __iomem *epio = musb->endpoints[epnum].regs; | |
265 | struct usb_request *request; | |
266 | u16 fifo_count = 0, csr; | |
267 | int use_dma = 0; | |
268 | ||
269 | musb_ep = req->ep; | |
270 | ||
271 | /* we shouldn't get here while DMA is active ... but we do ... */ | |
272 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
273 | DBG(4, "dma pending...\n"); | |
274 | return; | |
275 | } | |
276 | ||
277 | /* read TXCSR before */ | |
278 | csr = musb_readw(epio, MUSB_TXCSR); | |
279 | ||
280 | request = &req->request; | |
281 | fifo_count = min(max_ep_writesize(musb, musb_ep), | |
282 | (int)(request->length - request->actual)); | |
283 | ||
284 | if (csr & MUSB_TXCSR_TXPKTRDY) { | |
285 | DBG(5, "%s old packet still ready , txcsr %03x\n", | |
286 | musb_ep->end_point.name, csr); | |
287 | return; | |
288 | } | |
289 | ||
290 | if (csr & MUSB_TXCSR_P_SENDSTALL) { | |
291 | DBG(5, "%s stalling, txcsr %03x\n", | |
292 | musb_ep->end_point.name, csr); | |
293 | return; | |
294 | } | |
295 | ||
296 | DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", | |
297 | epnum, musb_ep->packet_sz, fifo_count, | |
298 | csr); | |
299 | ||
300 | #ifndef CONFIG_MUSB_PIO_ONLY | |
301 | if (is_dma_capable() && musb_ep->dma) { | |
302 | struct dma_controller *c = musb->dma_controller; | |
66af83dd ML |
303 | size_t request_size; |
304 | ||
305 | /* setup DMA, then program endpoint CSR */ | |
306 | request_size = min_t(size_t, request->length - request->actual, | |
307 | musb_ep->dma->max_len); | |
550a7375 FB |
308 | |
309 | use_dma = (request->dma != DMA_ADDR_INVALID); | |
310 | ||
311 | /* MUSB_TXCSR_P_ISO is still set correctly */ | |
312 | ||
313 | #ifdef CONFIG_USB_INVENTRA_DMA | |
314 | { | |
d1043a26 | 315 | if (request_size < musb_ep->packet_sz) |
550a7375 FB |
316 | musb_ep->dma->desired_mode = 0; |
317 | else | |
318 | musb_ep->dma->desired_mode = 1; | |
319 | ||
320 | use_dma = use_dma && c->channel_program( | |
321 | musb_ep->dma, musb_ep->packet_sz, | |
322 | musb_ep->dma->desired_mode, | |
796a83fa | 323 | request->dma + request->actual, request_size); |
550a7375 FB |
324 | if (use_dma) { |
325 | if (musb_ep->dma->desired_mode == 0) { | |
b6e434a5 SS |
326 | /* |
327 | * We must not clear the DMAMODE bit | |
328 | * before the DMAENAB bit -- and the | |
329 | * latter doesn't always get cleared | |
330 | * before we get here... | |
331 | */ | |
332 | csr &= ~(MUSB_TXCSR_AUTOSET | |
333 | | MUSB_TXCSR_DMAENAB); | |
334 | musb_writew(epio, MUSB_TXCSR, csr | |
335 | | MUSB_TXCSR_P_WZC_BITS); | |
336 | csr &= ~MUSB_TXCSR_DMAMODE; | |
550a7375 FB |
337 | csr |= (MUSB_TXCSR_DMAENAB | |
338 | MUSB_TXCSR_MODE); | |
339 | /* against programming guide */ | |
340 | } else | |
341 | csr |= (MUSB_TXCSR_AUTOSET | |
342 | | MUSB_TXCSR_DMAENAB | |
343 | | MUSB_TXCSR_DMAMODE | |
344 | | MUSB_TXCSR_MODE); | |
345 | ||
346 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
347 | musb_writew(epio, MUSB_TXCSR, csr); | |
348 | } | |
349 | } | |
350 | ||
351 | #elif defined(CONFIG_USB_TI_CPPI_DMA) | |
352 | /* program endpoint CSR first, then setup DMA */ | |
b6e434a5 | 353 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); |
37e3ee99 SS |
354 | csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | |
355 | MUSB_TXCSR_MODE; | |
550a7375 FB |
356 | musb_writew(epio, MUSB_TXCSR, |
357 | (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) | |
358 | | csr); | |
359 | ||
360 | /* ensure writebuffer is empty */ | |
361 | csr = musb_readw(epio, MUSB_TXCSR); | |
362 | ||
363 | /* NOTE host side sets DMAENAB later than this; both are | |
364 | * OK since the transfer dma glue (between CPPI and Mentor | |
365 | * fifos) just tells CPPI it could start. Data only moves | |
366 | * to the USB TX fifo when both fifos are ready. | |
367 | */ | |
368 | ||
369 | /* "mode" is irrelevant here; handle terminating ZLPs like | |
370 | * PIO does, since the hardware RNDIS mode seems unreliable | |
371 | * except for the last-packet-is-already-short case. | |
372 | */ | |
373 | use_dma = use_dma && c->channel_program( | |
374 | musb_ep->dma, musb_ep->packet_sz, | |
375 | 0, | |
66af83dd ML |
376 | request->dma + request->actual, |
377 | request_size); | |
550a7375 FB |
378 | if (!use_dma) { |
379 | c->channel_release(musb_ep->dma); | |
380 | musb_ep->dma = NULL; | |
b6e434a5 SS |
381 | csr &= ~MUSB_TXCSR_DMAENAB; |
382 | musb_writew(epio, MUSB_TXCSR, csr); | |
550a7375 FB |
383 | /* invariant: prequest->buf is non-null */ |
384 | } | |
385 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) | |
386 | use_dma = use_dma && c->channel_program( | |
387 | musb_ep->dma, musb_ep->packet_sz, | |
388 | request->zero, | |
66af83dd ML |
389 | request->dma + request->actual, |
390 | request_size); | |
550a7375 FB |
391 | #endif |
392 | } | |
393 | #endif | |
394 | ||
395 | if (!use_dma) { | |
396 | musb_write_fifo(musb_ep->hw_ep, fifo_count, | |
397 | (u8 *) (request->buf + request->actual)); | |
398 | request->actual += fifo_count; | |
399 | csr |= MUSB_TXCSR_TXPKTRDY; | |
400 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
401 | musb_writew(epio, MUSB_TXCSR, csr); | |
402 | } | |
403 | ||
404 | /* host may already have the data when this message shows... */ | |
405 | DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", | |
406 | musb_ep->end_point.name, use_dma ? "dma" : "pio", | |
407 | request->actual, request->length, | |
408 | musb_readw(epio, MUSB_TXCSR), | |
409 | fifo_count, | |
410 | musb_readw(epio, MUSB_TXMAXP)); | |
411 | } | |
412 | ||
413 | /* | |
414 | * FIFO state update (e.g. data ready). | |
415 | * Called from IRQ, with controller locked. | |
416 | */ | |
417 | void musb_g_tx(struct musb *musb, u8 epnum) | |
418 | { | |
419 | u16 csr; | |
420 | struct usb_request *request; | |
421 | u8 __iomem *mbase = musb->mregs; | |
422 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; | |
423 | void __iomem *epio = musb->endpoints[epnum].regs; | |
424 | struct dma_channel *dma; | |
425 | ||
426 | musb_ep_select(mbase, epnum); | |
427 | request = next_request(musb_ep); | |
428 | ||
429 | csr = musb_readw(epio, MUSB_TXCSR); | |
430 | DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); | |
431 | ||
432 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
7723de7e SS |
433 | |
434 | /* | |
435 | * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX | |
436 | * probably rates reporting as a host error. | |
437 | */ | |
438 | if (csr & MUSB_TXCSR_P_SENTSTALL) { | |
439 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
440 | csr &= ~MUSB_TXCSR_P_SENTSTALL; | |
441 | musb_writew(epio, MUSB_TXCSR, csr); | |
442 | return; | |
443 | } | |
444 | ||
445 | if (csr & MUSB_TXCSR_P_UNDERRUN) { | |
446 | /* We NAKed, no big deal... little reason to care. */ | |
447 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
448 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
449 | musb_writew(epio, MUSB_TXCSR, csr); | |
450 | DBG(20, "underrun on ep%d, req %p\n", epnum, request); | |
451 | } | |
452 | ||
453 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
454 | /* | |
455 | * SHOULD NOT HAPPEN... has with CPPI though, after | |
456 | * changing SENDSTALL (and other cases); harmless? | |
550a7375 | 457 | */ |
7723de7e SS |
458 | DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); |
459 | return; | |
460 | } | |
550a7375 | 461 | |
7723de7e SS |
462 | if (request) { |
463 | u8 is_dma = 0; | |
464 | ||
465 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { | |
466 | is_dma = 1; | |
550a7375 | 467 | csr |= MUSB_TXCSR_P_WZC_BITS; |
7723de7e SS |
468 | csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | |
469 | MUSB_TXCSR_TXPKTRDY); | |
550a7375 | 470 | musb_writew(epio, MUSB_TXCSR, csr); |
7723de7e SS |
471 | /* Ensure writebuffer is empty. */ |
472 | csr = musb_readw(epio, MUSB_TXCSR); | |
473 | request->actual += musb_ep->dma->actual_len; | |
474 | DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n", | |
475 | epnum, csr, musb_ep->dma->actual_len, request); | |
550a7375 FB |
476 | } |
477 | ||
7723de7e SS |
478 | if (is_dma || request->actual == request->length) { |
479 | /* | |
480 | * First, maybe a terminating short packet. Some DMA | |
481 | * engines might handle this by themselves. | |
550a7375 | 482 | */ |
7723de7e SS |
483 | if ((request->zero && request->length |
484 | && request->length % musb_ep->packet_sz == 0) | |
550a7375 | 485 | #ifdef CONFIG_USB_INVENTRA_DMA |
7723de7e SS |
486 | || (is_dma && (!dma->desired_mode || |
487 | (request->actual & | |
488 | (musb_ep->packet_sz - 1)))) | |
550a7375 | 489 | #endif |
7723de7e SS |
490 | ) { |
491 | /* | |
492 | * On DMA completion, FIFO may not be | |
493 | * available yet... | |
550a7375 | 494 | */ |
7723de7e SS |
495 | if (csr & MUSB_TXCSR_TXPKTRDY) |
496 | return; | |
497 | ||
498 | DBG(4, "sending zero pkt\n"); | |
499 | musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE | |
500 | | MUSB_TXCSR_TXPKTRDY); | |
501 | request->zero = 0; | |
550a7375 FB |
502 | } |
503 | ||
bb27bc2c ML |
504 | if (request->actual == request->length) { |
505 | musb_g_giveback(musb_ep, request, 0); | |
506 | request = musb_ep->desc ? next_request(musb_ep) : NULL; | |
507 | if (!request) { | |
508 | DBG(4, "%s idle now\n", | |
509 | musb_ep->end_point.name); | |
510 | return; | |
511 | } | |
95962a77 | 512 | } |
550a7375 FB |
513 | } |
514 | ||
7723de7e SS |
515 | txstate(musb, to_musb_request(request)); |
516 | } | |
550a7375 FB |
517 | } |
518 | ||
519 | /* ------------------------------------------------------------ */ | |
520 | ||
521 | #ifdef CONFIG_USB_INVENTRA_DMA | |
522 | ||
523 | /* Peripheral rx (OUT) using Mentor DMA works as follows: | |
524 | - Only mode 0 is used. | |
525 | ||
526 | - Request is queued by the gadget class driver. | |
527 | -> if queue was previously empty, rxstate() | |
528 | ||
529 | - Host sends OUT token which causes an endpoint interrupt | |
530 | /\ -> RxReady | |
531 | | -> if request queued, call rxstate | |
532 | | /\ -> setup DMA | |
533 | | | -> DMA interrupt on completion | |
534 | | | -> RxReady | |
535 | | | -> stop DMA | |
536 | | | -> ack the read | |
537 | | | -> if data recd = max expected | |
538 | | | by the request, or host | |
539 | | | sent a short packet, | |
540 | | | complete the request, | |
541 | | | and start the next one. | |
542 | | |_____________________________________| | |
543 | | else just wait for the host | |
544 | | to send the next OUT token. | |
545 | |__________________________________________________| | |
546 | ||
547 | * Non-Mentor DMA engines can of course work differently. | |
548 | */ | |
549 | ||
550 | #endif | |
551 | ||
552 | /* | |
553 | * Context: controller locked, IRQs blocked, endpoint selected | |
554 | */ | |
555 | static void rxstate(struct musb *musb, struct musb_request *req) | |
556 | { | |
550a7375 FB |
557 | const u8 epnum = req->epnum; |
558 | struct usb_request *request = &req->request; | |
bd2e74d6 | 559 | struct musb_ep *musb_ep; |
550a7375 | 560 | void __iomem *epio = musb->endpoints[epnum].regs; |
c2c96321 | 561 | unsigned fifo_count = 0; |
bd2e74d6 | 562 | u16 len; |
cea83241 | 563 | u16 csr = musb_readw(epio, MUSB_RXCSR); |
bd2e74d6 ML |
564 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
565 | ||
566 | if (hw_ep->is_shared_fifo) | |
567 | musb_ep = &hw_ep->ep_in; | |
568 | else | |
569 | musb_ep = &hw_ep->ep_out; | |
570 | ||
571 | len = musb_ep->packet_sz; | |
550a7375 | 572 | |
cea83241 SS |
573 | /* We shouldn't get here while DMA is active, but we do... */ |
574 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
575 | DBG(4, "DMA pending...\n"); | |
576 | return; | |
577 | } | |
578 | ||
579 | if (csr & MUSB_RXCSR_P_SENDSTALL) { | |
580 | DBG(5, "%s stalling, RXCSR %04x\n", | |
581 | musb_ep->end_point.name, csr); | |
582 | return; | |
583 | } | |
550a7375 FB |
584 | |
585 | if (is_cppi_enabled() && musb_ep->dma) { | |
586 | struct dma_controller *c = musb->dma_controller; | |
587 | struct dma_channel *channel = musb_ep->dma; | |
588 | ||
589 | /* NOTE: CPPI won't actually stop advancing the DMA | |
590 | * queue after short packet transfers, so this is almost | |
591 | * always going to run as IRQ-per-packet DMA so that | |
592 | * faults will be handled correctly. | |
593 | */ | |
594 | if (c->channel_program(channel, | |
595 | musb_ep->packet_sz, | |
596 | !request->short_not_ok, | |
597 | request->dma + request->actual, | |
598 | request->length - request->actual)) { | |
599 | ||
600 | /* make sure that if an rxpkt arrived after the irq, | |
601 | * the cppi engine will be ready to take it as soon | |
602 | * as DMA is enabled | |
603 | */ | |
604 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
605 | | MUSB_RXCSR_DMAMODE); | |
606 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; | |
607 | musb_writew(epio, MUSB_RXCSR, csr); | |
608 | return; | |
609 | } | |
610 | } | |
611 | ||
612 | if (csr & MUSB_RXCSR_RXPKTRDY) { | |
613 | len = musb_readw(epio, MUSB_RXCOUNT); | |
614 | if (request->actual < request->length) { | |
615 | #ifdef CONFIG_USB_INVENTRA_DMA | |
616 | if (is_dma_capable() && musb_ep->dma) { | |
617 | struct dma_controller *c; | |
618 | struct dma_channel *channel; | |
619 | int use_dma = 0; | |
620 | ||
621 | c = musb->dma_controller; | |
622 | channel = musb_ep->dma; | |
623 | ||
624 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in | |
625 | * mode 0 only. So we do not get endpoint interrupts due to DMA | |
626 | * completion. We only get interrupts from DMA controller. | |
627 | * | |
628 | * We could operate in DMA mode 1 if we knew the size of the tranfer | |
629 | * in advance. For mass storage class, request->length = what the host | |
630 | * sends, so that'd work. But for pretty much everything else, | |
631 | * request->length is routinely more than what the host sends. For | |
632 | * most these gadgets, end of is signified either by a short packet, | |
633 | * or filling the last byte of the buffer. (Sending extra data in | |
634 | * that last pckate should trigger an overflow fault.) But in mode 1, | |
635 | * we don't get DMA completion interrrupt for short packets. | |
636 | * | |
637 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), | |
638 | * to get endpoint interrupt on every DMA req, but that didn't seem | |
639 | * to work reliably. | |
640 | * | |
641 | * REVISIT an updated g_file_storage can set req->short_not_ok, which | |
642 | * then becomes usable as a runtime "use mode 1" hint... | |
643 | */ | |
644 | ||
645 | csr |= MUSB_RXCSR_DMAENAB; | |
550a7375 | 646 | csr |= MUSB_RXCSR_AUTOCLEAR; |
490e5fbe | 647 | #ifdef USE_MODE1 |
550a7375 FB |
648 | /* csr |= MUSB_RXCSR_DMAMODE; */ |
649 | ||
650 | /* this special sequence (enabling and then | |
651 | * disabling MUSB_RXCSR_DMAMODE) is required | |
652 | * to get DMAReq to activate | |
653 | */ | |
654 | musb_writew(epio, MUSB_RXCSR, | |
655 | csr | MUSB_RXCSR_DMAMODE); | |
656 | #endif | |
657 | musb_writew(epio, MUSB_RXCSR, csr); | |
658 | ||
659 | if (request->actual < request->length) { | |
660 | int transfer_size = 0; | |
661 | #ifdef USE_MODE1 | |
1018b4e4 | 662 | transfer_size = min(request->length - request->actual, |
550a7375 FB |
663 | channel->max_len); |
664 | #else | |
1018b4e4 ML |
665 | transfer_size = min(request->length - request->actual, |
666 | (unsigned)len); | |
550a7375 FB |
667 | #endif |
668 | if (transfer_size <= musb_ep->packet_sz) | |
669 | musb_ep->dma->desired_mode = 0; | |
670 | else | |
671 | musb_ep->dma->desired_mode = 1; | |
672 | ||
673 | use_dma = c->channel_program( | |
674 | channel, | |
675 | musb_ep->packet_sz, | |
676 | channel->desired_mode, | |
677 | request->dma | |
678 | + request->actual, | |
679 | transfer_size); | |
680 | } | |
681 | ||
682 | if (use_dma) | |
683 | return; | |
684 | } | |
685 | #endif /* Mentor's DMA */ | |
686 | ||
687 | fifo_count = request->length - request->actual; | |
688 | DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", | |
689 | musb_ep->end_point.name, | |
690 | len, fifo_count, | |
691 | musb_ep->packet_sz); | |
692 | ||
c2c96321 | 693 | fifo_count = min_t(unsigned, len, fifo_count); |
550a7375 FB |
694 | |
695 | #ifdef CONFIG_USB_TUSB_OMAP_DMA | |
696 | if (tusb_dma_omap() && musb_ep->dma) { | |
697 | struct dma_controller *c = musb->dma_controller; | |
698 | struct dma_channel *channel = musb_ep->dma; | |
699 | u32 dma_addr = request->dma + request->actual; | |
700 | int ret; | |
701 | ||
702 | ret = c->channel_program(channel, | |
703 | musb_ep->packet_sz, | |
704 | channel->desired_mode, | |
705 | dma_addr, | |
706 | fifo_count); | |
707 | if (ret) | |
708 | return; | |
709 | } | |
710 | #endif | |
711 | ||
712 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) | |
713 | (request->buf + request->actual)); | |
714 | request->actual += fifo_count; | |
715 | ||
716 | /* REVISIT if we left anything in the fifo, flush | |
717 | * it and report -EOVERFLOW | |
718 | */ | |
719 | ||
720 | /* ack the read! */ | |
721 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
722 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
723 | musb_writew(epio, MUSB_RXCSR, csr); | |
724 | } | |
725 | } | |
726 | ||
727 | /* reach the end or short packet detected */ | |
728 | if (request->actual == request->length || len < musb_ep->packet_sz) | |
729 | musb_g_giveback(musb_ep, request, 0); | |
730 | } | |
731 | ||
732 | /* | |
733 | * Data ready for a request; called from IRQ | |
734 | */ | |
735 | void musb_g_rx(struct musb *musb, u8 epnum) | |
736 | { | |
737 | u16 csr; | |
738 | struct usb_request *request; | |
739 | void __iomem *mbase = musb->mregs; | |
bd2e74d6 | 740 | struct musb_ep *musb_ep; |
550a7375 FB |
741 | void __iomem *epio = musb->endpoints[epnum].regs; |
742 | struct dma_channel *dma; | |
bd2e74d6 ML |
743 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
744 | ||
745 | if (hw_ep->is_shared_fifo) | |
746 | musb_ep = &hw_ep->ep_in; | |
747 | else | |
748 | musb_ep = &hw_ep->ep_out; | |
550a7375 FB |
749 | |
750 | musb_ep_select(mbase, epnum); | |
751 | ||
752 | request = next_request(musb_ep); | |
0abdc36f MM |
753 | if (!request) |
754 | return; | |
550a7375 FB |
755 | |
756 | csr = musb_readw(epio, MUSB_RXCSR); | |
757 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
758 | ||
759 | DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, | |
760 | csr, dma ? " (dma)" : "", request); | |
761 | ||
762 | if (csr & MUSB_RXCSR_P_SENTSTALL) { | |
550a7375 FB |
763 | csr |= MUSB_RXCSR_P_WZC_BITS; |
764 | csr &= ~MUSB_RXCSR_P_SENTSTALL; | |
765 | musb_writew(epio, MUSB_RXCSR, csr); | |
cea83241 | 766 | return; |
550a7375 FB |
767 | } |
768 | ||
769 | if (csr & MUSB_RXCSR_P_OVERRUN) { | |
770 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ | |
771 | csr &= ~MUSB_RXCSR_P_OVERRUN; | |
772 | musb_writew(epio, MUSB_RXCSR, csr); | |
773 | ||
774 | DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); | |
775 | if (request && request->status == -EINPROGRESS) | |
776 | request->status = -EOVERFLOW; | |
777 | } | |
778 | if (csr & MUSB_RXCSR_INCOMPRX) { | |
779 | /* REVISIT not necessarily an error */ | |
780 | DBG(4, "%s, incomprx\n", musb_ep->end_point.name); | |
781 | } | |
782 | ||
783 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
784 | /* "should not happen"; likely RXPKTRDY pending for DMA */ | |
785 | DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, | |
786 | "%s busy, csr %04x\n", | |
787 | musb_ep->end_point.name, csr); | |
cea83241 | 788 | return; |
550a7375 FB |
789 | } |
790 | ||
791 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { | |
792 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
793 | | MUSB_RXCSR_DMAENAB | |
794 | | MUSB_RXCSR_DMAMODE); | |
795 | musb_writew(epio, MUSB_RXCSR, | |
796 | MUSB_RXCSR_P_WZC_BITS | csr); | |
797 | ||
798 | request->actual += musb_ep->dma->actual_len; | |
799 | ||
800 | DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", | |
801 | epnum, csr, | |
802 | musb_readw(epio, MUSB_RXCSR), | |
803 | musb_ep->dma->actual_len, request); | |
804 | ||
805 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) | |
806 | /* Autoclear doesn't clear RxPktRdy for short packets */ | |
807 | if ((dma->desired_mode == 0) | |
808 | || (dma->actual_len | |
809 | & (musb_ep->packet_sz - 1))) { | |
810 | /* ack the read! */ | |
811 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
812 | musb_writew(epio, MUSB_RXCSR, csr); | |
813 | } | |
814 | ||
815 | /* incomplete, and not short? wait for next IN packet */ | |
816 | if ((request->actual < request->length) | |
817 | && (musb_ep->dma->actual_len | |
818 | == musb_ep->packet_sz)) | |
cea83241 | 819 | return; |
550a7375 FB |
820 | #endif |
821 | musb_g_giveback(musb_ep, request, 0); | |
822 | ||
823 | request = next_request(musb_ep); | |
824 | if (!request) | |
cea83241 | 825 | return; |
550a7375 FB |
826 | } |
827 | ||
550a7375 FB |
828 | /* analyze request if the ep is hot */ |
829 | if (request) | |
830 | rxstate(musb, to_musb_request(request)); | |
831 | else | |
832 | DBG(3, "packet waiting for %s%s request\n", | |
833 | musb_ep->desc ? "" : "inactive ", | |
834 | musb_ep->end_point.name); | |
550a7375 FB |
835 | return; |
836 | } | |
837 | ||
838 | /* ------------------------------------------------------------ */ | |
839 | ||
840 | static int musb_gadget_enable(struct usb_ep *ep, | |
841 | const struct usb_endpoint_descriptor *desc) | |
842 | { | |
843 | unsigned long flags; | |
844 | struct musb_ep *musb_ep; | |
845 | struct musb_hw_ep *hw_ep; | |
846 | void __iomem *regs; | |
847 | struct musb *musb; | |
848 | void __iomem *mbase; | |
849 | u8 epnum; | |
850 | u16 csr; | |
851 | unsigned tmp; | |
852 | int status = -EINVAL; | |
853 | ||
854 | if (!ep || !desc) | |
855 | return -EINVAL; | |
856 | ||
857 | musb_ep = to_musb_ep(ep); | |
858 | hw_ep = musb_ep->hw_ep; | |
859 | regs = hw_ep->regs; | |
860 | musb = musb_ep->musb; | |
861 | mbase = musb->mregs; | |
862 | epnum = musb_ep->current_epnum; | |
863 | ||
864 | spin_lock_irqsave(&musb->lock, flags); | |
865 | ||
866 | if (musb_ep->desc) { | |
867 | status = -EBUSY; | |
868 | goto fail; | |
869 | } | |
96bcd090 | 870 | musb_ep->type = usb_endpoint_type(desc); |
550a7375 FB |
871 | |
872 | /* check direction and (later) maxpacket size against endpoint */ | |
96bcd090 | 873 | if (usb_endpoint_num(desc) != epnum) |
550a7375 FB |
874 | goto fail; |
875 | ||
876 | /* REVISIT this rules out high bandwidth periodic transfers */ | |
877 | tmp = le16_to_cpu(desc->wMaxPacketSize); | |
878 | if (tmp & ~0x07ff) | |
879 | goto fail; | |
880 | musb_ep->packet_sz = tmp; | |
881 | ||
882 | /* enable the interrupts for the endpoint, set the endpoint | |
883 | * packet size (or fail), set the mode, clear the fifo | |
884 | */ | |
885 | musb_ep_select(mbase, epnum); | |
96bcd090 | 886 | if (usb_endpoint_dir_in(desc)) { |
550a7375 FB |
887 | u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); |
888 | ||
889 | if (hw_ep->is_shared_fifo) | |
890 | musb_ep->is_in = 1; | |
891 | if (!musb_ep->is_in) | |
892 | goto fail; | |
893 | if (tmp > hw_ep->max_packet_sz_tx) | |
894 | goto fail; | |
895 | ||
896 | int_txe |= (1 << epnum); | |
897 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
898 | ||
899 | /* REVISIT if can_bulk_split(), use by updating "tmp"; | |
900 | * likewise high bandwidth periodic tx | |
901 | */ | |
9f445cb2 CC |
902 | /* Set TXMAXP with the FIFO size of the endpoint |
903 | * to disable double buffering mode. Currently, It seems that double | |
904 | * buffering has problem if musb RTL revision number < 2.0. | |
905 | */ | |
906 | if (musb->hwvers < MUSB_HWVERS_2000) | |
907 | musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); | |
908 | else | |
909 | musb_writew(regs, MUSB_TXMAXP, tmp); | |
550a7375 FB |
910 | |
911 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; | |
912 | if (musb_readw(regs, MUSB_TXCSR) | |
913 | & MUSB_TXCSR_FIFONOTEMPTY) | |
914 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
915 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
916 | csr |= MUSB_TXCSR_P_ISO; | |
917 | ||
918 | /* set twice in case of double buffering */ | |
919 | musb_writew(regs, MUSB_TXCSR, csr); | |
920 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
921 | musb_writew(regs, MUSB_TXCSR, csr); | |
922 | ||
923 | } else { | |
924 | u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); | |
925 | ||
926 | if (hw_ep->is_shared_fifo) | |
927 | musb_ep->is_in = 0; | |
928 | if (musb_ep->is_in) | |
929 | goto fail; | |
930 | if (tmp > hw_ep->max_packet_sz_rx) | |
931 | goto fail; | |
932 | ||
933 | int_rxe |= (1 << epnum); | |
934 | musb_writew(mbase, MUSB_INTRRXE, int_rxe); | |
935 | ||
936 | /* REVISIT if can_bulk_combine() use by updating "tmp" | |
937 | * likewise high bandwidth periodic rx | |
938 | */ | |
9f445cb2 CC |
939 | /* Set RXMAXP with the FIFO size of the endpoint |
940 | * to disable double buffering mode. | |
941 | */ | |
942 | if (musb->hwvers < MUSB_HWVERS_2000) | |
943 | musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_rx); | |
944 | else | |
945 | musb_writew(regs, MUSB_RXMAXP, tmp); | |
550a7375 FB |
946 | |
947 | /* force shared fifo to OUT-only mode */ | |
948 | if (hw_ep->is_shared_fifo) { | |
949 | csr = musb_readw(regs, MUSB_TXCSR); | |
950 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); | |
951 | musb_writew(regs, MUSB_TXCSR, csr); | |
952 | } | |
953 | ||
954 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; | |
955 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
956 | csr |= MUSB_RXCSR_P_ISO; | |
957 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) | |
958 | csr |= MUSB_RXCSR_DISNYET; | |
959 | ||
960 | /* set twice in case of double buffering */ | |
961 | musb_writew(regs, MUSB_RXCSR, csr); | |
962 | musb_writew(regs, MUSB_RXCSR, csr); | |
963 | } | |
964 | ||
965 | /* NOTE: all the I/O code _should_ work fine without DMA, in case | |
966 | * for some reason you run out of channels here. | |
967 | */ | |
968 | if (is_dma_capable() && musb->dma_controller) { | |
969 | struct dma_controller *c = musb->dma_controller; | |
970 | ||
971 | musb_ep->dma = c->channel_alloc(c, hw_ep, | |
972 | (desc->bEndpointAddress & USB_DIR_IN)); | |
973 | } else | |
974 | musb_ep->dma = NULL; | |
975 | ||
976 | musb_ep->desc = desc; | |
977 | musb_ep->busy = 0; | |
47e97605 | 978 | musb_ep->wedged = 0; |
550a7375 FB |
979 | status = 0; |
980 | ||
981 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", | |
982 | musb_driver_name, musb_ep->end_point.name, | |
983 | ({ char *s; switch (musb_ep->type) { | |
984 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; | |
985 | case USB_ENDPOINT_XFER_INT: s = "int"; break; | |
986 | default: s = "iso"; break; | |
987 | }; s; }), | |
988 | musb_ep->is_in ? "IN" : "OUT", | |
989 | musb_ep->dma ? "dma, " : "", | |
990 | musb_ep->packet_sz); | |
991 | ||
992 | schedule_work(&musb->irq_work); | |
993 | ||
994 | fail: | |
995 | spin_unlock_irqrestore(&musb->lock, flags); | |
996 | return status; | |
997 | } | |
998 | ||
999 | /* | |
1000 | * Disable an endpoint flushing all requests queued. | |
1001 | */ | |
1002 | static int musb_gadget_disable(struct usb_ep *ep) | |
1003 | { | |
1004 | unsigned long flags; | |
1005 | struct musb *musb; | |
1006 | u8 epnum; | |
1007 | struct musb_ep *musb_ep; | |
1008 | void __iomem *epio; | |
1009 | int status = 0; | |
1010 | ||
1011 | musb_ep = to_musb_ep(ep); | |
1012 | musb = musb_ep->musb; | |
1013 | epnum = musb_ep->current_epnum; | |
1014 | epio = musb->endpoints[epnum].regs; | |
1015 | ||
1016 | spin_lock_irqsave(&musb->lock, flags); | |
1017 | musb_ep_select(musb->mregs, epnum); | |
1018 | ||
1019 | /* zero the endpoint sizes */ | |
1020 | if (musb_ep->is_in) { | |
1021 | u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); | |
1022 | int_txe &= ~(1 << epnum); | |
1023 | musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); | |
1024 | musb_writew(epio, MUSB_TXMAXP, 0); | |
1025 | } else { | |
1026 | u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); | |
1027 | int_rxe &= ~(1 << epnum); | |
1028 | musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); | |
1029 | musb_writew(epio, MUSB_RXMAXP, 0); | |
1030 | } | |
1031 | ||
1032 | musb_ep->desc = NULL; | |
1033 | ||
1034 | /* abort all pending DMA and requests */ | |
1035 | nuke(musb_ep, -ESHUTDOWN); | |
1036 | ||
1037 | schedule_work(&musb->irq_work); | |
1038 | ||
1039 | spin_unlock_irqrestore(&(musb->lock), flags); | |
1040 | ||
1041 | DBG(2, "%s\n", musb_ep->end_point.name); | |
1042 | ||
1043 | return status; | |
1044 | } | |
1045 | ||
1046 | /* | |
1047 | * Allocate a request for an endpoint. | |
1048 | * Reused by ep0 code. | |
1049 | */ | |
1050 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) | |
1051 | { | |
1052 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1053 | struct musb_request *request = NULL; | |
1054 | ||
1055 | request = kzalloc(sizeof *request, gfp_flags); | |
1056 | if (request) { | |
1057 | INIT_LIST_HEAD(&request->request.list); | |
1058 | request->request.dma = DMA_ADDR_INVALID; | |
1059 | request->epnum = musb_ep->current_epnum; | |
1060 | request->ep = musb_ep; | |
1061 | } | |
1062 | ||
1063 | return &request->request; | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Free a request | |
1068 | * Reused by ep0 code. | |
1069 | */ | |
1070 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) | |
1071 | { | |
1072 | kfree(to_musb_request(req)); | |
1073 | } | |
1074 | ||
1075 | static LIST_HEAD(buffers); | |
1076 | ||
1077 | struct free_record { | |
1078 | struct list_head list; | |
1079 | struct device *dev; | |
1080 | unsigned bytes; | |
1081 | dma_addr_t dma; | |
1082 | }; | |
1083 | ||
1084 | /* | |
1085 | * Context: controller locked, IRQs blocked. | |
1086 | */ | |
a666e3e6 | 1087 | void musb_ep_restart(struct musb *musb, struct musb_request *req) |
550a7375 FB |
1088 | { |
1089 | DBG(3, "<== %s request %p len %u on hw_ep%d\n", | |
1090 | req->tx ? "TX/IN" : "RX/OUT", | |
1091 | &req->request, req->request.length, req->epnum); | |
1092 | ||
1093 | musb_ep_select(musb->mregs, req->epnum); | |
1094 | if (req->tx) | |
1095 | txstate(musb, req); | |
1096 | else | |
1097 | rxstate(musb, req); | |
1098 | } | |
1099 | ||
1100 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, | |
1101 | gfp_t gfp_flags) | |
1102 | { | |
1103 | struct musb_ep *musb_ep; | |
1104 | struct musb_request *request; | |
1105 | struct musb *musb; | |
1106 | int status = 0; | |
1107 | unsigned long lockflags; | |
1108 | ||
1109 | if (!ep || !req) | |
1110 | return -EINVAL; | |
1111 | if (!req->buf) | |
1112 | return -ENODATA; | |
1113 | ||
1114 | musb_ep = to_musb_ep(ep); | |
1115 | musb = musb_ep->musb; | |
1116 | ||
1117 | request = to_musb_request(req); | |
1118 | request->musb = musb; | |
1119 | ||
1120 | if (request->ep != musb_ep) | |
1121 | return -EINVAL; | |
1122 | ||
1123 | DBG(4, "<== to %s request=%p\n", ep->name, req); | |
1124 | ||
1125 | /* request is mine now... */ | |
1126 | request->request.actual = 0; | |
1127 | request->request.status = -EINPROGRESS; | |
1128 | request->epnum = musb_ep->current_epnum; | |
1129 | request->tx = musb_ep->is_in; | |
1130 | ||
1131 | if (is_dma_capable() && musb_ep->dma) { | |
1132 | if (request->request.dma == DMA_ADDR_INVALID) { | |
1133 | request->request.dma = dma_map_single( | |
1134 | musb->controller, | |
1135 | request->request.buf, | |
1136 | request->request.length, | |
1137 | request->tx | |
1138 | ? DMA_TO_DEVICE | |
1139 | : DMA_FROM_DEVICE); | |
1140 | request->mapped = 1; | |
1141 | } else { | |
1142 | dma_sync_single_for_device(musb->controller, | |
1143 | request->request.dma, | |
1144 | request->request.length, | |
1145 | request->tx | |
1146 | ? DMA_TO_DEVICE | |
1147 | : DMA_FROM_DEVICE); | |
1148 | request->mapped = 0; | |
1149 | } | |
1150 | } else if (!req->buf) { | |
1151 | return -ENODATA; | |
1152 | } else | |
1153 | request->mapped = 0; | |
1154 | ||
1155 | spin_lock_irqsave(&musb->lock, lockflags); | |
1156 | ||
1157 | /* don't queue if the ep is down */ | |
1158 | if (!musb_ep->desc) { | |
1159 | DBG(4, "req %p queued to %s while ep %s\n", | |
1160 | req, ep->name, "disabled"); | |
1161 | status = -ESHUTDOWN; | |
1162 | goto cleanup; | |
1163 | } | |
1164 | ||
1165 | /* add request to the list */ | |
1166 | list_add_tail(&(request->request.list), &(musb_ep->req_list)); | |
1167 | ||
1168 | /* it this is the head of the queue, start i/o ... */ | |
1169 | if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next) | |
1170 | musb_ep_restart(musb, request); | |
1171 | ||
1172 | cleanup: | |
1173 | spin_unlock_irqrestore(&musb->lock, lockflags); | |
1174 | return status; | |
1175 | } | |
1176 | ||
1177 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) | |
1178 | { | |
1179 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1180 | struct usb_request *r; | |
1181 | unsigned long flags; | |
1182 | int status = 0; | |
1183 | struct musb *musb = musb_ep->musb; | |
1184 | ||
1185 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) | |
1186 | return -EINVAL; | |
1187 | ||
1188 | spin_lock_irqsave(&musb->lock, flags); | |
1189 | ||
1190 | list_for_each_entry(r, &musb_ep->req_list, list) { | |
1191 | if (r == request) | |
1192 | break; | |
1193 | } | |
1194 | if (r != request) { | |
1195 | DBG(3, "request %p not queued to %s\n", request, ep->name); | |
1196 | status = -EINVAL; | |
1197 | goto done; | |
1198 | } | |
1199 | ||
1200 | /* if the hardware doesn't have the request, easy ... */ | |
1201 | if (musb_ep->req_list.next != &request->list || musb_ep->busy) | |
1202 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1203 | ||
1204 | /* ... else abort the dma transfer ... */ | |
1205 | else if (is_dma_capable() && musb_ep->dma) { | |
1206 | struct dma_controller *c = musb->dma_controller; | |
1207 | ||
1208 | musb_ep_select(musb->mregs, musb_ep->current_epnum); | |
1209 | if (c->channel_abort) | |
1210 | status = c->channel_abort(musb_ep->dma); | |
1211 | else | |
1212 | status = -EBUSY; | |
1213 | if (status == 0) | |
1214 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1215 | } else { | |
1216 | /* NOTE: by sticking to easily tested hardware/driver states, | |
1217 | * we leave counting of in-flight packets imprecise. | |
1218 | */ | |
1219 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1220 | } | |
1221 | ||
1222 | done: | |
1223 | spin_unlock_irqrestore(&musb->lock, flags); | |
1224 | return status; | |
1225 | } | |
1226 | ||
1227 | /* | |
1228 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any | |
1229 | * data but will queue requests. | |
1230 | * | |
1231 | * exported to ep0 code | |
1232 | */ | |
1b6c3b0f | 1233 | static int musb_gadget_set_halt(struct usb_ep *ep, int value) |
550a7375 FB |
1234 | { |
1235 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1236 | u8 epnum = musb_ep->current_epnum; | |
1237 | struct musb *musb = musb_ep->musb; | |
1238 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1239 | void __iomem *mbase; | |
1240 | unsigned long flags; | |
1241 | u16 csr; | |
cea83241 | 1242 | struct musb_request *request; |
550a7375 FB |
1243 | int status = 0; |
1244 | ||
1245 | if (!ep) | |
1246 | return -EINVAL; | |
1247 | mbase = musb->mregs; | |
1248 | ||
1249 | spin_lock_irqsave(&musb->lock, flags); | |
1250 | ||
1251 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { | |
1252 | status = -EINVAL; | |
1253 | goto done; | |
1254 | } | |
1255 | ||
1256 | musb_ep_select(mbase, epnum); | |
1257 | ||
550a7375 | 1258 | request = to_musb_request(next_request(musb_ep)); |
cea83241 SS |
1259 | if (value) { |
1260 | if (request) { | |
1261 | DBG(3, "request in progress, cannot halt %s\n", | |
1262 | ep->name); | |
1263 | status = -EAGAIN; | |
1264 | goto done; | |
1265 | } | |
1266 | /* Cannot portably stall with non-empty FIFO */ | |
1267 | if (musb_ep->is_in) { | |
1268 | csr = musb_readw(epio, MUSB_TXCSR); | |
1269 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1270 | DBG(3, "FIFO busy, cannot halt %s\n", ep->name); | |
1271 | status = -EAGAIN; | |
1272 | goto done; | |
1273 | } | |
550a7375 | 1274 | } |
47e97605 SS |
1275 | } else |
1276 | musb_ep->wedged = 0; | |
550a7375 FB |
1277 | |
1278 | /* set/clear the stall and toggle bits */ | |
1279 | DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); | |
1280 | if (musb_ep->is_in) { | |
1281 | csr = musb_readw(epio, MUSB_TXCSR); | |
550a7375 FB |
1282 | csr |= MUSB_TXCSR_P_WZC_BITS |
1283 | | MUSB_TXCSR_CLRDATATOG; | |
1284 | if (value) | |
1285 | csr |= MUSB_TXCSR_P_SENDSTALL; | |
1286 | else | |
1287 | csr &= ~(MUSB_TXCSR_P_SENDSTALL | |
1288 | | MUSB_TXCSR_P_SENTSTALL); | |
1289 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
1290 | musb_writew(epio, MUSB_TXCSR, csr); | |
1291 | } else { | |
1292 | csr = musb_readw(epio, MUSB_RXCSR); | |
1293 | csr |= MUSB_RXCSR_P_WZC_BITS | |
1294 | | MUSB_RXCSR_FLUSHFIFO | |
1295 | | MUSB_RXCSR_CLRDATATOG; | |
1296 | if (value) | |
1297 | csr |= MUSB_RXCSR_P_SENDSTALL; | |
1298 | else | |
1299 | csr &= ~(MUSB_RXCSR_P_SENDSTALL | |
1300 | | MUSB_RXCSR_P_SENTSTALL); | |
1301 | musb_writew(epio, MUSB_RXCSR, csr); | |
1302 | } | |
1303 | ||
550a7375 FB |
1304 | /* maybe start the first request in the queue */ |
1305 | if (!musb_ep->busy && !value && request) { | |
1306 | DBG(3, "restarting the request\n"); | |
1307 | musb_ep_restart(musb, request); | |
1308 | } | |
1309 | ||
cea83241 | 1310 | done: |
550a7375 FB |
1311 | spin_unlock_irqrestore(&musb->lock, flags); |
1312 | return status; | |
1313 | } | |
1314 | ||
47e97605 SS |
1315 | /* |
1316 | * Sets the halt feature with the clear requests ignored | |
1317 | */ | |
1b6c3b0f | 1318 | static int musb_gadget_set_wedge(struct usb_ep *ep) |
47e97605 SS |
1319 | { |
1320 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1321 | ||
1322 | if (!ep) | |
1323 | return -EINVAL; | |
1324 | ||
1325 | musb_ep->wedged = 1; | |
1326 | ||
1327 | return usb_ep_set_halt(ep); | |
1328 | } | |
1329 | ||
550a7375 FB |
1330 | static int musb_gadget_fifo_status(struct usb_ep *ep) |
1331 | { | |
1332 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1333 | void __iomem *epio = musb_ep->hw_ep->regs; | |
1334 | int retval = -EINVAL; | |
1335 | ||
1336 | if (musb_ep->desc && !musb_ep->is_in) { | |
1337 | struct musb *musb = musb_ep->musb; | |
1338 | int epnum = musb_ep->current_epnum; | |
1339 | void __iomem *mbase = musb->mregs; | |
1340 | unsigned long flags; | |
1341 | ||
1342 | spin_lock_irqsave(&musb->lock, flags); | |
1343 | ||
1344 | musb_ep_select(mbase, epnum); | |
1345 | /* FIXME return zero unless RXPKTRDY is set */ | |
1346 | retval = musb_readw(epio, MUSB_RXCOUNT); | |
1347 | ||
1348 | spin_unlock_irqrestore(&musb->lock, flags); | |
1349 | } | |
1350 | return retval; | |
1351 | } | |
1352 | ||
1353 | static void musb_gadget_fifo_flush(struct usb_ep *ep) | |
1354 | { | |
1355 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1356 | struct musb *musb = musb_ep->musb; | |
1357 | u8 epnum = musb_ep->current_epnum; | |
1358 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1359 | void __iomem *mbase; | |
1360 | unsigned long flags; | |
1361 | u16 csr, int_txe; | |
1362 | ||
1363 | mbase = musb->mregs; | |
1364 | ||
1365 | spin_lock_irqsave(&musb->lock, flags); | |
1366 | musb_ep_select(mbase, (u8) epnum); | |
1367 | ||
1368 | /* disable interrupts */ | |
1369 | int_txe = musb_readw(mbase, MUSB_INTRTXE); | |
1370 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); | |
1371 | ||
1372 | if (musb_ep->is_in) { | |
1373 | csr = musb_readw(epio, MUSB_TXCSR); | |
1374 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1375 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; | |
1376 | musb_writew(epio, MUSB_TXCSR, csr); | |
1377 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1378 | musb_writew(epio, MUSB_TXCSR, csr); | |
1379 | } | |
1380 | } else { | |
1381 | csr = musb_readw(epio, MUSB_RXCSR); | |
1382 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; | |
1383 | musb_writew(epio, MUSB_RXCSR, csr); | |
1384 | musb_writew(epio, MUSB_RXCSR, csr); | |
1385 | } | |
1386 | ||
1387 | /* re-enable interrupt */ | |
1388 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
1389 | spin_unlock_irqrestore(&musb->lock, flags); | |
1390 | } | |
1391 | ||
1392 | static const struct usb_ep_ops musb_ep_ops = { | |
1393 | .enable = musb_gadget_enable, | |
1394 | .disable = musb_gadget_disable, | |
1395 | .alloc_request = musb_alloc_request, | |
1396 | .free_request = musb_free_request, | |
1397 | .queue = musb_gadget_queue, | |
1398 | .dequeue = musb_gadget_dequeue, | |
1399 | .set_halt = musb_gadget_set_halt, | |
47e97605 | 1400 | .set_wedge = musb_gadget_set_wedge, |
550a7375 FB |
1401 | .fifo_status = musb_gadget_fifo_status, |
1402 | .fifo_flush = musb_gadget_fifo_flush | |
1403 | }; | |
1404 | ||
1405 | /* ----------------------------------------------------------------------- */ | |
1406 | ||
1407 | static int musb_gadget_get_frame(struct usb_gadget *gadget) | |
1408 | { | |
1409 | struct musb *musb = gadget_to_musb(gadget); | |
1410 | ||
1411 | return (int)musb_readw(musb->mregs, MUSB_FRAME); | |
1412 | } | |
1413 | ||
1414 | static int musb_gadget_wakeup(struct usb_gadget *gadget) | |
1415 | { | |
1416 | struct musb *musb = gadget_to_musb(gadget); | |
1417 | void __iomem *mregs = musb->mregs; | |
1418 | unsigned long flags; | |
1419 | int status = -EINVAL; | |
1420 | u8 power, devctl; | |
1421 | int retries; | |
1422 | ||
1423 | spin_lock_irqsave(&musb->lock, flags); | |
1424 | ||
84e250ff | 1425 | switch (musb->xceiv->state) { |
550a7375 FB |
1426 | case OTG_STATE_B_PERIPHERAL: |
1427 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; | |
1428 | * that's part of the standard usb 1.1 state machine, and | |
1429 | * doesn't affect OTG transitions. | |
1430 | */ | |
1431 | if (musb->may_wakeup && musb->is_suspended) | |
1432 | break; | |
1433 | goto done; | |
1434 | case OTG_STATE_B_IDLE: | |
1435 | /* Start SRP ... OTG not required. */ | |
1436 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1437 | DBG(2, "Sending SRP: devctl: %02x\n", devctl); | |
1438 | devctl |= MUSB_DEVCTL_SESSION; | |
1439 | musb_writeb(mregs, MUSB_DEVCTL, devctl); | |
1440 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1441 | retries = 100; | |
1442 | while (!(devctl & MUSB_DEVCTL_SESSION)) { | |
1443 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1444 | if (retries-- < 1) | |
1445 | break; | |
1446 | } | |
1447 | retries = 10000; | |
1448 | while (devctl & MUSB_DEVCTL_SESSION) { | |
1449 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1450 | if (retries-- < 1) | |
1451 | break; | |
1452 | } | |
1453 | ||
1454 | /* Block idling for at least 1s */ | |
1455 | musb_platform_try_idle(musb, | |
1456 | jiffies + msecs_to_jiffies(1 * HZ)); | |
1457 | ||
1458 | status = 0; | |
1459 | goto done; | |
1460 | default: | |
1461 | DBG(2, "Unhandled wake: %s\n", otg_state_string(musb)); | |
1462 | goto done; | |
1463 | } | |
1464 | ||
1465 | status = 0; | |
1466 | ||
1467 | power = musb_readb(mregs, MUSB_POWER); | |
1468 | power |= MUSB_POWER_RESUME; | |
1469 | musb_writeb(mregs, MUSB_POWER, power); | |
1470 | DBG(2, "issue wakeup\n"); | |
1471 | ||
1472 | /* FIXME do this next chunk in a timer callback, no udelay */ | |
1473 | mdelay(2); | |
1474 | ||
1475 | power = musb_readb(mregs, MUSB_POWER); | |
1476 | power &= ~MUSB_POWER_RESUME; | |
1477 | musb_writeb(mregs, MUSB_POWER, power); | |
1478 | done: | |
1479 | spin_unlock_irqrestore(&musb->lock, flags); | |
1480 | return status; | |
1481 | } | |
1482 | ||
1483 | static int | |
1484 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) | |
1485 | { | |
1486 | struct musb *musb = gadget_to_musb(gadget); | |
1487 | ||
1488 | musb->is_self_powered = !!is_selfpowered; | |
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | static void musb_pullup(struct musb *musb, int is_on) | |
1493 | { | |
1494 | u8 power; | |
1495 | ||
1496 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1497 | if (is_on) | |
1498 | power |= MUSB_POWER_SOFTCONN; | |
1499 | else | |
1500 | power &= ~MUSB_POWER_SOFTCONN; | |
1501 | ||
1502 | /* FIXME if on, HdrcStart; if off, HdrcStop */ | |
1503 | ||
1504 | DBG(3, "gadget %s D+ pullup %s\n", | |
1505 | musb->gadget_driver->function, is_on ? "on" : "off"); | |
1506 | musb_writeb(musb->mregs, MUSB_POWER, power); | |
1507 | } | |
1508 | ||
1509 | #if 0 | |
1510 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) | |
1511 | { | |
1512 | DBG(2, "<= %s =>\n", __func__); | |
1513 | ||
1514 | /* | |
1515 | * FIXME iff driver's softconnect flag is set (as it is during probe, | |
1516 | * though that can clear it), just musb_pullup(). | |
1517 | */ | |
1518 | ||
1519 | return -EINVAL; | |
1520 | } | |
1521 | #endif | |
1522 | ||
1523 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1524 | { | |
1525 | struct musb *musb = gadget_to_musb(gadget); | |
1526 | ||
84e250ff | 1527 | if (!musb->xceiv->set_power) |
550a7375 | 1528 | return -EOPNOTSUPP; |
84e250ff | 1529 | return otg_set_power(musb->xceiv, mA); |
550a7375 FB |
1530 | } |
1531 | ||
1532 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1533 | { | |
1534 | struct musb *musb = gadget_to_musb(gadget); | |
1535 | unsigned long flags; | |
1536 | ||
1537 | is_on = !!is_on; | |
1538 | ||
1539 | /* NOTE: this assumes we are sensing vbus; we'd rather | |
1540 | * not pullup unless the B-session is active. | |
1541 | */ | |
1542 | spin_lock_irqsave(&musb->lock, flags); | |
1543 | if (is_on != musb->softconnect) { | |
1544 | musb->softconnect = is_on; | |
1545 | musb_pullup(musb, is_on); | |
1546 | } | |
1547 | spin_unlock_irqrestore(&musb->lock, flags); | |
1548 | return 0; | |
1549 | } | |
1550 | ||
1551 | static const struct usb_gadget_ops musb_gadget_operations = { | |
1552 | .get_frame = musb_gadget_get_frame, | |
1553 | .wakeup = musb_gadget_wakeup, | |
1554 | .set_selfpowered = musb_gadget_set_self_powered, | |
1555 | /* .vbus_session = musb_gadget_vbus_session, */ | |
1556 | .vbus_draw = musb_gadget_vbus_draw, | |
1557 | .pullup = musb_gadget_pullup, | |
1558 | }; | |
1559 | ||
1560 | /* ----------------------------------------------------------------------- */ | |
1561 | ||
1562 | /* Registration */ | |
1563 | ||
1564 | /* Only this registration code "knows" the rule (from USB standards) | |
1565 | * about there being only one external upstream port. It assumes | |
1566 | * all peripheral ports are external... | |
1567 | */ | |
1568 | static struct musb *the_gadget; | |
1569 | ||
1570 | static void musb_gadget_release(struct device *dev) | |
1571 | { | |
1572 | /* kref_put(WHAT) */ | |
1573 | dev_dbg(dev, "%s\n", __func__); | |
1574 | } | |
1575 | ||
1576 | ||
1577 | static void __init | |
1578 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) | |
1579 | { | |
1580 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1581 | ||
1582 | memset(ep, 0, sizeof *ep); | |
1583 | ||
1584 | ep->current_epnum = epnum; | |
1585 | ep->musb = musb; | |
1586 | ep->hw_ep = hw_ep; | |
1587 | ep->is_in = is_in; | |
1588 | ||
1589 | INIT_LIST_HEAD(&ep->req_list); | |
1590 | ||
1591 | sprintf(ep->name, "ep%d%s", epnum, | |
1592 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( | |
1593 | is_in ? "in" : "out")); | |
1594 | ep->end_point.name = ep->name; | |
1595 | INIT_LIST_HEAD(&ep->end_point.ep_list); | |
1596 | if (!epnum) { | |
1597 | ep->end_point.maxpacket = 64; | |
1598 | ep->end_point.ops = &musb_g_ep0_ops; | |
1599 | musb->g.ep0 = &ep->end_point; | |
1600 | } else { | |
1601 | if (is_in) | |
1602 | ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; | |
1603 | else | |
1604 | ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; | |
1605 | ep->end_point.ops = &musb_ep_ops; | |
1606 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | /* | |
1611 | * Initialize the endpoints exposed to peripheral drivers, with backlinks | |
1612 | * to the rest of the driver state. | |
1613 | */ | |
1614 | static inline void __init musb_g_init_endpoints(struct musb *musb) | |
1615 | { | |
1616 | u8 epnum; | |
1617 | struct musb_hw_ep *hw_ep; | |
1618 | unsigned count = 0; | |
1619 | ||
1620 | /* intialize endpoint list just once */ | |
1621 | INIT_LIST_HEAD(&(musb->g.ep_list)); | |
1622 | ||
1623 | for (epnum = 0, hw_ep = musb->endpoints; | |
1624 | epnum < musb->nr_endpoints; | |
1625 | epnum++, hw_ep++) { | |
1626 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1627 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); | |
1628 | count++; | |
1629 | } else { | |
1630 | if (hw_ep->max_packet_sz_tx) { | |
1631 | init_peripheral_ep(musb, &hw_ep->ep_in, | |
1632 | epnum, 1); | |
1633 | count++; | |
1634 | } | |
1635 | if (hw_ep->max_packet_sz_rx) { | |
1636 | init_peripheral_ep(musb, &hw_ep->ep_out, | |
1637 | epnum, 0); | |
1638 | count++; | |
1639 | } | |
1640 | } | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | /* called once during driver setup to initialize and link into | |
1645 | * the driver model; memory is zeroed. | |
1646 | */ | |
1647 | int __init musb_gadget_setup(struct musb *musb) | |
1648 | { | |
1649 | int status; | |
1650 | ||
1651 | /* REVISIT minor race: if (erroneously) setting up two | |
1652 | * musb peripherals at the same time, only the bus lock | |
1653 | * is probably held. | |
1654 | */ | |
1655 | if (the_gadget) | |
1656 | return -EBUSY; | |
1657 | the_gadget = musb; | |
1658 | ||
1659 | musb->g.ops = &musb_gadget_operations; | |
1660 | musb->g.is_dualspeed = 1; | |
1661 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1662 | ||
1663 | /* this "gadget" abstracts/virtualizes the controller */ | |
427c4f33 | 1664 | dev_set_name(&musb->g.dev, "gadget"); |
550a7375 FB |
1665 | musb->g.dev.parent = musb->controller; |
1666 | musb->g.dev.dma_mask = musb->controller->dma_mask; | |
1667 | musb->g.dev.release = musb_gadget_release; | |
1668 | musb->g.name = musb_driver_name; | |
1669 | ||
1670 | if (is_otg_enabled(musb)) | |
1671 | musb->g.is_otg = 1; | |
1672 | ||
1673 | musb_g_init_endpoints(musb); | |
1674 | ||
1675 | musb->is_active = 0; | |
1676 | musb_platform_try_idle(musb, 0); | |
1677 | ||
1678 | status = device_register(&musb->g.dev); | |
1679 | if (status != 0) | |
1680 | the_gadget = NULL; | |
1681 | return status; | |
1682 | } | |
1683 | ||
1684 | void musb_gadget_cleanup(struct musb *musb) | |
1685 | { | |
1686 | if (musb != the_gadget) | |
1687 | return; | |
1688 | ||
1689 | device_unregister(&musb->g.dev); | |
1690 | the_gadget = NULL; | |
1691 | } | |
1692 | ||
1693 | /* | |
1694 | * Register the gadget driver. Used by gadget drivers when | |
1695 | * registering themselves with the controller. | |
1696 | * | |
1697 | * -EINVAL something went wrong (not driver) | |
1698 | * -EBUSY another gadget is already using the controller | |
1699 | * -ENOMEM no memeory to perform the operation | |
1700 | * | |
1701 | * @param driver the gadget driver | |
1702 | * @return <0 if error, 0 if everything is fine | |
1703 | */ | |
1704 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | |
1705 | { | |
1706 | int retval; | |
1707 | unsigned long flags; | |
1708 | struct musb *musb = the_gadget; | |
1709 | ||
1710 | if (!driver | |
1711 | || driver->speed != USB_SPEED_HIGH | |
1712 | || !driver->bind | |
1713 | || !driver->setup) | |
1714 | return -EINVAL; | |
1715 | ||
1716 | /* driver must be initialized to support peripheral mode */ | |
08e6c972 | 1717 | if (!musb) { |
550a7375 FB |
1718 | DBG(1, "%s, no dev??\n", __func__); |
1719 | return -ENODEV; | |
1720 | } | |
1721 | ||
1722 | DBG(3, "registering driver %s\n", driver->function); | |
1723 | spin_lock_irqsave(&musb->lock, flags); | |
1724 | ||
1725 | if (musb->gadget_driver) { | |
1726 | DBG(1, "%s is already bound to %s\n", | |
1727 | musb_driver_name, | |
1728 | musb->gadget_driver->driver.name); | |
1729 | retval = -EBUSY; | |
1730 | } else { | |
1731 | musb->gadget_driver = driver; | |
1732 | musb->g.dev.driver = &driver->driver; | |
1733 | driver->driver.bus = NULL; | |
1734 | musb->softconnect = 1; | |
1735 | retval = 0; | |
1736 | } | |
1737 | ||
1738 | spin_unlock_irqrestore(&musb->lock, flags); | |
1739 | ||
f362a475 | 1740 | if (retval == 0) { |
550a7375 | 1741 | retval = driver->bind(&musb->g); |
f362a475 FB |
1742 | if (retval != 0) { |
1743 | DBG(3, "bind to driver %s failed --> %d\n", | |
1744 | driver->driver.name, retval); | |
1745 | musb->gadget_driver = NULL; | |
1746 | musb->g.dev.driver = NULL; | |
1747 | } | |
550a7375 | 1748 | |
550a7375 FB |
1749 | spin_lock_irqsave(&musb->lock, flags); |
1750 | ||
84e250ff | 1751 | otg_set_peripheral(musb->xceiv, &musb->g); |
d4c433fe | 1752 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
1753 | musb->is_active = 1; |
1754 | ||
1755 | /* FIXME this ignores the softconnect flag. Drivers are | |
1756 | * allowed hold the peripheral inactive until for example | |
1757 | * userspace hooks up printer hardware or DSP codecs, so | |
1758 | * hosts only see fully functional devices. | |
1759 | */ | |
1760 | ||
1761 | if (!is_otg_enabled(musb)) | |
1762 | musb_start(musb); | |
1763 | ||
84e250ff DB |
1764 | otg_set_peripheral(musb->xceiv, &musb->g); |
1765 | ||
550a7375 FB |
1766 | spin_unlock_irqrestore(&musb->lock, flags); |
1767 | ||
1768 | if (is_otg_enabled(musb)) { | |
1769 | DBG(3, "OTG startup...\n"); | |
1770 | ||
1771 | /* REVISIT: funcall to other code, which also | |
1772 | * handles power budgeting ... this way also | |
1773 | * ensures HdrcStart is indirectly called. | |
1774 | */ | |
1775 | retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
1776 | if (retval < 0) { | |
1777 | DBG(1, "add_hcd failed, %d\n", retval); | |
1778 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 1779 | otg_set_peripheral(musb->xceiv, NULL); |
550a7375 FB |
1780 | musb->gadget_driver = NULL; |
1781 | musb->g.dev.driver = NULL; | |
1782 | spin_unlock_irqrestore(&musb->lock, flags); | |
1783 | } | |
1784 | } | |
1785 | } | |
1786 | ||
1787 | return retval; | |
1788 | } | |
1789 | EXPORT_SYMBOL(usb_gadget_register_driver); | |
1790 | ||
1791 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) | |
1792 | { | |
1793 | int i; | |
1794 | struct musb_hw_ep *hw_ep; | |
1795 | ||
1796 | /* don't disconnect if it's not connected */ | |
1797 | if (musb->g.speed == USB_SPEED_UNKNOWN) | |
1798 | driver = NULL; | |
1799 | else | |
1800 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1801 | ||
1802 | /* deactivate the hardware */ | |
1803 | if (musb->softconnect) { | |
1804 | musb->softconnect = 0; | |
1805 | musb_pullup(musb, 0); | |
1806 | } | |
1807 | musb_stop(musb); | |
1808 | ||
1809 | /* killing any outstanding requests will quiesce the driver; | |
1810 | * then report disconnect | |
1811 | */ | |
1812 | if (driver) { | |
1813 | for (i = 0, hw_ep = musb->endpoints; | |
1814 | i < musb->nr_endpoints; | |
1815 | i++, hw_ep++) { | |
1816 | musb_ep_select(musb->mregs, i); | |
1817 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1818 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1819 | } else { | |
1820 | if (hw_ep->max_packet_sz_tx) | |
1821 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1822 | if (hw_ep->max_packet_sz_rx) | |
1823 | nuke(&hw_ep->ep_out, -ESHUTDOWN); | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | spin_unlock(&musb->lock); | |
1828 | driver->disconnect(&musb->g); | |
1829 | spin_lock(&musb->lock); | |
1830 | } | |
1831 | } | |
1832 | ||
1833 | /* | |
1834 | * Unregister the gadget driver. Used by gadget drivers when | |
1835 | * unregistering themselves from the controller. | |
1836 | * | |
1837 | * @param driver the gadget driver to unregister | |
1838 | */ | |
1839 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1840 | { | |
1841 | unsigned long flags; | |
1842 | int retval = 0; | |
1843 | struct musb *musb = the_gadget; | |
1844 | ||
1845 | if (!driver || !driver->unbind || !musb) | |
1846 | return -EINVAL; | |
1847 | ||
1848 | /* REVISIT always use otg_set_peripheral() here too; | |
1849 | * this needs to shut down the OTG engine. | |
1850 | */ | |
1851 | ||
1852 | spin_lock_irqsave(&musb->lock, flags); | |
1853 | ||
1854 | #ifdef CONFIG_USB_MUSB_OTG | |
1855 | musb_hnp_stop(musb); | |
1856 | #endif | |
1857 | ||
1858 | if (musb->gadget_driver == driver) { | |
1859 | ||
1860 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1861 | ||
84e250ff | 1862 | musb->xceiv->state = OTG_STATE_UNDEFINED; |
550a7375 | 1863 | stop_activity(musb, driver); |
84e250ff | 1864 | otg_set_peripheral(musb->xceiv, NULL); |
550a7375 FB |
1865 | |
1866 | DBG(3, "unregistering driver %s\n", driver->function); | |
1867 | spin_unlock_irqrestore(&musb->lock, flags); | |
1868 | driver->unbind(&musb->g); | |
1869 | spin_lock_irqsave(&musb->lock, flags); | |
1870 | ||
1871 | musb->gadget_driver = NULL; | |
1872 | musb->g.dev.driver = NULL; | |
1873 | ||
1874 | musb->is_active = 0; | |
1875 | musb_platform_try_idle(musb, 0); | |
1876 | } else | |
1877 | retval = -EINVAL; | |
1878 | spin_unlock_irqrestore(&musb->lock, flags); | |
1879 | ||
1880 | if (is_otg_enabled(musb) && retval == 0) { | |
1881 | usb_remove_hcd(musb_to_hcd(musb)); | |
1882 | /* FIXME we need to be able to register another | |
1883 | * gadget driver here and have everything work; | |
1884 | * that currently misbehaves. | |
1885 | */ | |
1886 | } | |
1887 | ||
1888 | return retval; | |
1889 | } | |
1890 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1891 | ||
1892 | ||
1893 | /* ----------------------------------------------------------------------- */ | |
1894 | ||
1895 | /* lifecycle operations called through plat_uds.c */ | |
1896 | ||
1897 | void musb_g_resume(struct musb *musb) | |
1898 | { | |
1899 | musb->is_suspended = 0; | |
84e250ff | 1900 | switch (musb->xceiv->state) { |
550a7375 FB |
1901 | case OTG_STATE_B_IDLE: |
1902 | break; | |
1903 | case OTG_STATE_B_WAIT_ACON: | |
1904 | case OTG_STATE_B_PERIPHERAL: | |
1905 | musb->is_active = 1; | |
1906 | if (musb->gadget_driver && musb->gadget_driver->resume) { | |
1907 | spin_unlock(&musb->lock); | |
1908 | musb->gadget_driver->resume(&musb->g); | |
1909 | spin_lock(&musb->lock); | |
1910 | } | |
1911 | break; | |
1912 | default: | |
1913 | WARNING("unhandled RESUME transition (%s)\n", | |
1914 | otg_state_string(musb)); | |
1915 | } | |
1916 | } | |
1917 | ||
1918 | /* called when SOF packets stop for 3+ msec */ | |
1919 | void musb_g_suspend(struct musb *musb) | |
1920 | { | |
1921 | u8 devctl; | |
1922 | ||
1923 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1924 | DBG(3, "devctl %02x\n", devctl); | |
1925 | ||
84e250ff | 1926 | switch (musb->xceiv->state) { |
550a7375 FB |
1927 | case OTG_STATE_B_IDLE: |
1928 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
84e250ff | 1929 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
1930 | break; |
1931 | case OTG_STATE_B_PERIPHERAL: | |
1932 | musb->is_suspended = 1; | |
1933 | if (musb->gadget_driver && musb->gadget_driver->suspend) { | |
1934 | spin_unlock(&musb->lock); | |
1935 | musb->gadget_driver->suspend(&musb->g); | |
1936 | spin_lock(&musb->lock); | |
1937 | } | |
1938 | break; | |
1939 | default: | |
1940 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; | |
1941 | * A_PERIPHERAL may need care too | |
1942 | */ | |
1943 | WARNING("unhandled SUSPEND transition (%s)\n", | |
1944 | otg_state_string(musb)); | |
1945 | } | |
1946 | } | |
1947 | ||
1948 | /* Called during SRP */ | |
1949 | void musb_g_wakeup(struct musb *musb) | |
1950 | { | |
1951 | musb_gadget_wakeup(&musb->g); | |
1952 | } | |
1953 | ||
1954 | /* called when VBUS drops below session threshold, and in other cases */ | |
1955 | void musb_g_disconnect(struct musb *musb) | |
1956 | { | |
1957 | void __iomem *mregs = musb->mregs; | |
1958 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1959 | ||
1960 | DBG(3, "devctl %02x\n", devctl); | |
1961 | ||
1962 | /* clear HR */ | |
1963 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); | |
1964 | ||
1965 | /* don't draw vbus until new b-default session */ | |
1966 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1967 | ||
1968 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1969 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { | |
1970 | spin_unlock(&musb->lock); | |
1971 | musb->gadget_driver->disconnect(&musb->g); | |
1972 | spin_lock(&musb->lock); | |
1973 | } | |
1974 | ||
84e250ff | 1975 | switch (musb->xceiv->state) { |
550a7375 FB |
1976 | default: |
1977 | #ifdef CONFIG_USB_MUSB_OTG | |
1978 | DBG(2, "Unhandled disconnect %s, setting a_idle\n", | |
1979 | otg_state_string(musb)); | |
84e250ff | 1980 | musb->xceiv->state = OTG_STATE_A_IDLE; |
ab983f2a | 1981 | MUSB_HST_MODE(musb); |
550a7375 FB |
1982 | break; |
1983 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae | 1984 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
ab983f2a | 1985 | MUSB_HST_MODE(musb); |
550a7375 FB |
1986 | break; |
1987 | case OTG_STATE_B_WAIT_ACON: | |
1988 | case OTG_STATE_B_HOST: | |
1989 | #endif | |
1990 | case OTG_STATE_B_PERIPHERAL: | |
1991 | case OTG_STATE_B_IDLE: | |
84e250ff | 1992 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
1993 | break; |
1994 | case OTG_STATE_B_SRP_INIT: | |
1995 | break; | |
1996 | } | |
1997 | ||
1998 | musb->is_active = 0; | |
1999 | } | |
2000 | ||
2001 | void musb_g_reset(struct musb *musb) | |
2002 | __releases(musb->lock) | |
2003 | __acquires(musb->lock) | |
2004 | { | |
2005 | void __iomem *mbase = musb->mregs; | |
2006 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); | |
2007 | u8 power; | |
2008 | ||
2009 | DBG(3, "<== %s addr=%x driver '%s'\n", | |
2010 | (devctl & MUSB_DEVCTL_BDEVICE) | |
2011 | ? "B-Device" : "A-Device", | |
2012 | musb_readb(mbase, MUSB_FADDR), | |
2013 | musb->gadget_driver | |
2014 | ? musb->gadget_driver->driver.name | |
2015 | : NULL | |
2016 | ); | |
2017 | ||
2018 | /* report disconnect, if we didn't already (flushing EP state) */ | |
2019 | if (musb->g.speed != USB_SPEED_UNKNOWN) | |
2020 | musb_g_disconnect(musb); | |
2021 | ||
2022 | /* clear HR */ | |
2023 | else if (devctl & MUSB_DEVCTL_HR) | |
2024 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
2025 | ||
2026 | ||
2027 | /* what speed did we negotiate? */ | |
2028 | power = musb_readb(mbase, MUSB_POWER); | |
2029 | musb->g.speed = (power & MUSB_POWER_HSMODE) | |
2030 | ? USB_SPEED_HIGH : USB_SPEED_FULL; | |
2031 | ||
2032 | /* start in USB_STATE_DEFAULT */ | |
2033 | musb->is_active = 1; | |
2034 | musb->is_suspended = 0; | |
2035 | MUSB_DEV_MODE(musb); | |
2036 | musb->address = 0; | |
2037 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; | |
2038 | ||
2039 | musb->may_wakeup = 0; | |
2040 | musb->g.b_hnp_enable = 0; | |
2041 | musb->g.a_alt_hnp_support = 0; | |
2042 | musb->g.a_hnp_support = 0; | |
2043 | ||
2044 | /* Normal reset, as B-Device; | |
2045 | * or else after HNP, as A-Device | |
2046 | */ | |
2047 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
84e250ff | 2048 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
2049 | musb->g.is_a_peripheral = 0; |
2050 | } else if (is_otg_enabled(musb)) { | |
84e250ff | 2051 | musb->xceiv->state = OTG_STATE_A_PERIPHERAL; |
550a7375 FB |
2052 | musb->g.is_a_peripheral = 1; |
2053 | } else | |
2054 | WARN_ON(1); | |
2055 | ||
2056 | /* start with default limits on VBUS power draw */ | |
2057 | (void) musb_gadget_vbus_draw(&musb->g, | |
2058 | is_otg_enabled(musb) ? 8 : 100); | |
2059 | } |