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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 SS |
69 | #include "xhci.h" |
70 | ||
71 | /* | |
72 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
73 | * address of the TRB. | |
74 | */ | |
23e3be11 | 75 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
76 | union xhci_trb *trb) |
77 | { | |
6071d836 | 78 | unsigned long segment_offset; |
7f84eef0 | 79 | |
6071d836 | 80 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 81 | return 0; |
6071d836 SS |
82 | /* offset in TRBs */ |
83 | segment_offset = trb - seg->trbs; | |
84 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 85 | return 0; |
6071d836 | 86 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
87 | } |
88 | ||
89 | /* Does this link TRB point to the first segment in a ring, | |
90 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
91 | */ | |
92 | static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
93 | struct xhci_segment *seg, union xhci_trb *trb) | |
94 | { | |
95 | if (ring == xhci->event_ring) | |
96 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
97 | (seg->next == xhci->event_ring->first_seg); | |
98 | else | |
99 | return trb->link.control & LINK_TOGGLE; | |
100 | } | |
101 | ||
102 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
103 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
104 | * event seg? | |
105 | */ | |
106 | static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
107 | struct xhci_segment *seg, union xhci_trb *trb) | |
108 | { | |
109 | if (ring == xhci->event_ring) | |
110 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
111 | else | |
112 | return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK); | |
113 | } | |
114 | ||
ae636747 SS |
115 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
116 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
117 | * effect the ring dequeue or enqueue pointers. | |
118 | */ | |
119 | static void next_trb(struct xhci_hcd *xhci, | |
120 | struct xhci_ring *ring, | |
121 | struct xhci_segment **seg, | |
122 | union xhci_trb **trb) | |
123 | { | |
124 | if (last_trb(xhci, ring, *seg, *trb)) { | |
125 | *seg = (*seg)->next; | |
126 | *trb = ((*seg)->trbs); | |
127 | } else { | |
128 | *trb = (*trb)++; | |
129 | } | |
130 | } | |
131 | ||
7f84eef0 SS |
132 | /* |
133 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
134 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
135 | */ | |
136 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) | |
137 | { | |
138 | union xhci_trb *next = ++(ring->dequeue); | |
66e49d87 | 139 | unsigned long long addr; |
7f84eef0 SS |
140 | |
141 | ring->deq_updates++; | |
142 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
143 | * the end of an event ring segment (which doesn't have link TRBS) | |
144 | */ | |
145 | while (last_trb(xhci, ring, ring->deq_seg, next)) { | |
146 | if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { | |
147 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
148 | if (!in_interrupt()) | |
700e2052 GKH |
149 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
150 | ring, | |
7f84eef0 SS |
151 | (unsigned int) ring->cycle_state); |
152 | } | |
153 | ring->deq_seg = ring->deq_seg->next; | |
154 | ring->dequeue = ring->deq_seg->trbs; | |
155 | next = ring->dequeue; | |
156 | } | |
66e49d87 SS |
157 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
158 | if (ring == xhci->event_ring) | |
159 | xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); | |
160 | else if (ring == xhci->cmd_ring) | |
161 | xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); | |
162 | else | |
163 | xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
164 | } |
165 | ||
166 | /* | |
167 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
168 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
169 | * | |
170 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
171 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
172 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
173 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
174 | * | |
175 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
176 | * set, but other sections talk about dealing with the chain bit set. This was |
177 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
178 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
7f84eef0 SS |
179 | */ |
180 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) | |
181 | { | |
182 | u32 chain; | |
183 | union xhci_trb *next; | |
66e49d87 | 184 | unsigned long long addr; |
7f84eef0 SS |
185 | |
186 | chain = ring->enqueue->generic.field[3] & TRB_CHAIN; | |
187 | next = ++(ring->enqueue); | |
188 | ||
189 | ring->enq_updates++; | |
190 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
191 | * the end of an event ring segment (which doesn't have link TRBS) | |
192 | */ | |
193 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
194 | if (!consumer) { | |
195 | if (ring != xhci->event_ring) { | |
b0567b3f SS |
196 | /* If we're not dealing with 0.95 hardware, |
197 | * carry over the chain bit of the previous TRB | |
198 | * (which may mean the chain bit is cleared). | |
199 | */ | |
200 | if (!xhci_link_trb_quirk(xhci)) { | |
201 | next->link.control &= ~TRB_CHAIN; | |
202 | next->link.control |= chain; | |
203 | } | |
7f84eef0 | 204 | /* Give this link TRB to the hardware */ |
b7116ebc | 205 | wmb(); |
7f84eef0 SS |
206 | if (next->link.control & TRB_CYCLE) |
207 | next->link.control &= (u32) ~TRB_CYCLE; | |
208 | else | |
209 | next->link.control |= (u32) TRB_CYCLE; | |
7f84eef0 SS |
210 | } |
211 | /* Toggle the cycle bit after the last ring segment. */ | |
212 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
213 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
214 | if (!in_interrupt()) | |
700e2052 GKH |
215 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
216 | ring, | |
7f84eef0 SS |
217 | (unsigned int) ring->cycle_state); |
218 | } | |
219 | } | |
220 | ring->enq_seg = ring->enq_seg->next; | |
221 | ring->enqueue = ring->enq_seg->trbs; | |
222 | next = ring->enqueue; | |
223 | } | |
66e49d87 SS |
224 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
225 | if (ring == xhci->event_ring) | |
226 | xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); | |
227 | else if (ring == xhci->cmd_ring) | |
228 | xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); | |
229 | else | |
230 | xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
231 | } |
232 | ||
233 | /* | |
234 | * Check to see if there's room to enqueue num_trbs on the ring. See rules | |
235 | * above. | |
236 | * FIXME: this would be simpler and faster if we just kept track of the number | |
237 | * of free TRBs in a ring. | |
238 | */ | |
239 | static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
240 | unsigned int num_trbs) | |
241 | { | |
242 | int i; | |
243 | union xhci_trb *enq = ring->enqueue; | |
244 | struct xhci_segment *enq_seg = ring->enq_seg; | |
44ebd037 SS |
245 | struct xhci_segment *cur_seg; |
246 | unsigned int left_on_ring; | |
7f84eef0 SS |
247 | |
248 | /* Check if ring is empty */ | |
44ebd037 SS |
249 | if (enq == ring->dequeue) { |
250 | /* Can't use link trbs */ | |
251 | left_on_ring = TRBS_PER_SEGMENT - 1; | |
252 | for (cur_seg = enq_seg->next; cur_seg != enq_seg; | |
253 | cur_seg = cur_seg->next) | |
254 | left_on_ring += TRBS_PER_SEGMENT - 1; | |
255 | ||
256 | /* Always need one TRB free in the ring. */ | |
257 | left_on_ring -= 1; | |
258 | if (num_trbs > left_on_ring) { | |
259 | xhci_warn(xhci, "Not enough room on ring; " | |
260 | "need %u TRBs, %u TRBs left\n", | |
261 | num_trbs, left_on_ring); | |
262 | return 0; | |
263 | } | |
7f84eef0 | 264 | return 1; |
44ebd037 | 265 | } |
7f84eef0 SS |
266 | /* Make sure there's an extra empty TRB available */ |
267 | for (i = 0; i <= num_trbs; ++i) { | |
268 | if (enq == ring->dequeue) | |
269 | return 0; | |
270 | enq++; | |
271 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
272 | enq_seg = enq_seg->next; | |
273 | enq = enq_seg->trbs; | |
274 | } | |
275 | } | |
276 | return 1; | |
277 | } | |
278 | ||
23e3be11 | 279 | void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
7f84eef0 | 280 | { |
8e595a5d | 281 | u64 temp; |
7f84eef0 SS |
282 | dma_addr_t deq; |
283 | ||
23e3be11 | 284 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, |
7f84eef0 SS |
285 | xhci->event_ring->dequeue); |
286 | if (deq == 0 && !in_interrupt()) | |
287 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
288 | "dequeue ptr.\n"); | |
289 | /* Update HC event ring dequeue pointer */ | |
8e595a5d | 290 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
7f84eef0 | 291 | temp &= ERST_PTR_MASK; |
2d83109b SS |
292 | /* Don't clear the EHB bit (which is RW1C) because |
293 | * there might be more events to service. | |
294 | */ | |
295 | temp &= ~ERST_EHB; | |
66e49d87 | 296 | xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n"); |
8e595a5d SS |
297 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
298 | &xhci->ir_set->erst_dequeue); | |
7f84eef0 SS |
299 | } |
300 | ||
301 | /* Ring the host controller doorbell after placing a command on the ring */ | |
23e3be11 | 302 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 SS |
303 | { |
304 | u32 temp; | |
305 | ||
306 | xhci_dbg(xhci, "// Ding dong!\n"); | |
307 | temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK; | |
308 | xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]); | |
309 | /* Flush PCI posted writes */ | |
310 | xhci_readl(xhci, &xhci->dba->doorbell[0]); | |
311 | } | |
312 | ||
ae636747 SS |
313 | static void ring_ep_doorbell(struct xhci_hcd *xhci, |
314 | unsigned int slot_id, | |
315 | unsigned int ep_index) | |
316 | { | |
63a0d9ab SS |
317 | struct xhci_virt_ep *ep; |
318 | unsigned int ep_state; | |
ae636747 SS |
319 | u32 field; |
320 | __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; | |
321 | ||
63a0d9ab SS |
322 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
323 | ep_state = ep->ep_state; | |
ae636747 SS |
324 | /* Don't ring the doorbell for this endpoint if there are pending |
325 | * cancellations because the we don't want to interrupt processing. | |
8df75f42 SS |
326 | * We don't want to restart any stream rings if there's a set dequeue |
327 | * pointer command pending because the device can choose to start any | |
328 | * stream once the endpoint is on the HW schedule. | |
329 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 330 | */ |
678539cf | 331 | if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING) |
63a0d9ab | 332 | && !(ep_state & EP_HALTED)) { |
ae636747 SS |
333 | field = xhci_readl(xhci, db_addr) & DB_MASK; |
334 | xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr); | |
335 | /* Flush PCI posted writes - FIXME Matthew Wilcox says this | |
336 | * isn't time-critical and we shouldn't make the CPU wait for | |
337 | * the flush. | |
338 | */ | |
339 | xhci_readl(xhci, db_addr); | |
340 | } | |
341 | } | |
342 | ||
343 | /* | |
344 | * Find the segment that trb is in. Start searching in start_seg. | |
345 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
346 | * bit set, then we will toggle the value pointed at by cycle_state. | |
347 | */ | |
348 | static struct xhci_segment *find_trb_seg( | |
349 | struct xhci_segment *start_seg, | |
350 | union xhci_trb *trb, int *cycle_state) | |
351 | { | |
352 | struct xhci_segment *cur_seg = start_seg; | |
353 | struct xhci_generic_trb *generic_trb; | |
354 | ||
355 | while (cur_seg->trbs > trb || | |
356 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
357 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
358 | if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK && | |
359 | (generic_trb->field[3] & LINK_TOGGLE)) | |
360 | *cycle_state = ~(*cycle_state) & 0x1; | |
361 | cur_seg = cur_seg->next; | |
362 | if (cur_seg == start_seg) | |
363 | /* Looped over the entire list. Oops! */ | |
364 | return 0; | |
365 | } | |
366 | return cur_seg; | |
367 | } | |
368 | ||
ae636747 SS |
369 | /* |
370 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
371 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
372 | * dequeue pointer, and new consumer cycle state in state. | |
373 | * Update our internal representation of the ring's dequeue pointer. | |
374 | * | |
375 | * We do this in three jumps: | |
376 | * - First we update our new ring state to be the same as when the xHC stopped. | |
377 | * - Then we traverse the ring to find the segment that contains | |
378 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
379 | * any link TRBs with the toggle cycle bit set. | |
380 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
381 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
382 | */ | |
c92bcfa7 | 383 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 384 | unsigned int slot_id, unsigned int ep_index, |
c92bcfa7 | 385 | struct xhci_td *cur_td, struct xhci_dequeue_state *state) |
ae636747 SS |
386 | { |
387 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
63a0d9ab | 388 | struct xhci_ring *ep_ring = dev->eps[ep_index].ring; |
ae636747 | 389 | struct xhci_generic_trb *trb; |
d115b048 | 390 | struct xhci_ep_ctx *ep_ctx; |
c92bcfa7 | 391 | dma_addr_t addr; |
ae636747 SS |
392 | |
393 | state->new_cycle_state = 0; | |
c92bcfa7 | 394 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
ae636747 | 395 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
63a0d9ab | 396 | dev->eps[ep_index].stopped_trb, |
ae636747 SS |
397 | &state->new_cycle_state); |
398 | if (!state->new_deq_seg) | |
399 | BUG(); | |
400 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ | |
c92bcfa7 | 401 | xhci_dbg(xhci, "Finding endpoint context\n"); |
d115b048 JY |
402 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
403 | state->new_cycle_state = 0x1 & ep_ctx->deq; | |
ae636747 SS |
404 | |
405 | state->new_deq_ptr = cur_td->last_trb; | |
c92bcfa7 | 406 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
ae636747 SS |
407 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
408 | state->new_deq_ptr, | |
409 | &state->new_cycle_state); | |
410 | if (!state->new_deq_seg) | |
411 | BUG(); | |
412 | ||
413 | trb = &state->new_deq_ptr->generic; | |
414 | if (TRB_TYPE(trb->field[3]) == TRB_LINK && | |
415 | (trb->field[3] & LINK_TOGGLE)) | |
416 | state->new_cycle_state = ~(state->new_cycle_state) & 0x1; | |
417 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); | |
418 | ||
419 | /* Don't update the ring cycle state for the producer (us). */ | |
c92bcfa7 SS |
420 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
421 | state->new_deq_seg); | |
422 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
423 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", | |
424 | (unsigned long long) addr); | |
425 | xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n"); | |
ae636747 SS |
426 | ep_ring->dequeue = state->new_deq_ptr; |
427 | ep_ring->deq_seg = state->new_deq_seg; | |
428 | } | |
429 | ||
23e3be11 | 430 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
ae636747 SS |
431 | struct xhci_td *cur_td) |
432 | { | |
433 | struct xhci_segment *cur_seg; | |
434 | union xhci_trb *cur_trb; | |
435 | ||
436 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
437 | true; | |
438 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
439 | if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) == | |
440 | TRB_TYPE(TRB_LINK)) { | |
441 | /* Unchain any chained Link TRBs, but | |
442 | * leave the pointers intact. | |
443 | */ | |
444 | cur_trb->generic.field[3] &= ~TRB_CHAIN; | |
445 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); | |
700e2052 GKH |
446 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
447 | "in seg %p (0x%llx dma)\n", | |
448 | cur_trb, | |
23e3be11 | 449 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
450 | cur_seg, |
451 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
452 | } else { |
453 | cur_trb->generic.field[0] = 0; | |
454 | cur_trb->generic.field[1] = 0; | |
455 | cur_trb->generic.field[2] = 0; | |
456 | /* Preserve only the cycle bit of this TRB */ | |
457 | cur_trb->generic.field[3] &= TRB_CYCLE; | |
458 | cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP); | |
700e2052 GKH |
459 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " |
460 | "in seg %p (0x%llx dma)\n", | |
461 | cur_trb, | |
23e3be11 | 462 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
463 | cur_seg, |
464 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
465 | } |
466 | if (cur_trb == cur_td->last_trb) | |
467 | break; | |
468 | } | |
469 | } | |
470 | ||
471 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
472 | unsigned int ep_index, struct xhci_segment *deq_seg, | |
473 | union xhci_trb *deq_ptr, u32 cycle_state); | |
474 | ||
c92bcfa7 | 475 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab SS |
476 | unsigned int slot_id, unsigned int ep_index, |
477 | struct xhci_dequeue_state *deq_state) | |
c92bcfa7 | 478 | { |
63a0d9ab SS |
479 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
480 | ||
c92bcfa7 SS |
481 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
482 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", | |
483 | deq_state->new_deq_seg, | |
484 | (unsigned long long)deq_state->new_deq_seg->dma, | |
485 | deq_state->new_deq_ptr, | |
486 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
487 | deq_state->new_cycle_state); | |
488 | queue_set_tr_deq(xhci, slot_id, ep_index, | |
489 | deq_state->new_deq_seg, | |
490 | deq_state->new_deq_ptr, | |
491 | (u32) deq_state->new_cycle_state); | |
492 | /* Stop the TD queueing code from ringing the doorbell until | |
493 | * this command completes. The HC won't set the dequeue pointer | |
494 | * if the ring is running, and ringing the doorbell starts the | |
495 | * ring running. | |
496 | */ | |
63a0d9ab | 497 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
498 | } |
499 | ||
6f5165cf SS |
500 | static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
501 | struct xhci_virt_ep *ep) | |
502 | { | |
503 | ep->ep_state &= ~EP_HALT_PENDING; | |
504 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
505 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
506 | * (since we didn't successfully stop the watchdog timer). | |
507 | */ | |
508 | if (del_timer(&ep->stop_cmd_timer)) | |
509 | ep->stop_cmds_pending--; | |
510 | } | |
511 | ||
512 | /* Must be called with xhci->lock held in interrupt context */ | |
513 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
514 | struct xhci_td *cur_td, int status, char *adjective) | |
515 | { | |
516 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
517 | ||
518 | cur_td->urb->hcpriv = NULL; | |
519 | usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb); | |
520 | xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb); | |
521 | ||
522 | spin_unlock(&xhci->lock); | |
523 | usb_hcd_giveback_urb(hcd, cur_td->urb, status); | |
524 | kfree(cur_td); | |
525 | spin_lock(&xhci->lock); | |
526 | xhci_dbg(xhci, "%s URB given back\n", adjective); | |
527 | } | |
528 | ||
ae636747 SS |
529 | /* |
530 | * When we get a command completion for a Stop Endpoint Command, we need to | |
531 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
532 | * | |
533 | * 1. If the HW was in the middle of processing the TD that needs to be | |
534 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
535 | * in the TD with a Set Dequeue Pointer Command. | |
536 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
537 | * bit cleared) so that the HW will skip over them. | |
538 | */ | |
539 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, | |
540 | union xhci_trb *trb) | |
541 | { | |
542 | unsigned int slot_id; | |
543 | unsigned int ep_index; | |
544 | struct xhci_ring *ep_ring; | |
63a0d9ab | 545 | struct xhci_virt_ep *ep; |
ae636747 SS |
546 | struct list_head *entry; |
547 | struct xhci_td *cur_td = 0; | |
548 | struct xhci_td *last_unlinked_td; | |
549 | ||
c92bcfa7 | 550 | struct xhci_dequeue_state deq_state; |
ae636747 SS |
551 | |
552 | memset(&deq_state, 0, sizeof(deq_state)); | |
553 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
554 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
63a0d9ab SS |
555 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
556 | ep_ring = ep->ring; | |
ae636747 | 557 | |
678539cf | 558 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 559 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
678539cf | 560 | ring_ep_doorbell(xhci, slot_id, ep_index); |
ae636747 | 561 | return; |
678539cf | 562 | } |
ae636747 SS |
563 | |
564 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
565 | * We have the xHCI lock, so nothing can modify this list until we drop | |
566 | * it. We're also in the event handler, so we can't get re-interrupted | |
567 | * if another Stop Endpoint command completes | |
568 | */ | |
63a0d9ab | 569 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 570 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
700e2052 GKH |
571 | xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n", |
572 | cur_td->first_trb, | |
23e3be11 | 573 | (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb)); |
ae636747 SS |
574 | /* |
575 | * If we stopped on the TD we need to cancel, then we have to | |
576 | * move the xHC endpoint ring dequeue pointer past this TD. | |
577 | */ | |
63a0d9ab | 578 | if (cur_td == ep->stopped_td) |
c92bcfa7 | 579 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td, |
ae636747 SS |
580 | &deq_state); |
581 | else | |
582 | td_to_noop(xhci, ep_ring, cur_td); | |
583 | /* | |
584 | * The event handler won't see a completion for this TD anymore, | |
585 | * so remove it from the endpoint ring's TD list. Keep it in | |
586 | * the cancelled TD list for URB completion later. | |
587 | */ | |
588 | list_del(&cur_td->td_list); | |
ae636747 SS |
589 | } |
590 | last_unlinked_td = cur_td; | |
6f5165cf | 591 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
592 | |
593 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
594 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
63a0d9ab | 595 | xhci_queue_new_dequeue_state(xhci, |
c92bcfa7 | 596 | slot_id, ep_index, &deq_state); |
ac9d8fe7 | 597 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
598 | } else { |
599 | /* Otherwise just ring the doorbell to restart the ring */ | |
600 | ring_ep_doorbell(xhci, slot_id, ep_index); | |
601 | } | |
1624ae1c SS |
602 | ep->stopped_td = NULL; |
603 | ep->stopped_trb = NULL; | |
ae636747 SS |
604 | |
605 | /* | |
606 | * Drop the lock and complete the URBs in the cancelled TD list. | |
607 | * New TDs to be cancelled might be added to the end of the list before | |
608 | * we can complete all the URBs for the TDs we already unlinked. | |
609 | * So stop when we've completed the URB for the last TD we unlinked. | |
610 | */ | |
611 | do { | |
63a0d9ab | 612 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 SS |
613 | struct xhci_td, cancelled_td_list); |
614 | list_del(&cur_td->cancelled_td_list); | |
615 | ||
616 | /* Clean up the cancelled URB */ | |
ae636747 SS |
617 | /* Doesn't matter what we pass for status, since the core will |
618 | * just overwrite it (because the URB has been unlinked). | |
619 | */ | |
6f5165cf | 620 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
ae636747 | 621 | |
6f5165cf SS |
622 | /* Stop processing the cancelled list if the watchdog timer is |
623 | * running. | |
624 | */ | |
625 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
626 | return; | |
ae636747 SS |
627 | } while (cur_td != last_unlinked_td); |
628 | ||
629 | /* Return to the event handler with xhci->lock re-acquired */ | |
630 | } | |
631 | ||
6f5165cf SS |
632 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
633 | * In this case, we assume the host controller is broken or dying or dead. The | |
634 | * host may still be completing some other events, so we have to be careful to | |
635 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
636 | * through xhci->state. | |
637 | * | |
638 | * The timer may also fire if the host takes a very long time to respond to the | |
639 | * command, and the stop endpoint command completion handler cannot delete the | |
640 | * timer before the timer function is called. Another endpoint cancellation may | |
641 | * sneak in before the timer function can grab the lock, and that may queue | |
642 | * another stop endpoint command and add the timer back. So we cannot use a | |
643 | * simple flag to say whether there is a pending stop endpoint command for a | |
644 | * particular endpoint. | |
645 | * | |
646 | * Instead we use a combination of that flag and a counter for the number of | |
647 | * pending stop endpoint commands. If the timer is the tail end of the last | |
648 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
649 | * the host is dying. | |
650 | */ | |
651 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
652 | { | |
653 | struct xhci_hcd *xhci; | |
654 | struct xhci_virt_ep *ep; | |
655 | struct xhci_virt_ep *temp_ep; | |
656 | struct xhci_ring *ring; | |
657 | struct xhci_td *cur_td; | |
658 | int ret, i, j; | |
659 | ||
660 | ep = (struct xhci_virt_ep *) arg; | |
661 | xhci = ep->xhci; | |
662 | ||
663 | spin_lock(&xhci->lock); | |
664 | ||
665 | ep->stop_cmds_pending--; | |
666 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
667 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " | |
668 | "xHCI as DYING, exiting.\n"); | |
669 | spin_unlock(&xhci->lock); | |
670 | return; | |
671 | } | |
672 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
673 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " | |
674 | "exiting.\n"); | |
675 | spin_unlock(&xhci->lock); | |
676 | return; | |
677 | } | |
678 | ||
679 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
680 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
681 | /* Oops, HC is dead or dying or at least not responding to the stop | |
682 | * endpoint command. | |
683 | */ | |
684 | xhci->xhc_state |= XHCI_STATE_DYING; | |
685 | /* Disable interrupts from the host controller and start halting it */ | |
686 | xhci_quiesce(xhci); | |
687 | spin_unlock(&xhci->lock); | |
688 | ||
689 | ret = xhci_halt(xhci); | |
690 | ||
691 | spin_lock(&xhci->lock); | |
692 | if (ret < 0) { | |
693 | /* This is bad; the host is not responding to commands and it's | |
694 | * not allowing itself to be halted. At least interrupts are | |
695 | * disabled, so we can set HC_STATE_HALT and notify the | |
696 | * USB core. But if we call usb_hc_died(), it will attempt to | |
697 | * disconnect all device drivers under this host. Those | |
698 | * disconnect() methods will wait for all URBs to be unlinked, | |
699 | * so we must complete them. | |
700 | */ | |
701 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
702 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
703 | /* We could turn all TDs on the rings to no-ops. This won't | |
704 | * help if the host has cached part of the ring, and is slow if | |
705 | * we want to preserve the cycle bit. Skip it and hope the host | |
706 | * doesn't touch the memory. | |
707 | */ | |
708 | } | |
709 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
710 | if (!xhci->devs[i]) | |
711 | continue; | |
712 | for (j = 0; j < 31; j++) { | |
713 | temp_ep = &xhci->devs[i]->eps[j]; | |
714 | ring = temp_ep->ring; | |
715 | if (!ring) | |
716 | continue; | |
717 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " | |
718 | "ep index %u\n", i, j); | |
719 | while (!list_empty(&ring->td_list)) { | |
720 | cur_td = list_first_entry(&ring->td_list, | |
721 | struct xhci_td, | |
722 | td_list); | |
723 | list_del(&cur_td->td_list); | |
724 | if (!list_empty(&cur_td->cancelled_td_list)) | |
725 | list_del(&cur_td->cancelled_td_list); | |
726 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
727 | -ESHUTDOWN, "killed"); | |
728 | } | |
729 | while (!list_empty(&temp_ep->cancelled_td_list)) { | |
730 | cur_td = list_first_entry( | |
731 | &temp_ep->cancelled_td_list, | |
732 | struct xhci_td, | |
733 | cancelled_td_list); | |
734 | list_del(&cur_td->cancelled_td_list); | |
735 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
736 | -ESHUTDOWN, "killed"); | |
737 | } | |
738 | } | |
739 | } | |
740 | spin_unlock(&xhci->lock); | |
741 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | |
742 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); | |
743 | usb_hc_died(xhci_to_hcd(xhci)); | |
744 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
745 | } | |
746 | ||
ae636747 SS |
747 | /* |
748 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
749 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
750 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
751 | * endpoint doorbell to restart the ring, but only if there aren't more | |
752 | * cancellations pending. | |
753 | */ | |
754 | static void handle_set_deq_completion(struct xhci_hcd *xhci, | |
755 | struct xhci_event_cmd *event, | |
756 | union xhci_trb *trb) | |
757 | { | |
758 | unsigned int slot_id; | |
759 | unsigned int ep_index; | |
760 | struct xhci_ring *ep_ring; | |
761 | struct xhci_virt_device *dev; | |
d115b048 JY |
762 | struct xhci_ep_ctx *ep_ctx; |
763 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 SS |
764 | |
765 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
766 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
767 | dev = xhci->devs[slot_id]; | |
63a0d9ab | 768 | ep_ring = dev->eps[ep_index].ring; |
d115b048 JY |
769 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
770 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 SS |
771 | |
772 | if (GET_COMP_CODE(event->status) != COMP_SUCCESS) { | |
773 | unsigned int ep_state; | |
774 | unsigned int slot_state; | |
775 | ||
776 | switch (GET_COMP_CODE(event->status)) { | |
777 | case COMP_TRB_ERR: | |
778 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " | |
779 | "of stream ID configuration\n"); | |
780 | break; | |
781 | case COMP_CTX_STATE: | |
782 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " | |
783 | "to incorrect slot or ep state.\n"); | |
d115b048 | 784 | ep_state = ep_ctx->ep_info; |
ae636747 | 785 | ep_state &= EP_STATE_MASK; |
d115b048 | 786 | slot_state = slot_ctx->dev_state; |
ae636747 SS |
787 | slot_state = GET_SLOT_STATE(slot_state); |
788 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", | |
789 | slot_state, ep_state); | |
790 | break; | |
791 | case COMP_EBADSLT: | |
792 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " | |
793 | "slot %u was not enabled.\n", slot_id); | |
794 | break; | |
795 | default: | |
796 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " | |
797 | "completion code of %u.\n", | |
798 | GET_COMP_CODE(event->status)); | |
799 | break; | |
800 | } | |
801 | /* OK what do we do now? The endpoint state is hosed, and we | |
802 | * should never get to this point if the synchronization between | |
803 | * queueing, and endpoint state are correct. This might happen | |
804 | * if the device gets disconnected after we've finished | |
805 | * cancelling URBs, which might not be an error... | |
806 | */ | |
807 | } else { | |
8e595a5d | 808 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
d115b048 | 809 | ep_ctx->deq); |
ae636747 SS |
810 | } |
811 | ||
63a0d9ab | 812 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
ae636747 SS |
813 | ring_ep_doorbell(xhci, slot_id, ep_index); |
814 | } | |
815 | ||
a1587d97 SS |
816 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
817 | struct xhci_event_cmd *event, | |
818 | union xhci_trb *trb) | |
819 | { | |
820 | int slot_id; | |
821 | unsigned int ep_index; | |
ac9d8fe7 | 822 | struct xhci_ring *ep_ring; |
a1587d97 SS |
823 | |
824 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
825 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
63a0d9ab | 826 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
a1587d97 SS |
827 | /* This command will only fail if the endpoint wasn't halted, |
828 | * but we don't care. | |
829 | */ | |
830 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", | |
831 | (unsigned int) GET_COMP_CODE(event->status)); | |
832 | ||
ac9d8fe7 SS |
833 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
834 | * command complete before the endpoint can be used. Queue that here | |
835 | * because the HW can't handle two commands being queued in a row. | |
836 | */ | |
837 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
838 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); | |
839 | xhci_queue_configure_endpoint(xhci, | |
913a8a34 SS |
840 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
841 | false); | |
ac9d8fe7 SS |
842 | xhci_ring_cmd_db(xhci); |
843 | } else { | |
844 | /* Clear our internal halted state and restart the ring */ | |
63a0d9ab | 845 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 SS |
846 | ring_ep_doorbell(xhci, slot_id, ep_index); |
847 | } | |
a1587d97 | 848 | } |
ae636747 | 849 | |
a50c8aa9 SS |
850 | /* Check to see if a command in the device's command queue matches this one. |
851 | * Signal the completion or free the command, and return 1. Return 0 if the | |
852 | * completed command isn't at the head of the command list. | |
853 | */ | |
854 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
855 | struct xhci_virt_device *virt_dev, | |
856 | struct xhci_event_cmd *event) | |
857 | { | |
858 | struct xhci_command *command; | |
859 | ||
860 | if (list_empty(&virt_dev->cmd_list)) | |
861 | return 0; | |
862 | ||
863 | command = list_entry(virt_dev->cmd_list.next, | |
864 | struct xhci_command, cmd_list); | |
865 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
866 | return 0; | |
867 | ||
868 | command->status = | |
869 | GET_COMP_CODE(event->status); | |
870 | list_del(&command->cmd_list); | |
871 | if (command->completion) | |
872 | complete(command->completion); | |
873 | else | |
874 | xhci_free_command(xhci, command); | |
875 | return 1; | |
876 | } | |
877 | ||
7f84eef0 SS |
878 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
879 | struct xhci_event_cmd *event) | |
880 | { | |
3ffbba95 | 881 | int slot_id = TRB_TO_SLOT_ID(event->flags); |
7f84eef0 SS |
882 | u64 cmd_dma; |
883 | dma_addr_t cmd_dequeue_dma; | |
ac9d8fe7 | 884 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 885 | struct xhci_virt_device *virt_dev; |
ac9d8fe7 SS |
886 | unsigned int ep_index; |
887 | struct xhci_ring *ep_ring; | |
888 | unsigned int ep_state; | |
7f84eef0 | 889 | |
8e595a5d | 890 | cmd_dma = event->cmd_trb; |
23e3be11 | 891 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
7f84eef0 SS |
892 | xhci->cmd_ring->dequeue); |
893 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ | |
894 | if (cmd_dequeue_dma == 0) { | |
895 | xhci->error_bitmask |= 1 << 4; | |
896 | return; | |
897 | } | |
898 | /* Does the DMA address match our internal dequeue pointer address? */ | |
899 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
900 | xhci->error_bitmask |= 1 << 5; | |
901 | return; | |
902 | } | |
903 | switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) { | |
3ffbba95 SS |
904 | case TRB_TYPE(TRB_ENABLE_SLOT): |
905 | if (GET_COMP_CODE(event->status) == COMP_SUCCESS) | |
906 | xhci->slot_id = slot_id; | |
907 | else | |
908 | xhci->slot_id = 0; | |
909 | complete(&xhci->addr_dev); | |
910 | break; | |
911 | case TRB_TYPE(TRB_DISABLE_SLOT): | |
912 | if (xhci->devs[slot_id]) | |
913 | xhci_free_virt_device(xhci, slot_id); | |
914 | break; | |
f94e0186 | 915 | case TRB_TYPE(TRB_CONFIG_EP): |
913a8a34 | 916 | virt_dev = xhci->devs[slot_id]; |
a50c8aa9 | 917 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
913a8a34 | 918 | break; |
ac9d8fe7 SS |
919 | /* |
920 | * Configure endpoint commands can come from the USB core | |
921 | * configuration or alt setting changes, or because the HW | |
922 | * needed an extra configure endpoint command after a reset | |
8df75f42 SS |
923 | * endpoint command or streams were being configured. |
924 | * If the command was for a halted endpoint, the xHCI driver | |
925 | * is not waiting on the configure endpoint command. | |
ac9d8fe7 SS |
926 | */ |
927 | ctrl_ctx = xhci_get_input_control_ctx(xhci, | |
913a8a34 | 928 | virt_dev->in_ctx); |
ac9d8fe7 SS |
929 | /* Input ctx add_flags are the endpoint index plus one */ |
930 | ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1; | |
06df5729 SS |
931 | /* A usb_set_interface() call directly after clearing a halted |
932 | * condition may race on this quirky hardware. | |
933 | * Not worth worrying about, since this is prototype hardware. | |
934 | */ | |
ac9d8fe7 | 935 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
06df5729 SS |
936 | ep_index != (unsigned int) -1 && |
937 | ctrl_ctx->add_flags - SLOT_FLAG == | |
938 | ctrl_ctx->drop_flags) { | |
939 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
940 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
941 | if (!(ep_state & EP_HALTED)) | |
942 | goto bandwidth_change; | |
943 | xhci_dbg(xhci, "Completed config ep cmd - " | |
944 | "last ep index = %d, state = %d\n", | |
945 | ep_index, ep_state); | |
ac9d8fe7 | 946 | /* Clear our internal halted state and restart ring */ |
63a0d9ab | 947 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
ac9d8fe7 SS |
948 | ~EP_HALTED; |
949 | ring_ep_doorbell(xhci, slot_id, ep_index); | |
06df5729 | 950 | break; |
ac9d8fe7 | 951 | } |
06df5729 SS |
952 | bandwidth_change: |
953 | xhci_dbg(xhci, "Completed config ep cmd\n"); | |
954 | xhci->devs[slot_id]->cmd_status = | |
955 | GET_COMP_CODE(event->status); | |
956 | complete(&xhci->devs[slot_id]->cmd_completion); | |
f94e0186 | 957 | break; |
2d3f1fac | 958 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
ac1c1b7f SS |
959 | virt_dev = xhci->devs[slot_id]; |
960 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
961 | break; | |
2d3f1fac SS |
962 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); |
963 | complete(&xhci->devs[slot_id]->cmd_completion); | |
964 | break; | |
3ffbba95 SS |
965 | case TRB_TYPE(TRB_ADDR_DEV): |
966 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); | |
967 | complete(&xhci->addr_dev); | |
968 | break; | |
ae636747 SS |
969 | case TRB_TYPE(TRB_STOP_RING): |
970 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue); | |
971 | break; | |
972 | case TRB_TYPE(TRB_SET_DEQ): | |
973 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); | |
974 | break; | |
7f84eef0 SS |
975 | case TRB_TYPE(TRB_CMD_NOOP): |
976 | ++xhci->noops_handled; | |
977 | break; | |
a1587d97 SS |
978 | case TRB_TYPE(TRB_RESET_EP): |
979 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); | |
980 | break; | |
2a8f82c4 SS |
981 | case TRB_TYPE(TRB_RESET_DEV): |
982 | xhci_dbg(xhci, "Completed reset device command.\n"); | |
983 | slot_id = TRB_TO_SLOT_ID( | |
984 | xhci->cmd_ring->dequeue->generic.field[3]); | |
985 | virt_dev = xhci->devs[slot_id]; | |
986 | if (virt_dev) | |
987 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | |
988 | else | |
989 | xhci_warn(xhci, "Reset device command completion " | |
990 | "for disabled slot %u\n", slot_id); | |
991 | break; | |
7f84eef0 SS |
992 | default: |
993 | /* Skip over unknown commands on the event ring */ | |
994 | xhci->error_bitmask |= 1 << 6; | |
995 | break; | |
996 | } | |
997 | inc_deq(xhci, xhci->cmd_ring, false); | |
998 | } | |
999 | ||
0f2a7930 SS |
1000 | static void handle_port_status(struct xhci_hcd *xhci, |
1001 | union xhci_trb *event) | |
1002 | { | |
1003 | u32 port_id; | |
1004 | ||
1005 | /* Port status change events always have a successful completion code */ | |
1006 | if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { | |
1007 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); | |
1008 | xhci->error_bitmask |= 1 << 8; | |
1009 | } | |
1010 | /* FIXME: core doesn't care about all port link state changes yet */ | |
1011 | port_id = GET_PORT_ID(event->generic.field[0]); | |
1012 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); | |
1013 | ||
1014 | /* Update event ring dequeue pointer before dropping the lock */ | |
1015 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1016 | xhci_set_hc_event_deq(xhci); |
0f2a7930 SS |
1017 | |
1018 | spin_unlock(&xhci->lock); | |
1019 | /* Pass this up to the core */ | |
1020 | usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); | |
1021 | spin_lock(&xhci->lock); | |
1022 | } | |
1023 | ||
d0e96f5a SS |
1024 | /* |
1025 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1026 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1027 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1028 | * returns 0. | |
1029 | */ | |
6648f29d | 1030 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1031 | union xhci_trb *start_trb, |
1032 | union xhci_trb *end_trb, | |
1033 | dma_addr_t suspect_dma) | |
1034 | { | |
1035 | dma_addr_t start_dma; | |
1036 | dma_addr_t end_seg_dma; | |
1037 | dma_addr_t end_trb_dma; | |
1038 | struct xhci_segment *cur_seg; | |
1039 | ||
23e3be11 | 1040 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1041 | cur_seg = start_seg; |
1042 | ||
1043 | do { | |
2fa88daa SS |
1044 | if (start_dma == 0) |
1045 | return 0; | |
ae636747 | 1046 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1047 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1048 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1049 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1050 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1051 | |
1052 | if (end_trb_dma > 0) { | |
1053 | /* The end TRB is in this segment, so suspect should be here */ | |
1054 | if (start_dma <= end_trb_dma) { | |
1055 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1056 | return cur_seg; | |
1057 | } else { | |
1058 | /* Case for one segment with | |
1059 | * a TD wrapped around to the top | |
1060 | */ | |
1061 | if ((suspect_dma >= start_dma && | |
1062 | suspect_dma <= end_seg_dma) || | |
1063 | (suspect_dma >= cur_seg->dma && | |
1064 | suspect_dma <= end_trb_dma)) | |
1065 | return cur_seg; | |
1066 | } | |
1067 | return 0; | |
1068 | } else { | |
1069 | /* Might still be somewhere in this segment */ | |
1070 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1071 | return cur_seg; | |
1072 | } | |
1073 | cur_seg = cur_seg->next; | |
23e3be11 | 1074 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1075 | } while (cur_seg != start_seg); |
d0e96f5a | 1076 | |
2fa88daa | 1077 | return 0; |
d0e96f5a SS |
1078 | } |
1079 | ||
bcef3fd5 SS |
1080 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1081 | unsigned int slot_id, unsigned int ep_index, | |
1082 | struct xhci_td *td, union xhci_trb *event_trb) | |
1083 | { | |
1084 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1085 | ep->ep_state |= EP_HALTED; | |
1086 | ep->stopped_td = td; | |
1087 | ep->stopped_trb = event_trb; | |
1624ae1c | 1088 | |
bcef3fd5 SS |
1089 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
1090 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); | |
1624ae1c SS |
1091 | |
1092 | ep->stopped_td = NULL; | |
1093 | ep->stopped_trb = NULL; | |
1094 | ||
bcef3fd5 SS |
1095 | xhci_ring_cmd_db(xhci); |
1096 | } | |
1097 | ||
1098 | /* Check if an error has halted the endpoint ring. The class driver will | |
1099 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1100 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1101 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1102 | * Ring Dequeue Pointer command manually. | |
1103 | */ | |
1104 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1105 | struct xhci_ep_ctx *ep_ctx, | |
1106 | unsigned int trb_comp_code) | |
1107 | { | |
1108 | /* TRB completion codes that may require a manual halt cleanup */ | |
1109 | if (trb_comp_code == COMP_TX_ERR || | |
1110 | trb_comp_code == COMP_BABBLE || | |
1111 | trb_comp_code == COMP_SPLIT_ERR) | |
1112 | /* The 0.96 spec says a babbling control endpoint | |
1113 | * is not halted. The 0.96 spec says it is. Some HW | |
1114 | * claims to be 0.95 compliant, but it halts the control | |
1115 | * endpoint anyway. Check if a babble halted the | |
1116 | * endpoint. | |
1117 | */ | |
1118 | if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED) | |
1119 | return 1; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
b45b5069 SS |
1124 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1125 | { | |
1126 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1127 | /* Vendor defined "informational" completion code, | |
1128 | * treat as not-an-error. | |
1129 | */ | |
1130 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1131 | trb_comp_code); | |
1132 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1133 | return 1; | |
1134 | } | |
1135 | return 0; | |
1136 | } | |
1137 | ||
d0e96f5a SS |
1138 | /* |
1139 | * If this function returns an error condition, it means it got a Transfer | |
1140 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
1141 | * At this point, the host controller is probably hosed and should be reset. | |
1142 | */ | |
1143 | static int handle_tx_event(struct xhci_hcd *xhci, | |
1144 | struct xhci_transfer_event *event) | |
1145 | { | |
1146 | struct xhci_virt_device *xdev; | |
63a0d9ab | 1147 | struct xhci_virt_ep *ep; |
d0e96f5a | 1148 | struct xhci_ring *ep_ring; |
82d1009f | 1149 | unsigned int slot_id; |
d0e96f5a SS |
1150 | int ep_index; |
1151 | struct xhci_td *td = 0; | |
1152 | dma_addr_t event_dma; | |
1153 | struct xhci_segment *event_seg; | |
1154 | union xhci_trb *event_trb; | |
ae636747 | 1155 | struct urb *urb = 0; |
d0e96f5a | 1156 | int status = -EINPROGRESS; |
d115b048 | 1157 | struct xhci_ep_ctx *ep_ctx; |
66d1eebc | 1158 | u32 trb_comp_code; |
d0e96f5a | 1159 | |
66e49d87 | 1160 | xhci_dbg(xhci, "In %s\n", __func__); |
82d1009f SS |
1161 | slot_id = TRB_TO_SLOT_ID(event->flags); |
1162 | xdev = xhci->devs[slot_id]; | |
d0e96f5a SS |
1163 | if (!xdev) { |
1164 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
1165 | return -ENODEV; | |
1166 | } | |
1167 | ||
1168 | /* Endpoint ID is 1 based, our index is zero based */ | |
1169 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | |
66e49d87 | 1170 | xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); |
63a0d9ab SS |
1171 | ep = &xdev->eps[ep_index]; |
1172 | ep_ring = ep->ring; | |
d115b048 JY |
1173 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
1174 | if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) { | |
d0e96f5a SS |
1175 | xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n"); |
1176 | return -ENODEV; | |
1177 | } | |
1178 | ||
8e595a5d | 1179 | event_dma = event->buffer; |
d0e96f5a | 1180 | /* This TRB should be in the TD at the head of this ring's TD list */ |
66e49d87 | 1181 | xhci_dbg(xhci, "%s - checking for list empty\n", __func__); |
d0e96f5a SS |
1182 | if (list_empty(&ep_ring->td_list)) { |
1183 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
1184 | TRB_TO_SLOT_ID(event->flags), ep_index); | |
1185 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
1186 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | |
1187 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
1188 | urb = NULL; | |
1189 | goto cleanup; | |
1190 | } | |
66e49d87 | 1191 | xhci_dbg(xhci, "%s - getting list entry\n", __func__); |
d0e96f5a SS |
1192 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
1193 | ||
1194 | /* Is this a TRB in the currently executing TD? */ | |
66e49d87 | 1195 | xhci_dbg(xhci, "%s - looking for TD\n", __func__); |
d0e96f5a SS |
1196 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, |
1197 | td->last_trb, event_dma); | |
66e49d87 | 1198 | xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg); |
d0e96f5a SS |
1199 | if (!event_seg) { |
1200 | /* HC is busted, give up! */ | |
1201 | xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n"); | |
1202 | return -ESHUTDOWN; | |
1203 | } | |
1204 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)]; | |
b10de142 SS |
1205 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
1206 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | |
8e595a5d SS |
1207 | xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n", |
1208 | lower_32_bits(event->buffer)); | |
1209 | xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n", | |
1210 | upper_32_bits(event->buffer)); | |
b10de142 SS |
1211 | xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n", |
1212 | (unsigned int) event->transfer_len); | |
1213 | xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n", | |
1214 | (unsigned int) event->flags); | |
1215 | ||
1216 | /* Look for common error cases */ | |
66d1eebc SS |
1217 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
1218 | switch (trb_comp_code) { | |
b10de142 SS |
1219 | /* Skip codes that require special handling depending on |
1220 | * transfer type | |
1221 | */ | |
1222 | case COMP_SUCCESS: | |
1223 | case COMP_SHORT_TX: | |
1224 | break; | |
ae636747 SS |
1225 | case COMP_STOP: |
1226 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
1227 | break; | |
1228 | case COMP_STOP_INVAL: | |
1229 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
1230 | break; | |
b10de142 SS |
1231 | case COMP_STALL: |
1232 | xhci_warn(xhci, "WARN: Stalled endpoint\n"); | |
63a0d9ab | 1233 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
1234 | status = -EPIPE; |
1235 | break; | |
1236 | case COMP_TRB_ERR: | |
1237 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
1238 | status = -EILSEQ; | |
1239 | break; | |
ec74e403 | 1240 | case COMP_SPLIT_ERR: |
b10de142 SS |
1241 | case COMP_TX_ERR: |
1242 | xhci_warn(xhci, "WARN: transfer error on endpoint\n"); | |
1243 | status = -EPROTO; | |
1244 | break; | |
4a73143c SS |
1245 | case COMP_BABBLE: |
1246 | xhci_warn(xhci, "WARN: babble error on endpoint\n"); | |
1247 | status = -EOVERFLOW; | |
1248 | break; | |
b10de142 SS |
1249 | case COMP_DB_ERR: |
1250 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
1251 | status = -ENOSR; | |
1252 | break; | |
1253 | default: | |
b45b5069 | 1254 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
1255 | status = 0; |
1256 | break; | |
1257 | } | |
b10de142 SS |
1258 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n"); |
1259 | urb = NULL; | |
1260 | goto cleanup; | |
1261 | } | |
d0e96f5a SS |
1262 | /* Now update the urb's actual_length and give back to the core */ |
1263 | /* Was this a control transfer? */ | |
1264 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) { | |
1265 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); | |
66d1eebc | 1266 | switch (trb_comp_code) { |
d0e96f5a SS |
1267 | case COMP_SUCCESS: |
1268 | if (event_trb == ep_ring->dequeue) { | |
1269 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n"); | |
1270 | status = -ESHUTDOWN; | |
1271 | } else if (event_trb != td->last_trb) { | |
1272 | xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n"); | |
1273 | status = -ESHUTDOWN; | |
1274 | } else { | |
1275 | xhci_dbg(xhci, "Successful control transfer!\n"); | |
1276 | status = 0; | |
1277 | } | |
1278 | break; | |
1279 | case COMP_SHORT_TX: | |
1280 | xhci_warn(xhci, "WARN: short transfer on control ep\n"); | |
204970a4 SS |
1281 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1282 | status = -EREMOTEIO; | |
1283 | else | |
1284 | status = 0; | |
d0e96f5a | 1285 | break; |
bcef3fd5 SS |
1286 | |
1287 | default: | |
1288 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1289 | ep_ctx, trb_comp_code)) | |
83fbcdcc | 1290 | break; |
bcef3fd5 SS |
1291 | xhci_dbg(xhci, "TRB error code %u, " |
1292 | "halted endpoint index = %u\n", | |
1293 | trb_comp_code, ep_index); | |
83fbcdcc | 1294 | /* else fall through */ |
82d1009f SS |
1295 | case COMP_STALL: |
1296 | /* Did we transfer part of the data (middle) phase? */ | |
1297 | if (event_trb != ep_ring->dequeue && | |
1298 | event_trb != td->last_trb) | |
1299 | td->urb->actual_length = | |
1300 | td->urb->transfer_buffer_length | |
1301 | - TRB_LEN(event->transfer_len); | |
1302 | else | |
1303 | td->urb->actual_length = 0; | |
1304 | ||
bcef3fd5 SS |
1305 | xhci_cleanup_halted_endpoint(xhci, |
1306 | slot_id, ep_index, td, event_trb); | |
82d1009f | 1307 | goto td_cleanup; |
d0e96f5a SS |
1308 | } |
1309 | /* | |
1310 | * Did we transfer any data, despite the errors that might have | |
1311 | * happened? I.e. did we get past the setup stage? | |
1312 | */ | |
1313 | if (event_trb != ep_ring->dequeue) { | |
1314 | /* The event was for the status stage */ | |
1315 | if (event_trb == td->last_trb) { | |
c92bcfa7 SS |
1316 | if (td->urb->actual_length != 0) { |
1317 | /* Don't overwrite a previously set error code */ | |
204970a4 SS |
1318 | if ((status == -EINPROGRESS || |
1319 | status == 0) && | |
1320 | (td->urb->transfer_flags | |
1321 | & URB_SHORT_NOT_OK)) | |
c92bcfa7 SS |
1322 | /* Did we already see a short data stage? */ |
1323 | status = -EREMOTEIO; | |
1324 | } else { | |
62889610 SS |
1325 | td->urb->actual_length = |
1326 | td->urb->transfer_buffer_length; | |
c92bcfa7 | 1327 | } |
d0e96f5a | 1328 | } else { |
ae636747 | 1329 | /* Maybe the event was for the data stage? */ |
66d1eebc | 1330 | if (trb_comp_code != COMP_STOP_INVAL) { |
ae636747 SS |
1331 | /* We didn't stop on a link TRB in the middle */ |
1332 | td->urb->actual_length = | |
1333 | td->urb->transfer_buffer_length - | |
1334 | TRB_LEN(event->transfer_len); | |
62889610 SS |
1335 | xhci_dbg(xhci, "Waiting for status stage event\n"); |
1336 | urb = NULL; | |
1337 | goto cleanup; | |
1338 | } | |
d0e96f5a SS |
1339 | } |
1340 | } | |
d0e96f5a | 1341 | } else { |
66d1eebc | 1342 | switch (trb_comp_code) { |
b10de142 SS |
1343 | case COMP_SUCCESS: |
1344 | /* Double check that the HW transferred everything. */ | |
1345 | if (event_trb != td->last_trb) { | |
1346 | xhci_warn(xhci, "WARN Successful completion " | |
1347 | "on short TX\n"); | |
1348 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1349 | status = -EREMOTEIO; | |
1350 | else | |
1351 | status = 0; | |
1352 | } else { | |
624defa1 SS |
1353 | if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) |
1354 | xhci_dbg(xhci, "Successful bulk " | |
1355 | "transfer!\n"); | |
1356 | else | |
1357 | xhci_dbg(xhci, "Successful interrupt " | |
1358 | "transfer!\n"); | |
b10de142 SS |
1359 | status = 0; |
1360 | } | |
1361 | break; | |
1362 | case COMP_SHORT_TX: | |
1363 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1364 | status = -EREMOTEIO; | |
1365 | else | |
1366 | status = 0; | |
1367 | break; | |
1368 | default: | |
1369 | /* Others already handled above */ | |
1370 | break; | |
1371 | } | |
1372 | dev_dbg(&td->urb->dev->dev, | |
1373 | "ep %#x - asked for %d bytes, " | |
1374 | "%d bytes untransferred\n", | |
1375 | td->urb->ep->desc.bEndpointAddress, | |
1376 | td->urb->transfer_buffer_length, | |
1377 | TRB_LEN(event->transfer_len)); | |
1378 | /* Fast path - was this the last TRB in the TD for this URB? */ | |
1379 | if (event_trb == td->last_trb) { | |
1380 | if (TRB_LEN(event->transfer_len) != 0) { | |
1381 | td->urb->actual_length = | |
1382 | td->urb->transfer_buffer_length - | |
1383 | TRB_LEN(event->transfer_len); | |
99eb32db SS |
1384 | if (td->urb->transfer_buffer_length < |
1385 | td->urb->actual_length) { | |
b10de142 SS |
1386 | xhci_warn(xhci, "HC gave bad length " |
1387 | "of %d bytes left\n", | |
1388 | TRB_LEN(event->transfer_len)); | |
1389 | td->urb->actual_length = 0; | |
2f697f6c SS |
1390 | if (td->urb->transfer_flags & |
1391 | URB_SHORT_NOT_OK) | |
1392 | status = -EREMOTEIO; | |
1393 | else | |
1394 | status = 0; | |
b10de142 | 1395 | } |
c92bcfa7 SS |
1396 | /* Don't overwrite a previously set error code */ |
1397 | if (status == -EINPROGRESS) { | |
1398 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1399 | status = -EREMOTEIO; | |
1400 | else | |
1401 | status = 0; | |
1402 | } | |
b10de142 SS |
1403 | } else { |
1404 | td->urb->actual_length = td->urb->transfer_buffer_length; | |
1405 | /* Ignore a short packet completion if the | |
1406 | * untransferred length was zero. | |
1407 | */ | |
c92bcfa7 SS |
1408 | if (status == -EREMOTEIO) |
1409 | status = 0; | |
b10de142 SS |
1410 | } |
1411 | } else { | |
ae636747 SS |
1412 | /* Slow path - walk the list, starting from the dequeue |
1413 | * pointer, to get the actual length transferred. | |
b10de142 | 1414 | */ |
ae636747 SS |
1415 | union xhci_trb *cur_trb; |
1416 | struct xhci_segment *cur_seg; | |
1417 | ||
b10de142 | 1418 | td->urb->actual_length = 0; |
ae636747 SS |
1419 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; |
1420 | cur_trb != event_trb; | |
1421 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
1422 | if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP && | |
1423 | TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK) | |
1424 | td->urb->actual_length += | |
1425 | TRB_LEN(cur_trb->generic.field[2]); | |
b10de142 | 1426 | } |
ae636747 SS |
1427 | /* If the ring didn't stop on a Link or No-op TRB, add |
1428 | * in the actual bytes transferred from the Normal TRB | |
1429 | */ | |
66d1eebc | 1430 | if (trb_comp_code != COMP_STOP_INVAL) |
ae636747 SS |
1431 | td->urb->actual_length += |
1432 | TRB_LEN(cur_trb->generic.field[2]) - | |
1433 | TRB_LEN(event->transfer_len); | |
b10de142 | 1434 | } |
d0e96f5a | 1435 | } |
66d1eebc SS |
1436 | if (trb_comp_code == COMP_STOP_INVAL || |
1437 | trb_comp_code == COMP_STOP) { | |
c92bcfa7 SS |
1438 | /* The Endpoint Stop Command completion will take care of any |
1439 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1440 | * the ring dequeue pointer or take this TD off any lists yet. | |
1441 | */ | |
63a0d9ab SS |
1442 | ep->stopped_td = td; |
1443 | ep->stopped_trb = event_trb; | |
ae636747 | 1444 | } else { |
bcef3fd5 | 1445 | if (trb_comp_code == COMP_STALL) { |
c92bcfa7 SS |
1446 | /* The transfer is completed from the driver's |
1447 | * perspective, but we need to issue a set dequeue | |
1448 | * command for this stalled endpoint to move the dequeue | |
1449 | * pointer past the TD. We can't do that here because | |
bcef3fd5 SS |
1450 | * the halt condition must be cleared first. Let the |
1451 | * USB class driver clear the stall later. | |
c92bcfa7 | 1452 | */ |
63a0d9ab SS |
1453 | ep->stopped_td = td; |
1454 | ep->stopped_trb = event_trb; | |
bcef3fd5 SS |
1455 | } else if (xhci_requires_manual_halt_cleanup(xhci, |
1456 | ep_ctx, trb_comp_code)) { | |
1457 | /* Other types of errors halt the endpoint, but the | |
1458 | * class driver doesn't call usb_reset_endpoint() unless | |
1459 | * the error is -EPIPE. Clear the halted status in the | |
1460 | * xHCI hardware manually. | |
1461 | */ | |
1462 | xhci_cleanup_halted_endpoint(xhci, | |
1463 | slot_id, ep_index, td, event_trb); | |
c92bcfa7 SS |
1464 | } else { |
1465 | /* Update ring dequeue pointer */ | |
1466 | while (ep_ring->dequeue != td->last_trb) | |
1467 | inc_deq(xhci, ep_ring, false); | |
ae636747 | 1468 | inc_deq(xhci, ep_ring, false); |
c92bcfa7 | 1469 | } |
b10de142 | 1470 | |
82d1009f | 1471 | td_cleanup: |
ae636747 SS |
1472 | /* Clean up the endpoint's TD list */ |
1473 | urb = td->urb; | |
99eb32db SS |
1474 | /* Do one last check of the actual transfer length. |
1475 | * If the host controller said we transferred more data than | |
1476 | * the buffer length, urb->actual_length will be a very big | |
1477 | * number (since it's unsigned). Play it safe and say we didn't | |
1478 | * transfer anything. | |
1479 | */ | |
1480 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1481 | xhci_warn(xhci, "URB transfer length is wrong, " | |
1482 | "xHC issue? req. len = %u, " | |
1483 | "act. len = %u\n", | |
1484 | urb->transfer_buffer_length, | |
1485 | urb->actual_length); | |
1486 | urb->actual_length = 0; | |
2f697f6c SS |
1487 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1488 | status = -EREMOTEIO; | |
1489 | else | |
1490 | status = 0; | |
99eb32db | 1491 | } |
ae636747 SS |
1492 | list_del(&td->td_list); |
1493 | /* Was this TD slated to be cancelled but completed anyway? */ | |
678539cf | 1494 | if (!list_empty(&td->cancelled_td_list)) |
ae636747 | 1495 | list_del(&td->cancelled_td_list); |
678539cf | 1496 | |
82d1009f SS |
1497 | /* Leave the TD around for the reset endpoint function to use |
1498 | * (but only if it's not a control endpoint, since we already | |
1499 | * queued the Set TR dequeue pointer command for stalled | |
1500 | * control endpoints). | |
1501 | */ | |
1502 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
83fbcdcc SS |
1503 | (trb_comp_code != COMP_STALL && |
1504 | trb_comp_code != COMP_BABBLE)) { | |
c92bcfa7 SS |
1505 | kfree(td); |
1506 | } | |
ae636747 SS |
1507 | urb->hcpriv = NULL; |
1508 | } | |
d0e96f5a SS |
1509 | cleanup: |
1510 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1511 | xhci_set_hc_event_deq(xhci); |
d0e96f5a | 1512 | |
b10de142 | 1513 | /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */ |
d0e96f5a SS |
1514 | if (urb) { |
1515 | usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); | |
66e49d87 | 1516 | xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n", |
9191eee7 | 1517 | urb, urb->actual_length, status); |
d0e96f5a SS |
1518 | spin_unlock(&xhci->lock); |
1519 | usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); | |
1520 | spin_lock(&xhci->lock); | |
1521 | } | |
1522 | return 0; | |
1523 | } | |
1524 | ||
0f2a7930 SS |
1525 | /* |
1526 | * This function handles all OS-owned events on the event ring. It may drop | |
1527 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
1528 | */ | |
b7258a4a | 1529 | void xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
1530 | { |
1531 | union xhci_trb *event; | |
0f2a7930 | 1532 | int update_ptrs = 1; |
d0e96f5a | 1533 | int ret; |
7f84eef0 | 1534 | |
66e49d87 | 1535 | xhci_dbg(xhci, "In %s\n", __func__); |
7f84eef0 SS |
1536 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
1537 | xhci->error_bitmask |= 1 << 1; | |
1538 | return; | |
1539 | } | |
1540 | ||
1541 | event = xhci->event_ring->dequeue; | |
1542 | /* Does the HC or OS own the TRB? */ | |
1543 | if ((event->event_cmd.flags & TRB_CYCLE) != | |
1544 | xhci->event_ring->cycle_state) { | |
1545 | xhci->error_bitmask |= 1 << 2; | |
1546 | return; | |
1547 | } | |
66e49d87 | 1548 | xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); |
7f84eef0 | 1549 | |
0f2a7930 | 1550 | /* FIXME: Handle more event types. */ |
7f84eef0 SS |
1551 | switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) { |
1552 | case TRB_TYPE(TRB_COMPLETION): | |
66e49d87 | 1553 | xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); |
7f84eef0 | 1554 | handle_cmd_completion(xhci, &event->event_cmd); |
66e49d87 | 1555 | xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); |
7f84eef0 | 1556 | break; |
0f2a7930 | 1557 | case TRB_TYPE(TRB_PORT_STATUS): |
66e49d87 | 1558 | xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); |
0f2a7930 | 1559 | handle_port_status(xhci, event); |
66e49d87 | 1560 | xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); |
0f2a7930 SS |
1561 | update_ptrs = 0; |
1562 | break; | |
d0e96f5a | 1563 | case TRB_TYPE(TRB_TRANSFER): |
66e49d87 | 1564 | xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); |
d0e96f5a | 1565 | ret = handle_tx_event(xhci, &event->trans_event); |
66e49d87 | 1566 | xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); |
d0e96f5a SS |
1567 | if (ret < 0) |
1568 | xhci->error_bitmask |= 1 << 9; | |
1569 | else | |
1570 | update_ptrs = 0; | |
1571 | break; | |
7f84eef0 SS |
1572 | default: |
1573 | xhci->error_bitmask |= 1 << 3; | |
1574 | } | |
6f5165cf SS |
1575 | /* Any of the above functions may drop and re-acquire the lock, so check |
1576 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
1577 | */ | |
1578 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
1579 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
1580 | "event handler.\n"); | |
1581 | return; | |
1582 | } | |
7f84eef0 | 1583 | |
0f2a7930 SS |
1584 | if (update_ptrs) { |
1585 | /* Update SW and HC event ring dequeue pointer */ | |
1586 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1587 | xhci_set_hc_event_deq(xhci); |
0f2a7930 | 1588 | } |
7f84eef0 | 1589 | /* Are there more items on the event ring? */ |
b7258a4a | 1590 | xhci_handle_event(xhci); |
7f84eef0 SS |
1591 | } |
1592 | ||
d0e96f5a SS |
1593 | /**** Endpoint Ring Operations ****/ |
1594 | ||
7f84eef0 SS |
1595 | /* |
1596 | * Generic function for queueing a TRB on a ring. | |
1597 | * The caller must have checked to make sure there's room on the ring. | |
1598 | */ | |
1599 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
1600 | bool consumer, | |
1601 | u32 field1, u32 field2, u32 field3, u32 field4) | |
1602 | { | |
1603 | struct xhci_generic_trb *trb; | |
1604 | ||
1605 | trb = &ring->enqueue->generic; | |
1606 | trb->field[0] = field1; | |
1607 | trb->field[1] = field2; | |
1608 | trb->field[2] = field3; | |
1609 | trb->field[3] = field4; | |
1610 | inc_enq(xhci, ring, consumer); | |
1611 | } | |
1612 | ||
d0e96f5a SS |
1613 | /* |
1614 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
1615 | * FIXME allocate segments if the ring is full. | |
1616 | */ | |
1617 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
1618 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) | |
1619 | { | |
1620 | /* Make sure the endpoint has been added to xHC schedule */ | |
1621 | xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); | |
1622 | switch (ep_state) { | |
1623 | case EP_STATE_DISABLED: | |
1624 | /* | |
1625 | * USB core changed config/interfaces without notifying us, | |
1626 | * or hardware is reporting the wrong state. | |
1627 | */ | |
1628 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
1629 | return -ENOENT; | |
d0e96f5a | 1630 | case EP_STATE_ERROR: |
c92bcfa7 | 1631 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
1632 | /* FIXME event handling code for error needs to clear it */ |
1633 | /* XXX not sure if this should be -ENOENT or not */ | |
1634 | return -EINVAL; | |
c92bcfa7 SS |
1635 | case EP_STATE_HALTED: |
1636 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
1637 | case EP_STATE_STOPPED: |
1638 | case EP_STATE_RUNNING: | |
1639 | break; | |
1640 | default: | |
1641 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
1642 | /* | |
1643 | * FIXME issue Configure Endpoint command to try to get the HC | |
1644 | * back into a known state. | |
1645 | */ | |
1646 | return -EINVAL; | |
1647 | } | |
1648 | if (!room_on_ring(xhci, ep_ring, num_trbs)) { | |
1649 | /* FIXME allocate more room */ | |
1650 | xhci_err(xhci, "ERROR no room on ep ring\n"); | |
1651 | return -ENOMEM; | |
1652 | } | |
1653 | return 0; | |
1654 | } | |
1655 | ||
23e3be11 | 1656 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
1657 | struct xhci_virt_device *xdev, |
1658 | unsigned int ep_index, | |
1659 | unsigned int num_trbs, | |
1660 | struct urb *urb, | |
1661 | struct xhci_td **td, | |
1662 | gfp_t mem_flags) | |
1663 | { | |
1664 | int ret; | |
d115b048 | 1665 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
63a0d9ab | 1666 | ret = prepare_ring(xhci, xdev->eps[ep_index].ring, |
d115b048 | 1667 | ep_ctx->ep_info & EP_STATE_MASK, |
d0e96f5a SS |
1668 | num_trbs, mem_flags); |
1669 | if (ret) | |
1670 | return ret; | |
1671 | *td = kzalloc(sizeof(struct xhci_td), mem_flags); | |
1672 | if (!*td) | |
1673 | return -ENOMEM; | |
1674 | INIT_LIST_HEAD(&(*td)->td_list); | |
ae636747 | 1675 | INIT_LIST_HEAD(&(*td)->cancelled_td_list); |
d0e96f5a SS |
1676 | |
1677 | ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); | |
1678 | if (unlikely(ret)) { | |
1679 | kfree(*td); | |
1680 | return ret; | |
1681 | } | |
1682 | ||
1683 | (*td)->urb = urb; | |
1684 | urb->hcpriv = (void *) (*td); | |
1685 | /* Add this TD to the tail of the endpoint ring's TD list */ | |
63a0d9ab SS |
1686 | list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list); |
1687 | (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg; | |
1688 | (*td)->first_trb = xdev->eps[ep_index].ring->enqueue; | |
d0e96f5a SS |
1689 | |
1690 | return 0; | |
1691 | } | |
1692 | ||
23e3be11 | 1693 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
1694 | { |
1695 | int num_sgs, num_trbs, running_total, temp, i; | |
1696 | struct scatterlist *sg; | |
1697 | ||
1698 | sg = NULL; | |
1699 | num_sgs = urb->num_sgs; | |
1700 | temp = urb->transfer_buffer_length; | |
1701 | ||
1702 | xhci_dbg(xhci, "count sg list trbs: \n"); | |
1703 | num_trbs = 0; | |
1704 | for_each_sg(urb->sg->sg, sg, num_sgs, i) { | |
1705 | unsigned int previous_total_trbs = num_trbs; | |
1706 | unsigned int len = sg_dma_len(sg); | |
1707 | ||
1708 | /* Scatter gather list entries may cross 64KB boundaries */ | |
1709 | running_total = TRB_MAX_BUFF_SIZE - | |
1710 | (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1711 | if (running_total != 0) | |
1712 | num_trbs++; | |
1713 | ||
1714 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
1715 | while (running_total < sg_dma_len(sg)) { | |
1716 | num_trbs++; | |
1717 | running_total += TRB_MAX_BUFF_SIZE; | |
1718 | } | |
700e2052 GKH |
1719 | xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n", |
1720 | i, (unsigned long long)sg_dma_address(sg), | |
1721 | len, len, num_trbs - previous_total_trbs); | |
8a96c052 SS |
1722 | |
1723 | len = min_t(int, len, temp); | |
1724 | temp -= len; | |
1725 | if (temp == 0) | |
1726 | break; | |
1727 | } | |
1728 | xhci_dbg(xhci, "\n"); | |
1729 | if (!in_interrupt()) | |
1730 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n", | |
1731 | urb->ep->desc.bEndpointAddress, | |
1732 | urb->transfer_buffer_length, | |
1733 | num_trbs); | |
1734 | return num_trbs; | |
1735 | } | |
1736 | ||
23e3be11 | 1737 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
1738 | { |
1739 | if (num_trbs != 0) | |
1740 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " | |
1741 | "TRBs, %d left\n", __func__, | |
1742 | urb->ep->desc.bEndpointAddress, num_trbs); | |
1743 | if (running_total != urb->transfer_buffer_length) | |
1744 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " | |
1745 | "queued %#x (%d), asked for %#x (%d)\n", | |
1746 | __func__, | |
1747 | urb->ep->desc.bEndpointAddress, | |
1748 | running_total, running_total, | |
1749 | urb->transfer_buffer_length, | |
1750 | urb->transfer_buffer_length); | |
1751 | } | |
1752 | ||
23e3be11 | 1753 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
8a96c052 SS |
1754 | unsigned int ep_index, int start_cycle, |
1755 | struct xhci_generic_trb *start_trb, struct xhci_td *td) | |
1756 | { | |
8a96c052 SS |
1757 | /* |
1758 | * Pass all the TRBs to the hardware at once and make sure this write | |
1759 | * isn't reordered. | |
1760 | */ | |
1761 | wmb(); | |
1762 | start_trb->field[3] |= start_cycle; | |
ae636747 | 1763 | ring_ep_doorbell(xhci, slot_id, ep_index); |
8a96c052 SS |
1764 | } |
1765 | ||
624defa1 SS |
1766 | /* |
1767 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
1768 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
1769 | * (comprised of sg list entries) can take several service intervals to | |
1770 | * transmit. | |
1771 | */ | |
1772 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
1773 | struct urb *urb, int slot_id, unsigned int ep_index) | |
1774 | { | |
1775 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
1776 | xhci->devs[slot_id]->out_ctx, ep_index); | |
1777 | int xhci_interval; | |
1778 | int ep_interval; | |
1779 | ||
1780 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); | |
1781 | ep_interval = urb->interval; | |
1782 | /* Convert to microframes */ | |
1783 | if (urb->dev->speed == USB_SPEED_LOW || | |
1784 | urb->dev->speed == USB_SPEED_FULL) | |
1785 | ep_interval *= 8; | |
1786 | /* FIXME change this to a warning and a suggestion to use the new API | |
1787 | * to set the polling interval (once the API is added). | |
1788 | */ | |
1789 | if (xhci_interval != ep_interval) { | |
1790 | if (!printk_ratelimit()) | |
1791 | dev_dbg(&urb->dev->dev, "Driver uses different interval" | |
1792 | " (%d microframe%s) than xHCI " | |
1793 | "(%d microframe%s)\n", | |
1794 | ep_interval, | |
1795 | ep_interval == 1 ? "" : "s", | |
1796 | xhci_interval, | |
1797 | xhci_interval == 1 ? "" : "s"); | |
1798 | urb->interval = xhci_interval; | |
1799 | /* Convert back to frames for LS/FS devices */ | |
1800 | if (urb->dev->speed == USB_SPEED_LOW || | |
1801 | urb->dev->speed == USB_SPEED_FULL) | |
1802 | urb->interval /= 8; | |
1803 | } | |
1804 | return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); | |
1805 | } | |
1806 | ||
04dd950d SS |
1807 | /* |
1808 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
1809 | * right shifted by 10. | |
1810 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
1811 | */ | |
1812 | static u32 xhci_td_remainder(unsigned int remainder) | |
1813 | { | |
1814 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
1815 | ||
1816 | if ((remainder >> 10) >= max) | |
1817 | return max << 17; | |
1818 | else | |
1819 | return (remainder >> 10) << 17; | |
1820 | } | |
1821 | ||
23e3be11 | 1822 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
1823 | struct urb *urb, int slot_id, unsigned int ep_index) |
1824 | { | |
1825 | struct xhci_ring *ep_ring; | |
1826 | unsigned int num_trbs; | |
1827 | struct xhci_td *td; | |
1828 | struct scatterlist *sg; | |
1829 | int num_sgs; | |
1830 | int trb_buff_len, this_sg_len, running_total; | |
1831 | bool first_trb; | |
1832 | u64 addr; | |
1833 | ||
1834 | struct xhci_generic_trb *start_trb; | |
1835 | int start_cycle; | |
1836 | ||
63a0d9ab | 1837 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
8a96c052 SS |
1838 | num_trbs = count_sg_trbs_needed(xhci, urb); |
1839 | num_sgs = urb->num_sgs; | |
1840 | ||
23e3be11 | 1841 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
8a96c052 SS |
1842 | ep_index, num_trbs, urb, &td, mem_flags); |
1843 | if (trb_buff_len < 0) | |
1844 | return trb_buff_len; | |
1845 | /* | |
1846 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
1847 | * until we've finished creating all the other TRBs. The ring's cycle | |
1848 | * state may change as we enqueue the other TRBs, so save it too. | |
1849 | */ | |
1850 | start_trb = &ep_ring->enqueue->generic; | |
1851 | start_cycle = ep_ring->cycle_state; | |
1852 | ||
1853 | running_total = 0; | |
1854 | /* | |
1855 | * How much data is in the first TRB? | |
1856 | * | |
1857 | * There are three forces at work for TRB buffer pointers and lengths: | |
1858 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
1859 | * 2. The transfer length that the driver requested may be smaller than | |
1860 | * the amount of memory allocated for this scatter-gather list. | |
1861 | * 3. TRBs buffers can't cross 64KB boundaries. | |
1862 | */ | |
1863 | sg = urb->sg->sg; | |
1864 | addr = (u64) sg_dma_address(sg); | |
1865 | this_sg_len = sg_dma_len(sg); | |
1866 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
1867 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1868 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
1869 | if (trb_buff_len > urb->transfer_buffer_length) | |
1870 | trb_buff_len = urb->transfer_buffer_length; | |
1871 | xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n", | |
1872 | trb_buff_len); | |
1873 | ||
1874 | first_trb = true; | |
1875 | /* Queue the first TRB, even if it's zero-length */ | |
1876 | do { | |
1877 | u32 field = 0; | |
f9dc68fe | 1878 | u32 length_field = 0; |
04dd950d | 1879 | u32 remainder = 0; |
8a96c052 SS |
1880 | |
1881 | /* Don't change the cycle bit of the first TRB until later */ | |
1882 | if (first_trb) | |
1883 | first_trb = false; | |
1884 | else | |
1885 | field |= ep_ring->cycle_state; | |
1886 | ||
1887 | /* Chain all the TRBs together; clear the chain bit in the last | |
1888 | * TRB to indicate it's the last TRB in the chain. | |
1889 | */ | |
1890 | if (num_trbs > 1) { | |
1891 | field |= TRB_CHAIN; | |
1892 | } else { | |
1893 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
1894 | td->last_trb = ep_ring->enqueue; | |
1895 | field |= TRB_IOC; | |
1896 | } | |
1897 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " | |
1898 | "64KB boundary at %#x, end dma = %#x\n", | |
1899 | (unsigned int) addr, trb_buff_len, trb_buff_len, | |
1900 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
1901 | (unsigned int) addr + trb_buff_len); | |
1902 | if (TRB_MAX_BUFF_SIZE - | |
1903 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) { | |
1904 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); | |
1905 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
1906 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
1907 | (unsigned int) addr + trb_buff_len); | |
1908 | } | |
04dd950d SS |
1909 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
1910 | running_total) ; | |
f9dc68fe | 1911 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 1912 | remainder | |
f9dc68fe | 1913 | TRB_INTR_TARGET(0); |
8a96c052 | 1914 | queue_trb(xhci, ep_ring, false, |
8e595a5d SS |
1915 | lower_32_bits(addr), |
1916 | upper_32_bits(addr), | |
f9dc68fe | 1917 | length_field, |
8a96c052 SS |
1918 | /* We always want to know if the TRB was short, |
1919 | * or we won't get an event when it completes. | |
1920 | * (Unless we use event data TRBs, which are a | |
1921 | * waste of space and HC resources.) | |
1922 | */ | |
1923 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
1924 | --num_trbs; | |
1925 | running_total += trb_buff_len; | |
1926 | ||
1927 | /* Calculate length for next transfer -- | |
1928 | * Are we done queueing all the TRBs for this sg entry? | |
1929 | */ | |
1930 | this_sg_len -= trb_buff_len; | |
1931 | if (this_sg_len == 0) { | |
1932 | --num_sgs; | |
1933 | if (num_sgs == 0) | |
1934 | break; | |
1935 | sg = sg_next(sg); | |
1936 | addr = (u64) sg_dma_address(sg); | |
1937 | this_sg_len = sg_dma_len(sg); | |
1938 | } else { | |
1939 | addr += trb_buff_len; | |
1940 | } | |
1941 | ||
1942 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
1943 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1944 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
1945 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
1946 | trb_buff_len = | |
1947 | urb->transfer_buffer_length - running_total; | |
1948 | } while (running_total < urb->transfer_buffer_length); | |
1949 | ||
1950 | check_trb_math(urb, num_trbs, running_total); | |
1951 | giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td); | |
1952 | return 0; | |
1953 | } | |
1954 | ||
b10de142 | 1955 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 1956 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
1957 | struct urb *urb, int slot_id, unsigned int ep_index) |
1958 | { | |
1959 | struct xhci_ring *ep_ring; | |
1960 | struct xhci_td *td; | |
1961 | int num_trbs; | |
1962 | struct xhci_generic_trb *start_trb; | |
1963 | bool first_trb; | |
1964 | int start_cycle; | |
f9dc68fe | 1965 | u32 field, length_field; |
b10de142 SS |
1966 | |
1967 | int running_total, trb_buff_len, ret; | |
1968 | u64 addr; | |
1969 | ||
ff9c895f | 1970 | if (urb->num_sgs) |
8a96c052 SS |
1971 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
1972 | ||
63a0d9ab | 1973 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
b10de142 SS |
1974 | |
1975 | num_trbs = 0; | |
1976 | /* How much data is (potentially) left before the 64KB boundary? */ | |
1977 | running_total = TRB_MAX_BUFF_SIZE - | |
1978 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1979 | ||
1980 | /* If there's some data on this 64KB chunk, or we have to send a | |
1981 | * zero-length transfer, we need at least one TRB | |
1982 | */ | |
1983 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
1984 | num_trbs++; | |
1985 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
1986 | while (running_total < urb->transfer_buffer_length) { | |
1987 | num_trbs++; | |
1988 | running_total += TRB_MAX_BUFF_SIZE; | |
1989 | } | |
1990 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
1991 | ||
1992 | if (!in_interrupt()) | |
700e2052 | 1993 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n", |
b10de142 | 1994 | urb->ep->desc.bEndpointAddress, |
8a96c052 SS |
1995 | urb->transfer_buffer_length, |
1996 | urb->transfer_buffer_length, | |
700e2052 | 1997 | (unsigned long long)urb->transfer_dma, |
b10de142 | 1998 | num_trbs); |
8a96c052 | 1999 | |
23e3be11 | 2000 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, |
b10de142 SS |
2001 | num_trbs, urb, &td, mem_flags); |
2002 | if (ret < 0) | |
2003 | return ret; | |
2004 | ||
2005 | /* | |
2006 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2007 | * until we've finished creating all the other TRBs. The ring's cycle | |
2008 | * state may change as we enqueue the other TRBs, so save it too. | |
2009 | */ | |
2010 | start_trb = &ep_ring->enqueue->generic; | |
2011 | start_cycle = ep_ring->cycle_state; | |
2012 | ||
2013 | running_total = 0; | |
2014 | /* How much data is in the first TRB? */ | |
2015 | addr = (u64) urb->transfer_dma; | |
2016 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2017 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2018 | if (urb->transfer_buffer_length < trb_buff_len) | |
2019 | trb_buff_len = urb->transfer_buffer_length; | |
2020 | ||
2021 | first_trb = true; | |
2022 | ||
2023 | /* Queue the first TRB, even if it's zero-length */ | |
2024 | do { | |
04dd950d | 2025 | u32 remainder = 0; |
b10de142 SS |
2026 | field = 0; |
2027 | ||
2028 | /* Don't change the cycle bit of the first TRB until later */ | |
2029 | if (first_trb) | |
2030 | first_trb = false; | |
2031 | else | |
2032 | field |= ep_ring->cycle_state; | |
2033 | ||
2034 | /* Chain all the TRBs together; clear the chain bit in the last | |
2035 | * TRB to indicate it's the last TRB in the chain. | |
2036 | */ | |
2037 | if (num_trbs > 1) { | |
2038 | field |= TRB_CHAIN; | |
2039 | } else { | |
2040 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2041 | td->last_trb = ep_ring->enqueue; | |
2042 | field |= TRB_IOC; | |
2043 | } | |
04dd950d SS |
2044 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
2045 | running_total); | |
f9dc68fe | 2046 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2047 | remainder | |
f9dc68fe | 2048 | TRB_INTR_TARGET(0); |
b10de142 | 2049 | queue_trb(xhci, ep_ring, false, |
8e595a5d SS |
2050 | lower_32_bits(addr), |
2051 | upper_32_bits(addr), | |
f9dc68fe | 2052 | length_field, |
b10de142 SS |
2053 | /* We always want to know if the TRB was short, |
2054 | * or we won't get an event when it completes. | |
2055 | * (Unless we use event data TRBs, which are a | |
2056 | * waste of space and HC resources.) | |
2057 | */ | |
2058 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
2059 | --num_trbs; | |
2060 | running_total += trb_buff_len; | |
2061 | ||
2062 | /* Calculate length for next transfer */ | |
2063 | addr += trb_buff_len; | |
2064 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
2065 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
2066 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
2067 | } while (running_total < urb->transfer_buffer_length); | |
2068 | ||
8a96c052 SS |
2069 | check_trb_math(urb, num_trbs, running_total); |
2070 | giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td); | |
b10de142 SS |
2071 | return 0; |
2072 | } | |
2073 | ||
d0e96f5a | 2074 | /* Caller must have locked xhci->lock */ |
23e3be11 | 2075 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
2076 | struct urb *urb, int slot_id, unsigned int ep_index) |
2077 | { | |
2078 | struct xhci_ring *ep_ring; | |
2079 | int num_trbs; | |
2080 | int ret; | |
2081 | struct usb_ctrlrequest *setup; | |
2082 | struct xhci_generic_trb *start_trb; | |
2083 | int start_cycle; | |
f9dc68fe | 2084 | u32 field, length_field; |
d0e96f5a SS |
2085 | struct xhci_td *td; |
2086 | ||
63a0d9ab | 2087 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
d0e96f5a SS |
2088 | |
2089 | /* | |
2090 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
2091 | * DMA address. | |
2092 | */ | |
2093 | if (!urb->setup_packet) | |
2094 | return -EINVAL; | |
2095 | ||
2096 | if (!in_interrupt()) | |
2097 | xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n", | |
2098 | slot_id, ep_index); | |
2099 | /* 1 TRB for setup, 1 for status */ | |
2100 | num_trbs = 2; | |
2101 | /* | |
2102 | * Don't need to check if we need additional event data and normal TRBs, | |
2103 | * since data in control transfers will never get bigger than 16MB | |
2104 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
2105 | */ | |
2106 | if (urb->transfer_buffer_length > 0) | |
2107 | num_trbs++; | |
23e3be11 | 2108 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs, |
d0e96f5a SS |
2109 | urb, &td, mem_flags); |
2110 | if (ret < 0) | |
2111 | return ret; | |
2112 | ||
2113 | /* | |
2114 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2115 | * until we've finished creating all the other TRBs. The ring's cycle | |
2116 | * state may change as we enqueue the other TRBs, so save it too. | |
2117 | */ | |
2118 | start_trb = &ep_ring->enqueue->generic; | |
2119 | start_cycle = ep_ring->cycle_state; | |
2120 | ||
2121 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
2122 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
2123 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
2124 | queue_trb(xhci, ep_ring, false, | |
2125 | /* FIXME endianness is probably going to bite my ass here. */ | |
2126 | setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16, | |
2127 | setup->wIndex | setup->wLength << 16, | |
2128 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
2129 | /* Immediate data in pointer */ | |
2130 | TRB_IDT | TRB_TYPE(TRB_SETUP)); | |
2131 | ||
2132 | /* If there's data, queue data TRBs */ | |
2133 | field = 0; | |
f9dc68fe | 2134 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 2135 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 2136 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
2137 | if (urb->transfer_buffer_length > 0) { |
2138 | if (setup->bRequestType & USB_DIR_IN) | |
2139 | field |= TRB_DIR_IN; | |
2140 | queue_trb(xhci, ep_ring, false, | |
2141 | lower_32_bits(urb->transfer_dma), | |
2142 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 2143 | length_field, |
d0e96f5a SS |
2144 | /* Event on short tx */ |
2145 | field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); | |
2146 | } | |
2147 | ||
2148 | /* Save the DMA address of the last TRB in the TD */ | |
2149 | td->last_trb = ep_ring->enqueue; | |
2150 | ||
2151 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
2152 | /* If the device sent data, the status stage is an OUT transfer */ | |
2153 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
2154 | field = 0; | |
2155 | else | |
2156 | field = TRB_DIR_IN; | |
2157 | queue_trb(xhci, ep_ring, false, | |
2158 | 0, | |
2159 | 0, | |
2160 | TRB_INTR_TARGET(0), | |
2161 | /* Event on completion */ | |
2162 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
2163 | ||
8a96c052 | 2164 | giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td); |
d0e96f5a SS |
2165 | return 0; |
2166 | } | |
2167 | ||
2168 | /**** Command Ring Operations ****/ | |
2169 | ||
913a8a34 SS |
2170 | /* Generic function for queueing a command TRB on the command ring. |
2171 | * Check to make sure there's room on the command ring for one command TRB. | |
2172 | * Also check that there's room reserved for commands that must not fail. | |
2173 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
2174 | * then only check for the number of reserved spots. | |
2175 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
2176 | * because the command event handler may want to resubmit a failed command. | |
2177 | */ | |
2178 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |
2179 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 2180 | { |
913a8a34 SS |
2181 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
2182 | if (!command_must_succeed) | |
2183 | reserved_trbs++; | |
2184 | ||
2185 | if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) { | |
7f84eef0 SS |
2186 | if (!in_interrupt()) |
2187 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
2188 | if (command_must_succeed) |
2189 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
2190 | "unfailable commands failed.\n"); | |
7f84eef0 SS |
2191 | return -ENOMEM; |
2192 | } | |
2193 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, | |
2194 | field4 | xhci->cmd_ring->cycle_state); | |
2195 | return 0; | |
2196 | } | |
2197 | ||
2198 | /* Queue a no-op command on the command ring */ | |
2199 | static int queue_cmd_noop(struct xhci_hcd *xhci) | |
2200 | { | |
913a8a34 | 2201 | return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false); |
7f84eef0 SS |
2202 | } |
2203 | ||
2204 | /* | |
2205 | * Place a no-op command on the command ring to test the command and | |
2206 | * event ring. | |
2207 | */ | |
23e3be11 | 2208 | void *xhci_setup_one_noop(struct xhci_hcd *xhci) |
7f84eef0 SS |
2209 | { |
2210 | if (queue_cmd_noop(xhci) < 0) | |
2211 | return NULL; | |
2212 | xhci->noops_submitted++; | |
23e3be11 | 2213 | return xhci_ring_cmd_db; |
7f84eef0 | 2214 | } |
3ffbba95 SS |
2215 | |
2216 | /* Queue a slot enable or disable request on the command ring */ | |
23e3be11 | 2217 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3ffbba95 SS |
2218 | { |
2219 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 2220 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
2221 | } |
2222 | ||
2223 | /* Queue an address device command TRB */ | |
23e3be11 SS |
2224 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
2225 | u32 slot_id) | |
3ffbba95 | 2226 | { |
8e595a5d SS |
2227 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
2228 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 | 2229 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
2a8f82c4 SS |
2230 | false); |
2231 | } | |
2232 | ||
2233 | /* Queue a reset device command TRB */ | |
2234 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) | |
2235 | { | |
2236 | return queue_command(xhci, 0, 0, 0, | |
2237 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), | |
913a8a34 | 2238 | false); |
3ffbba95 | 2239 | } |
f94e0186 SS |
2240 | |
2241 | /* Queue a configure endpoint command TRB */ | |
23e3be11 | 2242 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
913a8a34 | 2243 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 2244 | { |
8e595a5d SS |
2245 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
2246 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
2247 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
2248 | command_must_succeed); | |
f94e0186 | 2249 | } |
ae636747 | 2250 | |
f2217e8e SS |
2251 | /* Queue an evaluate context command TRB */ |
2252 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |
2253 | u32 slot_id) | |
2254 | { | |
2255 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), | |
2256 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
2257 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
2258 | false); | |
f2217e8e SS |
2259 | } |
2260 | ||
23e3be11 | 2261 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
ae636747 SS |
2262 | unsigned int ep_index) |
2263 | { | |
2264 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2265 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2266 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
2267 | ||
2268 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 2269 | trb_slot_id | trb_ep_index | type, false); |
ae636747 SS |
2270 | } |
2271 | ||
2272 | /* Set Transfer Ring Dequeue Pointer command. | |
2273 | * This should not be used for endpoints that have streams enabled. | |
2274 | */ | |
2275 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
2276 | unsigned int ep_index, struct xhci_segment *deq_seg, | |
2277 | union xhci_trb *deq_ptr, u32 cycle_state) | |
2278 | { | |
2279 | dma_addr_t addr; | |
2280 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2281 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2282 | u32 type = TRB_TYPE(TRB_SET_DEQ); | |
2283 | ||
23e3be11 | 2284 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 2285 | if (addr == 0) { |
ae636747 | 2286 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
2287 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
2288 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
2289 | return 0; |
2290 | } | |
8e595a5d SS |
2291 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
2292 | upper_32_bits(addr), 0, | |
913a8a34 | 2293 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 2294 | } |
a1587d97 SS |
2295 | |
2296 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, | |
2297 | unsigned int ep_index) | |
2298 | { | |
2299 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2300 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2301 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
2302 | ||
913a8a34 SS |
2303 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
2304 | false); | |
a1587d97 | 2305 | } |