[net-next-2.6.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

/*-------------------------------------------------------------------------*/

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	u32			temp;
	int			retval;

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, 0x0a);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if ((temp & (3 << 13)) == (1 << 13)) {
			temp &= 0x1fff;
			ehci->debug = ehci_to_hcd(ehci)->regs + temp;
			temp = ehci_readl(ehci, &ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				HCS_DEBUG_PORT(ehci->hcs_params),
				(temp & DBGP_ENABLED)
					? " IN USE"
					: "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	/* we expect static quirk code to handle the "extended capabilities"
	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	ehci_port_power(ehci, 0);

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	u32			temp;
	int			retval;

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TOSHIBA_2:
		/* celleb's companion chip */
		if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
			ehci->big_endian_mmio = 1;
#else
			ehci_warn(ehci,
				  "unsupported big endian Toshiba quirk\n");
#endif
		}
		break;
	}

	ehci->caps = hcd->regs;
	ehci->regs = hcd->regs +
		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));

	dbg_hcs_params(ehci, "reset");
	dbg_hcc_params(ehci, "reset");

        /* ehci_init() causes memory for DMA transfers to be
         * allocated.  Thus, any vendor-specific workarounds based on
         * limiting the type of memory used for DMA transfers must
         * happen before ehci_init() is called. */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_31BIT_MASK) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;
		}
		break;
	}

	/* cache this readonly data; minimize chip reads */
	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);

	retval = ehci_halt(ehci);
	if (retval)
		return retval;

	/* data structure init */
	retval = ehci_init(hcd);
	if (retval)
		return retval;

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
			ehci->is_tdi_rh_tt = 1;
			tdi_reset(ehci);
		}
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		switch (pdev->device) {
		/* Some NForce2 chips have problems with selective suspend;
		 * fixed in newer silicon.
		 */
		case 0x0068:
			if (pdev->revision < 0xa4)
				ehci->no_selective_suspend = 1;
			break;
		}
		break;
	}

	if (ehci_is_TDI(ehci))
		ehci_reset(ehci);

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Workaround current PCI init glitch:  wakeup bits aren't
	 * being set from PCI PM capability.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001)
			device_init_wakeup(&pdev->dev, 1);
	}

#ifdef	CONFIG_USB_SUSPEND
	/* REVISIT: the controller works fine for wakeup iff the root hub
	 * itself is "globally" suspended, but usbcore currently doesn't
	 * understand such things.
	 *
	 * System suspend currently expects to be able to suspend the entire
	 * device tree, device-at-a-time.  If we failed selective suspend
	 * reports, system suspend would fail; so the root hub code must claim
	 * success.  That's lying to usbcore, and it matters for for runtime
	 * PM scenarios with selective suspend and remote wakeup...
	 */
	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif

	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	unsigned long		flags;
	int			rc = 0;

	if (time_before(jiffies, ehci->next_statechange))
		msleep(10);

	/* Root hub was already suspended. Disable irq emission and
	 * mark HW unaccessible, bail out if RH has been resumed. Use
	 * the spinlock to properly synchronize with possible pending
	 * RH suspend or resume activity.
	 *
	 * This is still racy as hcd->state is manipulated outside of
	 * any locks =P But that will be a different fix.
	 */
	spin_lock_irqsave (&ehci->lock, flags);
	if (hcd->state != HC_STATE_SUSPENDED) {
		rc = -EINVAL;
		goto bail;
	}
	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
	(void)ehci_readl(ehci, &ehci->regs->intr_enable);

	/* make sure snapshot being resumed re-enumerates everything */
	if (message.event == PM_EVENT_PRETHAW) {
		ehci_halt(ehci);
		ehci_reset(ehci);
	}

	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 bail:
	spin_unlock_irqrestore (&ehci->lock, flags);

	// could save FLADJ in case of Vaux power loss
	// ... we'd only use it to handle clock skew

	return rc;
}

static int ehci_pci_resume(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	// maybe restore FLADJ

	if (time_before(jiffies, ehci->next_statechange))
		msleep(100);

	/* Mark hardware accessible again as we are out of D3 state by now */
	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);

	/* If CF is still set, we maintained PCI Vaux power.
	 * Just undo the effect of ehci_pci_suspend().
	 */
	if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
		int	mask = INTR_MASK;

		if (!device_may_wakeup(&hcd->self.root_hub->dev))
			mask &= ~STS_PCD;
		ehci_writel(ehci, mask, &ehci->regs->intr_enable);
		ehci_readl(ehci, &ehci->regs->intr_enable);
		return 0;
	}

	ehci_dbg(ehci, "lost power, restarting\n");
	usb_root_hub_lost_power(hcd->self.root_hub);

	/* Else reset, to cope with power loss or flush-to-storage
	 * style "resume" having let BIOS kick in during reboot.
	 */
	(void) ehci_halt(ehci);
	(void) ehci_reset(ehci);
	(void) ehci_pci_reinit(ehci, pdev);

	/* emptying the schedule aborts any urbs */
	spin_lock_irq(&ehci->lock);
	if (ehci->reclaim)
		ehci->reclaim_ready = 1;
	ehci_work(ehci);
	spin_unlock_irq(&ehci->lock);

	/* here we "know" root ports should always stay powered */
	ehci_port_power(ehci, 1);

	ehci_writel(ehci, ehci->command, &ehci->regs->command);
	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
	ehci_readl(ehci, &ehci->regs->command);	/* unblock posted writes */

	hcd->state = HC_STATE_SUSPENDED;
	return 0;
}
#endif

static const struct hc_driver ehci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"EHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ehci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ehci_irq,
	.flags =		HCD_MEMORY | HCD_USB2,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ehci_pci_setup,
	.start =		ehci_run,
#ifdef	CONFIG_PM
	.suspend =		ehci_pci_suspend,
	.resume =		ehci_pci_resume,
#endif
	.stop =			ehci_stop,
	.shutdown =		ehci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ehci_urb_enqueue,
	.urb_dequeue =		ehci_urb_dequeue,
	.endpoint_disable =	ehci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ehci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ehci_hub_status_data,
	.hub_control =		ehci_hub_control,
	.bus_suspend =		ehci_bus_suspend,
	.bus_resume =		ehci_bus_resume,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,

#ifdef	CONFIG_PM
	.suspend =	usb_hcd_pci_suspend,
	.resume =	usb_hcd_pci_resume,
#endif
	.shutdown = 	usb_hcd_pci_shutdown,
};
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#ifndef CONFIG_PCI
	22	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	23	#endif
	24
	25	/-------------------------------------------------------------------------/
	26
18807521 DB	27	/* called after powerup, by probe or system-pm "wakeup" */
	28	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	29	{
	30	u32 temp;
	31	int retval;
18807521 DB	32
	33	/* optional debug port, normally in the first BAR */
	34	temp = pci_find_capability(pdev, 0x0a);
	35	if (temp) {
	36	pci_read_config_dword(pdev, temp, &temp);
	37	temp >>= 16;
	38	if ((temp & (3 << 13)) == (1 << 13)) {
	39	temp &= 0x1fff;
	40	ehci->debug = ehci_to_hcd(ehci)->regs + temp;
083522d7	41	temp = ehci_readl(ehci, &ehci->debug->control);
18807521 DB	42	ehci_info(ehci, "debug port %d%s\n",
	43	HCS_DEBUG_PORT(ehci->hcs_params),
	44	(temp & DBGP_ENABLED)
	45	? " IN USE"
	46	: "");
	47	if (!(temp & DBGP_ENABLED))
	48	ehci->debug = NULL;
	49	}
	50	}
	51
401feafa DB	52	/* we expect static quirk code to handle the "extended capabilities"
	53	* (currently just BIOS handoff) allowed starting with EHCI 0.96
	54	*/
18807521 DB	55
	56	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	57	retval = pci_set_mwi(pdev);
	58	if (!retval)
	59	ehci_dbg(ehci, "MWI active\n");
	60
	61	ehci_port_power(ehci, 0);
	62
	63	return 0;
	64	}
	65
8926bfa7 DB	66	/* called during probe() after chip reset completes */
8926bfa7 DB	67	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	68	{
abcc9448 DB	69	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	70	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	71	u32 temp;
18807521	72	int retval;
7ff71d6a	73
083522d7 BH	74	switch (pdev->vendor) {
	75	case PCI_VENDOR_ID_TOSHIBA_2:
	76	/* celleb's companion chip */
	77	if (pdev->device == 0x01b5) {
	78	#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
	79	ehci->big_endian_mmio = 1;
	80	#else
	81	ehci_warn(ehci,
	82	"unsupported big endian Toshiba quirk\n");
	83	#endif
	84	}
	85	break;
	86	}
	87
7ff71d6a	88	ehci->caps = hcd->regs;
083522d7 BH	89	ehci->regs = hcd->regs +
	90	HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
	91
abcc9448 DB	92	dbg_hcs_params(ehci, "reset");
abcc9448 DB	93	dbg_hcc_params(ehci, "reset");
7ff71d6a	94
c32ba30f PS	95	/* ehci_init() causes memory for DMA transfers to be
	96	* allocated. Thus, any vendor-specific workarounds based on
	97	* limiting the type of memory used for DMA transfers must
	98	* happen before ehci_init() is called. */
	99	switch (pdev->vendor) {
	100	case PCI_VENDOR_ID_NVIDIA:
	101	/* NVidia reports that certain chips don't handle
	102	* QH, ITD, or SITD addresses above 2GB. (But TD,
	103	* data buffer, and periodic schedule are normal.)
	104	*/
	105	switch (pdev->device) {
	106	case 0x003c: /* MCP04 */
	107	case 0x005b: /* CK804 */
	108	case 0x00d8: /* CK8 */
	109	case 0x00e8: /* CK8S */
	110	if (pci_set_consistent_dma_mask(pdev,
	111	DMA_31BIT_MASK) < 0)
	112	ehci_warn(ehci, "can't enable NVidia "
	113	"workaround for >2GB RAM\n");
	114	break;
	115	}
	116	break;
	117	}
	118
7ff71d6a	119	/* cache this readonly data; minimize chip reads */
083522d7	120	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
7ff71d6a	121
18807521 DB	122	retval = ehci_halt(ehci);
	123	if (retval)
	124	return retval;
	125
8926bfa7 DB	126	/* data structure init */
	127	retval = ehci_init(hcd);
	128	if (retval)
	129	return retval;
	130
abcc9448 DB	131	switch (pdev->vendor) {
	132	case PCI_VENDOR_ID_TDI:
	133	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
	134	ehci->is_tdi_rh_tt = 1;
	135	tdi_reset(ehci);
	136	}
	137	break;
	138	case PCI_VENDOR_ID_AMD:
	139	/* AMD8111 EHCI doesn't work, according to AMD errata */
	140	if (pdev->device == 0x7463) {
	141	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	142	retval = -EIO;
8926bfa7 DB	143	goto done;
abcc9448 DB	144	}
	145	break;
	146	case PCI_VENDOR_ID_NVIDIA:
f8aeb3bb	147	switch (pdev->device) {
f8aeb3bb DB	148	/* Some NForce2 chips have problems with selective suspend;
	149	* fixed in newer silicon.
	150	*/
	151	case 0x0068:
44c10138	152	if (pdev->revision < 0xa4)
f8aeb3bb DB	153	ehci->no_selective_suspend = 1;
f8aeb3bb DB	154	break;
7ff71d6a	155	}
abcc9448 DB	156	break;
abcc9448 DB	157	}
7ff71d6a	158
7ff71d6a	159	if (ehci_is_TDI(ehci))
abcc9448	160	ehci_reset(ehci);
7ff71d6a	161
7ff71d6a MP	162	/* at least the Genesys GL880S needs fixup here */
	163	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	164	temp &= 0x0f;
	165	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	166	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	167	"cc=%d x pcc=%d < ports=%d\n",
	168	HCS_N_CC(ehci->hcs_params),
	169	HCS_N_PCC(ehci->hcs_params),
	170	HCS_N_PORTS(ehci->hcs_params));
	171
abcc9448 DB	172	switch (pdev->vendor) {
	173	case 0x17a0: /* GENESYS */
	174	/* GL880S: should be PORTS=2 */
	175	temp \|= (ehci->hcs_params & ~0xf);
	176	ehci->hcs_params = temp;
	177	break;
	178	case PCI_VENDOR_ID_NVIDIA:
	179	/* NF4: should be PCC=10 */
	180	break;
7ff71d6a MP	181	}
	182	}
	183
abcc9448 DB	184	/* Serial Bus Release Number is at PCI 0x60 offset */
abcc9448 DB	185	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	186
2c1c3c4c DB	187	/* Workaround current PCI init glitch: wakeup bits aren't
	188	* being set from PCI PM capability.
	189	*/
	190	if (!device_can_wakeup(&pdev->dev)) {
	191	u16 port_wake;
	192
	193	pci_read_config_word(pdev, 0x62, &port_wake);
	194	if (port_wake & 0x0001)
	195	device_init_wakeup(&pdev->dev, 1);
	196	}
7ff71d6a	197
f8aeb3bb DB	198	#ifdef CONFIG_USB_SUSPEND
	199	/* REVISIT: the controller works fine for wakeup iff the root hub
	200	* itself is "globally" suspended, but usbcore currently doesn't
	201	* understand such things.
	202	*
	203	* System suspend currently expects to be able to suspend the entire
	204	* device tree, device-at-a-time. If we failed selective suspend
	205	* reports, system suspend would fail; so the root hub code must claim
	206	* success. That's lying to usbcore, and it matters for for runtime
	207	* PM scenarios with selective suspend and remote wakeup...
	208	*/
	209	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
	210	ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
	211	#endif
	212
18807521	213	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	214	done:
8926bfa7 DB	215	return retval;
7ff71d6a MP	216	}
	217
	218	/-------------------------------------------------------------------------/
	219
	220	#ifdef CONFIG_PM
	221
	222	/* suspend/resume, section 4.3 */
	223
f03c17fc	224	/* These routines rely on the PCI bus glue
7ff71d6a MP	225	* to handle powerdown and wakeup, and currently also on
	226	* transceivers that don't need any software attention to set up
	227	* the right sort of wakeup.
f03c17fc	228	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	229	*/
7ff71d6a MP	230
abcc9448	231	static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
7ff71d6a	232	{
abcc9448	233	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
8de98402 BH	234	unsigned long flags;
8de98402 BH	235	int rc = 0;
7ff71d6a	236
abcc9448 DB	237	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	238	msleep(10);
7ff71d6a	239
8de98402 BH	240	/* Root hub was already suspended. Disable irq emission and
	241	* mark HW unaccessible, bail out if RH has been resumed. Use
	242	* the spinlock to properly synchronize with possible pending
	243	* RH suspend or resume activity.
	244	*
	245	* This is still racy as hcd->state is manipulated outside of
	246	* any locks =P But that will be a different fix.
	247	*/
	248	spin_lock_irqsave (&ehci->lock, flags);
	249	if (hcd->state != HC_STATE_SUSPENDED) {
	250	rc = -EINVAL;
	251	goto bail;
	252	}
083522d7 BH	253	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
083522d7 BH	254	(void)ehci_readl(ehci, &ehci->regs->intr_enable);
8de98402	255
18584999 DB	256	/* make sure snapshot being resumed re-enumerates everything */
	257	if (message.event == PM_EVENT_PRETHAW) {
	258	ehci_halt(ehci);
	259	ehci_reset(ehci);
	260	}
	261
8de98402 BH	262	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	263	bail:
	264	spin_unlock_irqrestore (&ehci->lock, flags);
	265
f03c17fc	266	// could save FLADJ in case of Vaux power loss
7ff71d6a MP	267	// ... we'd only use it to handle clock skew
7ff71d6a MP	268
8de98402	269	return rc;
7ff71d6a MP	270	}
7ff71d6a MP	271
abcc9448	272	static int ehci_pci_resume(struct usb_hcd *hcd)
7ff71d6a	273	{
abcc9448	274	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
18807521	275	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	276
f03c17fc	277	// maybe restore FLADJ
7ff71d6a	278
abcc9448 DB	279	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	280	msleep(100);
7ff71d6a	281
8de98402 BH	282	/* Mark hardware accessible again as we are out of D3 state by now */
	283	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	284
8c03356a AS	285	/* If CF is still set, we maintained PCI Vaux power.
8c03356a AS	286	* Just undo the effect of ehci_pci_suspend().
7ff71d6a	287	*/
083522d7	288	if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
8c03356a AS	289	int mask = INTR_MASK;
	290
	291	if (!device_may_wakeup(&hcd->self.root_hub->dev))
	292	mask &= ~STS_PCD;
083522d7 BH	293	ehci_writel(ehci, mask, &ehci->regs->intr_enable);
083522d7 BH	294	ehci_readl(ehci, &ehci->regs->intr_enable);
8c03356a	295	return 0;
f03c17fc DB	296	}
f03c17fc DB	297
f03c17fc	298	ehci_dbg(ehci, "lost power, restarting\n");
1c50c317	299	usb_root_hub_lost_power(hcd->self.root_hub);
7ff71d6a MP	300
7ff71d6a MP	301	/* Else reset, to cope with power loss or flush-to-storage
f03c17fc	302	* style "resume" having let BIOS kick in during reboot.
7ff71d6a	303	*/
abcc9448 DB	304	(void) ehci_halt(ehci);
abcc9448 DB	305	(void) ehci_reset(ehci);
18807521	306	(void) ehci_pci_reinit(ehci, pdev);
f03c17fc DB	307
f03c17fc DB	308	/* emptying the schedule aborts any urbs */
abcc9448	309	spin_lock_irq(&ehci->lock);
f03c17fc	310	if (ehci->reclaim)
64f89798	311	ehci->reclaim_ready = 1;
7d12e780	312	ehci_work(ehci);
abcc9448	313	spin_unlock_irq(&ehci->lock);
f03c17fc	314
18807521	315	/* here we "know" root ports should always stay powered */
abcc9448	316	ehci_port_power(ehci, 1);
7ff71d6a	317
083522d7 BH	318	ehci_writel(ehci, ehci->command, &ehci->regs->command);
	319	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
	320	ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
8c03356a AS	321
	322	hcd->state = HC_STATE_SUSPENDED;
	323	return 0;
7ff71d6a MP	324	}
	325	#endif
	326
	327	static const struct hc_driver ehci_pci_hc_driver = {
	328	.description = hcd_name,
	329	.product_desc = "EHCI Host Controller",
	330	.hcd_priv_size = sizeof(struct ehci_hcd),
	331
	332	/*
	333	* generic hardware linkage
	334	*/
	335	.irq = ehci_irq,
	336	.flags = HCD_MEMORY \| HCD_USB2,
	337
	338	/*
	339	* basic lifecycle operations
	340	*/
8926bfa7	341	.reset = ehci_pci_setup,
18807521	342	.start = ehci_run,
7ff71d6a MP	343	#ifdef CONFIG_PM
	344	.suspend = ehci_pci_suspend,
	345	.resume = ehci_pci_resume,
	346	#endif
18807521	347	.stop = ehci_stop,
64a21d02	348	.shutdown = ehci_shutdown,
7ff71d6a MP	349
	350	/*
	351	* managing i/o requests and associated device resources
	352	*/
	353	.urb_enqueue = ehci_urb_enqueue,
	354	.urb_dequeue = ehci_urb_dequeue,
	355	.endpoint_disable = ehci_endpoint_disable,
	356
	357	/*
	358	* scheduling support
	359	*/
	360	.get_frame_number = ehci_get_frame,
	361
	362	/*
	363	* root hub support
	364	*/
	365	.hub_status_data = ehci_hub_status_data,
	366	.hub_control = ehci_hub_control,
0c0382e3 AS	367	.bus_suspend = ehci_bus_suspend,
0c0382e3 AS	368	.bus_resume = ehci_bus_resume,
7ff71d6a MP	369	};
	370
	371	/-------------------------------------------------------------------------/
	372
	373	/* PCI driver selection metadata; PCI hotplugging uses this */
	374	static const struct pci_device_id pci_ids [] = { {
	375	/* handle any USB 2.0 EHCI controller */
c67808ee	376	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
7ff71d6a MP	377	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	378	},
	379	{ /* end: all zeroes */ }
	380	};
abcc9448	381	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	382
	383	/* pci driver glue; this is a "new style" PCI driver module */
	384	static struct pci_driver ehci_pci_driver = {
	385	.name = (char *) hcd_name,
	386	.id_table = pci_ids,
	387
	388	.probe = usb_hcd_pci_probe,
	389	.remove = usb_hcd_pci_remove,
	390
	391	#ifdef CONFIG_PM
	392	.suspend = usb_hcd_pci_suspend,
	393	.resume = usb_hcd_pci_resume,
	394	#endif
64a21d02	395	.shutdown = usb_hcd_pci_shutdown,
7ff71d6a	396	};