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Staging: vme: Add ca91cx42 rmw support
[net-next-2.6.git] / drivers / staging / vme / bridges / vme_ca91cx42.c
CommitLineData
60479690
MW		 1/*
2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
3 *
66bd8db5
MW		 4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
60479690
MW		 6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * Derived from ca91c042.c by Michael Wyrick
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
60479690
MW		 18#include <linux/module.h>
19#include <linux/mm.h>
20#include <linux/types.h>
21#include <linux/errno.h>
60479690
MW		 22#include <linux/pci.h>
23#include <linux/dma-mapping.h>
24#include <linux/poll.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
6af783c8 27#include <linux/sched.h>
60479690
MW		 28#include <asm/time.h>
29#include <asm/io.h>
30#include <asm/uaccess.h>
31
32#include "../vme.h"
33#include "../vme_bridge.h"
34#include "vme_ca91cx42.h"
35
3d0f8bc7
MW		 36static int __init ca91cx42_init(void);
37static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
38static void ca91cx42_remove(struct pci_dev *);
39static void __exit ca91cx42_exit(void);
60479690 40
12b2d5c0
MW		 41/* Module parameters */
42static int geoid;
43
3d0f8bc7 44static char driver_name[] = "vme_ca91cx42";
60479690 45
13ac58da 46static const struct pci_device_id ca91cx42_ids[] = {
3d0f8bc7
MW		 47 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
48 { },
60479690
MW		 49};
50
3d0f8bc7
MW		 51static struct pci_driver ca91cx42_driver = {
52 .name = driver_name,
53 .id_table = ca91cx42_ids,
54 .probe = ca91cx42_probe,
55 .remove = ca91cx42_remove,
60479690
MW		 56};
57
29848ac9 58static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
60479690 59{
29848ac9 60 wake_up(&(bridge->dma_queue));
60479690 61
3d0f8bc7
MW		 62 return CA91CX42_LINT_DMA;
63}
60479690 64
29848ac9 65static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
3d0f8bc7
MW		 66{
67 int i;
68 u32 serviced = 0;
60479690 69
3d0f8bc7
MW		 70 for (i = 0; i < 4; i++) {
71 if (stat & CA91CX42_LINT_LM[i]) {
72 /* We only enable interrupts if the callback is set */
29848ac9 73 bridge->lm_callback[i](i);
3d0f8bc7 74 serviced |= CA91CX42_LINT_LM[i];
60479690 75 }
60479690 76 }
60479690 77
3d0f8bc7
MW		 78 return serviced;
79}
60479690 80
3d0f8bc7 81/* XXX This needs to be split into 4 queues */
29848ac9 82static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
3d0f8bc7 83{
29848ac9 84 wake_up(&(bridge->mbox_queue));
60479690 85
3d0f8bc7
MW		 86 return CA91CX42_LINT_MBOX;
87}
60479690 88
29848ac9 89static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
3d0f8bc7 90{
29848ac9 91 wake_up(&(bridge->iack_queue));
60479690 92
3d0f8bc7 93 return CA91CX42_LINT_SW_IACK;
60479690
MW		 94}
95
3d0f8bc7
MW		 96#if 0
97int ca91cx42_bus_error_chk(int clrflag)
60479690
MW		 98{
99 int tmp;
29848ac9 100 tmp = ioread32(bridge->base + PCI_COMMAND);
3d0f8bc7 101 if (tmp & 0x08000000) { /* S_TA is Set */
60479690 102 if (clrflag)
3d0f8bc7 103 iowrite32(tmp | 0x08000000,
29848ac9 104 bridge->base + PCI_COMMAND);
3d0f8bc7 105 return 1;
60479690 106 }
3d0f8bc7 107 return 0;
60479690 108}
3d0f8bc7 109#endif
60479690 110
29848ac9 111static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge)
60479690
MW		 112{
113 int val;
114
29848ac9 115 val = ioread32(bridge->base + DGCS);
60479690
MW		 116
117 if (!(val & 0x00000800)) {
3d0f8bc7
MW		 118 printk(KERN_ERR "ca91c042: ca91cx42_VERR_irqhandler DMA Read "
119 "Error DGCS=%08X\n", val);
60479690 120 }
3d0f8bc7
MW		 121
122 return CA91CX42_LINT_VERR;
60479690
MW		 123}
124
29848ac9 125static u32 ca91cx42_LERR_irqhandler(struct ca91cx42_driver *bridge)
60479690
MW		 126{
127 int val;
128
29848ac9 129 val = ioread32(bridge->base + DGCS);
60479690
MW		 130
131 if (!(val & 0x00000800)) {
3d0f8bc7
MW		 132 printk(KERN_ERR "ca91c042: ca91cx42_LERR_irqhandler DMA Read "
133 "Error DGCS=%08X\n", val);
60479690 134
60479690 135 }
60479690 136
3d0f8bc7 137 return CA91CX42_LINT_LERR;
60479690
MW		 138}
139
3d0f8bc7 140
29848ac9
MW		 141static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
142 int stat)
60479690 143{
3d0f8bc7 144 int vec, i, serviced = 0;
29848ac9
MW		 145 struct ca91cx42_driver *bridge;
146
147 bridge = ca91cx42_bridge->driver_priv;
148
60479690
MW		 149
150 for (i = 7; i > 0; i--) {
3d0f8bc7 151 if (stat & (1 << i)) {
29848ac9 152 vec = ioread32(bridge->base +
3d0f8bc7
MW		 153 CA91CX42_V_STATID[i]) & 0xff;
154
c813f592 155 vme_irq_handler(ca91cx42_bridge, i, vec);
3d0f8bc7
MW		 156
157 serviced |= (1 << i);
60479690
MW		 158 }
159 }
3d0f8bc7
MW		 160
161 return serviced;
60479690
MW		 162}
163
29848ac9 164static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
60479690 165{
3d0f8bc7 166 u32 stat, enable, serviced = 0;
29848ac9
MW		 167 struct vme_bridge *ca91cx42_bridge;
168 struct ca91cx42_driver *bridge;
60479690 169
29848ac9 170 ca91cx42_bridge = ptr;
60479690 171
29848ac9
MW		 172 bridge = ca91cx42_bridge->driver_priv;
173
174 enable = ioread32(bridge->base + LINT_EN);
175 stat = ioread32(bridge->base + LINT_STAT);
60479690 176
3d0f8bc7
MW		 177 /* Only look at unmasked interrupts */
178 stat &= enable;
179
180 if (unlikely(!stat))
181 return IRQ_NONE;
182
183 if (stat & CA91CX42_LINT_DMA)
29848ac9 184 serviced |= ca91cx42_DMA_irqhandler(bridge);
3d0f8bc7
MW		 185 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
186 CA91CX42_LINT_LM3))
29848ac9 187 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
3d0f8bc7 188 if (stat & CA91CX42_LINT_MBOX)
29848ac9 189 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
3d0f8bc7 190 if (stat & CA91CX42_LINT_SW_IACK)
29848ac9 191 serviced |= ca91cx42_IACK_irqhandler(bridge);
3d0f8bc7 192 if (stat & CA91CX42_LINT_VERR)
29848ac9 193 serviced |= ca91cx42_VERR_irqhandler(bridge);
3d0f8bc7 194 if (stat & CA91CX42_LINT_LERR)
29848ac9 195 serviced |= ca91cx42_LERR_irqhandler(bridge);
3d0f8bc7
MW		 196 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
197 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
198 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
199 CA91CX42_LINT_VIRQ7))
29848ac9 200 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
3d0f8bc7
MW		 201
202 /* Clear serviced interrupts */
29848ac9 203 iowrite32(stat, bridge->base + LINT_STAT);
60479690
MW		 204
205 return IRQ_HANDLED;
206}
207
29848ac9 208static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
60479690 209{
3d0f8bc7
MW		 210 int result, tmp;
211 struct pci_dev *pdev;
29848ac9
MW		 212 struct ca91cx42_driver *bridge;
213
214 bridge = ca91cx42_bridge->driver_priv;
60479690 215
3d0f8bc7 216 /* Need pdev */
29848ac9 217 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
60479690 218
3d0f8bc7 219 /* Initialise list for VME bus errors */
29848ac9 220 INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors));
60479690 221
29848ac9 222 mutex_init(&(ca91cx42_bridge->irq_mtx));
c813f592 223
3d0f8bc7
MW		 224 /* Disable interrupts from PCI to VME */
225 iowrite32(0, bridge->base + VINT_EN);
60479690 226
3d0f8bc7
MW		 227 /* Disable PCI interrupts */
228 iowrite32(0, bridge->base + LINT_EN);
229 /* Clear Any Pending PCI Interrupts */
230 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
60479690 231
3d0f8bc7 232 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
29848ac9 233 driver_name, ca91cx42_bridge);
3d0f8bc7
MW		 234 if (result) {
235 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
236 pdev->irq);
237 return result;
60479690
MW		 238 }
239
3d0f8bc7
MW		 240 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
241 iowrite32(0, bridge->base + LINT_MAP0);
242 iowrite32(0, bridge->base + LINT_MAP1);
243 iowrite32(0, bridge->base + LINT_MAP2);
244
245 /* Enable DMA, mailbox & LM Interrupts */
246 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
247 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
248 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
249
250 iowrite32(tmp, bridge->base + LINT_EN);
60479690 251
3d0f8bc7 252 return 0;
60479690
MW		 253}
254
29848ac9
MW		 255static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
256 struct pci_dev *pdev)
60479690 257{
3d0f8bc7 258 /* Disable interrupts from PCI to VME */
29848ac9 259 iowrite32(0, bridge->base + VINT_EN);
60479690 260
3d0f8bc7 261 /* Disable PCI interrupts */
29848ac9 262 iowrite32(0, bridge->base + LINT_EN);
3d0f8bc7 263 /* Clear Any Pending PCI Interrupts */
29848ac9 264 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
60479690 265
3d0f8bc7
MW		 266 free_irq(pdev->irq, pdev);
267}
60479690 268
3d0f8bc7
MW		 269/*
270 * Set up an VME interrupt
271 */
29848ac9
MW		 272void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state,
273 int sync)
c813f592 274
3d0f8bc7 275{
c813f592 276 struct pci_dev *pdev;
3d0f8bc7 277 u32 tmp;
29848ac9
MW		 278 struct ca91cx42_driver *bridge;
279
280 bridge = ca91cx42_bridge->driver_priv;
60479690 281
3d0f8bc7 282 /* Enable IRQ level */
29848ac9 283 tmp = ioread32(bridge->base + LINT_EN);
3d0f8bc7 284
c813f592 285 if (state == 0)
3d0f8bc7 286 tmp &= ~CA91CX42_LINT_VIRQ[level];
c813f592
MW		 287 else
288 tmp |= CA91CX42_LINT_VIRQ[level];
60479690 289
29848ac9 290 iowrite32(tmp, bridge->base + LINT_EN);
c813f592
MW		 291
292 if ((state == 0) && (sync != 0)) {
3d0f8bc7
MW		 293 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
294 dev);
295
296 synchronize_irq(pdev->irq);
60479690 297 }
60479690
MW		 298}
299
29848ac9
MW		 300int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
301 int statid)
60479690 302{
3d0f8bc7 303 u32 tmp;
29848ac9
MW		 304 struct ca91cx42_driver *bridge;
305
306 bridge = ca91cx42_bridge->driver_priv;
60479690 307
3d0f8bc7
MW		 308 /* Universe can only generate even vectors */
309 if (statid & 1)
310 return -EINVAL;
60479690 311
29848ac9 312 mutex_lock(&(bridge->vme_int));
60479690 313
29848ac9 314 tmp = ioread32(bridge->base + VINT_EN);
60479690 315
3d0f8bc7 316 /* Set Status/ID */
29848ac9 317 iowrite32(statid << 24, bridge->base + STATID);
3d0f8bc7
MW		 318
319 /* Assert VMEbus IRQ */
320 tmp = tmp | (1 << (level + 24));
29848ac9 321 iowrite32(tmp, bridge->base + VINT_EN);
60479690 322
3d0f8bc7 323 /* Wait for IACK */
29848ac9 324 wait_event_interruptible(bridge->iack_queue, 0);
3d0f8bc7
MW		 325
326 /* Return interrupt to low state */
29848ac9 327 tmp = ioread32(bridge->base + VINT_EN);
3d0f8bc7 328 tmp = tmp & ~(1 << (level + 24));
29848ac9 329 iowrite32(tmp, bridge->base + VINT_EN);
3d0f8bc7 330
29848ac9 331 mutex_unlock(&(bridge->vme_int));
3d0f8bc7
MW		 332
333 return 0;
60479690
MW		 334}
335
3d0f8bc7
MW		 336int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
337 unsigned long long vme_base, unsigned long long size,
338 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
60479690 339{
21e0cf6d 340 unsigned int i, addr = 0, granularity;
3d0f8bc7
MW		 341 unsigned int temp_ctl = 0;
342 unsigned int vme_bound, pci_offset;
29848ac9
MW		 343 struct ca91cx42_driver *bridge;
344
345 bridge = image->parent->driver_priv;
60479690 346
3d0f8bc7 347 i = image->number;
60479690 348
3d0f8bc7
MW		 349 switch (aspace) {
350 case VME_A16:
351 addr |= CA91CX42_VSI_CTL_VAS_A16;
352 break;
353 case VME_A24:
354 addr |= CA91CX42_VSI_CTL_VAS_A24;
355 break;
356 case VME_A32:
357 addr |= CA91CX42_VSI_CTL_VAS_A32;
358 break;
359 case VME_USER1:
360 addr |= CA91CX42_VSI_CTL_VAS_USER1;
361 break;
362 case VME_USER2:
363 addr |= CA91CX42_VSI_CTL_VAS_USER2;
364 break;
365 case VME_A64:
366 case VME_CRCSR:
367 case VME_USER3:
368 case VME_USER4:
369 default:
370 printk(KERN_ERR "Invalid address space\n");
371 return -EINVAL;
372 break;
60479690
MW		 373 }
374
3d0f8bc7
MW		 375 /*
376 * Bound address is a valid address for the window, adjust
377 * accordingly
378 */
21e0cf6d 379 vme_bound = vme_base + size;
3d0f8bc7
MW		 380 pci_offset = pci_base - vme_base;
381
382 /* XXX Need to check that vme_base, vme_bound and pci_offset aren't
383 * too big for registers
384 */
385
386 if ((i == 0) || (i == 4))
387 granularity = 0x1000;
388 else
389 granularity = 0x10000;
390
391 if (vme_base & (granularity - 1)) {
392 printk(KERN_ERR "Invalid VME base alignment\n");
393 return -EINVAL;
394 }
395 if (vme_bound & (granularity - 1)) {
396 printk(KERN_ERR "Invalid VME bound alignment\n");
397 return -EINVAL;
398 }
399 if (pci_offset & (granularity - 1)) {
400 printk(KERN_ERR "Invalid PCI Offset alignment\n");
401 return -EINVAL;
60479690
MW		 402 }
403
3d0f8bc7 404 /* Disable while we are mucking around */
29848ac9 405 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7 406 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
29848ac9 407 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
60479690 408
3d0f8bc7 409 /* Setup mapping */
29848ac9
MW		 410 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
411 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
412 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
3d0f8bc7
MW		 413
414/* XXX Prefetch stuff currently unsupported */
415#if 0
416 if (vmeIn->wrPostEnable)
417 temp_ctl |= CA91CX42_VSI_CTL_PWEN;
418 if (vmeIn->prefetchEnable)
419 temp_ctl |= CA91CX42_VSI_CTL_PREN;
420 if (vmeIn->rmwLock)
421 temp_ctl |= CA91CX42_VSI_CTL_LLRMW;
422 if (vmeIn->data64BitCapable)
423 temp_ctl |= CA91CX42_VSI_CTL_LD64EN;
424#endif
425
426 /* Setup address space */
427 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
428 temp_ctl |= addr;
429
430 /* Setup cycle types */
431 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
432 if (cycle & VME_SUPER)
433 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
434 if (cycle & VME_USER)
435 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
436 if (cycle & VME_PROG)
437 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
438 if (cycle & VME_DATA)
439 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
440
441 /* Write ctl reg without enable */
29848ac9 442 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7
MW		 443
444 if (enabled)
445 temp_ctl |= CA91CX42_VSI_CTL_EN;
446
29848ac9 447 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7
MW		 448
449 return 0;
60479690
MW		 450}
451
3d0f8bc7
MW		 452int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
453 unsigned long long *vme_base, unsigned long long *size,
454 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
60479690 455{
3d0f8bc7
MW		 456 unsigned int i, granularity = 0, ctl = 0;
457 unsigned long long vme_bound, pci_offset;
29848ac9
MW		 458 struct ca91cx42_driver *bridge;
459
460 bridge = image->parent->driver_priv;
3d0f8bc7
MW		 461
462 i = image->number;
60479690 463
3d0f8bc7
MW		 464 if ((i == 0) || (i == 4))
465 granularity = 0x1000;
466 else
467 granularity = 0x10000;
468
469 /* Read Registers */
29848ac9 470 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
3d0f8bc7 471
29848ac9
MW		 472 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
473 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
474 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
3d0f8bc7
MW		 475
476 *pci_base = (dma_addr_t)vme_base + pci_offset;
477 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
478
479 *enabled = 0;
480 *aspace = 0;
481 *cycle = 0;
482
483 if (ctl & CA91CX42_VSI_CTL_EN)
484 *enabled = 1;
485
486 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
487 *aspace = VME_A16;
488 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
489 *aspace = VME_A24;
490 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
491 *aspace = VME_A32;
492 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
493 *aspace = VME_USER1;
494 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
495 *aspace = VME_USER2;
496
497 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
498 *cycle |= VME_SUPER;
499 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
500 *cycle |= VME_USER;
501 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
502 *cycle |= VME_PROG;
503 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
504 *cycle |= VME_DATA;
505
506 return 0;
507}
508
509/*
510 * Allocate and map PCI Resource
511 */
512static int ca91cx42_alloc_resource(struct vme_master_resource *image,
513 unsigned long long size)
514{
515 unsigned long long existing_size;
516 int retval = 0;
517 struct pci_dev *pdev;
29848ac9
MW		 518 struct vme_bridge *ca91cx42_bridge;
519
520 ca91cx42_bridge = image->parent;
3d0f8bc7
MW		 521
522 /* Find pci_dev container of dev */
523 if (ca91cx42_bridge->parent == NULL) {
524 printk(KERN_ERR "Dev entry NULL\n");
525 return -EINVAL;
526 }
527 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
528
8fafb476
MW		 529 existing_size = (unsigned long long)(image->bus_resource.end -
530 image->bus_resource.start);
3d0f8bc7
MW		 531
532 /* If the existing size is OK, return */
533 if (existing_size == (size - 1))
534 return 0;
535
536 if (existing_size != 0) {
537 iounmap(image->kern_base);
538 image->kern_base = NULL;
8fafb476
MW		 539 if (image->bus_resource.name != NULL)
540 kfree(image->bus_resource.name);
541 release_resource(&(image->bus_resource));
542 memset(&(image->bus_resource), 0, sizeof(struct resource));
3d0f8bc7
MW		 543 }
544
8fafb476
MW		 545 if (image->bus_resource.name == NULL) {
546 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
547 if (image->bus_resource.name == NULL) {
3d0f8bc7
MW		 548 printk(KERN_ERR "Unable to allocate memory for resource"
549 " name\n");
550 retval = -ENOMEM;
551 goto err_name;
552 }
60479690 553 }
3d0f8bc7 554
8fafb476 555 sprintf((char *)image->bus_resource.name, "%s.%d",
3d0f8bc7
MW		 556 ca91cx42_bridge->name, image->number);
557
8fafb476
MW		 558 image->bus_resource.start = 0;
559 image->bus_resource.end = (unsigned long)size;
560 image->bus_resource.flags = IORESOURCE_MEM;
3d0f8bc7
MW		 561
562 retval = pci_bus_alloc_resource(pdev->bus,
8fafb476 563 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
3d0f8bc7
MW		 564 0, NULL, NULL);
565 if (retval) {
566 printk(KERN_ERR "Failed to allocate mem resource for "
567 "window %d size 0x%lx start 0x%lx\n",
568 image->number, (unsigned long)size,
8fafb476 569 (unsigned long)image->bus_resource.start);
3d0f8bc7 570 goto err_resource;
60479690 571 }
3d0f8bc7
MW		 572
573 image->kern_base = ioremap_nocache(
8fafb476 574 image->bus_resource.start, size);
3d0f8bc7
MW		 575 if (image->kern_base == NULL) {
576 printk(KERN_ERR "Failed to remap resource\n");
577 retval = -ENOMEM;
578 goto err_remap;
60479690
MW		 579 }
580
3d0f8bc7
MW		 581 return 0;
582
583 iounmap(image->kern_base);
584 image->kern_base = NULL;
585err_remap:
8fafb476 586 release_resource(&(image->bus_resource));
3d0f8bc7 587err_resource:
8fafb476
MW		 588 kfree(image->bus_resource.name);
589 memset(&(image->bus_resource), 0, sizeof(struct resource));
3d0f8bc7
MW		 590err_name:
591 return retval;
592}
593
594/*
4860ab74
MW		 595 * Free and unmap PCI Resource
596 */
3d0f8bc7
MW		 597static void ca91cx42_free_resource(struct vme_master_resource *image)
598{
599 iounmap(image->kern_base);
600 image->kern_base = NULL;
8fafb476
MW		 601 release_resource(&(image->bus_resource));
602 kfree(image->bus_resource.name);
603 memset(&(image->bus_resource), 0, sizeof(struct resource));
3d0f8bc7
MW		 604}
605
606
607int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
608 unsigned long long vme_base, unsigned long long size,
609 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
610{
611 int retval = 0;
21e0cf6d 612 unsigned int i, granularity = 0;
3d0f8bc7
MW		 613 unsigned int temp_ctl = 0;
614 unsigned long long pci_bound, vme_offset, pci_base;
29848ac9
MW		 615 struct ca91cx42_driver *bridge;
616
617 bridge = image->parent->driver_priv;
3d0f8bc7 618
21e0cf6d
MW		 619 i = image->number;
620
621 if ((i == 0) || (i == 4))
622 granularity = 0x1000;
623 else
624 granularity = 0x10000;
625
3d0f8bc7 626 /* Verify input data */
21e0cf6d 627 if (vme_base & (granularity - 1)) {
3d0f8bc7
MW		 628 printk(KERN_ERR "Invalid VME Window alignment\n");
629 retval = -EINVAL;
630 goto err_window;
631 }
21e0cf6d 632 if (size & (granularity - 1)) {
3d0f8bc7
MW		 633 printk(KERN_ERR "Invalid VME Window alignment\n");
634 retval = -EINVAL;
635 goto err_window;
636 }
637
638 spin_lock(&(image->lock));
639
640 /* XXX We should do this much later, so that we can exit without
641 * needing to redo the mapping...
642 */
643 /*
644 * Let's allocate the resource here rather than further up the stack as
645 * it avoids pushing loads of bus dependant stuff up the stack
646 */
647 retval = ca91cx42_alloc_resource(image, size);
648 if (retval) {
649 spin_unlock(&(image->lock));
650 printk(KERN_ERR "Unable to allocate memory for resource "
651 "name\n");
652 retval = -ENOMEM;
653 goto err_res;
654 }
655
8fafb476 656 pci_base = (unsigned long long)image->bus_resource.start;
3d0f8bc7
MW		 657
658 /*
659 * Bound address is a valid address for the window, adjust
660 * according to window granularity.
661 */
21e0cf6d 662 pci_bound = pci_base + size;
3d0f8bc7
MW		 663 vme_offset = vme_base - pci_base;
664
3d0f8bc7 665 /* Disable while we are mucking around */
29848ac9 666 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7 667 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
29848ac9 668 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7
MW		 669
670/* XXX Prefetch stuff currently unsupported */
671#if 0
672 if (vmeOut->wrPostEnable)
673 temp_ctl |= 0x40000000;
674#endif
675
676 /* Setup cycle types */
677 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
678 if (cycle & VME_BLT)
679 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
680 if (cycle & VME_MBLT)
681 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
682
683 /* Setup data width */
684 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
685 switch (dwidth) {
686 case VME_D8:
687 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
688 break;
689 case VME_D16:
690 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
691 break;
692 case VME_D32:
693 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
694 break;
695 case VME_D64:
696 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
697 break;
698 default:
699 spin_unlock(&(image->lock));
700 printk(KERN_ERR "Invalid data width\n");
701 retval = -EINVAL;
702 goto err_dwidth;
703 break;
60479690 704 }
3d0f8bc7
MW		 705
706 /* Setup address space */
707 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
708 switch (aspace) {
60479690 709 case VME_A16:
3d0f8bc7 710 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
60479690
MW		 711 break;
712 case VME_A24:
3d0f8bc7 713 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
60479690
MW		 714 break;
715 case VME_A32:
3d0f8bc7
MW		 716 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
717 break;
718 case VME_CRCSR:
719 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
60479690
MW		 720 break;
721 case VME_USER1:
3d0f8bc7 722 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
60479690
MW		 723 break;
724 case VME_USER2:
3d0f8bc7
MW		 725 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
726 break;
727 case VME_A64:
728 case VME_USER3:
729 case VME_USER4:
730 default:
731 spin_unlock(&(image->lock));
732 printk(KERN_ERR "Invalid address space\n");
733 retval = -EINVAL;
734 goto err_aspace;
60479690
MW		 735 break;
736 }
737
3d0f8bc7
MW		 738 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
739 if (cycle & VME_SUPER)
740 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
741 if (cycle & VME_PROG)
742 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
60479690 743
3d0f8bc7 744 /* Setup mapping */
29848ac9
MW		 745 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
746 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
747 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
3d0f8bc7
MW		 748
749 /* Write ctl reg without enable */
29848ac9 750 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7
MW		 751
752 if (enabled)
753 temp_ctl |= CA91CX42_LSI_CTL_EN;
754
29848ac9 755 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7
MW		 756
757 spin_unlock(&(image->lock));
758 return 0;
759
760err_aspace:
761err_dwidth:
762 ca91cx42_free_resource(image);
763err_res:
764err_window:
765 return retval;
766}
767
768int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
769 unsigned long long *vme_base, unsigned long long *size,
770 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
771{
772 unsigned int i, ctl;
773 unsigned long long pci_base, pci_bound, vme_offset;
29848ac9
MW		 774 struct ca91cx42_driver *bridge;
775
776 bridge = image->parent->driver_priv;
3d0f8bc7
MW		 777
778 i = image->number;
779
29848ac9 780 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
3d0f8bc7 781
29848ac9
MW		 782 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
783 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
784 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
3d0f8bc7
MW		 785
786 *vme_base = pci_base + vme_offset;
21e0cf6d 787 *size = (unsigned long long)(pci_bound - pci_base);
3d0f8bc7
MW		 788
789 *enabled = 0;
790 *aspace = 0;
791 *cycle = 0;
792 *dwidth = 0;
793
794 if (ctl & CA91CX42_LSI_CTL_EN)
795 *enabled = 1;
796
797 /* Setup address space */
798 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
799 case CA91CX42_LSI_CTL_VAS_A16:
800 *aspace = VME_A16;
801 break;
802 case CA91CX42_LSI_CTL_VAS_A24:
803 *aspace = VME_A24;
804 break;
805 case CA91CX42_LSI_CTL_VAS_A32:
806 *aspace = VME_A32;
807 break;
808 case CA91CX42_LSI_CTL_VAS_CRCSR:
809 *aspace = VME_CRCSR;
810 break;
811 case CA91CX42_LSI_CTL_VAS_USER1:
812 *aspace = VME_USER1;
813 break;
814 case CA91CX42_LSI_CTL_VAS_USER2:
815 *aspace = VME_USER2;
816 break;
817 }
818
819 /* XXX Not sure howto check for MBLT */
820 /* Setup cycle types */
821 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
822 *cycle |= VME_BLT;
823 else
824 *cycle |= VME_SCT;
825
826 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
827 *cycle |= VME_SUPER;
828 else
829 *cycle |= VME_USER;
830
831 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
832 *cycle = VME_PROG;
833 else
834 *cycle = VME_DATA;
835
836 /* Setup data width */
837 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
838 case CA91CX42_LSI_CTL_VDW_D8:
839 *dwidth = VME_D8;
840 break;
841 case CA91CX42_LSI_CTL_VDW_D16:
842 *dwidth = VME_D16;
843 break;
844 case CA91CX42_LSI_CTL_VDW_D32:
845 *dwidth = VME_D32;
846 break;
847 case CA91CX42_LSI_CTL_VDW_D64:
848 *dwidth = VME_D64;
849 break;
850 }
851
852/* XXX Prefetch stuff currently unsupported */
853#if 0
854 if (ctl & 0x40000000)
855 vmeOut->wrPostEnable = 1;
856#endif
857
858 return 0;
859}
860
861int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
862 unsigned long long *vme_base, unsigned long long *size,
863 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
864{
865 int retval;
866
867 spin_lock(&(image->lock));
868
869 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
870 cycle, dwidth);
871
872 spin_unlock(&(image->lock));
873
874 return retval;
875}
876
877ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf,
878 size_t count, loff_t offset)
879{
21e0cf6d 880 ssize_t retval;
60479690 881
3d0f8bc7 882 spin_lock(&(image->lock));
60479690 883
3d0f8bc7
MW		 884 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
885 retval = count;
60479690 886
3d0f8bc7
MW		 887 spin_unlock(&(image->lock));
888
889 return retval;
60479690
MW		 890}
891
3d0f8bc7
MW		 892ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
893 size_t count, loff_t offset)
60479690 894{
3d0f8bc7 895 int retval = 0;
60479690 896
3d0f8bc7 897 spin_lock(&(image->lock));
60479690 898
3d0f8bc7
MW		 899 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
900 retval = count;
901
902 spin_unlock(&(image->lock));
903
904 return retval;
60479690
MW		 905}
906
04e10e15
MW		 907unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
908 unsigned int mask, unsigned int compare, unsigned int swap,
909 loff_t offset)
910{
911 u32 pci_addr, result;
912 int i;
913 struct ca91cx42_driver *bridge;
914 struct device *dev;
915
916 bridge = image->parent->driver_priv;
917 dev = image->parent->parent;
918
919 /* Find the PCI address that maps to the desired VME address */
920 i = image->number;
921
922 /* Locking as we can only do one of these at a time */
923 mutex_lock(&(bridge->vme_rmw));
924
925 /* Lock image */
926 spin_lock(&(image->lock));
927
928 pci_addr = (u32)image->kern_base + offset;
929
930 /* Address must be 4-byte aligned */
931 if (pci_addr & 0x3) {
932 dev_err(dev, "RMW Address not 4-byte aligned\n");
933 return -EINVAL;
934 }
935
936 /* Ensure RMW Disabled whilst configuring */
937 iowrite32(0, bridge->base + SCYC_CTL);
938
939 /* Configure registers */
940 iowrite32(mask, bridge->base + SCYC_EN);
941 iowrite32(compare, bridge->base + SCYC_CMP);
942 iowrite32(swap, bridge->base + SCYC_SWP);
943 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
944
945 /* Enable RMW */
946 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
947
948 /* Kick process off with a read to the required address. */
949 result = ioread32(image->kern_base + offset);
950
951 /* Disable RMW */
952 iowrite32(0, bridge->base + SCYC_CTL);
953
954 spin_unlock(&(image->lock));
955
956 mutex_unlock(&(bridge->vme_rmw));
957
958 return result;
959}
960
4860ab74
MW		 961int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
962 struct vme_dma_attr *dest, size_t count)
963{
964 struct ca91cx42_dma_entry *entry, *prev;
965 struct vme_dma_pci *pci_attr;
966 struct vme_dma_vme *vme_attr;
967 dma_addr_t desc_ptr;
968 int retval = 0;
969
970 /* XXX descriptor must be aligned on 64-bit boundaries */
971 entry = (struct ca91cx42_dma_entry *)
972 kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
973 if (entry == NULL) {
974 printk(KERN_ERR "Failed to allocate memory for dma resource "
975 "structure\n");
976 retval = -ENOMEM;
977 goto err_mem;
978 }
979
980 /* Test descriptor alignment */
981 if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) {
982 printk("Descriptor not aligned to 16 byte boundary as "
983 "required: %p\n", &(entry->descriptor));
984 retval = -EINVAL;
985 goto err_align;
986 }
987
988 memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor));
989
990 if (dest->type == VME_DMA_VME) {
991 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
992 vme_attr = (struct vme_dma_vme *)dest->private;
993 pci_attr = (struct vme_dma_pci *)src->private;
994 } else {
995 vme_attr = (struct vme_dma_vme *)src->private;
996 pci_attr = (struct vme_dma_pci *)dest->private;
997 }
998
999 /* Check we can do fullfill required attributes */
1000 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1001 VME_USER2)) != 0) {
1002
1003 printk(KERN_ERR "Unsupported cycle type\n");
1004 retval = -EINVAL;
1005 goto err_aspace;
1006 }
1007
1008 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1009 VME_PROG | VME_DATA)) != 0) {
1010
1011 printk(KERN_ERR "Unsupported cycle type\n");
1012 retval = -EINVAL;
1013 goto err_cycle;
1014 }
1015
1016 /* Check to see if we can fullfill source and destination */
1017 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1018 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1019
1020 printk(KERN_ERR "Cannot perform transfer with this "
1021 "source-destination combination\n");
1022 retval = -EINVAL;
1023 goto err_direct;
1024 }
1025
1026 /* Setup cycle types */
1027 if (vme_attr->cycle & VME_BLT)
1028 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1029
1030 /* Setup data width */
1031 switch (vme_attr->dwidth) {
1032 case VME_D8:
1033 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1034 break;
1035 case VME_D16:
1036 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1037 break;
1038 case VME_D32:
1039 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1040 break;
1041 case VME_D64:
1042 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1043 break;
1044 default:
1045 printk(KERN_ERR "Invalid data width\n");
1046 return -EINVAL;
1047 }
1048
1049 /* Setup address space */
1050 switch (vme_attr->aspace) {
1051 case VME_A16:
1052 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1053 break;
1054 case VME_A24:
1055 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1056 break;
1057 case VME_A32:
1058 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1059 break;
1060 case VME_USER1:
1061 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1062 break;
1063 case VME_USER2:
1064 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1065 break;
1066 default:
1067 printk(KERN_ERR "Invalid address space\n");
1068 return -EINVAL;
1069 break;
1070 }
1071
1072 if (vme_attr->cycle & VME_SUPER)
1073 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1074 if (vme_attr->cycle & VME_PROG)
1075 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1076
1077 entry->descriptor.dtbc = count;
1078 entry->descriptor.dla = pci_attr->address;
1079 entry->descriptor.dva = vme_attr->address;
1080 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1081
1082 /* Add to list */
1083 list_add_tail(&(entry->list), &(list->entries));
1084
1085 /* Fill out previous descriptors "Next Address" */
1086 if (entry->list.prev != &(list->entries)) {
1087 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1088 list);
1089 /* We need the bus address for the pointer */
1090 desc_ptr = virt_to_bus(&(entry->descriptor));
1091 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1092 }
1093
1094 return 0;
1095
1096err_cycle:
1097err_aspace:
1098err_direct:
1099err_align:
1100 kfree(entry);
1101err_mem:
1102 return retval;
1103}
1104
1105static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1106{
1107 u32 tmp;
1108 struct ca91cx42_driver *bridge;
1109
1110 bridge = ca91cx42_bridge->driver_priv;
1111
1112 tmp = ioread32(bridge->base + DGCS);
1113
1114 if (tmp & CA91CX42_DGCS_ACT)
1115 return 0;
1116 else
1117 return 1;
1118}
1119
1120int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1121{
1122 struct vme_dma_resource *ctrlr;
1123 struct ca91cx42_dma_entry *entry;
1124 int retval = 0;
1125 dma_addr_t bus_addr;
1126 u32 val;
1127
1128 struct ca91cx42_driver *bridge;
1129
1130 ctrlr = list->parent;
1131
1132 bridge = ctrlr->parent->driver_priv;
1133
1134 mutex_lock(&(ctrlr->mtx));
1135
1136 if (!(list_empty(&(ctrlr->running)))) {
1137 /*
1138 * XXX We have an active DMA transfer and currently haven't
1139 * sorted out the mechanism for "pending" DMA transfers.
1140 * Return busy.
1141 */
1142 /* Need to add to pending here */
1143 mutex_unlock(&(ctrlr->mtx));
1144 return -EBUSY;
1145 } else {
1146 list_add(&(list->list), &(ctrlr->running));
1147 }
1148
1149 /* Get first bus address and write into registers */
1150 entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry,
1151 list);
1152
1153 bus_addr = virt_to_bus(&(entry->descriptor));
1154
1155 mutex_unlock(&(ctrlr->mtx));
1156
1157 iowrite32(0, bridge->base + DTBC);
1158 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1159
1160 /* Start the operation */
1161 val = ioread32(bridge->base + DGCS);
1162
1163 /* XXX Could set VMEbus On and Off Counters here */
1164 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1165
1166 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1167 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1168 CA91CX42_DGCS_PERR);
1169
1170 iowrite32(val, bridge->base + DGCS);
1171
1172 val |= CA91CX42_DGCS_GO;
1173
1174 iowrite32(val, bridge->base + DGCS);
1175
1176 wait_event_interruptible(bridge->dma_queue,
1177 ca91cx42_dma_busy(ctrlr->parent));
1178
1179 /*
1180 * Read status register, this register is valid until we kick off a
1181 * new transfer.
1182 */
1183 val = ioread32(bridge->base + DGCS);
1184
1185 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1186 CA91CX42_DGCS_PERR)) {
1187
1188 printk(KERN_ERR "ca91c042: DMA Error. DGCS=%08X\n", val);
1189 val = ioread32(bridge->base + DCTL);
1190 }
1191
1192 /* Remove list from running list */
1193 mutex_lock(&(ctrlr->mtx));
1194 list_del(&(list->list));
1195 mutex_unlock(&(ctrlr->mtx));
1196
1197 return retval;
1198
1199}
1200
1201int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1202{
1203 struct list_head *pos, *temp;
1204 struct ca91cx42_dma_entry *entry;
1205
1206 /* detach and free each entry */
1207 list_for_each_safe(pos, temp, &(list->entries)) {
1208 list_del(pos);
1209 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1210 kfree(entry);
1211 }
1212
1213 return 0;
1214}
1215
2b82beb8
MW		 1216/*
1217 * All 4 location monitors reside at the same base - this is therefore a
1218 * system wide configuration.
1219 *
1220 * This does not enable the LM monitor - that should be done when the first
1221 * callback is attached and disabled when the last callback is removed.
1222 */
1223int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1224 vme_address_t aspace, vme_cycle_t cycle)
1225{
1226 u32 temp_base, lm_ctl = 0;
1227 int i;
1228 struct ca91cx42_driver *bridge;
1229 struct device *dev;
1230
1231 bridge = lm->parent->driver_priv;
1232 dev = lm->parent->parent;
1233
1234 /* Check the alignment of the location monitor */
1235 temp_base = (u32)lm_base;
1236 if (temp_base & 0xffff) {
1237 dev_err(dev, "Location monitor must be aligned to 64KB "
1238 "boundary");
1239 return -EINVAL;
1240 }
1241
1242 mutex_lock(&(lm->mtx));
1243
1244 /* If we already have a callback attached, we can't move it! */
1245 for (i = 0; i < lm->monitors; i++) {
1246 if (bridge->lm_callback[i] != NULL) {
1247 mutex_unlock(&(lm->mtx));
1248 dev_err(dev, "Location monitor callback attached, "
1249 "can't reset\n");
1250 return -EBUSY;
1251 }
1252 }
1253
1254 switch (aspace) {
1255 case VME_A16:
1256 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1257 break;
1258 case VME_A24:
1259 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1260 break;
1261 case VME_A32:
1262 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1263 break;
1264 default:
1265 mutex_unlock(&(lm->mtx));
1266 dev_err(dev, "Invalid address space\n");
1267 return -EINVAL;
1268 break;
1269 }
1270
1271 if (cycle & VME_SUPER)
1272 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1273 if (cycle & VME_USER)
1274 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1275 if (cycle & VME_PROG)
1276 lm_ctl |= CA91CX42_LM_CTL_PGM;
1277 if (cycle & VME_DATA)
1278 lm_ctl |= CA91CX42_LM_CTL_DATA;
1279
1280 iowrite32(lm_base, bridge->base + LM_BS);
1281 iowrite32(lm_ctl, bridge->base + LM_CTL);
1282
1283 mutex_unlock(&(lm->mtx));
1284
1285 return 0;
1286}
1287
1288/* Get configuration of the callback monitor and return whether it is enabled
1289 * or disabled.
1290 */
1291int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
1292 vme_address_t *aspace, vme_cycle_t *cycle)
1293{
1294 u32 lm_ctl, enabled = 0;
1295 struct ca91cx42_driver *bridge;
1296
1297 bridge = lm->parent->driver_priv;
1298
1299 mutex_lock(&(lm->mtx));
1300
1301 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1302 lm_ctl = ioread32(bridge->base + LM_CTL);
1303
1304 if (lm_ctl & CA91CX42_LM_CTL_EN)
1305 enabled = 1;
1306
1307 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1308 *aspace = VME_A16;
1309 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1310 *aspace = VME_A24;
1311 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1312 *aspace = VME_A32;
1313
1314 *cycle = 0;
1315 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1316 *cycle |= VME_SUPER;
1317 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1318 *cycle |= VME_USER;
1319 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1320 *cycle |= VME_PROG;
1321 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1322 *cycle |= VME_DATA;
1323
1324 mutex_unlock(&(lm->mtx));
1325
1326 return enabled;
1327}
1328
1329/*
1330 * Attach a callback to a specific location monitor.
1331 *
1332 * Callback will be passed the monitor triggered.
1333 */
1334int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1335 void (*callback)(int))
1336{
1337 u32 lm_ctl, tmp;
1338 struct ca91cx42_driver *bridge;
1339 struct device *dev;
1340
1341 bridge = lm->parent->driver_priv;
1342 dev = lm->parent->parent;
1343
1344 mutex_lock(&(lm->mtx));
1345
1346 /* Ensure that the location monitor is configured - need PGM or DATA */
1347 lm_ctl = ioread32(bridge->base + LM_CTL);
1348 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1349 mutex_unlock(&(lm->mtx));
1350 dev_err(dev, "Location monitor not properly configured\n");
1351 return -EINVAL;
1352 }
1353
1354 /* Check that a callback isn't already attached */
1355 if (bridge->lm_callback[monitor] != NULL) {
1356 mutex_unlock(&(lm->mtx));
1357 dev_err(dev, "Existing callback attached\n");
1358 return -EBUSY;
1359 }
1360
1361 /* Attach callback */
1362 bridge->lm_callback[monitor] = callback;
1363
1364 /* Enable Location Monitor interrupt */
1365 tmp = ioread32(bridge->base + LINT_EN);
1366 tmp |= CA91CX42_LINT_LM[monitor];
1367 iowrite32(tmp, bridge->base + LINT_EN);
1368
1369 /* Ensure that global Location Monitor Enable set */
1370 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1371 lm_ctl |= CA91CX42_LM_CTL_EN;
1372 iowrite32(lm_ctl, bridge->base + LM_CTL);
1373 }
1374
1375 mutex_unlock(&(lm->mtx));
1376
1377 return 0;
1378}
1379
1380/*
1381 * Detach a callback function forn a specific location monitor.
1382 */
1383int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1384{
1385 u32 tmp;
1386 struct ca91cx42_driver *bridge;
1387
1388 bridge = lm->parent->driver_priv;
1389
1390 mutex_lock(&(lm->mtx));
1391
1392 /* Disable Location Monitor and ensure previous interrupts are clear */
1393 tmp = ioread32(bridge->base + LINT_EN);
1394 tmp &= ~CA91CX42_LINT_LM[monitor];
1395 iowrite32(tmp, bridge->base + LINT_EN);
1396
1397 iowrite32(CA91CX42_LINT_LM[monitor],
1398 bridge->base + LINT_STAT);
1399
1400 /* Detach callback */
1401 bridge->lm_callback[monitor] = NULL;
1402
1403 /* If all location monitors disabled, disable global Location Monitor */
1404 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1405 CA91CX42_LINT_LM3)) == 0) {
1406 tmp = ioread32(bridge->base + LM_CTL);
1407 tmp &= ~CA91CX42_LM_CTL_EN;
1408 iowrite32(tmp, bridge->base + LM_CTL);
1409 }
1410
1411 mutex_unlock(&(lm->mtx));
1412
1413 return 0;
1414}
1415
29848ac9 1416int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
60479690 1417{
3d0f8bc7 1418 u32 slot = 0;
29848ac9
MW		 1419 struct ca91cx42_driver *bridge;
1420
1421 bridge = ca91cx42_bridge->driver_priv;
60479690 1422
12b2d5c0 1423 if (!geoid) {
29848ac9 1424 slot = ioread32(bridge->base + VCSR_BS);
12b2d5c0
MW		 1425 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1426 } else
1427 slot = geoid;
1428
3d0f8bc7
MW		 1429 return (int)slot;
1430
1431}
1432
1433static int __init ca91cx42_init(void)
1434{
1435 return pci_register_driver(&ca91cx42_driver);
1436}
1437
1438/*
1439 * Configure CR/CSR space
1440 *
1441 * Access to the CR/CSR can be configured at power-up. The location of the
1442 * CR/CSR registers in the CR/CSR address space is determined by the boards
1443 * Auto-ID or Geographic address. This function ensures that the window is
1444 * enabled at an offset consistent with the boards geopgraphic address.
1445 */
29848ac9
MW		 1446static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1447 struct pci_dev *pdev)
3d0f8bc7
MW		 1448{
1449 unsigned int crcsr_addr;
1450 int tmp, slot;
29848ac9
MW		 1451 struct ca91cx42_driver *bridge;
1452
1453 bridge = ca91cx42_bridge->driver_priv;
3d0f8bc7
MW		 1454
1455/* XXX We may need to set this somehow as the Universe II does not support
1456 * geographical addressing.
1457 */
1458#if 0
1459 if (vme_slotnum != -1)
29848ac9 1460 iowrite32(vme_slotnum << 27, bridge->base + VCSR_BS);
3d0f8bc7 1461#endif
29848ac9 1462 slot = ca91cx42_slot_get(ca91cx42_bridge);
3d0f8bc7
MW		 1463 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1464 if (slot == 0) {
1465 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1466 "CR/CSR space\n");
1467 return -EINVAL;
60479690 1468 }
3d0f8bc7
MW		 1469
1470 /* Allocate mem for CR/CSR image */
29848ac9
MW		 1471 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1472 &(bridge->crcsr_bus));
1473 if (bridge->crcsr_kernel == NULL) {
3d0f8bc7
MW		 1474 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1475 "image\n");
1476 return -ENOMEM;
60479690
MW		 1477 }
1478
29848ac9 1479 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
60479690 1480
3d0f8bc7 1481 crcsr_addr = slot * (512 * 1024);
29848ac9 1482 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
60479690 1483
29848ac9 1484 tmp = ioread32(bridge->base + VCSR_CTL);
3d0f8bc7 1485 tmp |= CA91CX42_VCSR_CTL_EN;
29848ac9 1486 iowrite32(tmp, bridge->base + VCSR_CTL);
60479690 1487
3d0f8bc7 1488 return 0;
60479690
MW		 1489}
1490
29848ac9
MW		 1491static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1492 struct pci_dev *pdev)
60479690 1493{
3d0f8bc7 1494 u32 tmp;
29848ac9
MW		 1495 struct ca91cx42_driver *bridge;
1496
1497 bridge = ca91cx42_bridge->driver_priv;
60479690 1498
3d0f8bc7 1499 /* Turn off CR/CSR space */
29848ac9 1500 tmp = ioread32(bridge->base + VCSR_CTL);
3d0f8bc7 1501 tmp &= ~CA91CX42_VCSR_CTL_EN;
29848ac9 1502 iowrite32(tmp, bridge->base + VCSR_CTL);
60479690 1503
3d0f8bc7 1504 /* Free image */
29848ac9 1505 iowrite32(0, bridge->base + VCSR_TO);
60479690 1506
29848ac9
MW		 1507 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1508 bridge->crcsr_bus);
3d0f8bc7 1509}
60479690 1510
3d0f8bc7
MW		 1511static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1512{
1513 int retval, i;
1514 u32 data;
1515 struct list_head *pos = NULL;
29848ac9
MW		 1516 struct vme_bridge *ca91cx42_bridge;
1517 struct ca91cx42_driver *ca91cx42_device;
3d0f8bc7
MW		 1518 struct vme_master_resource *master_image;
1519 struct vme_slave_resource *slave_image;
3d0f8bc7 1520 struct vme_dma_resource *dma_ctrlr;
3d0f8bc7
MW		 1521 struct vme_lm_resource *lm;
1522
1523 /* We want to support more than one of each bridge so we need to
1524 * dynamically allocate the bridge structure
1525 */
1526 ca91cx42_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1527
1528 if (ca91cx42_bridge == NULL) {
1529 dev_err(&pdev->dev, "Failed to allocate memory for device "
1530 "structure\n");
1531 retval = -ENOMEM;
1532 goto err_struct;
1533 }
1534
1535 memset(ca91cx42_bridge, 0, sizeof(struct vme_bridge));
1536
29848ac9
MW		 1537 ca91cx42_device = kmalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1538
1539 if (ca91cx42_device == NULL) {
1540 dev_err(&pdev->dev, "Failed to allocate memory for device "
1541 "structure\n");
1542 retval = -ENOMEM;
1543 goto err_driver;
1544 }
1545
1546 memset(ca91cx42_device, 0, sizeof(struct ca91cx42_driver));
1547
1548 ca91cx42_bridge->driver_priv = ca91cx42_device;
1549
3d0f8bc7
MW		 1550 /* Enable the device */
1551 retval = pci_enable_device(pdev);
1552 if (retval) {
1553 dev_err(&pdev->dev, "Unable to enable device\n");
1554 goto err_enable;
1555 }
1556
1557 /* Map Registers */
1558 retval = pci_request_regions(pdev, driver_name);
1559 if (retval) {
1560 dev_err(&pdev->dev, "Unable to reserve resources\n");
1561 goto err_resource;
1562 }
1563
1564 /* map registers in BAR 0 */
29848ac9 1565 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
3d0f8bc7 1566 4096);
29848ac9 1567 if (!ca91cx42_device->base) {
3d0f8bc7
MW		 1568 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1569 retval = -EIO;
1570 goto err_remap;
1571 }
1572
1573 /* Check to see if the mapping worked out */
29848ac9 1574 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
3d0f8bc7
MW		 1575 if (data != PCI_VENDOR_ID_TUNDRA) {
1576 dev_err(&pdev->dev, "PCI_ID check failed\n");
1577 retval = -EIO;
1578 goto err_test;
1579 }
1580
1581 /* Initialize wait queues & mutual exclusion flags */
29848ac9
MW		 1582 init_waitqueue_head(&(ca91cx42_device->dma_queue));
1583 init_waitqueue_head(&(ca91cx42_device->iack_queue));
1584 mutex_init(&(ca91cx42_device->vme_int));
1585 mutex_init(&(ca91cx42_device->vme_rmw));
3d0f8bc7
MW		 1586
1587 ca91cx42_bridge->parent = &(pdev->dev);
1588 strcpy(ca91cx42_bridge->name, driver_name);
1589
1590 /* Setup IRQ */
1591 retval = ca91cx42_irq_init(ca91cx42_bridge);
1592 if (retval != 0) {
1593 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1594 goto err_irq;
1595 }
1596
1597 /* Add master windows to list */
1598 INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources));
1599 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1600 master_image = kmalloc(sizeof(struct vme_master_resource),
1601 GFP_KERNEL);
1602 if (master_image == NULL) {
1603 dev_err(&pdev->dev, "Failed to allocate memory for "
1604 "master resource structure\n");
1605 retval = -ENOMEM;
1606 goto err_master;
1607 }
1608 master_image->parent = ca91cx42_bridge;
1609 spin_lock_init(&(master_image->lock));
1610 master_image->locked = 0;
1611 master_image->number = i;
1612 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1613 VME_CRCSR | VME_USER1 | VME_USER2;
1614 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1615 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1616 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
8fafb476 1617 memset(&(master_image->bus_resource), 0,
3d0f8bc7
MW		 1618 sizeof(struct resource));
1619 master_image->kern_base = NULL;
1620 list_add_tail(&(master_image->list),
1621 &(ca91cx42_bridge->master_resources));
1622 }
1623
1624 /* Add slave windows to list */
1625 INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources));
1626 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1627 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1628 GFP_KERNEL);
1629 if (slave_image == NULL) {
1630 dev_err(&pdev->dev, "Failed to allocate memory for "
1631 "slave resource structure\n");
1632 retval = -ENOMEM;
1633 goto err_slave;
1634 }
1635 slave_image->parent = ca91cx42_bridge;
1636 mutex_init(&(slave_image->mtx));
1637 slave_image->locked = 0;
1638 slave_image->number = i;
1639 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1640 VME_USER2;
1641
1642 /* Only windows 0 and 4 support A16 */
1643 if (i == 0 || i == 4)
1644 slave_image->address_attr |= VME_A16;
1645
1646 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1647 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1648 list_add_tail(&(slave_image->list),
1649 &(ca91cx42_bridge->slave_resources));
1650 }
4860ab74 1651
3d0f8bc7
MW		 1652 /* Add dma engines to list */
1653 INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources));
1654 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1655 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1656 GFP_KERNEL);
1657 if (dma_ctrlr == NULL) {
1658 dev_err(&pdev->dev, "Failed to allocate memory for "
1659 "dma resource structure\n");
1660 retval = -ENOMEM;
1661 goto err_dma;
1662 }
1663 dma_ctrlr->parent = ca91cx42_bridge;
1664 mutex_init(&(dma_ctrlr->mtx));
1665 dma_ctrlr->locked = 0;
1666 dma_ctrlr->number = i;
4f723df4
MW		 1667 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1668 VME_DMA_MEM_TO_VME;
3d0f8bc7
MW		 1669 INIT_LIST_HEAD(&(dma_ctrlr->pending));
1670 INIT_LIST_HEAD(&(dma_ctrlr->running));
1671 list_add_tail(&(dma_ctrlr->list),
1672 &(ca91cx42_bridge->dma_resources));
1673 }
4860ab74 1674
3d0f8bc7
MW		 1675 /* Add location monitor to list */
1676 INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources));
1677 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1678 if (lm == NULL) {
1679 dev_err(&pdev->dev, "Failed to allocate memory for "
1680 "location monitor resource structure\n");
1681 retval = -ENOMEM;
1682 goto err_lm;
1683 }
1684 lm->parent = ca91cx42_bridge;
1685 mutex_init(&(lm->mtx));
1686 lm->locked = 0;
1687 lm->number = 1;
1688 lm->monitors = 4;
1689 list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources));
1690
1691 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1692 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1693 ca91cx42_bridge->master_get = ca91cx42_master_get;
1694 ca91cx42_bridge->master_set = ca91cx42_master_set;
1695 ca91cx42_bridge->master_read = ca91cx42_master_read;
1696 ca91cx42_bridge->master_write = ca91cx42_master_write;
3d0f8bc7
MW		 1697 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1698 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1699 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1700 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
c813f592
MW		 1701 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1702 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
3d0f8bc7
MW		 1703 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1704 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1705 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1706 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
3d0f8bc7
MW		 1707 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1708
29848ac9 1709 data = ioread32(ca91cx42_device->base + MISC_CTL);
3d0f8bc7
MW		 1710 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1711 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
29848ac9
MW		 1712 dev_info(&pdev->dev, "Slot ID is %d\n",
1713 ca91cx42_slot_get(ca91cx42_bridge));
3d0f8bc7 1714
29848ac9 1715 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) {
3d0f8bc7
MW		 1716 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1717 retval = -EINVAL;
1718#if 0
1719 goto err_crcsr;
1720#endif
60479690 1721 }
60479690 1722
3d0f8bc7
MW		 1723 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1724 * ca91cx42_remove()
1725 */
1726 retval = vme_register_bridge(ca91cx42_bridge);
1727 if (retval != 0) {
1728 dev_err(&pdev->dev, "Chip Registration failed.\n");
1729 goto err_reg;
1730 }
1731
29848ac9
MW		 1732 pci_set_drvdata(pdev, ca91cx42_bridge);
1733
3d0f8bc7
MW		 1734 return 0;
1735
1736 vme_unregister_bridge(ca91cx42_bridge);
1737err_reg:
29848ac9 1738 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
70d7aa88 1739#if 0
3d0f8bc7 1740err_crcsr:
70d7aa88 1741#endif
3d0f8bc7
MW		 1742err_lm:
1743 /* resources are stored in link list */
1744 list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1745 lm = list_entry(pos, struct vme_lm_resource, list);
1746 list_del(pos);
1747 kfree(lm);
1748 }
3d0f8bc7
MW		 1749err_dma:
1750 /* resources are stored in link list */
1751 list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1752 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1753 list_del(pos);
1754 kfree(dma_ctrlr);
60479690 1755 }
3d0f8bc7
MW		 1756err_slave:
1757 /* resources are stored in link list */
1758 list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1759 slave_image = list_entry(pos, struct vme_slave_resource, list);
1760 list_del(pos);
1761 kfree(slave_image);
1762 }
1763err_master:
1764 /* resources are stored in link list */
1765 list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1766 master_image = list_entry(pos, struct vme_master_resource,
1767 list);
1768 list_del(pos);
1769 kfree(master_image);
1770 }
1771
29848ac9 1772 ca91cx42_irq_exit(ca91cx42_device, pdev);
3d0f8bc7
MW		 1773err_irq:
1774err_test:
29848ac9 1775 iounmap(ca91cx42_device->base);
3d0f8bc7
MW		 1776err_remap:
1777 pci_release_regions(pdev);
1778err_resource:
1779 pci_disable_device(pdev);
1780err_enable:
29848ac9
MW		 1781 kfree(ca91cx42_device);
1782err_driver:
3d0f8bc7
MW		 1783 kfree(ca91cx42_bridge);
1784err_struct:
1785 return retval;
60479690 1786
60479690
MW		 1787}
1788
3d0f8bc7 1789void ca91cx42_remove(struct pci_dev *pdev)
60479690 1790{
3d0f8bc7
MW		 1791 struct list_head *pos = NULL;
1792 struct vme_master_resource *master_image;
1793 struct vme_slave_resource *slave_image;
1794 struct vme_dma_resource *dma_ctrlr;
1795 struct vme_lm_resource *lm;
29848ac9
MW		 1796 struct ca91cx42_driver *bridge;
1797 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1798
1799 bridge = ca91cx42_bridge->driver_priv;
1800
60479690 1801
3d0f8bc7 1802 /* Turn off Ints */
29848ac9 1803 iowrite32(0, bridge->base + LINT_EN);
3d0f8bc7
MW		 1804
1805 /* Turn off the windows */
29848ac9
MW		 1806 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1807 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1808 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1809 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1810 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1811 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1812 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1813 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1814 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1815 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1816 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1817 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1818 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1819 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1820 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1821 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
3d0f8bc7
MW		 1822
1823 vme_unregister_bridge(ca91cx42_bridge);
1824#if 0
1825 ca91cx42_crcsr_exit(pdev);
1826#endif
1827 /* resources are stored in link list */
1828 list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1829 lm = list_entry(pos, struct vme_lm_resource, list);
1830 list_del(pos);
1831 kfree(lm);
60479690 1832 }
3d0f8bc7
MW		 1833
1834 /* resources are stored in link list */
1835 list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1836 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1837 list_del(pos);
1838 kfree(dma_ctrlr);
60479690
MW		 1839 }
1840
3d0f8bc7
MW		 1841 /* resources are stored in link list */
1842 list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1843 slave_image = list_entry(pos, struct vme_slave_resource, list);
1844 list_del(pos);
1845 kfree(slave_image);
1846 }
60479690 1847
3d0f8bc7
MW		 1848 /* resources are stored in link list */
1849 list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1850 master_image = list_entry(pos, struct vme_master_resource,
1851 list);
1852 list_del(pos);
1853 kfree(master_image);
1854 }
60479690 1855
29848ac9 1856 ca91cx42_irq_exit(bridge, pdev);
60479690 1857
29848ac9 1858 iounmap(bridge->base);
60479690 1859
3d0f8bc7 1860 pci_release_regions(pdev);
60479690 1861
3d0f8bc7
MW		 1862 pci_disable_device(pdev);
1863
1864 kfree(ca91cx42_bridge);
60479690
MW		 1865}
1866
3d0f8bc7 1867static void __exit ca91cx42_exit(void)
60479690 1868{
3d0f8bc7
MW		 1869 pci_unregister_driver(&ca91cx42_driver);
1870}
60479690 1871
12b2d5c0
MW		 1872MODULE_PARM_DESC(geoid, "Override geographical addressing");
1873module_param(geoid, int, 0);
1874
3d0f8bc7
MW		 1875MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1876MODULE_LICENSE("GPL");
60479690 1877
3d0f8bc7
MW		 1878module_init(ca91cx42_init);
1879module_exit(ca91cx42_exit);
60479690 1880
3d0f8bc7
MW		 1881/*----------------------------------------------------------------------------
1882 * STAGING
1883 *--------------------------------------------------------------------------*/
1884
1885#if 0
60479690 1886
3d0f8bc7
MW		 1887int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb)
1888{
1889 int temp_ctl = 0;
1890 int vbto = 0;
60479690 1891
29848ac9 1892 temp_ctl = ioread32(bridge->base + MISC_CTL);
3d0f8bc7 1893 temp_ctl &= 0x00FFFFFF;
60479690 1894
3d0f8bc7
MW		 1895 if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) {
1896 vbto = 7;
1897 } else if (vmeArb->globalTimeoutTimer > 1024) {
1898 return -EINVAL;
1899 } else if (vmeArb->globalTimeoutTimer == 0) {
1900 vbto = 0;
60479690 1901 } else {
3d0f8bc7
MW		 1902 vbto = 1;
1903 while ((16 * (1 << (vbto - 1))) < vmeArb->globalTimeoutTimer)
1904 vbto += 1;
60479690 1905 }
3d0f8bc7
MW		 1906 temp_ctl |= (vbto << 28);
1907
1908 if (vmeArb->arbiterMode == VME_PRIORITY_MODE)
1909 temp_ctl |= 1 << 26;
1910
1911 if (vmeArb->arbiterTimeoutFlag)
1912 temp_ctl |= 2 << 24;
1913
29848ac9 1914 iowrite32(temp_ctl, bridge->base + MISC_CTL);
3d0f8bc7
MW		 1915 return 0;
1916}
1917
1918int ca91cx42_get_arbiter(vmeArbiterCfg_t *vmeArb)
1919{
1920 int temp_ctl = 0;
1921 int vbto = 0;
1922
29848ac9 1923 temp_ctl = ioread32(bridge->base + MISC_CTL);
3d0f8bc7
MW		 1924
1925 vbto = (temp_ctl >> 28) & 0xF;
1926 if (vbto != 0)
1927 vmeArb->globalTimeoutTimer = (16 * (1 << (vbto - 1)));
1928
1929 if (temp_ctl & (1 << 26))
1930 vmeArb->arbiterMode = VME_PRIORITY_MODE;
1931 else
1932 vmeArb->arbiterMode = VME_R_ROBIN_MODE;
1933
1934 if (temp_ctl & (3 << 24))
1935 vmeArb->arbiterTimeoutFlag = 1;
1936
1937 return 0;
1938}
1939
1940int ca91cx42_set_requestor(vmeRequesterCfg_t *vmeReq)
1941{
1942 int temp_ctl = 0;
1943
29848ac9 1944 temp_ctl = ioread32(bridge->base + MAST_CTL);
3d0f8bc7
MW		 1945 temp_ctl &= 0xFF0FFFFF;
1946
1947 if (vmeReq->releaseMode == 1)
1948 temp_ctl |= (1 << 20);
1949
1950 if (vmeReq->fairMode == 1)
1951 temp_ctl |= (1 << 21);
1952
1953 temp_ctl |= (vmeReq->requestLevel << 22);
1954
29848ac9 1955 iowrite32(temp_ctl, bridge->base + MAST_CTL);
3d0f8bc7
MW		 1956 return 0;
1957}
1958
1959int ca91cx42_get_requestor(vmeRequesterCfg_t *vmeReq)
1960{
1961 int temp_ctl = 0;
1962
29848ac9 1963 temp_ctl = ioread32(bridge->base + MAST_CTL);
3d0f8bc7
MW		 1964
1965 if (temp_ctl & (1 << 20))
1966 vmeReq->releaseMode = 1;
1967
1968 if (temp_ctl & (1 << 21))
1969 vmeReq->fairMode = 1;
1970
1971 vmeReq->requestLevel = (temp_ctl & 0xC00000) >> 22;
1972
1973 return 0;
60479690 1974}
3d0f8bc7
MW		 1975
1976
1977#endif
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