[net-next-2.6.git] / drivers / staging / tm6000 / tm6000-core.c

/*
   tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices

   Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>

   Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
       - DVB-T support

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation version 2

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/usb.h>
#include <linux/i2c.h>
#include "tm6000.h"
#include "tm6000-regs.h"
#include <media/v4l2-common.h>
#include <media/tuner.h>

#define USB_TIMEOUT	5*HZ /* ms */

int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
			   u16 value, u16 index, u8 *buf, u16 len)
{
	int          ret, i;
	unsigned int pipe;
	static int   ini=0, last=0, n=0;
	u8	     *data=NULL;

	if (len)
		data = kzalloc(len, GFP_KERNEL);


	if (req_type & USB_DIR_IN)
		pipe=usb_rcvctrlpipe(dev->udev, 0);
	else {
		pipe=usb_sndctrlpipe(dev->udev, 0);
		memcpy(data, buf, len);
	}

	if (tm6000_debug & V4L2_DEBUG_I2C) {
		if (!ini)
			last=ini=jiffies;

		printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);

		printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
			(req_type & USB_DIR_IN)?" IN":"OUT",
			jiffies_to_msecs(jiffies-last),
			jiffies_to_msecs(jiffies-ini),
			req_type, req,value&0xff,value>>8, index&0xff, index>>8,
			len&0xff, len>>8);
		last=jiffies;
		n++;

		if ( !(req_type & USB_DIR_IN) ) {
			printk(">>> ");
			for (i=0;i<len;i++) {
				printk(" %02x",buf[i]);
			}
		printk("\n");
		}
	}

	ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
			      len, USB_TIMEOUT);

	if (req_type &  USB_DIR_IN)
		memcpy(buf, data, len);

	if (tm6000_debug & V4L2_DEBUG_I2C) {
		if (ret<0) {
			if (req_type &  USB_DIR_IN)
				printk("<<< (len=%d)\n",len);

			printk("%s: Error #%d\n", __FUNCTION__, ret);
		} else if (req_type &  USB_DIR_IN) {
			printk("<<< ");
			for (i=0;i<len;i++) {
				printk(" %02x",buf[i]);
			}
			printk("\n");
		}
	}

	kfree(data);

	msleep(5);

	return ret;
}

int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	return
		tm6000_read_write_usb (dev, USB_DIR_OUT | USB_TYPE_VENDOR,
				       req, value, index, NULL, 0);
}
EXPORT_SYMBOL_GPL(tm6000_set_reg);

int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	int rc;
	u8 buf[1];

	rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
				       value, index, buf, 1);

	if (rc<0)
		return rc;

	return *buf;
}
EXPORT_SYMBOL_GPL(tm6000_get_reg);

int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
{
	int rc;
	u8 buf[2];

	rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
				       value, index, buf, 2);

	if (rc<0)
		return rc;

	return buf[1]|buf[0]<<8;
}

void tm6000_set_fourcc_format(struct tm6000_core *dev)
{
	if (dev->dev_type == TM6010) {
		if (dev->fourcc == V4L2_PIX_FMT_UYVY)
			tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfc);
		else
			tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfd);
	} else {
		if (dev->fourcc == V4L2_PIX_FMT_UYVY)
			tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
		else
			tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
	}
}

int tm6000_init_analog_mode (struct tm6000_core *dev)
{
	if (dev->dev_type == TM6010) {
		int val;

		/* Enable video */
		val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
		val |= 0x60;
		tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
		tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xcf);

	} else {
		/* Enables soft reset */
		tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);

		if (dev->scaler) {
			tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
		} else {
			/* Enable Hfilter and disable TS Drop err */
			tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
		}

		tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
		tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
		tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
		tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
		tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
		tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);

		/* AP Software reset */
		tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
		tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);

		tm6000_set_fourcc_format(dev);

		/* Disables soft reset */
		tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);

		/* E3: Select input 0 - TV tuner */
		tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
		tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);

		/* This controls input */
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
		tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
	}
	msleep(20);

	/* Tuner firmware can now be loaded */

	/*FIXME: Hack!!! */
	struct v4l2_frequency f;
	mutex_lock(&dev->lock);
	f.frequency=dev->freq;
	v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
	mutex_unlock(&dev->lock);

	msleep(100);
	tm6000_set_standard (dev, &dev->norm);
	tm6000_set_audio_bitrate (dev,48000);

	return 0;
}

int tm6000_init_digital_mode (struct tm6000_core *dev)
{
	if (dev->dev_type == TM6010) {
		int val;
		u8 buf[2];

		/* digital init */
		val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
		val &= ~0x60;
		tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
		val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
		val |= 0x40;
		tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
		tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
		tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
		tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
		tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
		tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
		printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);


	} else  {
		tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
		tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
		tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
		tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
		tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
		tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
		tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
		tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
		tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
		tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
		tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
		tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
		tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);

		tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
		tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
		tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
		msleep(50);

		tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
		msleep(50);
		tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
		msleep(50);
		tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
		msleep(100);
	}
	return 0;
}

struct reg_init {
	u8 req;
	u8 reg;
	u8 val;
};

/* The meaning of those initializations are unknown */
struct reg_init tm6000_init_tab[] = {
	/* REG  VALUE */
	{ TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
	{ TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
	{ TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
	{ TM6010_REQ07_RD5_POWERSAVE, 0x4f },
	{ TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
	{ TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
	{ TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
	{ TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
	{ TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
	{ TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
	{ REQ_07_SET_GET_AVREG,  0xeb, 0x64 },		/* 48000 bits/sample, external input */
	{ REQ_07_SET_GET_AVREG,  0xee, 0xc2 },
	{ TM6010_REQ07_R3F_RESET, 0x01 },		/* Start of soft reset */
	{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
	{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
	{ TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
	{ TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
	{ TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
	{ TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
	{ TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
	{ TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
	{ TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
	{ TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
	{ TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
	{ TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
	{ TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
	{ TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
	{ TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
	{ TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
	{ TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
	{ TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
	{ TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
	{ TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
	{ TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
	{ TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
	{ TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
	{ TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
	{ TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
	{ TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
	{ TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
	{ TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
	{ TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
	{ TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
	{ TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
	{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
	{ TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
	{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
	{ TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
	{ TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
	{ TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
	{ TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
	{ TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
	{ TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
	{ TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
	{ TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
	{ TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
	{ TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
	{ TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
	{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
	{ TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
	{ TM6010_REQ07_RC3_HSTART1, 0x88 },
	{ TM6010_REQ07_R3F_RESET, 0x00 },		/* End of the soft reset */
	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
};

struct reg_init tm6010_init_tab[] = {
	{ TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
	{ TM6010_REQ07_RC4_HSTART0, 0xa0 },
	{ TM6010_REQ07_RC6_HEND0, 0x40 },
	{ TM6010_REQ07_RCA_VEND0, 0x31 },
	{ TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
	{ TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
	{ TM6010_REQ07_RFE_POWER_DOWN, 0x7f },

	{ TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
	{ TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
	{ TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
	{ TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
	{ TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
	{ TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
	{ TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
	{ TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
	{ TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },

	{ TM6010_REQ07_R3F_RESET, 0x01 },
	{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
	{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
	{ TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
	{ TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
	{ TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
	{ TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
	{ TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
	{ TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
	{ TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
	{ TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
	{ TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
	{ TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
	{ TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
	{ TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
	{ TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
	{ TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
	{ TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
	{ TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
	{ TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
	{ TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
	{ TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
	{ TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
	{ TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
	{ TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
	{ TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
	{ TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
	{ TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
	{ TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
	{ TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
	{ TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
	{ TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
	{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
	{ TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
	{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
	{ TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
	{ TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
	{ TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
	{ TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
	{ TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
	{ TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
	{ TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
	{ TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
	{ TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
	{ TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
	{ TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
	{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
	{ TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
	{ TM6010_REQ07_RC3_HSTART1, 0x88 },
	{ TM6010_REQ07_R3F_RESET, 0x00 },

	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },

	{ TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
	{ TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
	{ TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
	{ TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
	{ REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
	{ TM6010_REQ07_RD8_IR, 0x2f },

	/* set remote wakeup key:any key wakeup */
	{ TM6010_REQ07_RE5_REMOTE_WAKEUP,  0xfe },
	{ TM6010_REQ07_RD8_IR_WAKEUP_SEL,  0xff },
};

int tm6000_init (struct tm6000_core *dev)
{
	int board, rc=0, i, size;
	struct reg_init *tab;

	if (dev->dev_type == TM6010) {
		tab = tm6010_init_tab;
		size = ARRAY_SIZE(tm6010_init_tab);
	} else {
		tab = tm6000_init_tab;
		size = ARRAY_SIZE(tm6000_init_tab);
	}

	/* Load board's initialization table */
	for (i=0; i< size; i++) {
		rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
		if (rc<0) {
			printk (KERN_ERR "Error %i while setting req %d, "
					 "reg %d to value %d\n", rc,
					 tab[i].req,tab[i].reg, tab[i].val);
			return rc;
		}
	}

	msleep(5); /* Just to be conservative */

	/* Check board version - maybe 10Moons specific */
	board=tm6000_get_reg16 (dev, 0x40, 0, 0);
	if (board >=0) {
		printk (KERN_INFO "Board version = 0x%04x\n",board);
	} else {
		printk (KERN_ERR "Error %i while retrieving board version\n",board);
	}

	rc = tm6000_cards_setup(dev);

	return rc;
}

int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
{
	int val;

	val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
printk("Original value=%d\n",val);
	if (val<0)
		return val;

	val &= 0x0f;		/* Preserve the audio input control bits */
	switch (bitrate) {
	case 44100:
		val|=0xd0;
		dev->audio_bitrate=bitrate;
		break;
	case 48000:
		val|=0x60;
		dev->audio_bitrate=bitrate;
		break;
	}
	val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);

	return val;
}
EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
Commit	Line	Data
9701dc94	1	/*
e28f49b0	2	tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
9701dc94 MCC	3
	4	Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
	5
3169c9b2 ML	6	Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
	7	- DVB-T support
	8
9701dc94 MCC	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation version 2
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/kernel.h>
	25	#include <linux/usb.h>
	26	#include <linux/i2c.h>
9701dc94 MCC	27	#include "tm6000.h"
	28	#include "tm6000-regs.h"
	29	#include <media/v4l2-common.h>
	30	#include <media/tuner.h>
	31
9701dc94 MCC	32	#define USB_TIMEOUT 5HZ / ms */
	33
	34	int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
	35	u16 value, u16 index, u8 *buf, u16 len)
	36	{
	37	int ret, i;
	38	unsigned int pipe;
	39	static int ini=0, last=0, n=0;
	40	u8 *data=NULL;
	41
	42	if (len)
	43	data = kzalloc(len, GFP_KERNEL);
	44
	45
	46	if (req_type & USB_DIR_IN)
	47	pipe=usb_rcvctrlpipe(dev->udev, 0);
	48	else {
	49	pipe=usb_sndctrlpipe(dev->udev, 0);
	50	memcpy(data, buf, len);
	51	}
	52
edecce0a	53	if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94 MCC	54	if (!ini)
	55	last=ini=jiffies;
	56
	57	printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);
	58
	59	printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
	60	(req_type & USB_DIR_IN)?" IN":"OUT",
	61	jiffies_to_msecs(jiffies-last),
	62	jiffies_to_msecs(jiffies-ini),
	63	req_type, req,value&0xff,value>>8, index&0xff, index>>8,
	64	len&0xff, len>>8);
	65	last=jiffies;
	66	n++;
	67
	68	if ( !(req_type & USB_DIR_IN) ) {
	69	printk(">>> ");
	70	for (i=0;i<len;i++) {
	71	printk(" %02x",buf[i]);
	72	}
8ae1fc6e	73	printk("\n");
9701dc94 MCC	74	}
	75	}
	76
	77	ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
	78	len, USB_TIMEOUT);
	79
	80	if (req_type & USB_DIR_IN)
	81	memcpy(buf, data, len);
	82
edecce0a	83	if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94 MCC	84	if (ret<0) {
	85	if (req_type & USB_DIR_IN)
	86	printk("<<< (len=%d)\n",len);
	87
	88	printk("%s: Error #%d\n", __FUNCTION__, ret);
	89	} else if (req_type & USB_DIR_IN) {
	90	printk("<<< ");
	91	for (i=0;i<len;i++) {
	92	printk(" %02x",buf[i]);
	93	}
	94	printk("\n");
	95	}
	96	}
	97
	98	kfree(data);
	99
a5adfbed ML	100	msleep(5);
a5adfbed ML	101
9701dc94 MCC	102	return ret;
	103	}
	104
	105	int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	106	{
	107	return
	108	tm6000_read_write_usb (dev, USB_DIR_OUT \| USB_TYPE_VENDOR,
	109	req, value, index, NULL, 0);
	110	}
29ec15e9	111	EXPORT_SYMBOL_GPL(tm6000_set_reg);
9701dc94 MCC	112
	113	int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	114	{
	115	int rc;
	116	u8 buf[1];
	117
	118	rc=tm6000_read_write_usb (dev, USB_DIR_IN \| USB_TYPE_VENDOR, req,
	119	value, index, buf, 1);
	120
	121	if (rc<0)
	122	return rc;
	123
	124	return *buf;
	125	}
29ec15e9	126	EXPORT_SYMBOL_GPL(tm6000_get_reg);
9701dc94 MCC	127
	128	int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
	129	{
	130	int rc;
	131	u8 buf[2];
	132
	133	rc=tm6000_read_write_usb (dev, USB_DIR_IN \| USB_TYPE_VENDOR, req,
	134	value, index, buf, 2);
	135
	136	if (rc<0)
	137	return rc;
	138
	139	return buf[1]\|buf[0]<<8;
	140	}
	141
	142	void tm6000_set_fourcc_format(struct tm6000_core *dev)
	143	{
717ecd2b MCC	144	if (dev->dev_type == TM6010) {
717ecd2b MCC	145	if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493	146	tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfc);
717ecd2b	147	else
9afec493	148	tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfd);
9701dc94	149	} else {
717ecd2b	150	if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493	151	tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
717ecd2b	152	else
9afec493	153	tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
9701dc94 MCC	154	}
	155	}
	156
	157	int tm6000_init_analog_mode (struct tm6000_core *dev)
	158	{
29c389be MCC	159	if (dev->dev_type == TM6010) {
29c389be MCC	160	int val;
9701dc94	161
29c389be	162	/* Enable video */
9afec493	163	val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
29c389be	164	val \|= 0x60;
9afec493 MCC	165	tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
9afec493 MCC	166	tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xcf);
9701dc94	167
9701dc94	168	} else {
29c389be	169	/* Enables soft reset */
9afec493	170	tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
29c389be MCC	171
29c389be MCC	172	if (dev->scaler) {
9afec493	173	tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
29c389be MCC	174	} else {
29c389be MCC	175	/* Enable Hfilter and disable TS Drop err */
9afec493	176	tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
29c389be	177	}
9701dc94	178
9afec493 MCC	179	tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
	180	tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
	181	tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
	182	tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
	183	tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
	184	tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
9701dc94	185
29c389be	186	/* AP Software reset */
9afec493 MCC	187	tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
9afec493 MCC	188	tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
9701dc94	189
29c389be	190	tm6000_set_fourcc_format(dev);
9701dc94	191
29c389be	192	/* Disables soft reset */
9afec493	193	tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
9701dc94	194
29c389be	195	/* E3: Select input 0 - TV tuner */
9afec493	196	tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
29c389be	197	tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94	198
29c389be MCC	199	/* This controls input */
	200	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
	201	tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
	202	}
9701dc94 MCC	203	msleep(20);
9701dc94 MCC	204
29c389be MCC	205	/* Tuner firmware can now be loaded */
29c389be MCC	206
9701dc94 MCC	207	/FIXME: Hack!!! /
	208	struct v4l2_frequency f;
	209	mutex_lock(&dev->lock);
	210	f.frequency=dev->freq;
427f7fac	211	v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94 MCC	212	mutex_unlock(&dev->lock);
	213
	214	msleep(100);
	215	tm6000_set_standard (dev, &dev->norm);
	216	tm6000_set_audio_bitrate (dev,48000);
	217
9701dc94 MCC	218	return 0;
	219	}
	220
3169c9b2 ML	221	int tm6000_init_digital_mode (struct tm6000_core *dev)
3169c9b2 ML	222	{
c733a4d5 SR	223	if (dev->dev_type == TM6010) {
	224	int val;
	225	u8 buf[2];
3169c9b2	226
c733a4d5	227	/* digital init */
9afec493	228	val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
c733a4d5	229	val &= ~0x60;
9afec493 MCC	230	tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
9afec493 MCC	231	val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
c733a4d5	232	val \|= 0x40;
9afec493 MCC	233	tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
	234	tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
	235	tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
	236	tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
	237	tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
c733a4d5 SR	238	tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
	239	printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);
	240
	241
	242	} else {
9afec493 MCC	243	tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
	244	tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
	245	tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
	246	tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
	247	tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
	248	tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5	249	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
9afec493 MCC	250	tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
	251	tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
	252	tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
	253	tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
	254	tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
	255	tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
	256	tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
	257
	258	tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
	259	tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5 SR	260	tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
	261	msleep(50);
	262
	263	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
	264	msleep(50);
	265	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
	266	msleep(50);
	267	tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
	268	msleep(100);
	269	}
3169c9b2 ML	270	return 0;
3169c9b2 ML	271	}
9701dc94	272
29c389be MCC	273	struct reg_init {
	274	u8 req;
	275	u8 reg;
	276	u8 val;
	277	};
	278
9701dc94	279	/* The meaning of those initializations are unknown */
29c389be	280	struct reg_init tm6000_init_tab[] = {
9701dc94	281	/* REG VALUE */
9afec493 MCC	282	{ TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
	283	{ TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
	284	{ TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
	285	{ TM6010_REQ07_RD5_POWERSAVE, 0x4f },
	286	{ TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
	287	{ TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
	288	{ TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
	289	{ TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
	290	{ TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
	291	{ TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
29c389be MCC	292	{ REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
29c389be MCC	293	{ REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
9afec493 MCC	294	{ TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
	295	{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
	296	{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
	297	{ TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
	298	{ TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
	299	{ TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
	300	{ TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
	301	{ TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
	302	{ TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
	303	{ TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
	304	{ TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
	305	{ TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
	306	{ TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
	307	{ TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
	308	{ TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
	309	{ TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
	310	{ TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
	311	{ TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
	312	{ TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
	313	{ TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
	314	{ TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
	315	{ TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
	316	{ TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
	317	{ TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
	318	{ TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
	319	{ TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
	320	{ TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
	321	{ TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
	322	{ TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
	323	{ TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
	324	{ TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
	325	{ TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
	326	{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
	327	{ TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
	328	{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
	329	{ TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
	330	{ TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
	331	{ TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
	332	{ TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
	333	{ TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
	334	{ TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
	335	{ TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
	336	{ TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
	337	{ TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
	338	{ TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
	339	{ TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
	340	{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
	341	{ TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
	342	{ TM6010_REQ07_RC3_HSTART1, 0x88 },
	343	{ TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
29c389be MCC	344	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
	345	};
	346
	347	struct reg_init tm6010_init_tab[] = {
9afec493 MCC	348	{ TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
	349	{ TM6010_REQ07_RC4_HSTART0, 0xa0 },
	350	{ TM6010_REQ07_RC6_HEND0, 0x40 },
	351	{ TM6010_REQ07_RCA_VEND0, 0x31 },
	352	{ TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
	353	{ TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
	354	{ TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
	355
	356	{ TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
	357	{ TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
	358	{ TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
	359	{ TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
	360	{ TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
	361	{ TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
	362	{ TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
	363	{ TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
	364	{ TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
	365
	366	{ TM6010_REQ07_R3F_RESET, 0x01 },
	367	{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
	368	{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
	369	{ TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
	370	{ TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
	371	{ TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
	372	{ TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
	373	{ TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
	374	{ TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
	375	{ TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
	376	{ TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
	377	{ TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
	378	{ TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
	379	{ TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
	380	{ TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
	381	{ TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
	382	{ TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
	383	{ TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
	384	{ TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
	385	{ TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
	386	{ TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
	387	{ TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
	388	{ TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
	389	{ TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
	390	{ TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
	391	{ TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
	392	{ TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
	393	{ TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
	394	{ TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
	395	{ TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
	396	{ TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
	397	{ TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
	398	{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
	399	{ TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
	400	{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
	401	{ TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
	402	{ TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
	403	{ TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
	404	{ TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
	405	{ TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
	406	{ TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
	407	{ TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
	408	{ TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
	409	{ TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
	410	{ TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
	411	{ TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
412	{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
413	{ TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
414	{ TM6010_REQ07_RC3_HSTART1, 0x88 },
415	{ TM6010_REQ07_R3F_RESET, 0x00 },
29c389be MCC	416
	417	{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
	418
9afec493 MCC	419	{ TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
	420	{ TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
	421	{ TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
	422	{ TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
d46ca932	423	{ REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
9afec493	424	{ TM6010_REQ07_RD8_IR, 0x2f },
d46ca932	425
29c389be	426	/* set remote wakeup key:any key wakeup */
9afec493 MCC	427	{ TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
9afec493 MCC	428	{ TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
9701dc94 MCC	429	};
	430
	431	int tm6000_init (struct tm6000_core *dev)
	432	{
29c389be MCC	433	int board, rc=0, i, size;
	434	struct reg_init *tab;
	435
	436	if (dev->dev_type == TM6010) {
	437	tab = tm6010_init_tab;
	438	size = ARRAY_SIZE(tm6010_init_tab);
	439	} else {
	440	tab = tm6000_init_tab;
	441	size = ARRAY_SIZE(tm6000_init_tab);
	442	}
9701dc94	443
9701dc94	444	/* Load board's initialization table */
29c389be MCC	445	for (i=0; i< size; i++) {
29c389be MCC	446	rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
9701dc94	447	if (rc<0) {
29c389be MCC	448	printk (KERN_ERR "Error %i while setting req %d, "
	449	"reg %d to value %d\n", rc,
	450	tab[i].req,tab[i].reg, tab[i].val);
9701dc94 MCC	451	return rc;
	452	}
	453	}
	454
29c389be MCC	455	msleep(5); /* Just to be conservative */
29c389be MCC	456
9701dc94 MCC	457	/* Check board version - maybe 10Moons specific */
	458	board=tm6000_get_reg16 (dev, 0x40, 0, 0);
	459	if (board >=0) {
	460	printk (KERN_INFO "Board version = 0x%04x\n",board);
	461	} else {
	462	printk (KERN_ERR "Error %i while retrieving board version\n",board);
	463	}
	464
e3ee9e5e	465	rc = tm6000_cards_setup(dev);
a5adfbed	466
e3ee9e5e	467	return rc;
9701dc94 MCC	468	}
9701dc94 MCC	469
44351aa0	470	int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94 MCC	471	{
	472	int val;
	473
	474	val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
	475	printk("Original value=%d\n",val);
	476	if (val<0)
	477	return val;
	478
	479	val &= 0x0f; /* Preserve the audio input control bits */
	480	switch (bitrate) {
	481	case 44100:
	482	val\|=0xd0;
c13dd704	483	dev->audio_bitrate=bitrate;
9701dc94 MCC	484	break;
	485	case 48000:
	486	val\|=0x60;
c13dd704	487	dev->audio_bitrate=bitrate;
9701dc94 MCC	488	break;
	489	}
	490	val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);
	491
	492	return val;
	493	}
44351aa0	494	EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);