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Merge git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-for-linus
[net-next-2.6.git] / drivers / staging / tm6000 / tm6000-core.c
CommitLineData
9701dc94 1/*
e28f49b0 2 tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
9701dc94
MCC		 3
4 Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
5
3169c9b2
ML		 6 Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
7 - DVB-T support
8
9701dc94
MCC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation version 2
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/usb.h>
26#include <linux/i2c.h>
9701dc94
MCC		 27#include "tm6000.h"
28#include "tm6000-regs.h"
29#include <media/v4l2-common.h>
30#include <media/tuner.h>
31
9701dc94
MCC		 32#define USB_TIMEOUT 5*HZ /* ms */
33
34int tm6000_read_write_usb (struct tm6000_core *dev, u8 req_type, u8 req,
35 u16 value, u16 index, u8 *buf, u16 len)
36{
37 int ret, i;
38 unsigned int pipe;
39 static int ini=0, last=0, n=0;
40 u8 *data=NULL;
41
42 if (len)
43 data = kzalloc(len, GFP_KERNEL);
44
45
46 if (req_type & USB_DIR_IN)
47 pipe=usb_rcvctrlpipe(dev->udev, 0);
48 else {
49 pipe=usb_sndctrlpipe(dev->udev, 0);
50 memcpy(data, buf, len);
51 }
52
edecce0a 53 if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94
MCC		 54 if (!ini)
55 last=ini=jiffies;
56
57 printk("%06i (dev %p, pipe %08x): ", n, dev->udev, pipe);
58
59 printk( "%s: %06u ms %06u ms %02x %02x %02x %02x %02x %02x %02x %02x ",
60 (req_type & USB_DIR_IN)?" IN":"OUT",
61 jiffies_to_msecs(jiffies-last),
62 jiffies_to_msecs(jiffies-ini),
63 req_type, req,value&0xff,value>>8, index&0xff, index>>8,
64 len&0xff, len>>8);
65 last=jiffies;
66 n++;
67
68 if ( !(req_type & USB_DIR_IN) ) {
69 printk(">>> ");
70 for (i=0;i<len;i++) {
71 printk(" %02x",buf[i]);
72 }
8ae1fc6e 73 printk("\n");
9701dc94
MCC		 74 }
75 }
76
77 ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index, data,
78 len, USB_TIMEOUT);
79
80 if (req_type & USB_DIR_IN)
81 memcpy(buf, data, len);
82
edecce0a 83 if (tm6000_debug & V4L2_DEBUG_I2C) {
9701dc94
MCC		 84 if (ret<0) {
85 if (req_type & USB_DIR_IN)
86 printk("<<< (len=%d)\n",len);
87
88 printk("%s: Error #%d\n", __FUNCTION__, ret);
89 } else if (req_type & USB_DIR_IN) {
90 printk("<<< ");
91 for (i=0;i<len;i++) {
92 printk(" %02x",buf[i]);
93 }
94 printk("\n");
95 }
96 }
97
98 kfree(data);
99
a5adfbed
ML		 100 msleep(5);
101
9701dc94
MCC		 102 return ret;
103}
104
105int tm6000_set_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
106{
107 return
108 tm6000_read_write_usb (dev, USB_DIR_OUT | USB_TYPE_VENDOR,
109 req, value, index, NULL, 0);
110}
29ec15e9 111EXPORT_SYMBOL_GPL(tm6000_set_reg);
9701dc94
MCC		 112
113int tm6000_get_reg (struct tm6000_core *dev, u8 req, u16 value, u16 index)
114{
115 int rc;
116 u8 buf[1];
117
118 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
119 value, index, buf, 1);
120
121 if (rc<0)
122 return rc;
123
124 return *buf;
125}
29ec15e9 126EXPORT_SYMBOL_GPL(tm6000_get_reg);
9701dc94
MCC		 127
128int tm6000_get_reg16 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
129{
130 int rc;
131 u8 buf[2];
132
133 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
134 value, index, buf, 2);
135
136 if (rc<0)
137 return rc;
138
139 return buf[1]|buf[0]<<8;
140}
141
2f790884
SR		 142int tm6000_get_reg32 (struct tm6000_core *dev, u8 req, u16 value, u16 index)
143{
144 int rc;
145 u8 buf[4];
146
147 rc=tm6000_read_write_usb (dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
148 value, index, buf, 4);
149
150 if (rc<0)
151 return rc;
152
153 return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
154}
155
2a15ac7a
DB		 156int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
157{
158 int rc;
159
160 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
161 if (rc < 0)
162 return rc;
163
164 msleep(tsleep);
165
166 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
167 msleep(tsleep);
168
169 return rc;
170}
171
9701dc94
MCC		 172void tm6000_set_fourcc_format(struct tm6000_core *dev)
173{
717ecd2b 174 if (dev->dev_type == TM6010) {
42238713
MCC		 175 int val;
176
177 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0) & 0xfc;
717ecd2b 178 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
42238713 179 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
717ecd2b 180 else
42238713 181 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val | 1);
9701dc94 182 } else {
717ecd2b 183 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
9afec493 184 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
717ecd2b 185 else
9afec493 186 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
9701dc94
MCC		 187 }
188}
189
190int tm6000_init_analog_mode (struct tm6000_core *dev)
191{
29c389be
MCC		 192 if (dev->dev_type == TM6010) {
193 int val;
9701dc94 194
29c389be 195 /* Enable video */
9afec493 196 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
29c389be 197 val |= 0x60;
9afec493 198 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
120756e1
SR		 199 val = tm6000_get_reg(dev,
200 TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
201 val &= ~0x40;
202 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
203
204 /* Init teletext */
205 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
206 tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
207 tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
208 tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
209 tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
210 tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
211 tm6000_set_reg(dev,
212 TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
213 tm6000_set_reg(dev,
214 TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
215 tm6000_set_reg(dev,
216 TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
217 tm6000_set_reg(dev,
218 TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
219 tm6000_set_reg(dev,
220 TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
221 tm6000_set_reg(dev,
222 TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
223 tm6000_set_reg(dev,
224 TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
225 tm6000_set_reg(dev,
226 TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
227 tm6000_set_reg(dev,
228 TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
229 tm6000_set_reg(dev,
230 TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
231 tm6000_set_reg(dev,
232 TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
233 tm6000_set_reg(dev,
234 TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
235 tm6000_set_reg(dev,
236 TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
237 tm6000_set_reg(dev,
238 TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
239 tm6000_set_reg(dev,
240 TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
241 tm6000_set_reg(dev,
242 TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
243 tm6000_set_reg(dev,
244 TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
245 tm6000_set_reg(dev,
246 TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
247 tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
248 tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
249 tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
250 tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
251 tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
252 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
253
254
255 /* Init audio */
256 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
257 tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04);
258 tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
259 tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0);
260 tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x05);
261 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x06);
262 tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00);
263 tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00);
264 tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08);
265 tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91);
266 tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20);
267 tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12);
268 tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20);
269 tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0);
270 tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80);
271 tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0);
272 tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80);
273 tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12);
274 tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe);
275 tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20);
276 tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14);
277 tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe);
278 tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01);
279 tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0);
280 tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32);
281 tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64);
282 tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20);
283 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00);
284 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00);
285 tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
286 tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00);
287 tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00);
288 tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
289 tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
290 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
9701dc94 291
9701dc94 292 } else {
29c389be 293 /* Enables soft reset */
9afec493 294 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
29c389be
MCC		 295
296 if (dev->scaler) {
9afec493 297 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
29c389be
MCC		 298 } else {
299 /* Enable Hfilter and disable TS Drop err */
9afec493 300 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
29c389be 301 }
9701dc94 302
9afec493
MCC		 303 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
304 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
305 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
306 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
307 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
308 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
9701dc94 309
29c389be 310 /* AP Software reset */
9afec493
MCC		 311 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
312 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
9701dc94 313
29c389be 314 tm6000_set_fourcc_format(dev);
9701dc94 315
29c389be 316 /* Disables soft reset */
9afec493 317 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
9701dc94 318
29c389be 319 /* E3: Select input 0 - TV tuner */
9afec493 320 tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
29c389be 321 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
9701dc94 322
29c389be
MCC		 323 /* This controls input */
324 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
325 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
326 }
9701dc94
MCC		 327 msleep(20);
328
29c389be
MCC		 329 /* Tuner firmware can now be loaded */
330
9701dc94
MCC		 331 /*FIXME: Hack!!! */
332 struct v4l2_frequency f;
333 mutex_lock(&dev->lock);
334 f.frequency=dev->freq;
427f7fac 335 v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
9701dc94
MCC		 336 mutex_unlock(&dev->lock);
337
338 msleep(100);
339 tm6000_set_standard (dev, &dev->norm);
340 tm6000_set_audio_bitrate (dev,48000);
341
f36cc034
SR		 342 /* switch dvb led off */
343 if (dev->gpio.dvb_led) {
344 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
345 dev->gpio.dvb_led, 0x01);
346 }
347
9701dc94
MCC		 348 return 0;
349}
350
3169c9b2
ML		 351int tm6000_init_digital_mode (struct tm6000_core *dev)
352{
c733a4d5
SR		 353 if (dev->dev_type == TM6010) {
354 int val;
355 u8 buf[2];
3169c9b2 356
c733a4d5 357 /* digital init */
9afec493 358 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
c733a4d5 359 val &= ~0x60;
9afec493
MCC		 360 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
361 val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
c733a4d5 362 val |= 0x40;
9afec493
MCC		 363 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
364 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
365 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
366 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
367 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
c733a4d5
SR		 368 tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
369 printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);
370
371
372 } else {
9afec493
MCC		 373 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
374 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
375 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
376 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
377 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
378 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5 379 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
9afec493
MCC		 380 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
381 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
382 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
383 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
384 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
385 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
386 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
387
388 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
389 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
c733a4d5
SR		 390 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
391 msleep(50);
392
393 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
394 msleep(50);
395 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
396 msleep(50);
397 tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
398 msleep(100);
399 }
f36cc034
SR		 400
401 /* switch dvb led on */
402 if (dev->gpio.dvb_led) {
403 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
404 dev->gpio.dvb_led, 0x00);
405 }
406
3169c9b2
ML		 407 return 0;
408}
9701dc94 409
29c389be
MCC		 410struct reg_init {
411 u8 req;
412 u8 reg;
413 u8 val;
414};
415
9701dc94 416/* The meaning of those initializations are unknown */
29c389be 417struct reg_init tm6000_init_tab[] = {
9701dc94 418 /* REG VALUE */
9afec493
MCC		 419 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
420 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
421 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
422 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
423 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
424 { TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
425 { TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
426 { TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
427 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
428 { TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
29c389be
MCC		 429 { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
430 { REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
9afec493
MCC		 431 { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
432 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
433 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
434 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
435 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
436 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
437 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
438 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
439 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
440 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
441 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
442 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
443 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
444 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
445 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
446 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
447 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
448 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
449 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
450 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
451 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
452 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
453 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
454 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
455 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
456 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
457 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
458 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
459 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
460 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
461 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
462 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
463 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
464 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
465 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
466 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
467 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
468 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
469 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
470 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
471 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
472 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
473 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
474 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
475 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
476 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
477 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
478 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
479 { TM6010_REQ07_RC3_HSTART1, 0x88 },
480 { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
2415a2c1 481 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be
MCC		 482};
483
484struct reg_init tm6010_init_tab[] = {
9afec493
MCC		 485 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
486 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
487 { TM6010_REQ07_RC6_HEND0, 0x40 },
488 { TM6010_REQ07_RCA_VEND0, 0x31 },
489 { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
490 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
491 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
492
493 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
494 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
495 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
496 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
497 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
498 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
499 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
500 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
501 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
502
503 { TM6010_REQ07_R3F_RESET, 0x01 },
504 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
505 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
506 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
507 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
508 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
509 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
510 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
511 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
512 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
513 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
514 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
515 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
516 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
517 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
518 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
519 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
520 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
521 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
522 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
523 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
524 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
525 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
526 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
527 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
528 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
529 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
530 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
531 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
532 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
533 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
534 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
535 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
536 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
537 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
538 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
539 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
540 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
541 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
542 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
543 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
544 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
545 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
546 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
547 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
548 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
549 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
550 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
551 { TM6010_REQ07_RC3_HSTART1, 0x88 },
552 { TM6010_REQ07_R3F_RESET, 0x00 },
29c389be 553
2415a2c1 554 { TM6010_REQ05_R18_IMASK7, 0x00 },
29c389be 555
9afec493
MCC		 556 { TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
557 { TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
558 { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
559 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
d46ca932 560 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
9afec493 561 { TM6010_REQ07_RD8_IR, 0x2f },
d46ca932 562
29c389be 563 /* set remote wakeup key:any key wakeup */
9afec493
MCC		 564 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
565 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
9701dc94
MCC		 566};
567
568int tm6000_init (struct tm6000_core *dev)
569{
29c389be
MCC		 570 int board, rc=0, i, size;
571 struct reg_init *tab;
572
573 if (dev->dev_type == TM6010) {
574 tab = tm6010_init_tab;
575 size = ARRAY_SIZE(tm6010_init_tab);
576 } else {
577 tab = tm6000_init_tab;
578 size = ARRAY_SIZE(tm6000_init_tab);
579 }
9701dc94 580
9701dc94 581 /* Load board's initialization table */
29c389be
MCC		 582 for (i=0; i< size; i++) {
583 rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
9701dc94 584 if (rc<0) {
29c389be
MCC		 585 printk (KERN_ERR "Error %i while setting req %d, "
586 "reg %d to value %d\n", rc,
587 tab[i].req,tab[i].reg, tab[i].val);
9701dc94
MCC		 588 return rc;
589 }
590 }
591
29c389be
MCC		 592 msleep(5); /* Just to be conservative */
593
9701dc94 594 /* Check board version - maybe 10Moons specific */
2f790884 595 board=tm6000_get_reg32 (dev, REQ_40_GET_VERSION, 0, 0);
9701dc94 596 if (board >=0) {
2f790884 597 printk (KERN_INFO "Board version = 0x%08x\n",board);
9701dc94
MCC		 598 } else {
599 printk (KERN_ERR "Error %i while retrieving board version\n",board);
600 }
601
e3ee9e5e 602 rc = tm6000_cards_setup(dev);
a5adfbed 603
e3ee9e5e 604 return rc;
9701dc94
MCC		 605}
606
44351aa0 607int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
9701dc94
MCC		 608{
609 int val;
610
611 val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x0);
612printk("Original value=%d\n",val);
613 if (val<0)
614 return val;
615
616 val &= 0x0f; /* Preserve the audio input control bits */
617 switch (bitrate) {
618 case 44100:
619 val|=0xd0;
c13dd704 620 dev->audio_bitrate=bitrate;
9701dc94
MCC		 621 break;
622 case 48000:
623 val|=0x60;
c13dd704 624 dev->audio_bitrate=bitrate;
9701dc94
MCC		 625 break;
626 }
627 val=tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, val);
628
629 return val;
630}
44351aa0 631EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
0439db75
SR		 632
633static LIST_HEAD(tm6000_devlist);
634static DEFINE_MUTEX(tm6000_devlist_mutex);
635
636/*
637 * tm6000_realease_resource()
638 */
639
640void tm6000_remove_from_devlist(struct tm6000_core *dev)
641{
642 mutex_lock(&tm6000_devlist_mutex);
643 list_del(&dev->devlist);
644 mutex_unlock(&tm6000_devlist_mutex);
645};
646
647void tm6000_add_into_devlist(struct tm6000_core *dev)
648{
649 mutex_lock(&tm6000_devlist_mutex);
650 list_add_tail(&dev->devlist, &tm6000_devlist);
651 mutex_unlock(&tm6000_devlist_mutex);
652};
653
654/*
655 * Extension interface
656 */
657
658static LIST_HEAD(tm6000_extension_devlist);
659static DEFINE_MUTEX(tm6000_extension_devlist_lock);
660
661int tm6000_register_extension(struct tm6000_ops *ops)
662{
663 struct tm6000_core *dev = NULL;
664
665 mutex_lock(&tm6000_devlist_mutex);
666 mutex_lock(&tm6000_extension_devlist_lock);
667 list_add_tail(&ops->next, &tm6000_extension_devlist);
668 list_for_each_entry(dev, &tm6000_devlist, devlist) {
669 if (dev)
670 ops->init(dev);
671 }
672 printk(KERN_INFO "tm6000: Initialized (%s) extension\n", ops->name);
673 mutex_unlock(&tm6000_extension_devlist_lock);
674 mutex_unlock(&tm6000_devlist_mutex);
675 return 0;
676}
677EXPORT_SYMBOL(tm6000_register_extension);
678
679void tm6000_unregister_extension(struct tm6000_ops *ops)
680{
681 struct tm6000_core *dev = NULL;
682
683 mutex_lock(&tm6000_devlist_mutex);
684 list_for_each_entry(dev, &tm6000_devlist, devlist) {
685 if (dev)
686 ops->fini(dev);
687 }
688
689 mutex_lock(&tm6000_extension_devlist_lock);
690 printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
691 list_del(&ops->next);
692 mutex_unlock(&tm6000_extension_devlist_lock);
693 mutex_unlock(&tm6000_devlist_mutex);
694}
695EXPORT_SYMBOL(tm6000_unregister_extension);
696
697void tm6000_init_extension(struct tm6000_core *dev)
698{
699 struct tm6000_ops *ops = NULL;
700
701 mutex_lock(&tm6000_extension_devlist_lock);
702 if (!list_empty(&tm6000_extension_devlist)) {
703 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
704 if (ops->init)
705 ops->init(dev);
706 }
707 }
708 mutex_unlock(&tm6000_extension_devlist_lock);
709}
710
711void tm6000_close_extension(struct tm6000_core *dev)
712{
713 struct tm6000_ops *ops = NULL;
714
715 mutex_lock(&tm6000_extension_devlist_lock);
716 if (!list_empty(&tm6000_extension_devlist)) {
717 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
718 if (ops->fini)
719 ops->fini(dev);
720 }
721 }
722 mutex_unlock(&tm6000_extension_devlist_lock);
723}
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