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[net-next-2.6.git] / drivers / staging / sep / sep_dev.h
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1#ifndef __SEP_DEV_H__
2#define __SEP_DEV_H__
3
4/*
5 *
6 * sep_dev.h - Security Processor Device Structures
7 *
8 * Copyright(c) 2009 Intel Corporation. All rights reserved.
9 * Copyright(c) 2009 Discretix. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Alan Cox alan@linux.intel.com
28 *
29 */
30
31struct sep_device {
32 /* pointer to pci dev */
904290c0 33 struct pci_dev *pdev;
f5e3980f 34
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35 unsigned long in_use;
36
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37 /* address of the shared memory allocated during init for SEP driver
38 (coherent alloc) */
39 void *shared_addr;
40 /* the physical address of the shared area */
41 dma_addr_t shared_bus;
f5e3980f 42
70ae04e6 43 /* restricted access region (coherent alloc) */
790cf1b9 44 dma_addr_t rar_bus;
904290c0 45 void *rar_addr;
70ae04e6 46 /* firmware regions: cache is at rar_addr */
f5e3980f 47 unsigned long cache_size;
f5e3980f 48
70ae04e6 49 /* follows the cache */
790cf1b9 50 dma_addr_t resident_bus;
f5e3980f 51 unsigned long resident_size;
904290c0 52 void *resident_addr;
f5e3980f 53
f5e3980f 54 /* start address of the access to the SEP registers from driver */
904290c0 55 void __iomem *reg_addr;
f5e3980f 56 /* transaction counter that coordinates the transactions between SEP and HOST */
904290c0 57 unsigned long send_ct;
f5e3980f 58 /* counter for the messages from sep */
904290c0 59 unsigned long reply_ct;
f5e3980f 60 /* counter for the number of bytes allocated in the pool for the current
d19cf32f 61 transaction */
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62 unsigned long data_pool_bytes_allocated;
63
64 /* array of pointers to the pages that represent input data for the synchronic
d19cf32f 65 DMA action */
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66 struct page **in_page_array;
67
68 /* array of pointers to the pages that represent out data for the synchronic
d19cf32f 69 DMA action */
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70 struct page **out_page_array;
71
72 /* number of pages in the sep_in_page_array */
73 unsigned long in_num_pages;
74
75 /* number of pages in the sep_out_page_array */
76 unsigned long out_num_pages;
77
78 /* global data for every flow */
904290c0 79 struct sep_flow_context_t flows[SEP_DRIVER_NUM_FLOWS];
f5e3980f 80
f5e3980f 81 /* pointer to the workqueue that handles the flow done interrupts */
904290c0 82 struct workqueue_struct *flow_wq;
f5e3980f 83
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84};
85
b10b483e 86static struct sep_device *sep_dev;
f5e3980f 87
79de99e8 88static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
f5e3980f 89{
904290c0 90 void __iomem *addr = dev->reg_addr + reg;
79de99e8 91 writel(value, addr);
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92}
93
79de99e8 94static inline u32 sep_read_reg(struct sep_device *dev, int reg)
f5e3980f 95{
904290c0 96 void __iomem *addr = dev->reg_addr + reg;
79de99e8 97 return readl(addr);
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98}
99
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100/* wait for SRAM write complete(indirect write */
101static inline void sep_wait_sram_write(struct sep_device *dev)
102{
103 u32 reg_val;
104 do
105 reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
d19cf32f 106 while (!(reg_val & 1));
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107}
108
109
f5e3980f 110#endif