git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 5f53d8ca JC |
1 | /* |
| 2 | This is part of rtl8187 OpenSource driver. | |
| 3 | Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> | |
| 4 | Released under the terms of GPL (General Public Licence) | |
| 5 | ||
| 6 | Parts of this driver are based on the GPL part of the | |
| 7 | official realtek driver | |
| 8 | ||
| 9 | Parts of this driver are based on the rtl8192 driver skeleton | |
| 10 | from Patric Schenke & Andres Salomon | |
| 11 | ||
| 12 | Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver | |
| 13 | ||
| 14 | We want to tanks the Authors of those projects and the Ndiswrapper | |
| 15 | project Authors. | |
| 16 | */ | |
| 17 | ||
| 18 | #ifndef R819xU_H | |
| 19 | #define R819xU_H | |
| 20 | ||
| 21 | #include <linux/module.h> | |
| 22 | #include <linux/kernel.h> | |
| 23 | //#include <linux/config.h> | |
| 24 | #include <linux/init.h> | |
| 25 | #include <linux/ioport.h> | |
| 26 | #include <linux/sched.h> | |
| 27 | #include <linux/types.h> | |
| 28 | #include <linux/slab.h> | |
| 29 | #include <linux/netdevice.h> | |
| 30 | //#include <linux/pci.h> | |
| 31 | #include <linux/usb.h> | |
| 32 | #include <linux/etherdevice.h> | |
| 33 | #include <linux/delay.h> | |
| 34 | #include <linux/rtnetlink.h> //for rtnl_lock() | |
| 35 | #include <linux/wireless.h> | |
| 36 | #include <linux/timer.h> | |
| 37 | #include <linux/proc_fs.h> // Necessary because we use the proc fs | |
| 38 | #include <linux/if_arp.h> | |
| 39 | #include <linux/random.h> | |
| 40 | #include <linux/version.h> | |
| 41 | #include <asm/io.h> | |
| 1ec9e48d | 42 | |
| 2a7d71ad | 43 | #include "ieee80211/ieee80211.h" |
| 5f53d8ca | 44 | |
| 5f53d8ca | 45 | #include "r8192S_firmware.h" |
| 5f53d8ca | 46 | |
| e3133b28 FS |
47 | /* EEPROM defs for use with linux/eeprom_93cx6.h */ |
| 48 | #define RTL819X_EEPROM_CMD_READ (1 << 0) | |
| 49 | #define RTL819X_EEPROM_CMD_WRITE (1 << 1) | |
| 50 | #define RTL819X_EEPROM_CMD_CK (1 << 2) | |
| 51 | #define RTL819X_EEPROM_CMD_CS (1 << 3) | |
| 52 | ||
| 5f53d8ca JC |
53 | //#define RTL8192U |
| 54 | #define RTL819xU_MODULE_NAME "rtl819xU" | |
| 55 | //added for HW security, john.0629 | |
| 56 | #define FALSE 0 | |
| 57 | #define TRUE 1 | |
| 58 | #define MAX_KEY_LEN 61 | |
| 59 | #define KEY_BUF_SIZE 5 | |
| 60 | ||
| 61 | #define BIT0 0x00000001 | |
| 62 | #define BIT1 0x00000002 | |
| 63 | #define BIT2 0x00000004 | |
| 64 | #define BIT3 0x00000008 | |
| 65 | #define BIT4 0x00000010 | |
| 66 | #define BIT5 0x00000020 | |
| 67 | #define BIT6 0x00000040 | |
| 68 | #define BIT7 0x00000080 | |
| 69 | #define BIT8 0x00000100 | |
| 70 | #define BIT9 0x00000200 | |
| 71 | #define BIT10 0x00000400 | |
| 72 | #define BIT11 0x00000800 | |
| 73 | #define BIT12 0x00001000 | |
| 74 | #define BIT13 0x00002000 | |
| 75 | #define BIT14 0x00004000 | |
| 76 | #define BIT15 0x00008000 | |
| 77 | #define BIT16 0x00010000 | |
| 78 | #define BIT17 0x00020000 | |
| 79 | #define BIT18 0x00040000 | |
| 80 | #define BIT19 0x00080000 | |
| 81 | #define BIT20 0x00100000 | |
| 82 | #define BIT21 0x00200000 | |
| 83 | #define BIT22 0x00400000 | |
| 84 | #define BIT23 0x00800000 | |
| 85 | #define BIT24 0x01000000 | |
| 86 | #define BIT25 0x02000000 | |
| 87 | #define BIT26 0x04000000 | |
| 88 | #define BIT27 0x08000000 | |
| 89 | #define BIT28 0x10000000 | |
| 90 | #define BIT29 0x20000000 | |
| 91 | #define BIT30 0x40000000 | |
| 92 | #define BIT31 0x80000000 | |
| 93 | ||
| 94 | // Rx smooth factor | |
| 95 | #define Rx_Smooth_Factor 20 | |
| 5f53d8ca JC |
96 | #define DMESG(x,a...) |
| 97 | #define DMESGW(x,a...) | |
| 98 | #define DMESGE(x,a...) | |
| 99 | extern u32 rt_global_debug_component; | |
| 100 | #define RT_TRACE(component, x, args...) \ | |
| 101 | do { if(rt_global_debug_component & component) \ | |
| 102 | printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \ | |
| 103 | ##args);\ | |
| 104 | }while(0); | |
| 105 | //---------------------------------------------------------------------- | |
| 106 | //// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15. | |
| 107 | ////---------------------------------------------------------------------- | |
| 108 | #define RX_DESC_SIZE 24 | |
| 109 | #define RX_DRV_INFO_SIZE_UNIT 8 | |
| 110 | ||
| 111 | #define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\ | |
| 112 | (_ieee->pairwise_key_type==KEY_TYPE_CCMP)) | |
| 113 | ||
| 114 | #define COMP_TRACE BIT0 // For function call tracing. | |
| 115 | #define COMP_DBG BIT1 // Only for temporary debug message. | |
| 116 | #define COMP_INIT BIT2 // during driver initialization / halt / reset. | |
| 117 | ||
| 118 | ||
| 119 | #define COMP_RECV BIT3 // Reveive part data path. | |
| 120 | #define COMP_SEND BIT4 // Send part path. | |
| 121 | #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02. | |
| 122 | #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related. | |
| 123 | #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS. | |
| 124 | #define COMP_SWBW BIT8 // For bandwidth switch. | |
| 125 | #define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING | |
| 126 | #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21. | |
| 127 | #define COMP_QOS BIT11 // For QoS. | |
| 128 | #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. | |
| 129 | #define COMP_LPS BIT13 // For Radio Measurement. | |
| 130 | #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko. | |
| 131 | #define COMP_PHY BIT15 | |
| 132 | #define COMP_CH BIT16 //channel setting debug | |
| 133 | #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko. | |
| 134 | #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko. | |
| 135 | #define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko. | |
| 136 | #define COMP_SEC BIT20 // Event handling | |
| 137 | #define COMP_LED BIT21 // For LED. | |
| 138 | #define COMP_RF BIT22 // For RF. | |
| 139 | //1!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
| 140 | #define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. | |
| 141 | //1//1Attention Please!!!<11n or 8190 specific code should be put below this line> | |
| 142 | //1!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
| 143 | ||
| 144 | #define COMP_FIRMWARE BIT24 //for firmware downloading | |
| 145 | #define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11 | |
| 146 | #define COMP_AMSDU BIT26 // For A-MSDU Debugging | |
| 147 | ||
| 148 | #define COMP_SCAN BIT27 | |
| 149 | #define COMP_CMD BIT28 | |
| 150 | #define COMP_DOWN BIT29 //for rm driver module | |
| 151 | #define COMP_RESET BIT30 //for silent reset | |
| 152 | #define COMP_ERR BIT31 //for error out, always on | |
| 5f53d8ca JC |
153 | |
| 154 | #define RTL819x_DEBUG | |
| 155 | #ifdef RTL819x_DEBUG | |
| 156 | #define assert(expr) \ | |
| 157 | if (!(expr)) { \ | |
| 158 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
| 159 | #expr,__FILE__,__FUNCTION__,__LINE__); \ | |
| 160 | } | |
| 161 | //wb added to debug out data buf | |
| 162 | //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA | |
| 163 | #define RT_DEBUG_DATA(level, data, datalen) \ | |
| 164 | do{ if ((rt_global_debug_component & (level)) == (level)) \ | |
| 165 | { \ | |
| 166 | int i; \ | |
| 167 | u8* pdata = (u8*) data; \ | |
| 168 | printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \ | |
| 169 | for(i=0; i<(int)(datalen); i++) \ | |
| 170 | { \ | |
| 171 | printk("%2x ", pdata[i]); \ | |
| 172 | if ((i+1)%16 == 0) printk("\n"); \ | |
| 173 | } \ | |
| 174 | printk("\n"); \ | |
| 175 | } \ | |
| 176 | } while (0) | |
| 177 | #else | |
| 178 | #define assert(expr) do {} while (0) | |
| 179 | #define RT_DEBUG_DATA(level, data, datalen) do {} while(0) | |
| 180 | #endif /* RTL8169_DEBUG */ | |
| 181 | ||
| 182 | //#ifdef RTL8192SU | |
| 183 | //2TODO: We should define 8192S firmware related macro settings here!! | |
| 184 | #define RTL819X_DEFAULT_RF_TYPE RF_1T2R | |
| 185 | #define RTL819X_TOTAL_RF_PATH 2 | |
| 186 | ||
| 187 | //#define Rtl819XFwBootArray Rtl8192UsbFwBootArray | |
| 188 | //#define Rtl819XFwMainArray Rtl8192UsbFwMainArray | |
| 189 | //#define Rtl819XFwDataArray Rtl8192UsbFwDataArray | |
| 190 | ||
| 191 | #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG | |
| 192 | #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array | |
| 193 | #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray | |
| 194 | #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray | |
| 195 | //#define Rtl819XRadioA_Array Rtl8192UsbRadioA_Array | |
| 196 | //#define Rtl819XRadioB_Array Rtl8192UsbRadioB_Array | |
| 197 | #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array | |
| 198 | #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array | |
| 199 | ||
| 200 | //2008.11.06 Add. | |
| 201 | #define Rtl819XFwImageArray Rtl8192SUFwImgArray | |
| 202 | #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array | |
| 203 | #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array | |
| 204 | #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray | |
| 205 | #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray | |
| 206 | #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray | |
| 207 | #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray | |
| 208 | #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG | |
| 209 | #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array | |
| 210 | #define Rtl819XRadioB_Array Rtl8192SURadioB_Array | |
| 211 | #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array | |
| 212 | #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array | |
| 213 | #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array | |
| 214 | //#endif | |
| 215 | ||
| 216 | // | |
| 217 | // Queue Select Value in TxDesc | |
| 218 | // | |
| 219 | #define QSLT_BK 0x1 | |
| 220 | #define QSLT_BE 0x0 | |
| 221 | #define QSLT_VI 0x4 | |
| 222 | #define QSLT_VO 0x6 | |
| 223 | #define QSLT_BEACON 0x10 | |
| 224 | #define QSLT_HIGH 0x11 | |
| 225 | #define QSLT_MGNT 0x12 | |
| 226 | #define QSLT_CMD 0x13 | |
| 227 | ||
| 228 | #define DESC90_RATE1M 0x00 | |
| 229 | #define DESC90_RATE2M 0x01 | |
| 230 | #define DESC90_RATE5_5M 0x02 | |
| 231 | #define DESC90_RATE11M 0x03 | |
| 232 | #define DESC90_RATE6M 0x04 | |
| 233 | #define DESC90_RATE9M 0x05 | |
| 234 | #define DESC90_RATE12M 0x06 | |
| 235 | #define DESC90_RATE18M 0x07 | |
| 236 | #define DESC90_RATE24M 0x08 | |
| 237 | #define DESC90_RATE36M 0x09 | |
| 238 | #define DESC90_RATE48M 0x0a | |
| 239 | #define DESC90_RATE54M 0x0b | |
| 240 | #define DESC90_RATEMCS0 0x00 | |
| 241 | #define DESC90_RATEMCS1 0x01 | |
| 242 | #define DESC90_RATEMCS2 0x02 | |
| 243 | #define DESC90_RATEMCS3 0x03 | |
| 244 | #define DESC90_RATEMCS4 0x04 | |
| 245 | #define DESC90_RATEMCS5 0x05 | |
| 246 | #define DESC90_RATEMCS6 0x06 | |
| 247 | #define DESC90_RATEMCS7 0x07 | |
| 248 | #define DESC90_RATEMCS8 0x08 | |
| 249 | #define DESC90_RATEMCS9 0x09 | |
| 250 | #define DESC90_RATEMCS10 0x0a | |
| 251 | #define DESC90_RATEMCS11 0x0b | |
| 252 | #define DESC90_RATEMCS12 0x0c | |
| 253 | #define DESC90_RATEMCS13 0x0d | |
| 254 | #define DESC90_RATEMCS14 0x0e | |
| 255 | #define DESC90_RATEMCS15 0x0f | |
| 256 | #define DESC90_RATEMCS32 0x20 | |
| 257 | ||
| 258 | //#ifdef RTL8192SU | |
| 259 | // CCK Rates, TxHT = 0 | |
| 260 | #define DESC92S_RATE1M 0x00 | |
| 261 | #define DESC92S_RATE2M 0x01 | |
| 262 | #define DESC92S_RATE5_5M 0x02 | |
| 263 | #define DESC92S_RATE11M 0x03 | |
| 264 | ||
| 265 | // OFDM Rates, TxHT = 0 | |
| 266 | #define DESC92S_RATE6M 0x04 | |
| 267 | #define DESC92S_RATE9M 0x05 | |
| 268 | #define DESC92S_RATE12M 0x06 | |
| 269 | #define DESC92S_RATE18M 0x07 | |
| 270 | #define DESC92S_RATE24M 0x08 | |
| 271 | #define DESC92S_RATE36M 0x09 | |
| 272 | #define DESC92S_RATE48M 0x0a | |
| 273 | #define DESC92S_RATE54M 0x0b | |
| 274 | ||
| 275 | // MCS Rates, TxHT = 1 | |
| 276 | #define DESC92S_RATEMCS0 0x0c | |
| 277 | #define DESC92S_RATEMCS1 0x0d | |
| 278 | #define DESC92S_RATEMCS2 0x0e | |
| 279 | #define DESC92S_RATEMCS3 0x0f | |
| 280 | #define DESC92S_RATEMCS4 0x10 | |
| 281 | #define DESC92S_RATEMCS5 0x11 | |
| 282 | #define DESC92S_RATEMCS6 0x12 | |
| 283 | #define DESC92S_RATEMCS7 0x13 | |
| 284 | #define DESC92S_RATEMCS8 0x14 | |
| 285 | #define DESC92S_RATEMCS9 0x15 | |
| 286 | #define DESC92S_RATEMCS10 0x16 | |
| 287 | #define DESC92S_RATEMCS11 0x17 | |
| 288 | #define DESC92S_RATEMCS12 0x18 | |
| 289 | #define DESC92S_RATEMCS13 0x19 | |
| 290 | #define DESC92S_RATEMCS14 0x1a | |
| 291 | #define DESC92S_RATEMCS15 0x1b | |
| 292 | #define DESC92S_RATEMCS15_SG 0x1c | |
| 293 | #define DESC92S_RATEMCS32 0x20 | |
| 294 | //#endif | |
| 295 | ||
| 296 | #define RTL819X_DEFAULT_RF_TYPE RF_1T2R | |
| 297 | ||
| 298 | #define IEEE80211_WATCH_DOG_TIME 2000 | |
| 299 | #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 | |
| 300 | //for txpowertracking by amy | |
| 301 | #define OFDM_Table_Length 19 | |
| 302 | #define CCK_Table_length 12 | |
| 303 | ||
| 5f53d8ca JC |
304 | // |
| 305 | //Tx Descriptor for RLT8192SU(Normal mode) | |
| 306 | // | |
| 307 | typedef struct _tx_desc_819x_usb { | |
| 308 | // DWORD 0 | |
| 309 | u16 PktSize;//:16; | |
| 310 | u8 Offset;//:8; | |
| 311 | u8 Type:2; // Reserved for MAC header Frame Type subfield. | |
| 312 | u8 LastSeg:1; | |
| 313 | u8 FirstSeg:1; | |
| 314 | u8 LINIP:1; | |
| 315 | u8 AMSDU:1; | |
| 316 | u8 GF:1; | |
| 317 | u8 OWN:1; | |
| 318 | ||
| 319 | // DWORD 1 | |
| 320 | u8 MacID:5; | |
| 321 | u8 MoreData:1; | |
| 322 | u8 MOREFRAG:1; | |
| 323 | u8 PIFS:1; | |
| 324 | u8 QueueSelect:5; | |
| 325 | u8 AckPolicy:2; | |
| 326 | u8 NoACM:1; | |
| 327 | u8 NonQos:1; | |
| 328 | u8 KeyID:2; | |
| 329 | u8 OUI:1; | |
| 330 | u8 PktType:1; | |
| 331 | u8 EnDescID:1; | |
| 332 | u8 SecType:2; | |
| 333 | u8 HTC:1; //padding0 | |
| 334 | u8 WDS:1; //padding1 | |
| 335 | u8 PktOffset:5; //padding_len (hw) | |
| 336 | u8 HWPC:1; | |
| 337 | ||
| 338 | // DWORD 2 | |
| 339 | u32 DataRetryLmt:6; | |
| 340 | u32 RetryLmtEn:1; | |
| 341 | u32 TSFL:5; | |
| 342 | u32 RTSRC:6; // Reserved for HW RTS Retry Count. | |
| 343 | u32 DATARC:6; // Reserved for HW DATA Retry Count. | |
| 344 | u32 Rsvd1:5; | |
| 345 | u32 AllowAggregation:1; | |
| 346 | u32 BK:1; //Aggregation break. | |
| 347 | u32 OwnMAC:1; | |
| 348 | ||
| 349 | // DWORD 3 | |
| 350 | u8 NextHeadPage;//:8; | |
| 351 | u8 TailPage;//:8; | |
| 352 | u16 Seq:12; | |
| 353 | u16 Frag:4; | |
| 354 | ||
| 355 | // DWORD 4 | |
| 356 | u32 RTSRate:6; | |
| 357 | u32 DisRTSFB:1; | |
| 358 | u32 RTSRateFBLmt:4; | |
| 359 | u32 CTS2Self:1; | |
| 360 | u32 RTSEn:1; | |
| 361 | u32 RaBRSRID:3; //Rate adaptive BRSR ID. | |
| 362 | u32 TxHT:1; | |
| 363 | u32 TxShort:1;//for data | |
| 364 | u32 TxBandwidth:1; | |
| 365 | u32 TxSubCarrier:2; | |
| 366 | u32 STBC:2; | |
| 367 | u32 RD:1; | |
| 368 | u32 RTSHT:1; | |
| 369 | u32 RTSShort:1; | |
| 370 | u32 RTSBW:1; | |
| 371 | u32 RTSSubcarrier:2; | |
| 372 | u32 RTSSTBC:2; | |
| 373 | u32 USERATE:1; | |
| 374 | // DWORD 5 | |
| 375 | u32 PktID:9; | |
| 376 | u32 TxRate:6; | |
| 377 | u32 DISFB:1; | |
| 378 | u32 DataRateFBLmt:5; | |
| 379 | u32 TxAGC:11; | |
| 380 | ||
| 381 | // DWORD 6 | |
| 382 | u16 IPChkSum;//:16; | |
| 383 | u16 TCPChkSum;//:16; | |
| 384 | ||
| 385 | // DWORD 7 | |
| 386 | //u16 TxBuffSize;//:16;//pcie | |
| 387 | u16 TxBufferSize; | |
| 388 | u16 IPHdrOffset:8; | |
| 389 | u16 Rsvd2:7; | |
| 390 | u16 TCPEn:1; | |
| 391 | }tx_desc_819x_usb, *ptx_desc_819x_usb; | |
| 392 | typedef struct _tx_status_desc_8192s_usb{ | |
| 393 | ||
| 394 | //DWORD 0 | |
| 395 | u8 TxRate:6; | |
| 396 | u8 Rsvd1:1; | |
| 397 | u8 BandWidth:1; | |
| 398 | u8 RTSRate:6; | |
| 399 | u8 AGGLS:1; | |
| 400 | u8 AGG:1; | |
| 401 | u8 RTSRC:6; | |
| 402 | u8 DataRC:6; | |
| 403 | u8 FailCause:2; | |
| 404 | u8 TxOK:1; | |
| 405 | u8 Own:1; | |
| 406 | ||
| 407 | //DWORD 1 | |
| 408 | u16 Seq:12; | |
| 409 | u8 QueueSel:5; | |
| 410 | u8 MACID:5; | |
| 411 | u8 PwrMgt:1; | |
| 412 | u8 MoreData:1; | |
| 413 | u8 Rsvd2; | |
| 414 | ||
| 415 | //DWORD 2 | |
| 416 | u8 RxAGC1; | |
| 417 | u8 RxAGC2; | |
| 418 | u8 RxAGC3; | |
| 419 | u8 RxAGC4; | |
| 420 | }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb; | |
| 5f53d8ca | 421 | |
| 5f53d8ca JC |
422 | |
| 423 | ||
| 5f53d8ca JC |
424 | // |
| 425 | //Tx Descriptor for RLT8192SU(Load FW mode) | |
| 426 | // | |
| 427 | typedef struct _tx_desc_cmd_819x_usb{ | |
| 428 | // DWORD 0 | |
| 429 | u16 PktSize; | |
| 430 | u8 Offset; | |
| 431 | u8 Rsvd0:4; | |
| 432 | u8 LINIP:1; | |
| 433 | u8 Rsvd1:2; | |
| 434 | u8 OWN:1; | |
| 435 | ||
| 436 | // DWORD 1, 2, 3, 4, 5, 6 are all reserved. | |
| 437 | u32 Rsvd2; | |
| 438 | u32 Rsvd3; | |
| 439 | u32 Rsvd4; | |
| 440 | u32 Rsvd5; | |
| 441 | u32 Rsvd6; | |
| 442 | u32 Rsvd7; | |
| 443 | ||
| 444 | // DWORD 7 | |
| 445 | u16 TxBuffSize;//pcie | |
| 446 | u16 Rsvd8; | |
| 447 | }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb; | |
| 448 | // | |
| 449 | //H2C Command for RLT8192SU(Host TxCmd) | |
| 450 | // | |
| 451 | typedef struct _tx_h2c_desc_cmd_8192s_usb{ | |
| 452 | // DWORD 0 | |
| 453 | u32 PktSize:16; | |
| 454 | u32 Offset:8; | |
| 455 | u32 Rsvd0:7; | |
| 456 | u32 OWN:1; | |
| 457 | ||
| 458 | // DWORD 1 | |
| 459 | u32 Rsvd1:8; | |
| 460 | u32 QSEL:5; | |
| 461 | u32 Rsvd2:19; | |
| 462 | ||
| 463 | // DWORD 2 | |
| 464 | u32 Rsvd3; | |
| 465 | ||
| 466 | // DWORD 3 | |
| 467 | u32 NextHeadPage:8; | |
| 468 | u32 TailPage:8; | |
| 469 | u32 Rsvd4:16; | |
| 470 | ||
| 471 | // DWORD 4, 5, 6, 7 | |
| 472 | u32 Rsvd5; | |
| 473 | u32 Rsvd6; | |
| 474 | u32 Rsvd7; | |
| 475 | u32 Rsvd8; | |
| 476 | }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb; | |
| 477 | ||
| 478 | ||
| 479 | typedef struct _tx_h2c_cmd_hdr_8192s_usb{ | |
| 480 | // DWORD 0 | |
| 481 | u32 CmdLen:16; | |
| 482 | u32 ElementID:8; | |
| 483 | u32 CmdSeq:8; | |
| 484 | ||
| 485 | // DWORD 1 | |
| 486 | u32 Rsvd0; | |
| 487 | }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb; | |
| 5f53d8ca | 488 | |
| 5f53d8ca JC |
489 | typedef struct _tx_fwinfo_819x_usb{ |
| 490 | //DWORD 0 | |
| 491 | u8 TxRate:7; | |
| 492 | u8 CtsEnable:1; | |
| 493 | u8 RtsRate:7; | |
| 494 | u8 RtsEnable:1; | |
| 495 | u8 TxHT:1; | |
| 496 | u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS | |
| 497 | u8 TxBandwidth:1; // This is used for HT MCS rate only. | |
| 498 | u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. | |
| 499 | u8 STBC:2; | |
| 500 | u8 AllowAggregation:1; | |
| 501 | u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate | |
| 502 | u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS | |
| 503 | u8 RtsBandwidth:1; // This is used for HT MCS rate only. | |
| 504 | u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. | |
| 505 | u8 RtsSTBC:2; | |
| 506 | u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration | |
| 507 | ||
| 508 | //DWORD 1 | |
| 509 | u32 RxMF:2; | |
| 510 | u32 RxAMD:3; | |
| 511 | u32 Reserved1:3; | |
| 512 | u32 TxAGCOffSet:4;//TxAGCOffset:4; | |
| 513 | u32 TxAGCSign:1; | |
| 514 | u32 Tx_INFO_RSVD:6; | |
| 515 | u32 PacketID:13; | |
| 516 | }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb; | |
| 5f53d8ca JC |
517 | |
| 518 | typedef struct rtl8192_rx_info { | |
| 519 | struct urb *urb; | |
| 520 | struct net_device *dev; | |
| 521 | u8 out_pipe; | |
| 522 | }rtl8192_rx_info ; | |
| 523 | ||
| 5f53d8ca JC |
524 | //typedef struct _RX_DESC_STATUS_8192SU{ |
| 525 | typedef struct rx_desc_819x_usb{ | |
| 526 | //DWORD 0 | |
| 527 | u16 Length:14; | |
| 528 | u16 CRC32:1; | |
| 529 | u16 ICV:1; | |
| 530 | u8 RxDrvInfoSize:4; | |
| 531 | u8 Security:3; | |
| 532 | u8 Qos:1; | |
| 533 | u8 Shift:2; | |
| 534 | u8 PHYStatus:1; | |
| 535 | u8 SWDec:1; | |
| 536 | u8 LastSeg:1; | |
| 537 | u8 FirstSeg:1; | |
| 538 | u8 EOR:1; | |
| 539 | u8 Own:1; | |
| 540 | ||
| 541 | //DWORD 1 | |
| 542 | u16 MACID:5; | |
| 543 | u16 TID:4; | |
| 544 | u16 HwRsvd:5; | |
| 545 | u16 PAGGR:1; | |
| 546 | u16 FAGGR:1; | |
| 547 | u8 A1_FIT:4; | |
| 548 | u8 A2_FIT:4; | |
| 549 | u8 PAM:1; | |
| 550 | u8 PWR:1; | |
| 551 | u8 MoreData:1; | |
| 552 | u8 MoreFrag:1; | |
| 553 | u8 Type:2; | |
| 554 | u8 MC:1; | |
| 555 | u8 BC:1; | |
| 556 | ||
| 557 | //DWORD 2 | |
| 558 | u16 Seq:12; | |
| 559 | u16 Frag:4; | |
| 5f53d8ca | 560 | u8 NextPktLen;//:8; |
| 5f53d8ca JC |
561 | u8 Rsvd0:6; |
| 562 | u8 NextIND:1; | |
| 563 | u8 Rsvd1:1; | |
| 564 | ||
| 565 | //DWORD 3 | |
| 566 | u8 RxMCS:6; | |
| 567 | u8 RxHT:1; | |
| 568 | u8 AMSDU:1; | |
| 569 | u8 SPLCP:1; | |
| 570 | u8 BW:1; | |
| 571 | u8 HTC:1; | |
| 572 | u8 TCPChkRpt:1; | |
| 573 | u8 IPChkRpt:1; | |
| 574 | u8 TCPChkValID:1; | |
| 575 | u8 HwPCErr:1; | |
| 576 | u8 HwPCInd:1; | |
| 577 | u16 IV0;//:16; | |
| 578 | ||
| 579 | //DWORD 4 | |
| 580 | u32 IV1; | |
| 581 | ||
| 582 | //DWORD 5 | |
| 583 | u32 TSFL; | |
| 584 | //}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU; | |
| 585 | }rx_desc_819x_usb, *prx_desc_819x_usb; | |
| 5f53d8ca | 586 | |
| 5f53d8ca | 587 | |
| 5f53d8ca JC |
588 | // |
| 589 | // Driver info are written to the begining of the RxBuffer | |
| 590 | // | |
| 591 | //typedef struct _RX_DRIVER_INFO_8192S{ | |
| 592 | typedef struct rx_drvinfo_819x_usb{ | |
| 593 | // | |
| 594 | // Driver info contain PHY status and other variabel size info | |
| 595 | // PHY Status content as below | |
| 596 | // | |
| 597 | ||
| 598 | //DWORD 0 | |
| 599 | /*u4Byte gain_0:7; | |
| 600 | u4Byte trsw_0:1; | |
| 601 | u4Byte gain_1:7; | |
| 602 | u4Byte trsw_1:1; | |
| 603 | u4Byte gain_2:7; | |
| 604 | u4Byte trsw_2:1; | |
| 605 | u4Byte gain_3:7; | |
| 606 | u4Byte trsw_3:1; */ | |
| 607 | u8 gain_trsw[4]; | |
| 608 | ||
| 609 | //DWORD 1 | |
| 610 | /*u4Byte pwdb_all:8; | |
| 611 | u4Byte cfosho_0:8; | |
| 612 | u4Byte cfosho_1:8; | |
| 613 | u4Byte cfosho_2:8;*/ | |
| 614 | u8 pwdb_all; | |
| 615 | u8 cfosho[4]; | |
| 616 | ||
| 617 | //DWORD 2 | |
| 618 | /*u4Byte cfosho_3:8; | |
| 619 | u4Byte cfotail_0:8; | |
| 620 | u4Byte cfotail_1:8; | |
| 621 | u4Byte cfotail_2:8;*/ | |
| 622 | u8 cfotail[4]; | |
| 623 | ||
| 624 | //DWORD 3 | |
| 625 | /*u4Byte cfotail_3:8; | |
| 626 | u4Byte rxevm_0:8; | |
| 627 | u4Byte rxevm_1:8; | |
| 628 | u4Byte rxsnr_0:8;*/ | |
| 629 | char rxevm[2]; | |
| 630 | char rxsnr[4]; | |
| 631 | ||
| 632 | //DWORD 4 | |
| 633 | /*u4Byte rxsnr_1:8; | |
| 634 | u4Byte rxsnr_2:8; | |
| 635 | u4Byte rxsnr_3:8; | |
| 636 | u4Byte pdsnr_0:8;*/ | |
| 637 | u8 pdsnr[2]; | |
| 638 | ||
| 639 | //DWORD 5 | |
| 640 | /*u4Byte pdsnr_1:8; | |
| 641 | u4Byte csi_current_0:8; | |
| 642 | u4Byte csi_current_1:8; | |
| 643 | u4Byte csi_target_0:8;*/ | |
| 644 | u8 csi_current[2]; | |
| 645 | u8 csi_target[2]; | |
| 646 | ||
| 647 | //DWORD 6 | |
| 648 | /*u4Byte csi_target_1:8; | |
| 649 | u4Byte sigevm:8; | |
| 650 | u4Byte max_ex_pwr:8; | |
| 651 | u4Byte ex_intf_flag:1; | |
| 652 | u4Byte sgi_en:1; | |
| 653 | u4Byte rxsc:2; | |
| 654 | u4Byte reserve:4;*/ | |
| 655 | u8 sigevm; | |
| 656 | u8 max_ex_pwr; | |
| 657 | u8 ex_intf_flag:1; | |
| 658 | u8 sgi_en:1; | |
| 659 | u8 rxsc:2; | |
| 660 | u8 reserve:4; | |
| 661 | ||
| 662 | }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb; | |
| 5f53d8ca JC |
663 | |
| 664 | #define HWSET_MAX_SIZE_92S 128 | |
| 5f53d8ca JC |
665 | #define MAX_802_11_HEADER_LENGTH 40 |
| 666 | #define MAX_PKT_AGG_NUM 256 | |
| 667 | #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN | |
| 5f53d8ca JC |
668 | |
| 669 | #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */ | |
| 670 | #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/ | |
| 671 | //#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) | |
| 672 | #define ENCRYPTION_MAX_OVERHEAD 128 | |
| 673 | #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb) | |
| 674 | //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) | |
| 675 | #define MAX_FRAGMENT_COUNT 8 | |
| 676 | #ifdef RTL8192U | |
| 5f53d8ca | 677 | #define MAX_TRANSMIT_BUFFER_SIZE 8000 |
| 5f53d8ca JC |
678 | #else |
| 679 | #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT) | |
| 680 | #endif | |
| 5f53d8ca JC |
681 | #define scrclng 4 // octets for crc32 (FCS, ICV) |
| 682 | ||
| 683 | typedef enum rf_optype | |
| 684 | { | |
| 685 | RF_OP_By_SW_3wire = 0, | |
| 686 | RF_OP_By_FW, | |
| 687 | RF_OP_MAX | |
| 688 | }rf_op_type; | |
| 689 | /* 8190 Loopback Mode definition */ | |
| 690 | typedef enum _rtl819xUsb_loopback{ | |
| 691 | RTL819xU_NO_LOOPBACK = 0, | |
| 692 | RTL819xU_MAC_LOOPBACK = 1, | |
| 693 | RTL819xU_DMA_LOOPBACK = 2, | |
| 694 | RTL819xU_CCK_LOOPBACK = 3, | |
| 695 | }rtl819xUsb_loopback_e; | |
| 696 | ||
| 697 | /* for rtl819x */ | |
| 698 | typedef enum _RT_STATUS{ | |
| 699 | RT_STATUS_SUCCESS = 0, | |
| 700 | RT_STATUS_FAILURE = 1, | |
| 701 | RT_STATUS_PENDING = 2, | |
| 702 | RT_STATUS_RESOURCE = 3 | |
| 703 | }RT_STATUS,*PRT_STATUS; | |
| 704 | ||
| 705 | //#ifdef RTL8192SU | |
| 706 | typedef enum _RTL8192SUSB_LOOPBACK{ | |
| 707 | RTL8192SU_NO_LOOPBACK = 0, | |
| 708 | RTL8192SU_MAC_LOOPBACK = 1, | |
| 709 | RTL8192SU_DMA_LOOPBACK = 2, | |
| 710 | RTL8192SU_CCK_LOOPBACK = 3, | |
| 711 | }RTL8192SUSB_LOOPBACK_E; | |
| 712 | //#endif | |
| 713 | ||
| 5f53d8ca JC |
714 | //+by amy 080507 |
| 715 | #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP | |
| 716 | ||
| 717 | ||
| 718 | /* Firmware Queue Layout */ | |
| 719 | #define NUM_OF_FIRMWARE_QUEUE 10 | |
| 720 | #define NUM_OF_PAGES_IN_FW 0x100 | |
| 721 | ||
| 5f53d8ca JC |
722 | |
| 723 | #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020 | |
| 724 | #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020 | |
| 725 | #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040 | |
| 726 | #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040 | |
| 727 | #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 | |
| 728 | #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4 | |
| 729 | #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20 | |
| 730 | #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 | |
| 731 | #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 | |
| 732 | #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18 | |
| 733 | ||
| 5f53d8ca JC |
734 | |
| 735 | #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 | |
| 736 | #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 | |
| 737 | #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 | |
| 738 | #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 | |
| 739 | #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 | |
| 740 | #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 | |
| 741 | #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08 | |
| 742 | #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 | |
| 743 | #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 | |
| 744 | //================================================================= | |
| 745 | //================================================================= | |
| 746 | ||
| 747 | #define EPROM_93c46 0 | |
| 748 | #define EPROM_93c56 1 | |
| 749 | ||
| 750 | #define DEFAULT_FRAG_THRESHOLD 2342U | |
| 751 | #define MIN_FRAG_THRESHOLD 256U | |
| 752 | #define DEFAULT_BEACONINTERVAL 0x64U | |
| 753 | #define DEFAULT_BEACON_ESSID "Rtl819xU" | |
| 754 | ||
| 755 | #define DEFAULT_SSID "" | |
| 756 | #define DEFAULT_RETRY_RTS 7 | |
| 757 | #define DEFAULT_RETRY_DATA 7 | |
| 758 | #define PRISM_HDR_SIZE 64 | |
| 759 | ||
| 760 | #define PHY_RSSI_SLID_WIN_MAX 100 | |
| 761 | ||
| 762 | ||
| 763 | typedef enum _WIRELESS_MODE { | |
| 764 | WIRELESS_MODE_UNKNOWN = 0x00, | |
| 765 | WIRELESS_MODE_A = 0x01, | |
| 766 | WIRELESS_MODE_B = 0x02, | |
| 767 | WIRELESS_MODE_G = 0x04, | |
| 768 | WIRELESS_MODE_AUTO = 0x08, | |
| 769 | WIRELESS_MODE_N_24G = 0x10, | |
| 770 | WIRELESS_MODE_N_5G = 0x20 | |
| 771 | } WIRELESS_MODE; | |
| 772 | ||
| 773 | ||
| 774 | #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 | |
| 775 | ||
| 776 | typedef struct buffer | |
| 777 | { | |
| 778 | struct buffer *next; | |
| 779 | u32 *buf; | |
| 780 | ||
| 781 | } buffer; | |
| 782 | ||
| 783 | typedef struct rtl_reg_debug{ | |
| 784 | unsigned int cmd; | |
| 785 | struct { | |
| 786 | unsigned char type; | |
| 787 | unsigned char addr; | |
| 788 | unsigned char page; | |
| 789 | unsigned char length; | |
| 790 | } head; | |
| 791 | unsigned char buf[0xff]; | |
| 792 | }rtl_reg_debug; | |
| 793 | ||
| 5f53d8ca JC |
794 | typedef struct _rt_9x_tx_rate_history { |
| 795 | u32 cck[4]; | |
| 796 | u32 ofdm[8]; | |
| 797 | // HT_MCS[0][]: BW=0 SG=0 | |
| 798 | // HT_MCS[1][]: BW=1 SG=0 | |
| 799 | // HT_MCS[2][]: BW=0 SG=1 | |
| 800 | // HT_MCS[3][]: BW=1 SG=1 | |
| 801 | u32 ht_mcs[4][16]; | |
| 802 | }rt_tx_rahis_t, *prt_tx_rahis_t; | |
| 803 | typedef struct _RT_SMOOTH_DATA_4RF { | |
| 804 | char elements[4][100];//array to store values | |
| 805 | u32 index; //index to current array to store | |
| 806 | u32 TotalNum; //num of valid elements | |
| 807 | u32 TotalVal[4]; //sum of valid elements | |
| 808 | }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF; | |
| 809 | ||
| 810 | #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size | |
| 811 | //stats seems messed up, clean it ASAP | |
| 812 | typedef struct Stats | |
| 813 | { | |
| 814 | unsigned long txrdu; | |
| 815 | // unsigned long rxrdu; | |
| 816 | //unsigned long rxnolast; | |
| 817 | //unsigned long rxnodata; | |
| 818 | // unsigned long rxreset; | |
| 819 | // unsigned long rxnopointer; | |
| 820 | unsigned long rxok; | |
| 821 | unsigned long rxframgment; | |
| 822 | unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query | |
| 823 | unsigned long rxurberr; | |
| 824 | unsigned long rxstaterr; | |
| 825 | unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa | |
| 826 | unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI | |
| 827 | unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) | |
| 828 | unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40) | |
| 829 | unsigned long numpacket_matchbssid; // debug use only. | |
| 830 | unsigned long numpacket_toself; // debug use only. | |
| 831 | unsigned long num_process_phyinfo; // debug use only. | |
| 832 | unsigned long numqry_phystatus; | |
| 833 | unsigned long numqry_phystatusCCK; | |
| 834 | unsigned long numqry_phystatusHT; | |
| 835 | unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate | |
| 836 | unsigned long txnperr; | |
| 837 | unsigned long txnpdrop; | |
| 838 | unsigned long txresumed; | |
| 839 | // unsigned long rxerr; | |
| 840 | // unsigned long rxoverflow; | |
| 841 | // unsigned long rxint; | |
| 842 | unsigned long txnpokint; | |
| 843 | // unsigned long txhpokint; | |
| 844 | // unsigned long txhperr; | |
| 845 | // unsigned long ints; | |
| 846 | // unsigned long shints; | |
| 847 | unsigned long txoverflow; | |
| 848 | // unsigned long rxdmafail; | |
| 849 | // unsigned long txbeacon; | |
| 850 | // unsigned long txbeaconerr; | |
| 851 | unsigned long txlpokint; | |
| 852 | unsigned long txlpdrop; | |
| 853 | unsigned long txlperr; | |
| 854 | unsigned long txbeokint; | |
| 855 | unsigned long txbedrop; | |
| 856 | unsigned long txbeerr; | |
| 857 | unsigned long txbkokint; | |
| 858 | unsigned long txbkdrop; | |
| 859 | unsigned long txbkerr; | |
| 860 | unsigned long txviokint; | |
| 861 | unsigned long txvidrop; | |
| 862 | unsigned long txvierr; | |
| 863 | unsigned long txvookint; | |
| 864 | unsigned long txvodrop; | |
| 865 | unsigned long txvoerr; | |
| 866 | unsigned long txbeaconokint; | |
| 867 | unsigned long txbeacondrop; | |
| 868 | unsigned long txbeaconerr; | |
| 869 | unsigned long txmanageokint; | |
| 870 | unsigned long txmanagedrop; | |
| 871 | unsigned long txmanageerr; | |
| 872 | unsigned long txdatapkt; | |
| 873 | unsigned long txfeedback; | |
| 874 | unsigned long txfeedbackok; | |
| 875 | ||
| 876 | unsigned long txoktotal; | |
| 877 | unsigned long txokbytestotal; | |
| 878 | unsigned long txokinperiod; | |
| 879 | unsigned long txmulticast; | |
| 880 | unsigned long txbytesmulticast; | |
| 881 | unsigned long txbroadcast; | |
| 882 | unsigned long txbytesbroadcast; | |
| 883 | unsigned long txunicast; | |
| 884 | unsigned long txbytesunicast; | |
| 885 | ||
| 886 | unsigned long rxoktotal; | |
| 887 | unsigned long rxbytesunicast; | |
| 888 | unsigned long txfeedbackfail; | |
| 889 | unsigned long txerrtotal; | |
| 890 | unsigned long txerrbytestotal; | |
| 891 | unsigned long txerrmulticast; | |
| 892 | unsigned long txerrbroadcast; | |
| 893 | unsigned long txerrunicast; | |
| 894 | unsigned long txretrycount; | |
| 895 | unsigned long txfeedbackretry; | |
| 896 | u8 last_packet_rate; | |
| 897 | unsigned long slide_signal_strength[100]; | |
| 898 | unsigned long slide_evm[100]; | |
| 899 | unsigned long slide_rssi_total; // For recording sliding window's RSSI value | |
| 900 | unsigned long slide_evm_total; // For recording sliding window's EVM value | |
| 901 | long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct. | |
| 902 | long signal_quality; | |
| 903 | long last_signal_strength_inpercent; | |
| 904 | long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now. | |
| 905 | u8 rx_rssi_percentage[4]; | |
| 906 | u8 rx_evm_percentage[2]; | |
| 907 | long rxSNRdB[4]; | |
| 908 | rt_tx_rahis_t txrate; | |
| 909 | u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi | |
| 910 | u32 Slide_Beacon_Total; //cosa add for beacon rssi | |
| 911 | RT_SMOOTH_DATA_4RF cck_adc_pwdb; | |
| 912 | ||
| 913 | u32 CurrentShowTxate; | |
| 914 | } Stats; | |
| 915 | ||
| 916 | ||
| 917 | // Bandwidth Offset | |
| 918 | #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 | |
| 919 | #define HAL_PRIME_CHNL_OFFSET_LOWER 1 | |
| 920 | #define HAL_PRIME_CHNL_OFFSET_UPPER 2 | |
| 921 | ||
| 922 | //+by amy 080507 | |
| 923 | ||
| 924 | typedef struct ChnlAccessSetting { | |
| 925 | u16 SIFS_Timer; | |
| 926 | u16 DIFS_Timer; | |
| 927 | u16 SlotTimeTimer; | |
| 928 | u16 EIFS_Timer; | |
| 929 | u16 CWminIndex; | |
| 930 | u16 CWmaxIndex; | |
| 931 | }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING; | |
| 932 | ||
| 933 | typedef struct _BB_REGISTER_DEFINITION{ | |
| 934 | u32 rfintfs; // set software control: // 0x870~0x877[8 bytes] | |
| 935 | u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes] | |
| 936 | u32 rfintfo; // output data: // 0x860~0x86f [16 bytes] | |
| 937 | u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes] | |
| 938 | u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes] | |
| 939 | u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes] | |
| 940 | u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes] | |
| 941 | u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] | |
| 942 | u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] | |
| 943 | u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes] | |
| 944 | u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] | |
| 945 | u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] | |
| 946 | u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] | |
| 947 | u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] | |
| 948 | u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] | |
| 949 | u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] | |
| 950 | u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes] | |
| 951 | u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B | |
| 952 | }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; | |
| 953 | ||
| 954 | typedef enum _RT_RF_TYPE_819xU{ | |
| 955 | RF_TYPE_MIN = 0, | |
| 956 | RF_8225, | |
| 957 | RF_8256, | |
| 958 | RF_8258, | |
| 959 | RF_6052=4, // 4 11b/g/n RF | |
| 960 | RF_PSEUDO_11N = 5, | |
| 961 | }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; | |
| 962 | ||
| 963 | //#ifdef RTL8192SU | |
| 964 | typedef enum _RF_POWER_STATE{ | |
| 965 | RF_ON, | |
| 966 | RF_SLEEP, | |
| 967 | RF_OFF, | |
| 968 | RF_SHUT_DOWN, | |
| 969 | }RF_POWER_STATE, *PRF_POWER_STATE; | |
| 970 | //#endif | |
| 971 | ||
| 972 | typedef struct _rate_adaptive | |
| 973 | { | |
| 974 | u8 rate_adaptive_disabled; | |
| 975 | u8 ratr_state; | |
| 976 | u16 reserve; | |
| 977 | ||
| 978 | u32 high_rssi_thresh_for_ra; | |
| 979 | u32 high2low_rssi_thresh_for_ra; | |
| 980 | u8 low2high_rssi_thresh_for_ra40M; | |
| 981 | u32 low_rssi_thresh_for_ra40M; | |
| 982 | u8 low2high_rssi_thresh_for_ra20M; | |
| 983 | u32 low_rssi_thresh_for_ra20M; | |
| 984 | u32 upper_rssi_threshold_ratr; | |
| 985 | u32 middle_rssi_threshold_ratr; | |
| 986 | u32 low_rssi_threshold_ratr; | |
| 987 | u32 low_rssi_threshold_ratr_40M; | |
| 988 | u32 low_rssi_threshold_ratr_20M; | |
| 989 | u8 ping_rssi_enable; //cosa add for test | |
| 990 | u32 ping_rssi_ratr; //cosa add for test | |
| 991 | u32 ping_rssi_thresh_for_ra;//cosa add for test | |
| 992 | u32 last_ratr; | |
| 993 | ||
| 994 | } rate_adaptive, *prate_adaptive; | |
| 995 | ||
| 996 | #define TxBBGainTableLength 37 | |
| 997 | #define CCKTxBBGainTableLength 23 | |
| 998 | ||
| 999 | typedef struct _txbbgain_struct | |
| 1000 | { | |
| 1001 | long txbb_iq_amplifygain; | |
| 1002 | u32 txbbgain_value; | |
| 1003 | } txbbgain_struct, *ptxbbgain_struct; | |
| 1004 | ||
| 1005 | typedef struct _ccktxbbgain_struct | |
| 1006 | { | |
| 1007 | //The Value is from a22 to a29 one Byte one time is much Safer | |
| 1008 | u8 ccktxbb_valuearray[8]; | |
| 1009 | } ccktxbbgain_struct,*pccktxbbgain_struct; | |
| 1010 | ||
| 1011 | ||
| 1012 | typedef struct _init_gain | |
| 1013 | { | |
| 1014 | u8 xaagccore1; | |
| 1015 | u8 xbagccore1; | |
| 1016 | u8 xcagccore1; | |
| 1017 | u8 xdagccore1; | |
| 1018 | u8 cca; | |
| 1019 | ||
| 1020 | } init_gain, *pinit_gain; | |
| 1021 | //by amy 0606 | |
| 1022 | ||
| 1023 | typedef struct _phy_ofdm_rx_status_report_819xusb | |
| 1024 | { | |
| 1025 | u8 trsw_gain_X[4]; | |
| 1026 | u8 pwdb_all; | |
| 1027 | u8 cfosho_X[4]; | |
| 1028 | u8 cfotail_X[4]; | |
| 1029 | u8 rxevm_X[2]; | |
| 1030 | u8 rxsnr_X[4]; | |
| 1031 | u8 pdsnr_X[2]; | |
| 1032 | u8 csi_current_X[2]; | |
| 1033 | u8 csi_target_X[2]; | |
| 1034 | u8 sigevm; | |
| 1035 | u8 max_ex_pwr; | |
| 1036 | u8 sgi_en; | |
| 1037 | u8 rxsc_sgien_exflg; | |
| 1038 | }phy_sts_ofdm_819xusb_t; | |
| 1039 | ||
| 1040 | typedef struct _phy_cck_rx_status_report_819xusb | |
| 1041 | { | |
| 1042 | /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend | |
| 1043 | 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ | |
| 1044 | u8 adc_pwdb_X[4]; | |
| 1045 | u8 sq_rpt; | |
| 1046 | u8 cck_agc_rpt; | |
| 1047 | }phy_sts_cck_819xusb_t; | |
| 1048 | ||
| 1049 | ||
| 1050 | typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{ | |
| 1051 | u8 reserved:4; | |
| 1052 | u8 rxsc:2; | |
| 1053 | u8 sgi_en:1; | |
| 1054 | u8 ex_intf_flag:1; | |
| 1055 | }phy_ofdm_rx_status_rxsc_sgien_exintfflag; | |
| 1056 | ||
| 1057 | typedef enum _RT_CUSTOMER_ID | |
| 1058 | { | |
| 1059 | RT_CID_DEFAULT = 0, | |
| 1060 | RT_CID_8187_ALPHA0 = 1, | |
| 1061 | RT_CID_8187_SERCOMM_PS = 2, | |
| 1062 | RT_CID_8187_HW_LED = 3, | |
| 1063 | RT_CID_8187_NETGEAR = 4, | |
| 1064 | RT_CID_WHQL = 5, | |
| 1065 | RT_CID_819x_CAMEO = 6, | |
| 1066 | RT_CID_819x_RUNTOP = 7, | |
| 1067 | RT_CID_819x_Senao = 8, | |
| 1068 | RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. | |
| 1069 | RT_CID_819x_Netcore = 10, | |
| 1070 | RT_CID_Nettronix = 11, | |
| 1071 | RT_CID_DLINK = 12, | |
| 1072 | RT_CID_PRONET = 13, | |
| 1073 | }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; | |
| 1074 | ||
| 1075 | //================================================================================ | |
| 1076 | // LED customization. | |
| 1077 | //================================================================================ | |
| 1078 | ||
| 1079 | typedef enum _LED_STRATEGY_8190{ | |
| 1080 | SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. | |
| 1081 | SW_LED_MODE1, // SW control for PCI Express | |
| 1082 | SW_LED_MODE2, // SW control for Cameo. | |
| 1083 | SW_LED_MODE3, // SW contorl for RunTop. | |
| 1084 | SW_LED_MODE4, // SW control for Netcore | |
| 1085 | HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) | |
| 1086 | }LED_STRATEGY_8190, *PLED_STRATEGY_8190; | |
| 1087 | ||
| 1088 | typedef enum _RESET_TYPE { | |
| 1089 | RESET_TYPE_NORESET = 0x00, | |
| 1090 | RESET_TYPE_NORMAL = 0x01, | |
| 1091 | RESET_TYPE_SILENT = 0x02 | |
| 1092 | } RESET_TYPE; | |
| 1093 | ||
| 1094 | /* The simple tx command OP code. */ | |
| 1095 | typedef enum _tag_TxCmd_Config_Index{ | |
| 1096 | TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, | |
| 1097 | TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, | |
| 1098 | TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, | |
| 1099 | TXCMD_SET_TX_DURATION = 0xFF900003, | |
| 1100 | TXCMD_SET_RX_RSSI = 0xFF900004, | |
| 1101 | TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, | |
| 1102 | TXCMD_XXXX_CTRL, | |
| 1103 | }DCMD_TXCMD_OP; | |
| 1104 | ||
| 1105 | typedef enum{ | |
| 1106 | NIC_8192U = 1, | |
| 1107 | NIC_8190P = 2, | |
| 1108 | NIC_8192E = 3, | |
| 1109 | NIC_8192SE = 4, | |
| 1110 | NIC_8192SU = 5, | |
| 1111 | } nic_t; | |
| 1112 | ||
| 1113 | //definded by WB. Ready to fill handlers for different NIC types. | |
| 1114 | //add handle here when necessary. | |
| 1115 | struct rtl819x_ops{ | |
| 1116 | nic_t nic_type; | |
| 1117 | void (* rtl819x_read_eeprom_info)(struct net_device *dev); | |
| 1118 | short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb); | |
| 1119 | short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb); | |
| 1120 | void (* rtl819x_rx_nomal)(struct sk_buff* skb); | |
| 1121 | void (* rtl819x_rx_cmd)(struct sk_buff *skb); | |
| 1122 | bool (* rtl819x_adapter_start)(struct net_device *dev); | |
| 1123 | void (* rtl819x_link_change)(struct net_device *dev); | |
| 1124 | void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation); | |
| 1125 | void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe); | |
| 1126 | }; | |
| 1127 | ||
| 1128 | typedef struct r8192_priv | |
| 1129 | { | |
| 1130 | struct rtl819x_ops* ops; | |
| 1131 | struct usb_device *udev; | |
| 1132 | //added for maintain info from eeprom | |
| 1133 | short epromtype; | |
| 1134 | u16 eeprom_vid; | |
| 1135 | u16 eeprom_pid; | |
| 1136 | u8 eeprom_CustomerID; | |
| 1137 | u8 eeprom_SubCustomerID; | |
| 1138 | u8 eeprom_ChannelPlan; | |
| 1139 | RT_CUSTOMER_ID CustomerID; | |
| 1140 | LED_STRATEGY_8190 LedStrategy; | |
| 1141 | u8 txqueue_to_outpipemap[9]; | |
| 1142 | u8 RtOutPipes[16]; | |
| 1143 | u8 RtInPipes[16]; | |
| 1144 | u8 ep_in_num; | |
| 1145 | u8 ep_out_num; | |
| 1146 | u8 ep_num; | |
| 1147 | int irq; | |
| 1148 | struct ieee80211_device *ieee80211; | |
| 1149 | ||
| 1150 | short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */ | |
| 1151 | u8 card_8192_version; /* if TCR reports card V B/C this discriminates */ | |
| 1152 | // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */ | |
| 1153 | short enable_gpio0; | |
| 1154 | enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type; | |
| 1155 | short hw_plcp_len; | |
| 1156 | short plcp_preamble_mode; | |
| 1157 | ||
| 1158 | spinlock_t irq_lock; | |
| 1159 | // spinlock_t irq_th_lock; | |
| 1160 | spinlock_t tx_lock; | |
| 1161 | spinlock_t ps_lock; | |
| 5f53d8ca | 1162 | struct mutex mutex; |
| 5f53d8ca JC |
1163 | spinlock_t rf_lock; //used to lock rf write operation added by wb |
| 1164 | ||
| 1165 | u16 irq_mask; | |
| 1166 | // short irq_enabled; | |
| 1167 | // struct net_device *dev; //comment this out. | |
| 1168 | short chan; | |
| 1169 | short sens; | |
| 1170 | short max_sens; | |
| 1171 | ||
| 1172 | ||
| 1173 | // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used | |
| 1174 | // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used | |
| 1175 | // u8 cck_txpwr_base; | |
| 1176 | // u8 ofdm_txpwr_base; | |
| 1177 | // u8 challow[15]; //channels from 1 to 14, 0 not used | |
| 1178 | short up; | |
| 1179 | short crcmon; //if 1 allow bad crc frame reception in monitor mode | |
| 1180 | // short prism_hdr; | |
| 1181 | ||
| 1182 | // struct timer_list scan_timer; | |
| 1183 | /*short scanpending; | |
| 1184 | short stopscan;*/ | |
| 1185 | // spinlock_t scan_lock; | |
| 1186 | // u8 active_probe; | |
| 1187 | //u8 active_scan_num; | |
| 1188 | struct semaphore wx_sem; | |
| 1189 | struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david | |
| 1190 | // short hw_wep; | |
| 1191 | ||
| 1192 | // short digphy; | |
| 1193 | // short antb; | |
| 1194 | // short diversity; | |
| 1195 | // u8 cs_treshold; | |
| 1196 | // short rcr_csense; | |
| 1197 | u8 rf_type; //0 means 1T2R, 1 means 2T4R | |
| 1198 | RT_RF_TYPE_819xU rf_chip; | |
| 1199 | ||
| 1200 | // u32 key0[4]; | |
| 1201 | short (*rf_set_sens)(struct net_device *dev,short sens); | |
| 1202 | u8 (*rf_set_chan)(struct net_device *dev,u8 ch); | |
| 1203 | void (*rf_close)(struct net_device *dev); | |
| 1204 | void (*rf_init)(struct net_device *dev); | |
| 1205 | //short rate; | |
| 1206 | short promisc; | |
| 1207 | /*stats*/ | |
| 1208 | struct Stats stats; | |
| 1209 | struct iw_statistics wstats; | |
| 1210 | struct proc_dir_entry *dir_dev; | |
| 1211 | ||
| 1212 | /*RX stuff*/ | |
| 1213 | // u32 *rxring; | |
| 1214 | // u32 *rxringtail; | |
| 1215 | // dma_addr_t rxringdma; | |
| 1216 | struct urb **rx_urb; | |
| 1217 | struct urb **rx_cmd_urb; | |
| 1218 | ||
| 1219 | /* modified by davad for Rx process */ | |
| 1220 | struct sk_buff_head rx_queue; | |
| 1221 | struct sk_buff_head skb_queue; | |
| 1ec9e48d | 1222 | |
| 5f53d8ca | 1223 | struct work_struct qos_activate; |
| 1ec9e48d | 1224 | |
| 5f53d8ca JC |
1225 | short tx_urb_index; |
| 1226 | atomic_t tx_pending[0x10];//UART_PRIORITY+1 | |
| 1227 | ||
| 1228 | ||
| 1229 | struct tasklet_struct irq_rx_tasklet; | |
| 1230 | struct urb *rxurb_task; | |
| 1231 | ||
| 1232 | //2 Tx Related variables | |
| 1233 | u16 ShortRetryLimit; | |
| 1234 | u16 LongRetryLimit; | |
| 1235 | u32 TransmitConfig; | |
| 1236 | u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27. | |
| 1237 | ||
| 1238 | u32 LastRxDescTSFHigh; | |
| 1239 | u32 LastRxDescTSFLow; | |
| 1240 | ||
| 1241 | ||
| 1242 | //2 Rx Related variables | |
| 1243 | u16 EarlyRxThreshold; | |
| 1244 | u32 ReceiveConfig; | |
| 1245 | u8 AcmControl; | |
| 1246 | ||
| 1247 | u8 RFProgType; | |
| 1248 | ||
| 1249 | u8 retry_data; | |
| 1250 | u8 retry_rts; | |
| 1251 | u16 rts; | |
| 1252 | ||
| 1253 | struct ChnlAccessSetting ChannelAccessSetting; | |
| 1ec9e48d | 1254 | |
| 5f53d8ca | 1255 | struct work_struct reset_wq; |
| 5f53d8ca JC |
1256 | |
| 1257 | /**********************************************************/ | |
| 1258 | //for rtl819xUsb | |
| 1259 | u16 basic_rate; | |
| 1260 | u8 short_preamble; | |
| 1261 | u8 slot_time; | |
| 1262 | bool bDcut; | |
| 1263 | bool bCurrentRxAggrEnable; | |
| 1264 | u8 Rf_Mode; //add for Firmware RF -R/W switch | |
| 1265 | prt_firmware pFirmware; | |
| 1266 | rtl819xUsb_loopback_e LoopbackMode; | |
| 5f53d8ca JC |
1267 | bool usb_error; |
| 1268 | ||
| 1269 | u16 EEPROMTxPowerDiff; | |
| 1270 | u8 EEPROMThermalMeter; | |
| 1271 | u8 EEPROMPwDiff; | |
| 1272 | u8 EEPROMCrystalCap; | |
| 1273 | u8 EEPROM_Def_Ver; | |
| 1274 | u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14 | |
| 1275 | u8 EEPROMTxPowerLevelCCK_V1[3]; | |
| 1276 | u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14 | |
| 1277 | u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G | |
| 1278 | ||
| 1279 | //RTL8192SU | |
| 1280 | bool bDmDisableProtect; | |
| 1281 | bool bIgnoreDiffRateTxPowerOffset; | |
| 1282 | ||
| 5f53d8ca JC |
1283 | // For EEPROM TX Power Index like 8190 series |
| 1284 | u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7 | |
| 1285 | u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 | |
| 1286 | u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7 | |
| 1287 | u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 | |
| 1288 | ||
| 1289 | // F92S new definition | |
| 1290 | //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14] | |
| 1291 | u8 RfCckChnlAreaTxPwr[2][3]; | |
| 1292 | u8 RfOfdmChnlAreaTxPwr1T[2][3]; | |
| 1293 | u8 RfOfdmChnlAreaTxPwr2T[2][3]; | |
| 5f53d8ca JC |
1294 | |
| 1295 | // Add For EEPROM Efuse switch and Efuse Shadow map Setting | |
| 1296 | bool EepromOrEfuse; | |
| 1297 | bool bBootFromEfuse; // system boot form EFUSE | |
| 1298 | u8 EfuseMap[2][HWSET_MAX_SIZE_92S]; | |
| 1299 | ||
| 1300 | u8 EEPROMUsbOption; | |
| 1301 | u8 EEPROMUsbPhyParam[5]; | |
| 1302 | u8 EEPROMTxPwrBase; | |
| 1303 | u8 EEPROMBoardType; | |
| 1304 | bool bBootFromEEPROM; // system boot from EEPROM | |
| 1305 | u8 EEPROMTSSI_A; | |
| 1306 | u8 EEPROMTSSI_B; | |
| 1307 | u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B. | |
| 1308 | u8 EEPROMTxPwrTkMode; | |
| 1309 | ||
| 1310 | u8 bTXPowerDataReadFromEEPORM; | |
| 1311 | ||
| 1312 | u8 EEPROMVersion; | |
| 1313 | u8 EEPROMUsbEndPointNumber; | |
| 1314 | ||
| 1315 | bool AutoloadFailFlag; | |
| 1316 | u8 RfTxPwrLevelCck[2][14]; | |
| 1317 | u8 RfTxPwrLevelOfdm1T[2][14]; | |
| 1318 | u8 RfTxPwrLevelOfdm2T[2][14]; | |
| 1319 | // 2009/01/20 MH Add for new EEPROM format. | |
| 1320 | u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff | |
| 1321 | u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff | |
| 1322 | u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel | |
| 1323 | u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel | |
| 1324 | u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel | |
| 1325 | u8 TxPwrbandEdgeFlag; // Band edge enable flag | |
| 1326 | ||
| 1327 | // L1 and L2 high power threshold. | |
| 1328 | u8 MidHighPwrTHR_L1; | |
| 1329 | u8 MidHighPwrTHR_L2; | |
| 1330 | u8 TxPwrSafetyFlag; // for Tx power safety spec | |
| 1331 | //RTL8192SU | |
| 1332 | ||
| 1333 | /*PHY related*/ | |
| 1334 | BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D | |
| 1335 | // Read/write are allow for following hardware information variables | |
| 5f53d8ca | 1336 | u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM |
| 5f53d8ca JC |
1337 | u32 CCKTxPowerLevelOriginalOffset; |
| 1338 | u8 TxPowerLevelCCK[14]; // CCK channel 1~14 | |
| 1339 | u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 | |
| 1340 | u8 TxPowerLevelOFDM5G[14]; // OFDM 5G | |
| 1341 | u32 Pwr_Track; | |
| 1342 | u8 TxPowerDiff; | |
| 1343 | u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D | |
| 1344 | u8 CrystalCap; // CrystalCap. | |
| 1345 | u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 | |
| 1346 | ||
| 1347 | u8 CckPwEnl; | |
| 1348 | // Use to calculate PWBD. | |
| 1349 | u8 bCckHighPower; | |
| 1350 | long undecorated_smoothed_pwdb; | |
| 1351 | ||
| 1352 | //for set channel | |
| 1353 | u8 SwChnlInProgress; | |
| 1354 | u8 SwChnlStage; | |
| 1355 | u8 SwChnlStep; | |
| 1356 | u8 SetBWModeInProgress; | |
| 1357 | HT_CHANNEL_WIDTH CurrentChannelBW; | |
| 1358 | u8 ChannelPlan; | |
| 1359 | u8 pwrGroupCnt; | |
| 1360 | // 8190 40MHz mode | |
| 1361 | // | |
| 1362 | u8 nCur40MhzPrimeSC; // Control channel sub-carrier | |
| 1363 | // Joseph test for shorten RF configuration time. | |
| 1364 | // We save RF reg0 in this variable to reduce RF reading. | |
| 1365 | // | |
| 1366 | u32 RfReg0Value[4]; | |
| 1367 | u8 NumTotalRFPath; | |
| 1368 | bool brfpath_rxenable[4]; | |
| 1369 | //RF set related | |
| 1370 | bool SetRFPowerStateInProgress; | |
| 1371 | //+by amy 080507 | |
| 1372 | struct timer_list watch_dog_timer; | |
| 1373 | ||
| 1374 | //+by amy 080515 for dynamic mechenism | |
| 1375 | //Add by amy Tx Power Control for Near/Far Range 2008/05/15 | |
| 1376 | bool bdynamic_txpower; //bDynamicTxPower | |
| 1377 | bool bDynamicTxHighPower; // Tx high power state | |
| 1378 | bool bDynamicTxLowPower; // Tx low power state | |
| 1379 | bool bLastDTPFlag_High; | |
| 1380 | bool bLastDTPFlag_Low; | |
| 1381 | ||
| 1382 | bool bstore_last_dtpflag; | |
| 1383 | bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index | |
| 1384 | //Add by amy for Rate Adaptive | |
| 1385 | rate_adaptive rate_adaptive; | |
| 1386 | //Add by amy for TX power tracking | |
| 1387 | //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING | |
| 1388 | txbbgain_struct txbbgain_table[TxBBGainTableLength]; | |
| 1389 | u8 EEPROMTxPowerTrackEnable; | |
| 1390 | u8 txpower_count;//For 6 sec do tracking again | |
| 1391 | bool btxpower_trackingInit; | |
| 1392 | u8 OFDM_index; | |
| 1393 | u8 CCK_index; | |
| 1394 | //2007/09/10 Mars Add CCK TX Power Tracking | |
| 1395 | ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength]; | |
| 1396 | ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength]; | |
| 1397 | u8 rfa_txpowertrackingindex; | |
| 1398 | u8 rfa_txpowertrackingindex_real; | |
| 1399 | u8 rfa_txpowertracking_default; | |
| 1400 | u8 rfc_txpowertrackingindex; | |
| 1401 | u8 rfc_txpowertrackingindex_real; | |
| 1402 | ||
| 1403 | s8 cck_present_attentuation; | |
| 1404 | u8 cck_present_attentuation_20Mdefault; | |
| 1405 | u8 cck_present_attentuation_40Mdefault; | |
| 1406 | char cck_present_attentuation_difference; | |
| 1407 | bool btxpower_tracking; | |
| 1408 | bool bcck_in_ch14; | |
| 1409 | bool btxpowerdata_readfromEEPORM; | |
| 1410 | u16 TSSI_13dBm; | |
| 1411 | //For Backup Initial Gain | |
| 1412 | init_gain initgain_backup; | |
| 1413 | u8 DefaultInitialGain[4]; | |
| 1414 | // For EDCA Turbo mode, Added by amy 080515. | |
| 1415 | bool bis_any_nonbepkts; | |
| 1416 | bool bcurrent_turbo_EDCA; | |
| 1417 | bool bis_cur_rdlstate; | |
| 1418 | struct timer_list fsync_timer; | |
| 1419 | bool bfsync_processing; // 500ms Fsync timer is active or not | |
| 1420 | u32 rate_record; | |
| 1421 | u32 rateCountDiffRecord; | |
| 1422 | u32 ContiuneDiffCount; | |
| 1423 | bool bswitch_fsync; | |
| 1424 | ||
| 1425 | u8 framesync; | |
| 1426 | u32 framesyncC34; | |
| 1427 | u8 framesyncMonitor; | |
| 1428 | //Added by amy 080516 for RX related | |
| 1429 | u16 nrxAMPDU_size; | |
| 1430 | u8 nrxAMPDU_aggr_num; | |
| 1431 | ||
| 1432 | //by amy for gpio | |
| 1433 | bool bHwRadioOff; | |
| 1434 | ||
| 1435 | //by amy for reset_count | |
| 1436 | u32 reset_count; | |
| 1437 | bool bpbc_pressed; | |
| 1438 | //by amy for debug | |
| 1439 | u32 txpower_checkcnt; | |
| 1440 | u32 txpower_tracking_callback_cnt; | |
| 1441 | u8 thermal_read_val[40]; | |
| 1442 | u8 thermal_readback_index; | |
| 1443 | u32 ccktxpower_adjustcnt_not_ch14; | |
| 1444 | u32 ccktxpower_adjustcnt_ch14; | |
| 1445 | u8 tx_fwinfo_force_subcarriermode; | |
| 1446 | u8 tx_fwinfo_force_subcarrierval; | |
| 1447 | //by amy for silent reset | |
| 1448 | RESET_TYPE ResetProgress; | |
| 1449 | bool bForcedSilentReset; | |
| 1450 | bool bDisableNormalResetCheck; | |
| 1451 | u16 TxCounter; | |
| 1452 | u16 RxCounter; | |
| 1453 | int IrpPendingCount; | |
| 1454 | bool bResetInProgress; | |
| 1455 | bool force_reset; | |
| 1456 | u8 InitialGainOperateType; | |
| 1457 | ||
| 1458 | u16 SifsTime; | |
| 1459 | ||
| 1460 | //define work item by amy 080526 | |
| 5f53d8ca JC |
1461 | struct delayed_work update_beacon_wq; |
| 1462 | struct delayed_work watch_dog_wq; | |
| 1463 | struct delayed_work txpower_tracking_wq; | |
| 1464 | struct delayed_work rfpath_check_wq; | |
| 1465 | struct delayed_work gpio_change_rf_wq; | |
| 1466 | struct delayed_work initialgain_operate_wq; | |
| 1ec9e48d | 1467 | |
| 5f53d8ca | 1468 | struct workqueue_struct *priv_wq; |
| 5f53d8ca JC |
1469 | //#ifdef RTL8192SU |
| 1470 | //lzm add for 8192S | |
| 1471 | u32 IntrMask; | |
| 1472 | // RF and BB access related synchronization flags. | |
| 1473 | bool bChangeBBInProgress; // BaseBand RW is still in progress. | |
| 1474 | bool bChangeRFInProgress; // RF RW is still in progress. | |
| 1475 | ||
| 1476 | u32 CCKTxPowerAdjustCntCh14; //debug only | |
| 1477 | u32 CCKTxPowerAdjustCntNotCh14; //debug only | |
| 1478 | u32 TXPowerTrackingCallbackCnt; //debug only | |
| 1479 | u32 TxPowerCheckCnt; //debug only | |
| 1480 | u32 RFWritePageCnt[3]; //debug only | |
| 1481 | u32 RFReadPageCnt[3]; //debug only | |
| 1482 | u8 ThermalReadBackIndex; //debug only | |
| 1483 | u8 ThermalReadVal[40]; //debug only | |
| 1484 | ||
| 1485 | // For HCT test, 2005.07.15, by rcnjko. | |
| 1486 | // not realize true, just define it, set it 0 default, because some func use it | |
| 1487 | bool bInHctTest; | |
| 1488 | ||
| 1489 | // The current Tx Power Level | |
| 1490 | u8 CurrentCckTxPwrIdx; | |
| 1491 | u8 CurrentOfdm24GTxPwrIdx; | |
| 1492 | ||
| 1493 | // For pass 92S common phycfg.c compiler | |
| 1494 | u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14 | |
| 1495 | u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14 | |
| 1496 | u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14 | |
| 1497 | u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14 | |
| 1498 | u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff | |
| 1499 | char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a | |
| 1500 | ||
| 1501 | bool bRFSiOrPi;//0=si, 1=pi. | |
| 1502 | //lzm add for 8192S | |
| 1503 | ||
| 1504 | bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only | |
| 1505 | u8 CurrentFwCmdIO; | |
| 1506 | ||
| 1507 | u8 MinSpaceCfg; | |
| 1508 | ||
| 1509 | u16 rf_pathmap; | |
| 1510 | //#endif | |
| 1511 | ||
| 1512 | ||
| 5f53d8ca JC |
1513 | |
| 1514 | ||
| 1515 | ||
| 1516 | }r8192_priv; | |
| 1517 | ||
| 1518 | // for rtl8187 | |
| 1519 | // now mirging to rtl8187B | |
| 1520 | /* | |
| 1521 | typedef enum{ | |
| 1522 | LOW_PRIORITY = 0x02, | |
| 1523 | NORM_PRIORITY | |
| 1524 | } priority_t; | |
| 1525 | */ | |
| 1526 | //for rtl8187B | |
| 1527 | typedef enum{ | |
| 1528 | BULK_PRIORITY = 0x01, | |
| 1529 | //RSVD0, | |
| 1530 | //RSVD1, | |
| 1531 | LOW_PRIORITY, | |
| 1532 | NORM_PRIORITY, | |
| 1533 | VO_PRIORITY, | |
| 1534 | VI_PRIORITY, //0x05 | |
| 1535 | BE_PRIORITY, | |
| 1536 | BK_PRIORITY, | |
| 1537 | RSVD2, | |
| 1538 | RSVD3, | |
| 1539 | BEACON_PRIORITY, //0x0A | |
| 1540 | HIGH_PRIORITY, | |
| 1541 | MANAGE_PRIORITY, | |
| 1542 | RSVD4, | |
| 1543 | RSVD5, | |
| 1544 | UART_PRIORITY //0x0F | |
| 1545 | } priority_t; | |
| 1546 | ||
| 5f53d8ca JC |
1547 | #ifdef JOHN_HWSEC |
| 1548 | struct ssid_thread { | |
| 1549 | struct net_device *dev; | |
| 1550 | u8 name[IW_ESSID_MAX_SIZE + 1]; | |
| 1551 | }; | |
| 1552 | #endif | |
| 1553 | ||
| 5f53d8ca JC |
1554 | short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb); |
| 1555 | short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb); | |
| 1556 | bool FirmwareDownload92S(struct net_device *dev); | |
| 5f53d8ca JC |
1557 | |
| 1558 | short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb); | |
| 1559 | short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); | |
| 1560 | ||
| 1561 | u32 read_cam(struct net_device *dev, u8 addr); | |
| 1562 | void write_cam(struct net_device *dev, u8 addr, u32 data); | |
| 1563 | ||
| 1564 | u8 read_nic_byte(struct net_device *dev, int x); | |
| 1565 | u8 read_nic_byte_E(struct net_device *dev, int x); | |
| 1566 | u32 read_nic_dword(struct net_device *dev, int x); | |
| 1567 | u16 read_nic_word(struct net_device *dev, int x) ; | |
| 1568 | void write_nic_byte(struct net_device *dev, int x,u8 y); | |
| 1569 | void write_nic_byte_E(struct net_device *dev, int x,u8 y); | |
| 1570 | void write_nic_word(struct net_device *dev, int x,u16 y); | |
| 1571 | void write_nic_dword(struct net_device *dev, int x,u32 y); | |
| 1572 | void force_pci_posting(struct net_device *dev); | |
| 1573 | ||
| 1574 | void rtl8192_rtx_disable(struct net_device *); | |
| 1575 | void rtl8192_rx_enable(struct net_device *); | |
| 1576 | void rtl8192_tx_enable(struct net_device *); | |
| 1577 | ||
| 1578 | void rtl8192_disassociate(struct net_device *dev); | |
| 1579 | //void fix_rx_fifo(struct net_device *dev); | |
| 1580 | void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a); | |
| 1581 | ||
| 1582 | void rtl8192_set_anaparam(struct net_device *dev,u32 a); | |
| 1583 | void rtl8185_set_anaparam2(struct net_device *dev,u32 a); | |
| 1584 | void rtl8192_update_msr(struct net_device *dev); | |
| 1585 | int rtl8192_down(struct net_device *dev); | |
| 1586 | int rtl8192_up(struct net_device *dev); | |
| 1587 | void rtl8192_commit(struct net_device *dev); | |
| 1588 | void rtl8192_set_chan(struct net_device *dev,short ch); | |
| 1589 | void write_phy(struct net_device *dev, u8 adr, u8 data); | |
| 1590 | void write_phy_cck(struct net_device *dev, u8 adr, u32 data); | |
| 1591 | void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data); | |
| 1592 | void rtl8185_tx_antenna(struct net_device *dev, u8 ant); | |
| 1593 | void rtl8192_set_rxconf(struct net_device *dev); | |
| 1594 | //short check_nic_enough_desc(struct net_device *dev, priority_t priority); | |
| 1595 | extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate); | |
| 1596 | void CamResetAllEntry(struct net_device* dev); | |
| 1597 | void EnableHWSecurityConfig8192(struct net_device *dev); | |
| 1598 | void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent ); | |
| 1599 | short rtl8192_is_tx_queue_empty(struct net_device *dev); | |
| 1600 | ||
| 1601 | #endif |