[net-next-2.6.git] / drivers / staging / rt3090 / chips / rt30xx.c

/*
 *************************************************************************
 * Ralink Tech Inc.
 * 5F., No.36, Taiyuan St., Jhubei City,
 * Hsinchu County 302,
 * Taiwan, R.O.C.
 *
 * (c) Copyright 2002-2007, Ralink Technology, Inc.
 *
 * This program is free software; you can redistribute it and/or modify  *
 * it under the terms of the GNU General Public License as published by  *
 * the Free Software Foundation; either version 2 of the License, or     *
 * (at your option) any later version.                                   *
 *                                                                       *
 * This program is distributed in the hope that it will be useful,       *
 * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 * GNU General Public License for more details.                          *
 *                                                                       *
 * You should have received a copy of the GNU General Public License     *
 * along with this program; if not, write to the                         *
 * Free Software Foundation, Inc.,                                       *
 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 *                                                                       *
 *************************************************************************

	Module Name:
	rt30xx.c

	Abstract:
	Specific funcitons and variables for RT30xx.

	Revision History:
	Who         When          What
	--------    ----------    ----------------------------------------------
*/


#ifdef RT30xx


#ifndef RTMP_RF_RW_SUPPORT
#error "You Should Enable compile flag RTMP_RF_RW_SUPPORT for this chip"
#endif // RTMP_RF_RW_SUPPORT //

#include "../rt_config.h"


//
// RF register initialization set
//
REG_PAIR   RT30xx_RFRegTable[] = {
        {RF_R04,          0x40},
        {RF_R05,          0x03},
        {RF_R06,          0x02},
        {RF_R07,          0x70},
        {RF_R09,          0x0F},
        {RF_R10,          0x41},
        {RF_R11,          0x21},
        {RF_R12,          0x7B},
        {RF_R14,          0x90},
        {RF_R15,          0x58},
        {RF_R16,          0xB3},
        {RF_R17,          0x92},
        {RF_R18,          0x2C},
        {RF_R19,          0x02},
        {RF_R20,          0xBA},
        {RF_R21,          0xDB},
        {RF_R24,          0x16},
        {RF_R25,          0x01},
        {RF_R29,          0x1F},
};

UCHAR NUM_RF_REG_PARMS = (sizeof(RT30xx_RFRegTable) / sizeof(REG_PAIR));


// Antenna divesity use GPIO3 and EESK pin for control
// Antenna and EEPROM access are both using EESK pin,
// Therefor we should avoid accessing EESK at the same time
// Then restore antenna after EEPROM access
// The original name of this function is AsicSetRxAnt(), now change to
//VOID AsicSetRxAnt(
VOID RT30xxSetRxAnt(
	IN PRTMP_ADAPTER	pAd,
	IN UCHAR			Ant)
{
	UINT32	Value;
	UINT32	x;

	if ((pAd->EepromAccess) ||
		(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS))	||
		(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))	||
		(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) ||
		(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
	{
		return;
	}

	// the antenna selection is through firmware and MAC register(GPIO3)
	if (Ant == 0)
	{
		// Main antenna
#ifdef RTMP_MAC_PCI
		RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
		x |= (EESK);
		RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
#else
		AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x1, 0x0);
#endif // RTMP_MAC_PCI //

		RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
		Value &= ~(0x0808);
		RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
		DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to main antenna\n"));
	}
	else
	{
		// Aux antenna
#ifdef RTMP_MAC_PCI
		RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
		x &= ~(EESK);
		RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
#else
		AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x0, 0x0);
#endif // RTMP_MAC_PCI //
		RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
		Value &= ~(0x0808);
		Value |= 0x08;
		RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
		DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to aux antenna\n"));
	}
}


/*
	========================================================================

	Routine Description:
		For RF filter calibration purpose

	Arguments:
		pAd                          Pointer to our adapter

	Return Value:
		None

	IRQL = PASSIVE_LEVEL

	========================================================================
*/
VOID RTMPFilterCalibration(
	IN PRTMP_ADAPTER pAd)
{
	UCHAR	R55x = 0, value, FilterTarget = 0x1E, BBPValue=0;
	UINT	loop = 0, count = 0, loopcnt = 0, ReTry = 0;
	UCHAR	RF_R24_Value = 0;

	// Give bbp filter initial value
	pAd->Mlme.CaliBW20RfR24 = 0x1F;
	pAd->Mlme.CaliBW40RfR24 = 0x2F; //Bit[5] must be 1 for BW 40

	do
	{
		if (loop == 1)	//BandWidth = 40 MHz
		{
			// Write 0x27 to RF_R24 to program filter
			RF_R24_Value = 0x27;
			RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
			if (IS_RT3090(pAd) || IS_RT3572(pAd)|| IS_RT3390(pAd))
				FilterTarget = 0x15;
			else
				FilterTarget = 0x19;

			// when calibrate BW40, BBP mask must set to BW40.
			RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
			BBPValue&= (~0x18);
			BBPValue|= (0x10);
			RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);

			// set to BW40
			RT30xxReadRFRegister(pAd, RF_R31, &value);
			value |= 0x20;
			RT30xxWriteRFRegister(pAd, RF_R31, value);
		}
		else			//BandWidth = 20 MHz
		{
			// Write 0x07 to RF_R24 to program filter
			RF_R24_Value = 0x07;
			RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
			if (IS_RT3090(pAd) || IS_RT3572(pAd)|| IS_RT3390(pAd))
				FilterTarget = 0x13;
			else
				FilterTarget = 0x16;

			// set to BW20
			RT30xxReadRFRegister(pAd, RF_R31, &value);
			value &= (~0x20);
			RT30xxWriteRFRegister(pAd, RF_R31, value);
		}

		// Write 0x01 to RF_R22 to enable baseband loopback mode
		RT30xxReadRFRegister(pAd, RF_R22, &value);
		value |= 0x01;
		RT30xxWriteRFRegister(pAd, RF_R22, value);

		// Write 0x00 to BBP_R24 to set power & frequency of passband test tone
		RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);

		do
		{
			// Write 0x90 to BBP_R25 to transmit test tone
			RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);

			RTMPusecDelay(1000);
			// Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0]
			RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
			R55x = value & 0xFF;

		} while ((ReTry++ < 100) && (R55x == 0));

		// Write 0x06 to BBP_R24 to set power & frequency of stopband test tone
		RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06);

		while(TRUE)
		{
			// Write 0x90 to BBP_R25 to transmit test tone
			RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);

			//We need to wait for calibration
			RTMPusecDelay(1000);
			RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
			value &= 0xFF;
			if ((R55x - value) < FilterTarget)
			{
				RF_R24_Value ++;
			}
			else if ((R55x - value) == FilterTarget)
			{
				RF_R24_Value ++;
				count ++;
			}
			else
			{
				break;
			}

			// prevent infinite loop cause driver hang.
			if (loopcnt++ > 100)
			{
				DBGPRINT(RT_DEBUG_ERROR, ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt));
				break;
			}

			// Write RF_R24 to program filter
			RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
		}

		if (count > 0)
		{
			RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
		}

		// Store for future usage
		if (loopcnt < 100)
		{
			if (loop++ == 0)
			{
				//BandWidth = 20 MHz
				pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value;
			}
			else
			{
				//BandWidth = 40 MHz
				pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value;
				break;
			}
		}
		else
			break;

		RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);

		// reset count
		count = 0;
	} while(TRUE);

	//
	// Set back to initial state
	//
	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);

	RT30xxReadRFRegister(pAd, RF_R22, &value);
	value &= ~(0x01);
	RT30xxWriteRFRegister(pAd, RF_R22, value);

	// set BBP back to BW20
	RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
	BBPValue&= (~0x18);
	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);

	DBGPRINT(RT_DEBUG_TRACE, ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
}


// add by johnli, RF power sequence setup
/*
	==========================================================================
	Description:

	Load RF normal operation-mode setup

	==========================================================================
 */
VOID RT30xxLoadRFNormalModeSetup(
	IN PRTMP_ADAPTER	pAd)
{
	UCHAR RFValue;

	// RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1
	RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
	RFValue = (RFValue & (~0x0C)) | 0x31;
	RT30xxWriteRFRegister(pAd, RF_R01, RFValue);

	// TX_LO2_en, RF R15 register Bit 3 to 0
	RT30xxReadRFRegister(pAd, RF_R15, &RFValue);
	RFValue &= (~0x08);
	RT30xxWriteRFRegister(pAd, RF_R15, RFValue);

	/* move to NICInitRT30xxRFRegisters
	// TX_LO1_en, RF R17 register Bit 3 to 0
	RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
	RFValue &= (~0x08);
	// to fix rx long range issue
	if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0))
	{
		RFValue |= 0x20;
	}
	// set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h
	if (pAd->TxMixerGain24G >= 2)
	{
		RFValue &= (~0x7);  // clean bit [2:0]
		RFValue |= pAd->TxMixerGain24G;
	}
	RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
	*/

	// RX_LO1_en, RF R20 register Bit 3 to 0
	RT30xxReadRFRegister(pAd, RF_R20, &RFValue);
	RFValue &= (~0x08);
	RT30xxWriteRFRegister(pAd, RF_R20, RFValue);

	// RX_LO2_en, RF R21 register Bit 3 to 0
	RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
	RFValue &= (~0x08);
	RT30xxWriteRFRegister(pAd, RF_R21, RFValue);

	/* add by johnli, reset RF_R27 when interface down & up to fix throughput problem*/
	// LDORF_VC, RF R27 register Bit 2 to 0
	RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
	// TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F).
	// Raising RF voltage is no longer needed for RT3070(F)
	if (IS_RT3090(pAd))	// RT309x and RT3071/72
	{
		if ((pAd->MACVersion & 0xffff) < 0x0211)
			RFValue = (RFValue & (~0x77)) | 0x3;
		else
			RFValue = (RFValue & (~0x77));
		RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
	}
	/* end johnli */
}

/*
	==========================================================================
	Description:

	Load RF sleep-mode setup

	==========================================================================
 */
VOID RT30xxLoadRFSleepModeSetup(
	IN PRTMP_ADAPTER	pAd)
{
	UCHAR RFValue;
	UINT32 MACValue;


	{
		// RF_BLOCK_en. RF R1 register Bit 0 to 0
		RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
		RFValue &= (~0x01);
		RT30xxWriteRFRegister(pAd, RF_R01, RFValue);

		// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
		RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
		RFValue &= (~0x30);
		RT30xxWriteRFRegister(pAd, RF_R07, RFValue);

		// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
		RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
		RFValue &= (~0x0E);
		RT30xxWriteRFRegister(pAd, RF_R09, RFValue);

		// RX_CTB_en, RF R21 register Bit 7 to 0
		RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
		RFValue &= (~0x80);
		RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
	}

	if (IS_RT3090(pAd) ||	// IS_RT3090 including RT309x and RT3071/72
		IS_RT3572(pAd) ||
		(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
	{
		{
			RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
			RFValue |= 0x77;
			RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
		}

		RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
		MACValue |= 0x1D000000;
		RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
	}
}

/*
	==========================================================================
	Description:

	Reverse RF sleep-mode setup

	==========================================================================
 */
VOID RT30xxReverseRFSleepModeSetup(
	IN PRTMP_ADAPTER	pAd)
{
	UCHAR RFValue;
	UINT32 MACValue;

	{
		// RF_BLOCK_en, RF R1 register Bit 0 to 1
		RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
		RFValue |= 0x01;
		RT30xxWriteRFRegister(pAd, RF_R01, RFValue);

		// VCO_IC, RF R7 register Bit 4 & Bit 5 to 1
		RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
		RFValue |= 0x30;
		RT30xxWriteRFRegister(pAd, RF_R07, RFValue);

		// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1
		RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
		RFValue |= 0x0E;
		RT30xxWriteRFRegister(pAd, RF_R09, RFValue);

		// RX_CTB_en, RF R21 register Bit 7 to 1
		RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
		RFValue |= 0x80;
		RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
	}

	if (IS_RT3090(pAd) ||	// IS_RT3090 including RT309x and RT3071/72
		IS_RT3572(pAd) ||
		IS_RT3390(pAd) ||
		(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
	{
		{
			RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
			if ((pAd->MACVersion & 0xffff) < 0x0211)
				RFValue = (RFValue & (~0x77)) | 0x3;
			else
				RFValue = (RFValue & (~0x77));
			RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
		}

		// RT3071 version E has fixed this issue
		if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
		{
			// patch tx EVM issue temporarily
			RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
			MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
			RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
		}
		else
		{
			RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
			MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
			RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
		}
	}

	if(IS_RT3572(pAd))
		RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
}
// end johnli

VOID RT30xxHaltAction(
	IN PRTMP_ADAPTER	pAd)
{
	UINT32		TxPinCfg = 0x00050F0F;

	//
	// Turn off LNA_PE or TRSW_POL
	//
	if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd))
	{
		if ((IS_RT3071(pAd) || IS_RT3572(pAd))
#ifdef RTMP_EFUSE_SUPPORT
			&& (pAd->bUseEfuse)
#endif // RTMP_EFUSE_SUPPORT //
			)
		{
			TxPinCfg &= 0xFFFBF0F0; // bit18 off
		}
		else
		{
			TxPinCfg &= 0xFFFFF0F0;
		}

		RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
	}
}

#endif // RT30xx //
Commit	Line	Data
36c7928c BZ	1	/*
	2	*************************************************************************
	3	* Ralink Tech Inc.
	4	* 5F., No.36, Taiyuan St., Jhubei City,
	5	* Hsinchu County 302,
	6	* Taiwan, R.O.C.
	7	*
	8	* (c) Copyright 2002-2007, Ralink Technology, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify *
	11	* it under the terms of the GNU General Public License as published by *
	12	* the Free Software Foundation; either version 2 of the License, or *
	13	* (at your option) any later version. *
	14	* *
	15	* This program is distributed in the hope that it will be useful, *
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	18	* GNU General Public License for more details. *
	19	* *
	20	* You should have received a copy of the GNU General Public License *
	21	* along with this program; if not, write to the *
	22	* Free Software Foundation, Inc., *
	23	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
	24	* *
	25	*************************************************************************
	26
	27	Module Name:
	28	rt30xx.c
	29
	30	Abstract:
	31	Specific funcitons and variables for RT30xx.
	32
	33	Revision History:
	34	Who When What
	35	-------- ---------- ----------------------------------------------
	36	*/
	37
	38
	39	#ifdef RT30xx
	40
	41
	42	#ifndef RTMP_RF_RW_SUPPORT
	43	#error "You Should Enable compile flag RTMP_RF_RW_SUPPORT for this chip"
	44	#endif // RTMP_RF_RW_SUPPORT //
	45
	46	#include "../rt_config.h"
	47
	48
	49	//
	50	// RF register initialization set
	51	//
	52	REG_PAIR RT30xx_RFRegTable[] = {
	53	{RF_R04, 0x40},
	54	{RF_R05, 0x03},
	55	{RF_R06, 0x02},
	56	{RF_R07, 0x70},
	57	{RF_R09, 0x0F},
	58	{RF_R10, 0x41},
	59	{RF_R11, 0x21},
	60	{RF_R12, 0x7B},
	61	{RF_R14, 0x90},
	62	{RF_R15, 0x58},
	63	{RF_R16, 0xB3},
	64	{RF_R17, 0x92},
65	{RF_R18, 0x2C},
66	{RF_R19, 0x02},
67	{RF_R20, 0xBA},
68	{RF_R21, 0xDB},
69	{RF_R24, 0x16},
70	{RF_R25, 0x01},
71	{RF_R29, 0x1F},
72	};
73
74	UCHAR NUM_RF_REG_PARMS = (sizeof(RT30xx_RFRegTable) / sizeof(REG_PAIR));
75
76
77
78	// Antenna divesity use GPIO3 and EESK pin for control
79	// Antenna and EEPROM access are both using EESK pin,
80	// Therefor we should avoid accessing EESK at the same time
81	// Then restore antenna after EEPROM access
82	// The original name of this function is AsicSetRxAnt(), now change to
83	//VOID AsicSetRxAnt(
84	VOID RT30xxSetRxAnt(
85	IN PRTMP_ADAPTER pAd,
86	IN UCHAR Ant)
87	{
88	UINT32 Value;
89	UINT32 x;
90
91	if ((pAd->EepromAccess) \|\|
92	(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) \|\|
93	(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) \|\|
94	(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) \|\|
95	(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
96	{
97	return;
98	}
99
100	// the antenna selection is through firmware and MAC register(GPIO3)
101	if (Ant == 0)
102	{
103	// Main antenna
104	#ifdef RTMP_MAC_PCI
105	RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
106	x \|= (EESK);
107	RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
108	#else
109	AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x1, 0x0);
110	#endif // RTMP_MAC_PCI //
111
112	RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
113	Value &= ~(0x0808);
114	RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
115	DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to main antenna\n"));
116	}
117	else
118	{
119	// Aux antenna
120	#ifdef RTMP_MAC_PCI
121	RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
122	x &= ~(EESK);
123	RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
124	#else
125	AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x0, 0x0);
126	#endif // RTMP_MAC_PCI //
127	RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
128	Value &= ~(0x0808);
129	Value \|= 0x08;
130	RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
131	DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to aux antenna\n"));
132	}
133	}
134
135
136	/*
137	========================================================================
138
139	Routine Description:
140	For RF filter calibration purpose
141
142	Arguments:
143	pAd Pointer to our adapter
144
145	Return Value:
146	None
147
148	IRQL = PASSIVE_LEVEL
149
150	========================================================================
151	*/
152	VOID RTMPFilterCalibration(
153	IN PRTMP_ADAPTER pAd)
154	{
155	UCHAR R55x = 0, value, FilterTarget = 0x1E, BBPValue=0;
156	UINT loop = 0, count = 0, loopcnt = 0, ReTry = 0;
157	UCHAR RF_R24_Value = 0;
158
159	// Give bbp filter initial value
160	pAd->Mlme.CaliBW20RfR24 = 0x1F;
161	pAd->Mlme.CaliBW40RfR24 = 0x2F; //Bit[5] must be 1 for BW 40
162
163	do
164	{
165	if (loop == 1) //BandWidth = 40 MHz
166	{
167	// Write 0x27 to RF_R24 to program filter
168	RF_R24_Value = 0x27;
169	RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
170	if (IS_RT3090(pAd) \|\| IS_RT3572(pAd)\|\| IS_RT3390(pAd))
171	FilterTarget = 0x15;
172	else
173	FilterTarget = 0x19;
174
175	// when calibrate BW40, BBP mask must set to BW40.
176	RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
177	BBPValue&= (~0x18);
178	BBPValue\|= (0x10);
179	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
180
181	// set to BW40
182	RT30xxReadRFRegister(pAd, RF_R31, &value);
183	value \|= 0x20;
184	RT30xxWriteRFRegister(pAd, RF_R31, value);
185	}
186	else //BandWidth = 20 MHz
187	{
188	// Write 0x07 to RF_R24 to program filter
189	RF_R24_Value = 0x07;
190	RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
191	if (IS_RT3090(pAd) \|\| IS_RT3572(pAd)\|\| IS_RT3390(pAd))
192	FilterTarget = 0x13;
193	else
194	FilterTarget = 0x16;
195
196	// set to BW20
197	RT30xxReadRFRegister(pAd, RF_R31, &value);
198	value &= (~0x20);
199	RT30xxWriteRFRegister(pAd, RF_R31, value);
200	}
201
202	// Write 0x01 to RF_R22 to enable baseband loopback mode
203	RT30xxReadRFRegister(pAd, RF_R22, &value);
204	value \|= 0x01;
205	RT30xxWriteRFRegister(pAd, RF_R22, value);
206
207	// Write 0x00 to BBP_R24 to set power & frequency of passband test tone
208	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
209
210	do
211	{
212	// Write 0x90 to BBP_R25 to transmit test tone
213	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
214
215	RTMPusecDelay(1000);
216	// Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0]
217	RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
218	R55x = value & 0xFF;
219
220	} while ((ReTry++ < 100) && (R55x == 0));
221
222	// Write 0x06 to BBP_R24 to set power & frequency of stopband test tone
223	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06);
224
225	while(TRUE)
226	{
227	// Write 0x90 to BBP_R25 to transmit test tone
228	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
229
230	//We need to wait for calibration
231	RTMPusecDelay(1000);
232	RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
233	value &= 0xFF;
234	if ((R55x - value) < FilterTarget)
235	{
236	RF_R24_Value ++;
237	}
238	else if ((R55x - value) == FilterTarget)
239	{
240	RF_R24_Value ++;
241	count ++;
242	}
243	else
244	{
245	break;
246	}
247
248	// prevent infinite loop cause driver hang.
249	if (loopcnt++ > 100)
250	{
251	DBGPRINT(RT_DEBUG_ERROR, ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt));
252	break;
253	}
254
255	// Write RF_R24 to program filter
256	RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
257	}
258
259	if (count > 0)
260	{
261	RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
262	}
263
264	// Store for future usage
265	if (loopcnt < 100)
266	{
267	if (loop++ == 0)
268	{
269	//BandWidth = 20 MHz
270	pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value;
271	}
272	else
273	{
274	//BandWidth = 40 MHz
275	pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value;
276	break;
277	}
278	}
279	else
280	break;
281
282	RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
283
284	// reset count
285	count = 0;
286	} while(TRUE);
287
288	//
289	// Set back to initial state
290	//
291	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
292
293	RT30xxReadRFRegister(pAd, RF_R22, &value);
294	value &= ~(0x01);
295	RT30xxWriteRFRegister(pAd, RF_R22, value);
296
297	// set BBP back to BW20
298	RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
299	BBPValue&= (~0x18);
300	RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
301
302	DBGPRINT(RT_DEBUG_TRACE, ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
303	}
304
305
306	// add by johnli, RF power sequence setup
307	/*
308	==========================================================================
309	Description:
310
311	Load RF normal operation-mode setup
312
313	==========================================================================
314	*/
315	VOID RT30xxLoadRFNormalModeSetup(
316	IN PRTMP_ADAPTER pAd)
317	{
318	UCHAR RFValue;
319
320	// RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1
321	RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
322	RFValue = (RFValue & (~0x0C)) \| 0x31;
323	RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
324
325	// TX_LO2_en, RF R15 register Bit 3 to 0
326	RT30xxReadRFRegister(pAd, RF_R15, &RFValue);
327	RFValue &= (~0x08);
328	RT30xxWriteRFRegister(pAd, RF_R15, RFValue);
329
330	/* move to NICInitRT30xxRFRegisters
331	// TX_LO1_en, RF R17 register Bit 3 to 0
332	RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
333	RFValue &= (~0x08);
334	// to fix rx long range issue
335	if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0))
336	{
337	RFValue \|= 0x20;
338	}
339	// set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h
340	if (pAd->TxMixerGain24G >= 2)
341	{
342	RFValue &= (~0x7); // clean bit [2:0]
343	RFValue \|= pAd->TxMixerGain24G;
344	}
345	RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
346	*/
347
348	// RX_LO1_en, RF R20 register Bit 3 to 0
349	RT30xxReadRFRegister(pAd, RF_R20, &RFValue);
350	RFValue &= (~0x08);
351	RT30xxWriteRFRegister(pAd, RF_R20, RFValue);
352
353	// RX_LO2_en, RF R21 register Bit 3 to 0
354	RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
355	RFValue &= (~0x08);
356	RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
357
358	/* add by johnli, reset RF_R27 when interface down & up to fix throughput problem*/
359	// LDORF_VC, RF R27 register Bit 2 to 0
360	RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
361	// TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F).
362	// Raising RF voltage is no longer needed for RT3070(F)
363	if (IS_RT3090(pAd)) // RT309x and RT3071/72
364	{
365	if ((pAd->MACVersion & 0xffff) < 0x0211)
366	RFValue = (RFValue & (~0x77)) \| 0x3;
367	else
368	RFValue = (RFValue & (~0x77));
369	RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
370	}
371	/* end johnli */
372	}
373
374	/*
375	==========================================================================
376	Description:
377
378	Load RF sleep-mode setup
379
380	==========================================================================
381	*/
382	VOID RT30xxLoadRFSleepModeSetup(
383	IN PRTMP_ADAPTER pAd)
384	{
385	UCHAR RFValue;
386	UINT32 MACValue;
387
388
389	{
390	// RF_BLOCK_en. RF R1 register Bit 0 to 0
391	RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
392	RFValue &= (~0x01);
393	RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
394
395	// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
396	RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
397	RFValue &= (~0x30);
398	RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
399
400	// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
401	RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
402	RFValue &= (~0x0E);
403	RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
404
405	// RX_CTB_en, RF R21 register Bit 7 to 0
406	RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
407	RFValue &= (~0x80);
408	RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
409	}
410
411	if (IS_RT3090(pAd) \|\| // IS_RT3090 including RT309x and RT3071/72
412	IS_RT3572(pAd) \|\|
413	(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
414	{
415	{
416	RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
417	RFValue \|= 0x77;
418	RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
419	}
420
421	RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
422	MACValue \|= 0x1D000000;
423	RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
424	}
425	}
426
427	/*
428	==========================================================================
429	Description:
430
431	Reverse RF sleep-mode setup
432
433	==========================================================================
434	*/
435	VOID RT30xxReverseRFSleepModeSetup(
436	IN PRTMP_ADAPTER pAd)
437	{
438	UCHAR RFValue;
439	UINT32 MACValue;
440
441	{
442	// RF_BLOCK_en, RF R1 register Bit 0 to 1
443	RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
444	RFValue \|= 0x01;
445	RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
446
447	// VCO_IC, RF R7 register Bit 4 & Bit 5 to 1
448	RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
449	RFValue \|= 0x30;
450	RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
451
452	// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1
453	RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
454	RFValue \|= 0x0E;
455	RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
456
457	// RX_CTB_en, RF R21 register Bit 7 to 1
458	RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
459	RFValue \|= 0x80;
460	RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
461	}
462
463	if (IS_RT3090(pAd) \|\| // IS_RT3090 including RT309x and RT3071/72
464	IS_RT3572(pAd) \|\|
465	IS_RT3390(pAd) \|\|
466	(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
467	{
468	{
469	RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
470	if ((pAd->MACVersion & 0xffff) < 0x0211)
471	RFValue = (RFValue & (~0x77)) \| 0x3;
472	else
473	RFValue = (RFValue & (~0x77));
474	RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
475	}
476
477	// RT3071 version E has fixed this issue
478	if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
479	{
480	// patch tx EVM issue temporarily
481	RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
482	MACValue = ((MACValue & 0xE0FFFFFF) \| 0x0D000000);
483	RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
484	}
485	else
486	{
487	RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
488	MACValue = ((MACValue & 0xE0FFFFFF) \| 0x01000000);
489	RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
490	}
491	}
492
493	if(IS_RT3572(pAd))
494	RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
495	}
496	// end johnli
497
498	VOID RT30xxHaltAction(
499	IN PRTMP_ADAPTER pAd)
500	{
501	UINT32 TxPinCfg = 0x00050F0F;
502
503	//
504	// Turn off LNA_PE or TRSW_POL
505	//
506	if (IS_RT3070(pAd) \|\| IS_RT3071(pAd) \|\| IS_RT3572(pAd))
507	{
508	if ((IS_RT3071(pAd) \|\| IS_RT3572(pAd))
509	#ifdef RTMP_EFUSE_SUPPORT
510	&& (pAd->bUseEfuse)
511	#endif // RTMP_EFUSE_SUPPORT //
512	)
513	{
514	TxPinCfg &= 0xFFFBF0F0; // bit18 off
515	}
516	else
517	{
518	TxPinCfg &= 0xFFFFF0F0;
519	}
520
521	RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
522	}
523	}
524
525	#endif // RT30xx //