[net-next-2.6.git] / drivers / staging / rt2860 / rtmp_chip.h

/*
 *************************************************************************
 * Ralink Tech Inc.
 * 5F., No.36, Taiyuan St., Jhubei City,
 * Hsinchu County 302,
 * Taiwan, R.O.C.
 *
 * (c) Copyright 2002-2007, Ralink Technology, Inc.
 *
 * This program is free software; you can redistribute it and/or modify  *
 * it under the terms of the GNU General Public License as published by  *
 * the Free Software Foundation; either version 2 of the License, or     *
 * (at your option) any later version.                                   *
 *                                                                       *
 * This program is distributed in the hope that it will be useful,       *
 * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 * GNU General Public License for more details.                          *
 *                                                                       *
 * You should have received a copy of the GNU General Public License     *
 * along with this program; if not, write to the                         *
 * Free Software Foundation, Inc.,                                       *
 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 *                                                                       *
 *************************************************************************

	Module Name:
	rtmp_chip.h

	Abstract:
	Ralink Wireless Chip related definition & structures

	Revision History:
	Who			When		  What
	--------	----------	  ----------------------------------------------
*/

#ifndef	__RTMP_CHIP_H__
#define	__RTMP_CHIP_H__

#include "rtmp_type.h"

#ifdef RT2860
#include "chip/rt2860.h"
#endif // RT2860 //
#ifdef RT2870
#include "chip/rt2870.h"
#endif // RT2870 //
#ifdef RT3070
#include "chip/rt3070.h"
#endif // RT3070 //
#ifdef RT3090
#include "chip/rt3090.h"
#endif // RT3090 //

// We will have a cost down version which mac version is 0x3090xxxx
//
// RT3090A facts
//
// a) 2.4 GHz
// b) Replacement for RT3090
// c) Internal LNA
// d) Interference over channel #14
// e) New BBP features (e.g., SIG re-modulation)
//
#define IS_RT3090A(_pAd)				((((_pAd)->MACVersion & 0xffff0000) == 0x30900000))

// We will have a cost down version which mac version is 0x3090xxxx
#define IS_RT3090(_pAd)				((((_pAd)->MACVersion & 0xffff0000) == 0x30710000) || (IS_RT3090A(_pAd)))

#define IS_RT3070(_pAd)		(((_pAd)->MACVersion & 0xffff0000) == 0x30700000)
#define IS_RT3071(_pAd)		(((_pAd)->MACVersion & 0xffff0000) == 0x30710000)
#define IS_RT2070(_pAd)		(((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27))

#define IS_RT30xx(_pAd)		(((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd))
//#define IS_RT305X(_pAd)               ((_pAd)->MACVersion == 0x28720200)

/* RT3572, 3592, 3562, 3062 share the same MAC version */
#define IS_RT3572(_pAd)		(((_pAd)->MACVersion & 0xffff0000) == 0x35720000)
#define IS_VERSION_BEFORE_F(_pAd)			(((_pAd)->MACVersion&0xffff) <= 0x0211)
// F version is 0x0212, E version is 0x0211. 309x can save more power after F version.
#define IS_VERSION_AFTER_F(_pAd)			((((_pAd)->MACVersion&0xffff) >= 0x0212) || (((_pAd)->b3090ESpecialChip == TRUE)))
//
// RT3390 facts
//
// a) Base on RT3090 (RF IC: RT3020)
// b) 2.4 GHz
// c) 1x1
// d) Single chip
// e) Internal components: PA and LNA
//
//RT3390,RT3370
#define IS_RT3390(_pAd)				(((_pAd)->MACVersion & 0xFFFF0000) == 0x33900000)

// ------------------------------------------------------
// PCI registers - base address 0x0000
// ------------------------------------------------------
#define CHIP_PCI_CFG		0x0000
#define CHIP_PCI_EECTRL		0x0004
#define CHIP_PCI_MCUCTRL	0x0008

#define OPT_14			0x114

#define RETRY_LIMIT		10

// ------------------------------------------------------
// BBP & RF     definition
// ------------------------------------------------------
#define	BUSY		                1
#define	IDLE		                0

//-------------------------------------------------------------------------
// EEPROM definition
//-------------------------------------------------------------------------
#define EEDO                        0x08
#define EEDI                        0x04
#define EECS                        0x02
#define EESK                        0x01
#define EERL                        0x80

#define EEPROM_WRITE_OPCODE         0x05
#define EEPROM_READ_OPCODE          0x06
#define EEPROM_EWDS_OPCODE          0x10
#define EEPROM_EWEN_OPCODE          0x13

#define NUM_EEPROM_BBP_PARMS		19	// Include NIC Config 0, 1, CR, TX ALC step, BBPs
#define NUM_EEPROM_TX_G_PARMS		7
#define EEPROM_NIC1_OFFSET          0x34	// The address is from NIC config 0, not BBP register ID
#define EEPROM_NIC2_OFFSET          0x36	// The address is from NIC config 0, not BBP register ID
#define EEPROM_BBP_BASE_OFFSET		0xf0	// The address is from NIC config 0, not BBP register ID
#define EEPROM_G_TX_PWR_OFFSET		0x52
#define EEPROM_G_TX2_PWR_OFFSET		0x60
#define EEPROM_LED1_OFFSET			0x3c
#define EEPROM_LED2_OFFSET			0x3e
#define EEPROM_LED3_OFFSET			0x40
#define EEPROM_LNA_OFFSET			0x44
#define EEPROM_RSSI_BG_OFFSET		0x46
#define EEPROM_TXMIXER_GAIN_2_4G	0x48
#define EEPROM_RSSI_A_OFFSET		0x4a
#define EEPROM_TXMIXER_GAIN_5G		0x4c
#define EEPROM_DEFINE_MAX_TXPWR		0x4e
#define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G	0xde	// 20MHZ 2.4G tx power.
#define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G	0xee	// 40MHZ 2.4G tx power.
#define EEPROM_TXPOWER_BYRATE_20MHZ_5G		0xfa	// 20MHZ 5G tx power.
#define EEPROM_TXPOWER_BYRATE_40MHZ_5G		0x10a	// 40MHZ 5G tx power.
#define EEPROM_A_TX_PWR_OFFSET      0x78
#define EEPROM_A_TX2_PWR_OFFSET      0xa6
//#define EEPROM_Japan_TX_PWR_OFFSET      0x90 // 802.11j
//#define EEPROM_Japan_TX2_PWR_OFFSET      0xbe
//#define EEPROM_TSSI_REF_OFFSET        0x54
//#define EEPROM_TSSI_DELTA_OFFSET      0x24
//#define EEPROM_CCK_TX_PWR_OFFSET  0x62
//#define EEPROM_CALIBRATE_OFFSET       0x7c
#define EEPROM_VERSION_OFFSET       0x02
#define EEPROM_FREQ_OFFSET			0x3a
#define EEPROM_TXPOWER_BYRATE	0xde	// 20MHZ power.
#define EEPROM_TXPOWER_DELTA		0x50	// 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
#define VALID_EEPROM_VERSION        1

/*
  *   EEPROM operation related marcos
  */
#define RT28xx_EEPROM_READ16(_pAd, _offset, _value)			\
	(_pAd)->chipOps.eeread((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (PUSHORT)&(_value))

// -------------------------------------------------------------------
//  E2PROM data layout
// -------------------------------------------------------------------

//
// MCU_LEDCS: MCU LED Control Setting.
//
typedef union _MCU_LEDCS_STRUC {
	struct {
		UCHAR LedMode:7;
		UCHAR Polarity:1;
	} field;
	UCHAR word;
} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;

//
// EEPROM antenna select format
//
typedef union _EEPROM_ANTENNA_STRUC {
	struct {
		USHORT RxPath:4;	// 1: 1R, 2: 2R, 3: 3R
		USHORT TxPath:4;	// 1: 1T, 2: 2T
		USHORT RfIcType:4;	// see E2PROM document
		USHORT Rsv:4;
	} field;
	USHORT word;
} EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;

typedef union _EEPROM_NIC_CINFIG2_STRUC {
	struct {
		USHORT HardwareRadioControl:1;	// 1:enable, 0:disable
		USHORT DynamicTxAgcControl:1;	//
		USHORT ExternalLNAForG:1;	//
		USHORT ExternalLNAForA:1;	// external LNA enable for 2.4G
		USHORT CardbusAcceleration:1;	// !!! NOTE: 0 - enable, 1 - disable
		USHORT BW40MSidebandForG:1;
		USHORT BW40MSidebandForA:1;
		USHORT EnableWPSPBC:1;	// WPS PBC Control bit
		USHORT BW40MAvailForG:1;	// 0:enable, 1:disable
		USHORT BW40MAvailForA:1;	// 0:enable, 1:disable
		USHORT Rsv1:1;	// must be 0
		USHORT AntDiversity:1;	// Antenna diversity
		USHORT Rsv2:3;	// must be 0
		USHORT DACTestBit:1;	// control if driver should patch the DAC issue
	} field;
	USHORT word;
} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;

//
// TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
//
typedef union _EEPROM_TX_PWR_STRUC {
	struct {
		CHAR Byte0;	// Low Byte
		CHAR Byte1;	// High Byte
	} field;
	USHORT word;
} EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;

typedef union _EEPROM_VERSION_STRUC {
	struct {
		UCHAR FaeReleaseNumber;	// Low Byte
		UCHAR Version;	// High Byte
	} field;
	USHORT word;
} EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;

typedef union _EEPROM_LED_STRUC {
	struct {
		USHORT PolarityRDY_G:1;	// Polarity RDY_G setting.
		USHORT PolarityRDY_A:1;	// Polarity RDY_A setting.
		USHORT PolarityACT:1;	// Polarity ACT setting.
		USHORT PolarityGPIO_0:1;	// Polarity GPIO#0 setting.
		USHORT PolarityGPIO_1:1;	// Polarity GPIO#1 setting.
		USHORT PolarityGPIO_2:1;	// Polarity GPIO#2 setting.
		USHORT PolarityGPIO_3:1;	// Polarity GPIO#3 setting.
		USHORT PolarityGPIO_4:1;	// Polarity GPIO#4 setting.
		USHORT LedMode:5;	// Led mode.
		USHORT Rsvd:3;	// Reserved
	} field;
	USHORT word;
} EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;

typedef union _EEPROM_TXPOWER_DELTA_STRUC {
	struct {
		UCHAR DeltaValue:6;	// Tx Power dalta value (MAX=4)
		UCHAR Type:1;	// 1: plus the delta value, 0: minus the delta value
		UCHAR TxPowerEnable:1;	// Enable
	} field;
	UCHAR value;
} EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;

#endif // __RTMP_CHIP_H__ //
Commit	Line	Data
ca97b838 BZ	1	/*
	2	*************************************************************************
	3	* Ralink Tech Inc.
	4	* 5F., No.36, Taiyuan St., Jhubei City,
	5	* Hsinchu County 302,
	6	* Taiwan, R.O.C.
	7	*
	8	* (c) Copyright 2002-2007, Ralink Technology, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify *
	11	* it under the terms of the GNU General Public License as published by *
	12	* the Free Software Foundation; either version 2 of the License, or *
	13	* (at your option) any later version. *
	14	* *
	15	* This program is distributed in the hope that it will be useful, *
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	18	* GNU General Public License for more details. *
	19	* *
	20	* You should have received a copy of the GNU General Public License *
	21	* along with this program; if not, write to the *
	22	* Free Software Foundation, Inc., *
	23	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
	24	* *
	25	*************************************************************************
	26
	27	Module Name:
	28	rtmp_chip.h
	29
	30	Abstract:
	31	Ralink Wireless Chip related definition & structures
	32
	33	Revision History:
	34	Who When What
	35	-------- ---------- ----------------------------------------------
	36	*/
	37
	38	#ifndef __RTMP_CHIP_H__
	39	#define __RTMP_CHIP_H__
	40
	41	#include "rtmp_type.h"
	42
	43	#ifdef RT2860
	44	#include "chip/rt2860.h"
	45	#endif // RT2860 //
	46	#ifdef RT2870
	47	#include "chip/rt2870.h"
	48	#endif // RT2870 //
	49	#ifdef RT3070
	50	#include "chip/rt3070.h"
	51	#endif // RT3070 //
e44fd1cf BZ	52	#ifdef RT3090
	53	#include "chip/rt3090.h"
	54	#endif // RT3090 //
ca97b838 BZ	55
	56	// We will have a cost down version which mac version is 0x3090xxxx
	57	//
	58	// RT3090A facts
	59	//
	60	// a) 2.4 GHz
	61	// b) Replacement for RT3090
	62	// c) Internal LNA
	63	// d) Interference over channel #14
	64	// e) New BBP features (e.g., SIG re-modulation)
	65	//
	66	#define IS_RT3090A(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30900000))
	67
	68	// We will have a cost down version which mac version is 0x3090xxxx
	69	#define IS_RT3090(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30710000) \|\| (IS_RT3090A(_pAd)))
	70
	71	#define IS_RT3070(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30700000)
	72	#define IS_RT3071(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30710000)
	73	#define IS_RT2070(_pAd) (((_pAd)->RfIcType == RFIC_2020) \|\| ((_pAd)->EFuseTag == 0x27))
	74
	75	#define IS_RT30xx(_pAd) (((_pAd)->MACVersion & 0xfff00000) == 0x30700000\|\|IS_RT3090A(_pAd))
52b81c89	76	//#define IS_RT305X(_pAd) ((_pAd)->MACVersion == 0x28720200)
ca97b838 BZ	77
	78	/* RT3572, 3592, 3562, 3062 share the same MAC version */
	79	#define IS_RT3572(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x35720000)
	80	#define IS_VERSION_BEFORE_F(_pAd) (((_pAd)->MACVersion&0xffff) <= 0x0211)
	81	// F version is 0x0212, E version is 0x0211. 309x can save more power after F version.
	82	#define IS_VERSION_AFTER_F(_pAd) ((((_pAd)->MACVersion&0xffff) >= 0x0212) \|\| (((_pAd)->b3090ESpecialChip == TRUE)))
	83	//
	84	// RT3390 facts
	85	//
	86	// a) Base on RT3090 (RF IC: RT3020)
	87	// b) 2.4 GHz
	88	// c) 1x1
	89	// d) Single chip
	90	// e) Internal components: PA and LNA
	91	//
	92	//RT3390,RT3370
	93	#define IS_RT3390(_pAd) (((_pAd)->MACVersion & 0xFFFF0000) == 0x33900000)
	94
	95	// ------------------------------------------------------
	96	// PCI registers - base address 0x0000
	97	// ------------------------------------------------------
	98	#define CHIP_PCI_CFG 0x0000
	99	#define CHIP_PCI_EECTRL 0x0004
	100	#define CHIP_PCI_MCUCTRL 0x0008
	101
	102	#define OPT_14 0x114
	103
	104	#define RETRY_LIMIT 10
	105
ca97b838	106	// ------------------------------------------------------
52b81c89	107	// BBP & RF definition
ca97b838 BZ	108	// ------------------------------------------------------
	109	#define BUSY 1
	110	#define IDLE 0
	111
ca97b838 BZ	112	//-------------------------------------------------------------------------
	113	// EEPROM definition
	114	//-------------------------------------------------------------------------
	115	#define EEDO 0x08
	116	#define EEDI 0x04
	117	#define EECS 0x02
	118	#define EESK 0x01
	119	#define EERL 0x80
	120
	121	#define EEPROM_WRITE_OPCODE 0x05
	122	#define EEPROM_READ_OPCODE 0x06
	123	#define EEPROM_EWDS_OPCODE 0x10
	124	#define EEPROM_EWEN_OPCODE 0x13
	125
52b81c89	126	#define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs
ca97b838	127	#define NUM_EEPROM_TX_G_PARMS 7
52b81c89 BZ	128	#define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID
	129	#define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID
	130	#define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID
ca97b838 BZ	131	#define EEPROM_G_TX_PWR_OFFSET 0x52
	132	#define EEPROM_G_TX2_PWR_OFFSET 0x60
	133	#define EEPROM_LED1_OFFSET 0x3c
	134	#define EEPROM_LED2_OFFSET 0x3e
	135	#define EEPROM_LED3_OFFSET 0x40
	136	#define EEPROM_LNA_OFFSET 0x44
	137	#define EEPROM_RSSI_BG_OFFSET 0x46
	138	#define EEPROM_TXMIXER_GAIN_2_4G 0x48
	139	#define EEPROM_RSSI_A_OFFSET 0x4a
	140	#define EEPROM_TXMIXER_GAIN_5G 0x4c
	141	#define EEPROM_DEFINE_MAX_TXPWR 0x4e
	142	#define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G 0xde // 20MHZ 2.4G tx power.
	143	#define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G 0xee // 40MHZ 2.4G tx power.
	144	#define EEPROM_TXPOWER_BYRATE_20MHZ_5G 0xfa // 20MHZ 5G tx power.
	145	#define EEPROM_TXPOWER_BYRATE_40MHZ_5G 0x10a // 40MHZ 5G tx power.
	146	#define EEPROM_A_TX_PWR_OFFSET 0x78
	147	#define EEPROM_A_TX2_PWR_OFFSET 0xa6
	148	//#define EEPROM_Japan_TX_PWR_OFFSET 0x90 // 802.11j
	149	//#define EEPROM_Japan_TX2_PWR_OFFSET 0xbe
52b81c89 BZ	150	//#define EEPROM_TSSI_REF_OFFSET 0x54
52b81c89 BZ	151	//#define EEPROM_TSSI_DELTA_OFFSET 0x24
ca97b838	152	//#define EEPROM_CCK_TX_PWR_OFFSET 0x62
52b81c89	153	//#define EEPROM_CALIBRATE_OFFSET 0x7c
ca97b838 BZ	154	#define EEPROM_VERSION_OFFSET 0x02
	155	#define EEPROM_FREQ_OFFSET 0x3a
	156	#define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power.
	157	#define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
	158	#define VALID_EEPROM_VERSION 1
	159
ca97b838 BZ	160	/*
	161	* EEPROM operation related marcos
	162	*/
	163	#define RT28xx_EEPROM_READ16(_pAd, _offset, _value) \
	164	(_pAd)->chipOps.eeread((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (PUSHORT)&(_value))
	165
ca97b838 BZ	166	// -------------------------------------------------------------------
	167	// E2PROM data layout
	168	// -------------------------------------------------------------------
	169
	170	//
	171	// MCU_LEDCS: MCU LED Control Setting.
	172	//
52b81c89 BZ	173	typedef union _MCU_LEDCS_STRUC {
	174	struct {
	175	UCHAR LedMode:7;
	176	UCHAR Polarity:1;
ca97b838	177	} field;
52b81c89	178	UCHAR word;
ca97b838 BZ	179	} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
ca97b838 BZ	180
ca97b838 BZ	181	//
	182	// EEPROM antenna select format
	183	//
52b81c89 BZ	184	typedef union _EEPROM_ANTENNA_STRUC {
	185	struct {
	186	USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R
	187	USHORT TxPath:4; // 1: 1T, 2: 2T
	188	USHORT RfIcType:4; // see E2PROM document
	189	USHORT Rsv:4;
	190	} field;
	191	USHORT word;
	192	} EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
ca97b838	193
52b81c89	194	typedef union _EEPROM_NIC_CINFIG2_STRUC {
ca97b838	195	struct {
52b81c89 BZ	196	USHORT HardwareRadioControl:1; // 1:enable, 0:disable
	197	USHORT DynamicTxAgcControl:1; //
	198	USHORT ExternalLNAForG:1; //
	199	USHORT ExternalLNAForA:1; // external LNA enable for 2.4G
	200	USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
	201	USHORT BW40MSidebandForG:1;
	202	USHORT BW40MSidebandForA:1;
	203	USHORT EnableWPSPBC:1; // WPS PBC Control bit
	204	USHORT BW40MAvailForG:1; // 0:enable, 1:disable
	205	USHORT BW40MAvailForA:1; // 0:enable, 1:disable
	206	USHORT Rsv1:1; // must be 0
	207	USHORT AntDiversity:1; // Antenna diversity
	208	USHORT Rsv2:3; // must be 0
	209	USHORT DACTestBit:1; // control if driver should patch the DAC issue
	210	} field;
	211	USHORT word;
	212	} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
ca97b838 BZ	213
	214	//
	215	// TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
	216	//
52b81c89 BZ	217	typedef union _EEPROM_TX_PWR_STRUC {
	218	struct {
	219	CHAR Byte0; // Low Byte
	220	CHAR Byte1; // High Byte
	221	} field;
	222	USHORT word;
	223	} EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
ca97b838	224
52b81c89 BZ	225	typedef union _EEPROM_VERSION_STRUC {
	226	struct {
	227	UCHAR FaeReleaseNumber; // Low Byte
	228	UCHAR Version; // High Byte
	229	} field;
	230	USHORT word;
	231	} EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
ca97b838	232
52b81c89 BZ	233	typedef union _EEPROM_LED_STRUC {
	234	struct {
	235	USHORT PolarityRDY_G:1; // Polarity RDY_G setting.
	236	USHORT PolarityRDY_A:1; // Polarity RDY_A setting.
	237	USHORT PolarityACT:1; // Polarity ACT setting.
	238	USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting.
	239	USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting.
	240	USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting.
	241	USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting.
	242	USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting.
	243	USHORT LedMode:5; // Led mode.
	244	USHORT Rsvd:3; // Reserved
	245	} field;
	246	USHORT word;
	247	} EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
ca97b838	248
52b81c89 BZ	249	typedef union _EEPROM_TXPOWER_DELTA_STRUC {
	250	struct {
	251	UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4)
	252	UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value
	253	UCHAR TxPowerEnable:1; // Enable
	254	} field;
	255	UCHAR value;
	256	} EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
ca97b838	257
52b81c89	258	#endif // __RTMP_CHIP_H__ //