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91980990 GKH |
1 | /* |
2 | ************************************************************************* | |
3 | * Ralink Tech Inc. | |
4 | * 5F., No.36, Taiyuan St., Jhubei City, | |
5 | * Hsinchu County 302, | |
6 | * Taiwan, R.O.C. | |
7 | * | |
8 | * (c) Copyright 2002-2007, Ralink Technology, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify * | |
11 | * it under the terms of the GNU General Public License as published by * | |
12 | * the Free Software Foundation; either version 2 of the License, or * | |
13 | * (at your option) any later version. * | |
14 | * * | |
15 | * This program is distributed in the hope that it will be useful, * | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
18 | * GNU General Public License for more details. * | |
19 | * * | |
20 | * You should have received a copy of the GNU General Public License * | |
21 | * along with this program; if not, write to the * | |
22 | * Free Software Foundation, Inc., * | |
23 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
24 | * * | |
25 | ************************************************************************* | |
26 | ||
27 | Module Name: | |
28 | rtmp_init.c | |
29 | ||
30 | Abstract: | |
31 | Miniport generic portion header file | |
32 | ||
33 | Revision History: | |
34 | Who When What | |
35 | -------- ---------- ---------------------------------------------- | |
91980990 GKH |
36 | */ |
37 | #include "../rt_config.h" | |
91980990 | 38 | |
51126deb | 39 | u8 BIT8[] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; |
96b3c83d BZ |
40 | char *CipherName[] = |
41 | { "none", "wep64", "wep128", "TKIP", "AES", "CKIP64", "CKIP128" }; | |
91980990 | 42 | |
ec278fa2 BZ |
43 | /* */ |
44 | /* BBP register initialization set */ | |
45 | /* */ | |
62eb734b | 46 | struct rt_reg_pair BBPRegTable[] = { |
ec278fa2 BZ |
47 | {BBP_R65, 0x2C}, /* fix rssi issue */ |
48 | {BBP_R66, 0x38}, /* Also set this default value to pAd->BbpTuning.R66CurrentValue at initial */ | |
96b3c83d | 49 | {BBP_R69, 0x12}, |
ec278fa2 | 50 | {BBP_R70, 0xa}, /* BBP_R70 will change to 0x8 in ApStartUp and LinkUp for rt2860C, otherwise value is 0xa */ |
96b3c83d BZ |
51 | {BBP_R73, 0x10}, |
52 | {BBP_R81, 0x37}, | |
53 | {BBP_R82, 0x62}, | |
54 | {BBP_R83, 0x6A}, | |
ec278fa2 BZ |
55 | {BBP_R84, 0x99}, /* 0x19 is for rt2860E and after. This is for extension channel overlapping IOT. 0x99 is for rt2860D and before */ |
56 | {BBP_R86, 0x00}, /* middle range issue, Rory @2008-01-28 */ | |
57 | {BBP_R91, 0x04}, /* middle range issue, Rory @2008-01-28 */ | |
58 | {BBP_R92, 0x00}, /* middle range issue, Rory @2008-01-28 */ | |
59 | {BBP_R103, 0x00}, /* near range high-power issue, requested from Gary @2008-0528 */ | |
60 | {BBP_R105, 0x05}, /* 0x05 is for rt2860E to turn on FEQ control. It is safe for rt2860D and before, because Bit 7:2 are reserved in rt2860D and before. */ | |
61 | {BBP_R106, 0x35}, /* for ShortGI throughput */ | |
91980990 | 62 | }; |
91980990 | 63 | |
62eb734b | 64 | #define NUM_BBP_REG_PARMS (sizeof(BBPRegTable) / sizeof(struct rt_reg_pair)) |
91980990 | 65 | |
ec278fa2 BZ |
66 | /* */ |
67 | /* ASIC register initialization sets */ | |
68 | /* */ | |
91980990 | 69 | |
62eb734b | 70 | struct rt_rtmp_reg_pair MACRegTable[] = { |
91980990 | 71 | #if defined(HW_BEACON_OFFSET) && (HW_BEACON_OFFSET == 0x200) |
96b3c83d BZ |
72 | {BCN_OFFSET0, 0xf8f0e8e0}, /* 0x3800(e0), 0x3A00(e8), 0x3C00(f0), 0x3E00(f8), 512B for each beacon */ |
73 | {BCN_OFFSET1, 0x6f77d0c8}, /* 0x3200(c8), 0x3400(d0), 0x1DC0(77), 0x1BC0(6f), 512B for each beacon */ | |
91980990 | 74 | #elif defined(HW_BEACON_OFFSET) && (HW_BEACON_OFFSET == 0x100) |
96b3c83d BZ |
75 | {BCN_OFFSET0, 0xece8e4e0}, /* 0x3800, 0x3A00, 0x3C00, 0x3E00, 512B for each beacon */ |
76 | {BCN_OFFSET1, 0xfcf8f4f0}, /* 0x3800, 0x3A00, 0x3C00, 0x3E00, 512B for each beacon */ | |
91980990 | 77 | #else |
96b3c83d | 78 | #error You must re-calculate new value for BCN_OFFSET0 & BCN_OFFSET1 in MACRegTable[]!!! |
ec278fa2 BZ |
79 | #endif /* HW_BEACON_OFFSET // */ |
80 | ||
81 | {LEGACY_BASIC_RATE, 0x0000013f}, /* Basic rate set bitmap */ | |
82 | {HT_BASIC_RATE, 0x00008003}, /* Basic HT rate set , 20M, MCS=3, MM. Format is the same as in TXWI. */ | |
83 | {MAC_SYS_CTRL, 0x00}, /* 0x1004, , default Disable RX */ | |
84 | {RX_FILTR_CFG, 0x17f97}, /*0x1400 , RX filter control, */ | |
85 | {BKOFF_SLOT_CFG, 0x209}, /* default set short slot time, CC_DELAY_TIME should be 2 */ | |
86 | /*{TX_SW_CFG0, 0x40a06}, // Gary,2006-08-23 */ | |
87 | {TX_SW_CFG0, 0x0}, /* Gary,2008-05-21 for CWC test */ | |
88 | {TX_SW_CFG1, 0x80606}, /* Gary,2006-08-23 */ | |
89 | {TX_LINK_CFG, 0x1020}, /* Gary,2006-08-23 */ | |
90 | /*{TX_TIMEOUT_CFG, 0x00182090}, // CCK has some problem. So increase timieout value. 2006-10-09// MArvek RT */ | |
91 | {TX_TIMEOUT_CFG, 0x000a2090}, /* CCK has some problem. So increase timieout value. 2006-10-09// MArvek RT , Modify for 2860E ,2007-08-01 */ | |
92 | {MAX_LEN_CFG, MAX_AGGREGATION_SIZE | 0x00001000}, /* 0x3018, MAX frame length. Max PSDU = 16kbytes. */ | |
93 | {LED_CFG, 0x7f031e46}, /* Gary, 2006-08-23 */ | |
94 | ||
95 | {PBF_MAX_PCNT, 0x1F3FBF9F}, /*0x1F3f7f9f}, //Jan, 2006/04/20 */ | |
96 | ||
97 | {TX_RTY_CFG, 0x47d01f0f}, /* Jan, 2006/11/16, Set TxWI->ACK =0 in Probe Rsp Modify for 2860E ,2007-08-03 */ | |
98 | ||
99 | {AUTO_RSP_CFG, 0x00000013}, /* Initial Auto_Responder, because QA will turn off Auto-Responder */ | |
100 | {CCK_PROT_CFG, 0x05740003 /*0x01740003 */ }, /* Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. */ | |
101 | {OFDM_PROT_CFG, 0x05740003 /*0x01740003 */ }, /* Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. */ | |
ca97b838 | 102 | #ifdef RTMP_MAC_USB |
ec278fa2 BZ |
103 | {PBF_CFG, 0xf40006}, /* Only enable Queue 2 */ |
104 | {MM40_PROT_CFG, 0x3F44084}, /* Initial Auto_Responder, because QA will turn off Auto-Responder */ | |
96b3c83d | 105 | {WPDMA_GLO_CFG, 0x00000030}, |
ec278fa2 BZ |
106 | #endif /* RTMP_MAC_USB // */ |
107 | {GF20_PROT_CFG, 0x01744004}, /* set 19:18 --> Short NAV for MIMO PS */ | |
96b3c83d BZ |
108 | {GF40_PROT_CFG, 0x03F44084}, |
109 | {MM20_PROT_CFG, 0x01744004}, | |
ca97b838 | 110 | #ifdef RTMP_MAC_PCI |
96b3c83d | 111 | {MM40_PROT_CFG, 0x03F54084}, |
ec278fa2 BZ |
112 | #endif /* RTMP_MAC_PCI // */ |
113 | {TXOP_CTRL_CFG, 0x0000583f, /*0x0000243f *//*0x000024bf */ }, /*Extension channel backoff. */ | |
96b3c83d | 114 | {TX_RTS_CFG, 0x00092b20}, |
ec278fa2 | 115 | {EXP_ACK_TIME, 0x002400ca}, /* default value */ |
ca97b838 | 116 | |
96b3c83d | 117 | {TXOP_HLDR_ET, 0x00000002}, |
91980990 GKH |
118 | |
119 | /* Jerry comments 2008/01/16: we use SIFS = 10us in CCK defaultly, but it seems that 10us | |
96b3c83d BZ |
120 | is too small for INTEL 2200bg card, so in MBSS mode, the delta time between beacon0 |
121 | and beacon1 is SIFS (10us), so if INTEL 2200bg card connects to BSS0, the ping | |
122 | will always lost. So we change the SIFS of CCK from 10us to 16us. */ | |
123 | {XIFS_TIME_CFG, 0x33a41010}, | |
ec278fa2 | 124 | {PWR_PIN_CFG, 0x00000003}, /* patch for 2880-E */ |
91980990 GKH |
125 | }; |
126 | ||
62eb734b | 127 | struct rt_rtmp_reg_pair STAMACRegTable[] = { |
96b3c83d BZ |
128 | {WMM_AIFSN_CFG, 0x00002273}, |
129 | {WMM_CWMIN_CFG, 0x00002344}, | |
130 | {WMM_CWMAX_CFG, 0x000034aa}, | |
91980990 | 131 | }; |
91980990 | 132 | |
62eb734b BZ |
133 | #define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(struct rt_rtmp_reg_pair)) |
134 | #define NUM_STA_MAC_REG_PARMS (sizeof(STAMACRegTable) / sizeof(struct rt_rtmp_reg_pair)) | |
91980990 | 135 | |
91980990 GKH |
136 | /* |
137 | ======================================================================== | |
138 | ||
139 | Routine Description: | |
62eb734b | 140 | Allocate struct rt_rtmp_adapter data block and do some initialization |
91980990 GKH |
141 | |
142 | Arguments: | |
143 | Adapter Pointer to our adapter | |
144 | ||
145 | Return Value: | |
146 | NDIS_STATUS_SUCCESS | |
147 | NDIS_STATUS_FAILURE | |
148 | ||
149 | IRQL = PASSIVE_LEVEL | |
150 | ||
151 | Note: | |
152 | ||
153 | ======================================================================== | |
154 | */ | |
51126deb | 155 | int RTMPAllocAdapterBlock(void *handle, |
62eb734b | 156 | struct rt_rtmp_adapter * * ppAdapter) |
91980990 | 157 | { |
62eb734b | 158 | struct rt_rtmp_adapter *pAd; |
51126deb BZ |
159 | int Status; |
160 | int index; | |
161 | u8 *pBeaconBuf = NULL; | |
91980990 GKH |
162 | |
163 | DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPAllocAdapterBlock\n")); | |
164 | ||
165 | *ppAdapter = NULL; | |
166 | ||
96b3c83d | 167 | do { |
62eb734b | 168 | /* Allocate struct rt_rtmp_adapter memory block */ |
91980990 | 169 | pBeaconBuf = kmalloc(MAX_BEACON_SIZE, MEM_ALLOC_FLAG); |
96b3c83d | 170 | if (pBeaconBuf == NULL) { |
91980990 GKH |
171 | Status = NDIS_STATUS_FAILURE; |
172 | DBGPRINT_ERR(("Failed to allocate memory - BeaconBuf!\n")); | |
173 | break; | |
174 | } | |
ca97b838 | 175 | NdisZeroMemory(pBeaconBuf, MAX_BEACON_SIZE); |
91980990 | 176 | |
51126deb | 177 | Status = AdapterBlockAllocateMemory(handle, (void **) & pAd); |
96b3c83d | 178 | if (Status != NDIS_STATUS_SUCCESS) { |
91980990 GKH |
179 | DBGPRINT_ERR(("Failed to allocate memory - ADAPTER\n")); |
180 | break; | |
181 | } | |
182 | pAd->BeaconBuf = pBeaconBuf; | |
96b3c83d BZ |
183 | DBGPRINT(RT_DEBUG_OFF, |
184 | ("\n\n=== pAd = %p, size = %d ===\n\n", pAd, | |
62eb734b | 185 | (u32)sizeof(struct rt_rtmp_adapter))); |
91980990 | 186 | |
ec278fa2 | 187 | /* Init spin locks */ |
91980990 | 188 | NdisAllocateSpinLock(&pAd->MgmtRingLock); |
ca97b838 | 189 | #ifdef RTMP_MAC_PCI |
91980990 | 190 | NdisAllocateSpinLock(&pAd->RxRingLock); |
e44fd1cf | 191 | #ifdef RT3090 |
96b3c83d | 192 | NdisAllocateSpinLock(&pAd->McuCmdLock); |
ec278fa2 BZ |
193 | #endif /* RT3090 // */ |
194 | #endif /* RTMP_MAC_PCI // */ | |
91980990 | 195 | |
96b3c83d | 196 | for (index = 0; index < NUM_OF_TX_RING; index++) { |
91980990 GKH |
197 | NdisAllocateSpinLock(&pAd->TxSwQueueLock[index]); |
198 | NdisAllocateSpinLock(&pAd->DeQueueLock[index]); | |
199 | pAd->DeQueueRunning[index] = FALSE; | |
200 | } | |
201 | ||
202 | NdisAllocateSpinLock(&pAd->irq_lock); | |
203 | ||
204 | } while (FALSE); | |
205 | ||
206 | if ((Status != NDIS_STATUS_SUCCESS) && (pBeaconBuf)) | |
207 | kfree(pBeaconBuf); | |
208 | ||
209 | *ppAdapter = pAd; | |
210 | ||
211 | DBGPRINT_S(Status, ("<-- RTMPAllocAdapterBlock, Status=%x\n", Status)); | |
212 | return Status; | |
213 | } | |
214 | ||
215 | /* | |
216 | ======================================================================== | |
217 | ||
218 | Routine Description: | |
219 | Read initial Tx power per MCS and BW from EEPROM | |
220 | ||
221 | Arguments: | |
222 | Adapter Pointer to our adapter | |
223 | ||
224 | Return Value: | |
225 | None | |
226 | ||
227 | IRQL = PASSIVE_LEVEL | |
228 | ||
229 | Note: | |
230 | ||
231 | ======================================================================== | |
232 | */ | |
62eb734b | 233 | void RTMPReadTxPwrPerRate(struct rt_rtmp_adapter *pAd) |
91980990 | 234 | { |
51126deb BZ |
235 | unsigned long data, Adata, Gdata; |
236 | u16 i, value, value2; | |
237 | int Apwrdelta, Gpwrdelta; | |
238 | u8 t1, t2, t3, t4; | |
96b3c83d | 239 | BOOLEAN bApwrdeltaMinus = TRUE, bGpwrdeltaMinus = TRUE; |
91980990 | 240 | |
ec278fa2 BZ |
241 | /* */ |
242 | /* Get power delta for 20MHz and 40MHz. */ | |
243 | /* */ | |
91980990 GKH |
244 | DBGPRINT(RT_DEBUG_TRACE, ("Txpower per Rate\n")); |
245 | RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_DELTA, value2); | |
246 | Apwrdelta = 0; | |
247 | Gpwrdelta = 0; | |
248 | ||
96b3c83d | 249 | if ((value2 & 0xff) != 0xff) { |
91980990 | 250 | if ((value2 & 0x80)) |
96b3c83d | 251 | Gpwrdelta = (value2 & 0xf); |
91980990 GKH |
252 | |
253 | if ((value2 & 0x40)) | |
254 | bGpwrdeltaMinus = FALSE; | |
255 | else | |
256 | bGpwrdeltaMinus = TRUE; | |
257 | } | |
96b3c83d | 258 | if ((value2 & 0xff00) != 0xff00) { |
91980990 | 259 | if ((value2 & 0x8000)) |
96b3c83d | 260 | Apwrdelta = ((value2 & 0xf00) >> 8); |
91980990 GKH |
261 | |
262 | if ((value2 & 0x4000)) | |
263 | bApwrdeltaMinus = FALSE; | |
264 | else | |
265 | bApwrdeltaMinus = TRUE; | |
266 | } | |
96b3c83d BZ |
267 | DBGPRINT(RT_DEBUG_TRACE, |
268 | ("Gpwrdelta = %x, Apwrdelta = %x .\n", Gpwrdelta, Apwrdelta)); | |
91980990 | 269 | |
ec278fa2 BZ |
270 | /* */ |
271 | /* Get Txpower per MCS for 20MHz in 2.4G. */ | |
272 | /* */ | |
96b3c83d BZ |
273 | for (i = 0; i < 5; i++) { |
274 | RT28xx_EEPROM_READ16(pAd, | |
275 | EEPROM_TXPOWER_BYRATE_20MHZ_2_4G + i * 4, | |
276 | value); | |
91980990 | 277 | data = value; |
96b3c83d BZ |
278 | if (bApwrdeltaMinus == FALSE) { |
279 | t1 = (value & 0xf) + (Apwrdelta); | |
91980990 GKH |
280 | if (t1 > 0xf) |
281 | t1 = 0xf; | |
96b3c83d | 282 | t2 = ((value & 0xf0) >> 4) + (Apwrdelta); |
91980990 GKH |
283 | if (t2 > 0xf) |
284 | t2 = 0xf; | |
96b3c83d | 285 | t3 = ((value & 0xf00) >> 8) + (Apwrdelta); |
91980990 GKH |
286 | if (t3 > 0xf) |
287 | t3 = 0xf; | |
96b3c83d | 288 | t4 = ((value & 0xf000) >> 12) + (Apwrdelta); |
91980990 GKH |
289 | if (t4 > 0xf) |
290 | t4 = 0xf; | |
96b3c83d BZ |
291 | } else { |
292 | if ((value & 0xf) > Apwrdelta) | |
293 | t1 = (value & 0xf) - (Apwrdelta); | |
91980990 GKH |
294 | else |
295 | t1 = 0; | |
96b3c83d BZ |
296 | if (((value & 0xf0) >> 4) > Apwrdelta) |
297 | t2 = ((value & 0xf0) >> 4) - (Apwrdelta); | |
91980990 GKH |
298 | else |
299 | t2 = 0; | |
96b3c83d BZ |
300 | if (((value & 0xf00) >> 8) > Apwrdelta) |
301 | t3 = ((value & 0xf00) >> 8) - (Apwrdelta); | |
91980990 GKH |
302 | else |
303 | t3 = 0; | |
96b3c83d BZ |
304 | if (((value & 0xf000) >> 12) > Apwrdelta) |
305 | t4 = ((value & 0xf000) >> 12) - (Apwrdelta); | |
91980990 GKH |
306 | else |
307 | t4 = 0; | |
308 | } | |
96b3c83d BZ |
309 | Adata = t1 + (t2 << 4) + (t3 << 8) + (t4 << 12); |
310 | if (bGpwrdeltaMinus == FALSE) { | |
311 | t1 = (value & 0xf) + (Gpwrdelta); | |
91980990 GKH |
312 | if (t1 > 0xf) |
313 | t1 = 0xf; | |
96b3c83d | 314 | t2 = ((value & 0xf0) >> 4) + (Gpwrdelta); |
91980990 GKH |
315 | if (t2 > 0xf) |
316 | t2 = 0xf; | |
96b3c83d | 317 | t3 = ((value & 0xf00) >> 8) + (Gpwrdelta); |
91980990 GKH |
318 | if (t3 > 0xf) |
319 | t3 = 0xf; | |
96b3c83d | 320 | t4 = ((value & 0xf000) >> 12) + (Gpwrdelta); |
91980990 GKH |
321 | if (t4 > 0xf) |
322 | t4 = 0xf; | |
96b3c83d BZ |
323 | } else { |
324 | if ((value & 0xf) > Gpwrdelta) | |
325 | t1 = (value & 0xf) - (Gpwrdelta); | |
91980990 GKH |
326 | else |
327 | t1 = 0; | |
96b3c83d BZ |
328 | if (((value & 0xf0) >> 4) > Gpwrdelta) |
329 | t2 = ((value & 0xf0) >> 4) - (Gpwrdelta); | |
91980990 GKH |
330 | else |
331 | t2 = 0; | |
96b3c83d BZ |
332 | if (((value & 0xf00) >> 8) > Gpwrdelta) |
333 | t3 = ((value & 0xf00) >> 8) - (Gpwrdelta); | |
91980990 GKH |
334 | else |
335 | t3 = 0; | |
96b3c83d BZ |
336 | if (((value & 0xf000) >> 12) > Gpwrdelta) |
337 | t4 = ((value & 0xf000) >> 12) - (Gpwrdelta); | |
91980990 GKH |
338 | else |
339 | t4 = 0; | |
340 | } | |
96b3c83d | 341 | Gdata = t1 + (t2 << 4) + (t3 << 8) + (t4 << 12); |
91980990 | 342 | |
96b3c83d BZ |
343 | RT28xx_EEPROM_READ16(pAd, |
344 | EEPROM_TXPOWER_BYRATE_20MHZ_2_4G + i * 4 + | |
345 | 2, value); | |
346 | if (bApwrdeltaMinus == FALSE) { | |
347 | t1 = (value & 0xf) + (Apwrdelta); | |
91980990 GKH |
348 | if (t1 > 0xf) |
349 | t1 = 0xf; | |
96b3c83d | 350 | t2 = ((value & 0xf0) >> 4) + (Apwrdelta); |
91980990 GKH |
351 | if (t2 > 0xf) |
352 | t2 = 0xf; | |
96b3c83d | 353 | t3 = ((value & 0xf00) >> 8) + (Apwrdelta); |
91980990 GKH |
354 | if (t3 > 0xf) |
355 | t3 = 0xf; | |
96b3c83d | 356 | t4 = ((value & 0xf000) >> 12) + (Apwrdelta); |
91980990 GKH |
357 | if (t4 > 0xf) |
358 | t4 = 0xf; | |
96b3c83d BZ |
359 | } else { |
360 | if ((value & 0xf) > Apwrdelta) | |
361 | t1 = (value & 0xf) - (Apwrdelta); | |
91980990 GKH |
362 | else |
363 | t1 = 0; | |
96b3c83d BZ |
364 | if (((value & 0xf0) >> 4) > Apwrdelta) |
365 | t2 = ((value & 0xf0) >> 4) - (Apwrdelta); | |
91980990 GKH |
366 | else |
367 | t2 = 0; | |
96b3c83d BZ |
368 | if (((value & 0xf00) >> 8) > Apwrdelta) |
369 | t3 = ((value & 0xf00) >> 8) - (Apwrdelta); | |
91980990 GKH |
370 | else |
371 | t3 = 0; | |
96b3c83d BZ |
372 | if (((value & 0xf000) >> 12) > Apwrdelta) |
373 | t4 = ((value & 0xf000) >> 12) - (Apwrdelta); | |
91980990 GKH |
374 | else |
375 | t4 = 0; | |
376 | } | |
96b3c83d BZ |
377 | Adata |= ((t1 << 16) + (t2 << 20) + (t3 << 24) + (t4 << 28)); |
378 | if (bGpwrdeltaMinus == FALSE) { | |
379 | t1 = (value & 0xf) + (Gpwrdelta); | |
91980990 GKH |
380 | if (t1 > 0xf) |
381 | t1 = 0xf; | |
96b3c83d | 382 | t2 = ((value & 0xf0) >> 4) + (Gpwrdelta); |
91980990 GKH |
383 | if (t2 > 0xf) |
384 | t2 = 0xf; | |
96b3c83d | 385 | t3 = ((value & 0xf00) >> 8) + (Gpwrdelta); |
91980990 GKH |
386 | if (t3 > 0xf) |
387 | t3 = 0xf; | |
96b3c83d | 388 | t4 = ((value & 0xf000) >> 12) + (Gpwrdelta); |
91980990 GKH |
389 | if (t4 > 0xf) |
390 | t4 = 0xf; | |
96b3c83d BZ |
391 | } else { |
392 | if ((value & 0xf) > Gpwrdelta) | |
393 | t1 = (value & 0xf) - (Gpwrdelta); | |
91980990 GKH |
394 | else |
395 | t1 = 0; | |
96b3c83d BZ |
396 | if (((value & 0xf0) >> 4) > Gpwrdelta) |
397 | t2 = ((value & 0xf0) >> 4) - (Gpwrdelta); | |
91980990 GKH |
398 | else |
399 | t2 = 0; | |
96b3c83d BZ |
400 | if (((value & 0xf00) >> 8) > Gpwrdelta) |
401 | t3 = ((value & 0xf00) >> 8) - (Gpwrdelta); | |
91980990 GKH |
402 | else |
403 | t3 = 0; | |
96b3c83d BZ |
404 | if (((value & 0xf000) >> 12) > Gpwrdelta) |
405 | t4 = ((value & 0xf000) >> 12) - (Gpwrdelta); | |
91980990 GKH |
406 | else |
407 | t4 = 0; | |
408 | } | |
96b3c83d BZ |
409 | Gdata |= ((t1 << 16) + (t2 << 20) + (t3 << 24) + (t4 << 28)); |
410 | data |= (value << 16); | |
91980990 | 411 | |
ca97b838 BZ |
412 | /* For 20M/40M Power Delta issue */ |
413 | pAd->Tx20MPwrCfgABand[i] = data; | |
414 | pAd->Tx20MPwrCfgGBand[i] = data; | |
415 | pAd->Tx40MPwrCfgABand[i] = Adata; | |
416 | pAd->Tx40MPwrCfgGBand[i] = Gdata; | |
91980990 GKH |
417 | |
418 | if (data != 0xffffffff) | |
96b3c83d BZ |
419 | RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i * 4, data); |
420 | DBGPRINT_RAW(RT_DEBUG_TRACE, | |
421 | ("20MHz BW, 2.4G band-%lx, Adata = %lx, Gdata = %lx \n", | |
422 | data, Adata, Gdata)); | |
91980990 | 423 | } |
91980990 GKH |
424 | } |
425 | ||
91980990 GKH |
426 | /* |
427 | ======================================================================== | |
428 | ||
429 | Routine Description: | |
430 | Read initial channel power parameters from EEPROM | |
431 | ||
432 | Arguments: | |
433 | Adapter Pointer to our adapter | |
434 | ||
435 | Return Value: | |
436 | None | |
437 | ||
438 | IRQL = PASSIVE_LEVEL | |
439 | ||
440 | Note: | |
441 | ||
442 | ======================================================================== | |
443 | */ | |
62eb734b | 444 | void RTMPReadChannelPwr(struct rt_rtmp_adapter *pAd) |
91980990 | 445 | { |
51126deb | 446 | u8 i, choffset; |
96b3c83d BZ |
447 | EEPROM_TX_PWR_STRUC Power; |
448 | EEPROM_TX_PWR_STRUC Power2; | |
91980990 | 449 | |
ec278fa2 BZ |
450 | /* Read Tx power value for all channels */ |
451 | /* Value from 1 - 0x7f. Default value is 24. */ | |
452 | /* Power value : 2.4G 0x00 (0) ~ 0x1F (31) */ | |
453 | /* : 5.5G 0xF9 (-7) ~ 0x0F (15) */ | |
91980990 | 454 | |
ec278fa2 | 455 | /* 0. 11b/g, ch1 - ch 14 */ |
96b3c83d BZ |
456 | for (i = 0; i < 7; i++) { |
457 | RT28xx_EEPROM_READ16(pAd, EEPROM_G_TX_PWR_OFFSET + i * 2, | |
458 | Power.word); | |
459 | RT28xx_EEPROM_READ16(pAd, EEPROM_G_TX2_PWR_OFFSET + i * 2, | |
460 | Power2.word); | |
91980990 GKH |
461 | pAd->TxPower[i * 2].Channel = i * 2 + 1; |
462 | pAd->TxPower[i * 2 + 1].Channel = i * 2 + 2; | |
463 | ||
464 | if ((Power.field.Byte0 > 31) || (Power.field.Byte0 < 0)) | |
465 | pAd->TxPower[i * 2].Power = DEFAULT_RF_TX_POWER; | |
466 | else | |
467 | pAd->TxPower[i * 2].Power = Power.field.Byte0; | |
468 | ||
469 | if ((Power.field.Byte1 > 31) || (Power.field.Byte1 < 0)) | |
470 | pAd->TxPower[i * 2 + 1].Power = DEFAULT_RF_TX_POWER; | |
471 | else | |
472 | pAd->TxPower[i * 2 + 1].Power = Power.field.Byte1; | |
473 | ||
474 | if ((Power2.field.Byte0 > 31) || (Power2.field.Byte0 < 0)) | |
475 | pAd->TxPower[i * 2].Power2 = DEFAULT_RF_TX_POWER; | |
476 | else | |
477 | pAd->TxPower[i * 2].Power2 = Power2.field.Byte0; | |
478 | ||
479 | if ((Power2.field.Byte1 > 31) || (Power2.field.Byte1 < 0)) | |
480 | pAd->TxPower[i * 2 + 1].Power2 = DEFAULT_RF_TX_POWER; | |
481 | else | |
482 | pAd->TxPower[i * 2 + 1].Power2 = Power2.field.Byte1; | |
483 | } | |
484 | ||
ec278fa2 BZ |
485 | /* 1. U-NII lower/middle band: 36, 38, 40; 44, 46, 48; 52, 54, 56; 60, 62, 64 (including central frequency in BW 40MHz) */ |
486 | /* 1.1 Fill up channel */ | |
91980990 | 487 | choffset = 14; |
96b3c83d BZ |
488 | for (i = 0; i < 4; i++) { |
489 | pAd->TxPower[3 * i + choffset + 0].Channel = 36 + i * 8 + 0; | |
490 | pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER; | |
491 | pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 492 | |
96b3c83d BZ |
493 | pAd->TxPower[3 * i + choffset + 1].Channel = 36 + i * 8 + 2; |
494 | pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER; | |
495 | pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 496 | |
96b3c83d BZ |
497 | pAd->TxPower[3 * i + choffset + 2].Channel = 36 + i * 8 + 4; |
498 | pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER; | |
499 | pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 GKH |
500 | } |
501 | ||
ec278fa2 | 502 | /* 1.2 Fill up power */ |
96b3c83d BZ |
503 | for (i = 0; i < 6; i++) { |
504 | RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX_PWR_OFFSET + i * 2, | |
505 | Power.word); | |
506 | RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX2_PWR_OFFSET + i * 2, | |
507 | Power2.word); | |
91980990 GKH |
508 | |
509 | if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7)) | |
96b3c83d BZ |
510 | pAd->TxPower[i * 2 + choffset + 0].Power = |
511 | Power.field.Byte0; | |
91980990 GKH |
512 | |
513 | if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7)) | |
96b3c83d BZ |
514 | pAd->TxPower[i * 2 + choffset + 1].Power = |
515 | Power.field.Byte1; | |
91980990 GKH |
516 | |
517 | if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7)) | |
96b3c83d BZ |
518 | pAd->TxPower[i * 2 + choffset + 0].Power2 = |
519 | Power2.field.Byte0; | |
91980990 GKH |
520 | |
521 | if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7)) | |
96b3c83d BZ |
522 | pAd->TxPower[i * 2 + choffset + 1].Power2 = |
523 | Power2.field.Byte1; | |
91980990 GKH |
524 | } |
525 | ||
ec278fa2 BZ |
526 | /* 2. HipperLAN 2 100, 102 ,104; 108, 110, 112; 116, 118, 120; 124, 126, 128; 132, 134, 136; 140 (including central frequency in BW 40MHz) */ |
527 | /* 2.1 Fill up channel */ | |
91980990 | 528 | choffset = 14 + 12; |
96b3c83d BZ |
529 | for (i = 0; i < 5; i++) { |
530 | pAd->TxPower[3 * i + choffset + 0].Channel = 100 + i * 8 + 0; | |
531 | pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER; | |
532 | pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 533 | |
96b3c83d BZ |
534 | pAd->TxPower[3 * i + choffset + 1].Channel = 100 + i * 8 + 2; |
535 | pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER; | |
536 | pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 537 | |
96b3c83d BZ |
538 | pAd->TxPower[3 * i + choffset + 2].Channel = 100 + i * 8 + 4; |
539 | pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER; | |
540 | pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 541 | } |
96b3c83d BZ |
542 | pAd->TxPower[3 * 5 + choffset + 0].Channel = 140; |
543 | pAd->TxPower[3 * 5 + choffset + 0].Power = DEFAULT_RF_TX_POWER; | |
544 | pAd->TxPower[3 * 5 + choffset + 0].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 545 | |
ec278fa2 | 546 | /* 2.2 Fill up power */ |
96b3c83d BZ |
547 | for (i = 0; i < 8; i++) { |
548 | RT28xx_EEPROM_READ16(pAd, | |
549 | EEPROM_A_TX_PWR_OFFSET + (choffset - 14) + | |
550 | i * 2, Power.word); | |
551 | RT28xx_EEPROM_READ16(pAd, | |
552 | EEPROM_A_TX2_PWR_OFFSET + (choffset - 14) + | |
553 | i * 2, Power2.word); | |
91980990 GKH |
554 | |
555 | if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7)) | |
96b3c83d BZ |
556 | pAd->TxPower[i * 2 + choffset + 0].Power = |
557 | Power.field.Byte0; | |
91980990 GKH |
558 | |
559 | if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7)) | |
96b3c83d BZ |
560 | pAd->TxPower[i * 2 + choffset + 1].Power = |
561 | Power.field.Byte1; | |
91980990 GKH |
562 | |
563 | if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7)) | |
96b3c83d BZ |
564 | pAd->TxPower[i * 2 + choffset + 0].Power2 = |
565 | Power2.field.Byte0; | |
91980990 GKH |
566 | |
567 | if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7)) | |
96b3c83d BZ |
568 | pAd->TxPower[i * 2 + choffset + 1].Power2 = |
569 | Power2.field.Byte1; | |
91980990 GKH |
570 | } |
571 | ||
ec278fa2 BZ |
572 | /* 3. U-NII upper band: 149, 151, 153; 157, 159, 161; 165, 167, 169; 171, 173 (including central frequency in BW 40MHz) */ |
573 | /* 3.1 Fill up channel */ | |
91980990 | 574 | choffset = 14 + 12 + 16; |
96b3c83d BZ |
575 | /*for (i = 0; i < 2; i++) */ |
576 | for (i = 0; i < 3; i++) { | |
577 | pAd->TxPower[3 * i + choffset + 0].Channel = 149 + i * 8 + 0; | |
578 | pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER; | |
579 | pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 580 | |
96b3c83d BZ |
581 | pAd->TxPower[3 * i + choffset + 1].Channel = 149 + i * 8 + 2; |
582 | pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER; | |
583 | pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 584 | |
96b3c83d BZ |
585 | pAd->TxPower[3 * i + choffset + 2].Channel = 149 + i * 8 + 4; |
586 | pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER; | |
587 | pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 588 | } |
96b3c83d BZ |
589 | pAd->TxPower[3 * 3 + choffset + 0].Channel = 171; |
590 | pAd->TxPower[3 * 3 + choffset + 0].Power = DEFAULT_RF_TX_POWER; | |
591 | pAd->TxPower[3 * 3 + choffset + 0].Power2 = DEFAULT_RF_TX_POWER; | |
ca97b838 | 592 | |
96b3c83d BZ |
593 | pAd->TxPower[3 * 3 + choffset + 1].Channel = 173; |
594 | pAd->TxPower[3 * 3 + choffset + 1].Power = DEFAULT_RF_TX_POWER; | |
595 | pAd->TxPower[3 * 3 + choffset + 1].Power2 = DEFAULT_RF_TX_POWER; | |
91980990 | 596 | |
ec278fa2 | 597 | /* 3.2 Fill up power */ |
96b3c83d BZ |
598 | /*for (i = 0; i < 4; i++) */ |
599 | for (i = 0; i < 6; i++) { | |
600 | RT28xx_EEPROM_READ16(pAd, | |
601 | EEPROM_A_TX_PWR_OFFSET + (choffset - 14) + | |
602 | i * 2, Power.word); | |
603 | RT28xx_EEPROM_READ16(pAd, | |
604 | EEPROM_A_TX2_PWR_OFFSET + (choffset - 14) + | |
605 | i * 2, Power2.word); | |
91980990 GKH |
606 | |
607 | if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7)) | |
96b3c83d BZ |
608 | pAd->TxPower[i * 2 + choffset + 0].Power = |
609 | Power.field.Byte0; | |
91980990 GKH |
610 | |
611 | if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7)) | |
96b3c83d BZ |
612 | pAd->TxPower[i * 2 + choffset + 1].Power = |
613 | Power.field.Byte1; | |
91980990 GKH |
614 | |
615 | if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7)) | |
96b3c83d BZ |
616 | pAd->TxPower[i * 2 + choffset + 0].Power2 = |
617 | Power2.field.Byte0; | |
91980990 GKH |
618 | |
619 | if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7)) | |
96b3c83d BZ |
620 | pAd->TxPower[i * 2 + choffset + 1].Power2 = |
621 | Power2.field.Byte1; | |
91980990 GKH |
622 | } |
623 | ||
ec278fa2 | 624 | /* 4. Print and Debug */ |
96b3c83d | 625 | /*choffset = 14 + 12 + 16 + 7; */ |
ca97b838 BZ |
626 | choffset = 14 + 12 + 16 + 11; |
627 | ||
91980990 GKH |
628 | } |
629 | ||
630 | /* | |
631 | ======================================================================== | |
632 | ||
633 | Routine Description: | |
634 | Read the following from the registry | |
635 | 1. All the parameters | |
636 | 2. NetworkAddres | |
637 | ||
638 | Arguments: | |
639 | Adapter Pointer to our adapter | |
640 | WrapperConfigurationContext For use by NdisOpenConfiguration | |
641 | ||
642 | Return Value: | |
643 | NDIS_STATUS_SUCCESS | |
644 | NDIS_STATUS_FAILURE | |
645 | NDIS_STATUS_RESOURCES | |
646 | ||
647 | IRQL = PASSIVE_LEVEL | |
648 | ||
649 | Note: | |
650 | ||
651 | ======================================================================== | |
652 | */ | |
62eb734b | 653 | int NICReadRegParameters(struct rt_rtmp_adapter *pAd, |
8a10a546 | 654 | void *WrapperConfigurationContext) |
91980990 | 655 | { |
51126deb | 656 | int Status = NDIS_STATUS_SUCCESS; |
91980990 GKH |
657 | DBGPRINT_S(Status, ("<-- NICReadRegParameters, Status=%x\n", Status)); |
658 | return Status; | |
659 | } | |
660 | ||
91980990 GKH |
661 | /* |
662 | ======================================================================== | |
663 | ||
664 | Routine Description: | |
665 | Read initial parameters from EEPROM | |
666 | ||
667 | Arguments: | |
668 | Adapter Pointer to our adapter | |
669 | ||
670 | Return Value: | |
671 | None | |
672 | ||
673 | IRQL = PASSIVE_LEVEL | |
674 | ||
675 | Note: | |
676 | ||
677 | ======================================================================== | |
678 | */ | |
62eb734b | 679 | void NICReadEEPROMParameters(struct rt_rtmp_adapter *pAd, u8 *mac_addr) |
91980990 | 680 | { |
51126deb BZ |
681 | u32 data = 0; |
682 | u16 i, value, value2; | |
683 | u8 TmpPhy; | |
96b3c83d BZ |
684 | EEPROM_TX_PWR_STRUC Power; |
685 | EEPROM_VERSION_STRUC Version; | |
686 | EEPROM_ANTENNA_STRUC Antenna; | |
687 | EEPROM_NIC_CONFIG2_STRUC NicConfig2; | |
91980990 GKH |
688 | |
689 | DBGPRINT(RT_DEBUG_TRACE, ("--> NICReadEEPROMParameters\n")); | |
690 | ||
ca97b838 BZ |
691 | if (pAd->chipOps.eeinit) |
692 | pAd->chipOps.eeinit(pAd); | |
ca97b838 | 693 | |
ec278fa2 | 694 | /* Init EEPROM Address Number, before access EEPROM; if 93c46, EEPROMAddressNum=6, else if 93c66, EEPROMAddressNum=8 */ |
91980990 GKH |
695 | RTMP_IO_READ32(pAd, E2PROM_CSR, &data); |
696 | DBGPRINT(RT_DEBUG_TRACE, ("--> E2PROM_CSR = 0x%x\n", data)); | |
697 | ||
96b3c83d | 698 | if ((data & 0x30) == 0) |
ec278fa2 | 699 | pAd->EEPROMAddressNum = 6; /* 93C46 */ |
96b3c83d | 700 | else if ((data & 0x30) == 0x10) |
ec278fa2 | 701 | pAd->EEPROMAddressNum = 8; /* 93C66 */ |
91980990 | 702 | else |
ec278fa2 | 703 | pAd->EEPROMAddressNum = 8; /* 93C86 */ |
96b3c83d BZ |
704 | DBGPRINT(RT_DEBUG_TRACE, |
705 | ("--> EEPROMAddressNum = %d\n", pAd->EEPROMAddressNum)); | |
91980990 | 706 | |
ec278fa2 BZ |
707 | /* RT2860 MAC no longer auto load MAC address from E2PROM. Driver has to intialize */ |
708 | /* MAC address registers according to E2PROM setting */ | |
91980990 | 709 | if (mac_addr == NULL || |
51126deb | 710 | strlen((char *)mac_addr) != 17 || |
96b3c83d BZ |
711 | mac_addr[2] != ':' || mac_addr[5] != ':' || mac_addr[8] != ':' || |
712 | mac_addr[11] != ':' || mac_addr[14] != ':') { | |
51126deb | 713 | u16 Addr01, Addr23, Addr45; |
91980990 GKH |
714 | |
715 | RT28xx_EEPROM_READ16(pAd, 0x04, Addr01); | |
716 | RT28xx_EEPROM_READ16(pAd, 0x06, Addr23); | |
717 | RT28xx_EEPROM_READ16(pAd, 0x08, Addr45); | |
718 | ||
51126deb BZ |
719 | pAd->PermanentAddress[0] = (u8)(Addr01 & 0xff); |
720 | pAd->PermanentAddress[1] = (u8)(Addr01 >> 8); | |
721 | pAd->PermanentAddress[2] = (u8)(Addr23 & 0xff); | |
722 | pAd->PermanentAddress[3] = (u8)(Addr23 >> 8); | |
723 | pAd->PermanentAddress[4] = (u8)(Addr45 & 0xff); | |
724 | pAd->PermanentAddress[5] = (u8)(Addr45 >> 8); | |
91980990 | 725 | |
96b3c83d BZ |
726 | DBGPRINT(RT_DEBUG_TRACE, |
727 | ("Initialize MAC Address from E2PROM \n")); | |
728 | } else { | |
51126deb BZ |
729 | int j; |
730 | char *macptr; | |
91980990 | 731 | |
51126deb | 732 | macptr = (char *)mac_addr; |
91980990 | 733 | |
96b3c83d | 734 | for (j = 0; j < MAC_ADDR_LEN; j++) { |
91980990 | 735 | AtoH(macptr, &pAd->PermanentAddress[j], 1); |
96b3c83d | 736 | macptr = macptr + 3; |
91980990 GKH |
737 | } |
738 | ||
96b3c83d BZ |
739 | DBGPRINT(RT_DEBUG_TRACE, |
740 | ("Initialize MAC Address from module parameter \n")); | |
91980990 GKH |
741 | } |
742 | ||
91980990 | 743 | { |
ec278fa2 | 744 | /*more conveninet to test mbssid, so ap's bssid &0xf1 */ |
91980990 | 745 | if (pAd->PermanentAddress[0] == 0xff) |
96b3c83d | 746 | pAd->PermanentAddress[0] = RandomByte(pAd) & 0xf8; |
91980990 | 747 | |
ec278fa2 BZ |
748 | /*if (pAd->PermanentAddress[5] == 0xff) */ |
749 | /* pAd->PermanentAddress[5] = RandomByte(pAd)&0xf8; */ | |
96b3c83d BZ |
750 | |
751 | DBGPRINT_RAW(RT_DEBUG_TRACE, | |
752 | ("E2PROM MAC: =%02x:%02x:%02x:%02x:%02x:%02x\n", | |
753 | pAd->PermanentAddress[0], | |
754 | pAd->PermanentAddress[1], | |
755 | pAd->PermanentAddress[2], | |
756 | pAd->PermanentAddress[3], | |
757 | pAd->PermanentAddress[4], | |
758 | pAd->PermanentAddress[5])); | |
759 | if (pAd->bLocalAdminMAC == FALSE) { | |
91980990 GKH |
760 | MAC_DW0_STRUC csr2; |
761 | MAC_DW1_STRUC csr3; | |
96b3c83d BZ |
762 | COPY_MAC_ADDR(pAd->CurrentAddress, |
763 | pAd->PermanentAddress); | |
91980990 GKH |
764 | csr2.field.Byte0 = pAd->CurrentAddress[0]; |
765 | csr2.field.Byte1 = pAd->CurrentAddress[1]; | |
766 | csr2.field.Byte2 = pAd->CurrentAddress[2]; | |
767 | csr2.field.Byte3 = pAd->CurrentAddress[3]; | |
768 | RTMP_IO_WRITE32(pAd, MAC_ADDR_DW0, csr2.word); | |
769 | csr3.word = 0; | |
770 | csr3.field.Byte4 = pAd->CurrentAddress[4]; | |
771 | csr3.field.Byte5 = pAd->CurrentAddress[5]; | |
772 | csr3.field.U2MeMask = 0xff; | |
773 | RTMP_IO_WRITE32(pAd, MAC_ADDR_DW1, csr3.word); | |
96b3c83d BZ |
774 | DBGPRINT_RAW(RT_DEBUG_TRACE, |
775 | ("E2PROM MAC: =%02x:%02x:%02x:%02x:%02x:%02x\n", | |
776 | PRINT_MAC(pAd->PermanentAddress))); | |
91980990 GKH |
777 | } |
778 | } | |
779 | ||
ec278fa2 BZ |
780 | /* if not return early. cause fail at emulation. */ |
781 | /* Init the channel number for TX channel power */ | |
91980990 GKH |
782 | RTMPReadChannelPwr(pAd); |
783 | ||
ec278fa2 BZ |
784 | /* if E2PROM version mismatch with driver's expectation, then skip */ |
785 | /* all subsequent E2RPOM retieval and set a system error bit to notify GUI */ | |
91980990 | 786 | RT28xx_EEPROM_READ16(pAd, EEPROM_VERSION_OFFSET, Version.word); |
96b3c83d BZ |
787 | pAd->EepromVersion = |
788 | Version.field.Version + Version.field.FaeReleaseNumber * 256; | |
789 | DBGPRINT(RT_DEBUG_TRACE, | |
790 | ("E2PROM: Version = %d, FAE release #%d\n", | |
791 | Version.field.Version, Version.field.FaeReleaseNumber)); | |
792 | ||
793 | if (Version.field.Version > VALID_EEPROM_VERSION) { | |
794 | DBGPRINT_ERR(("E2PROM: WRONG VERSION 0x%x, should be %d\n", | |
795 | Version.field.Version, VALID_EEPROM_VERSION)); | |
91980990 GKH |
796 | /*pAd->SystemErrorBitmap |= 0x00000001; |
797 | ||
96b3c83d BZ |
798 | // hard-code default value when no proper E2PROM installed |
799 | pAd->bAutoTxAgcA = FALSE; | |
800 | pAd->bAutoTxAgcG = FALSE; | |
91980990 | 801 | |
96b3c83d BZ |
802 | // Default the channel power |
803 | for (i = 0; i < MAX_NUM_OF_CHANNELS; i++) | |
804 | pAd->TxPower[i].Power = DEFAULT_RF_TX_POWER; | |
91980990 | 805 | |
96b3c83d BZ |
806 | // Default the channel power |
807 | for (i = 0; i < MAX_NUM_OF_11JCHANNELS; i++) | |
808 | pAd->TxPower11J[i].Power = DEFAULT_RF_TX_POWER; | |
91980990 | 809 | |
96b3c83d BZ |
810 | for(i = 0; i < NUM_EEPROM_BBP_PARMS; i++) |
811 | pAd->EEPROMDefaultValue[i] = 0xffff; | |
812 | return; */ | |
91980990 | 813 | } |
ec278fa2 | 814 | /* Read BBP default value from EEPROM and store to array(EEPROMDefaultValue) in pAd */ |
91980990 GKH |
815 | RT28xx_EEPROM_READ16(pAd, EEPROM_NIC1_OFFSET, value); |
816 | pAd->EEPROMDefaultValue[0] = value; | |
817 | ||
818 | RT28xx_EEPROM_READ16(pAd, EEPROM_NIC2_OFFSET, value); | |
819 | pAd->EEPROMDefaultValue[1] = value; | |
820 | ||
ec278fa2 | 821 | RT28xx_EEPROM_READ16(pAd, 0x38, value); /* Country Region */ |
91980990 GKH |
822 | pAd->EEPROMDefaultValue[2] = value; |
823 | ||
96b3c83d BZ |
824 | for (i = 0; i < 8; i++) { |
825 | RT28xx_EEPROM_READ16(pAd, EEPROM_BBP_BASE_OFFSET + i * 2, | |
826 | value); | |
827 | pAd->EEPROMDefaultValue[i + 3] = value; | |
91980990 GKH |
828 | } |
829 | ||
ec278fa2 BZ |
830 | /* We have to parse NIC configuration 0 at here. */ |
831 | /* If TSSI did not have preloaded value, it should reset the TxAutoAgc to false */ | |
832 | /* Therefore, we have to read TxAutoAgc control beforehand. */ | |
833 | /* Read Tx AGC control bit */ | |
91980990 | 834 | Antenna.word = pAd->EEPROMDefaultValue[0]; |
96b3c83d | 835 | if (Antenna.word == 0xFFFF) { |
ca97b838 | 836 | #ifdef RT30xx |
96b3c83d | 837 | if (IS_RT3090(pAd) || IS_RT3390(pAd)) { |
59fe2d89 BZ |
838 | Antenna.word = 0; |
839 | Antenna.field.RfIcType = RFIC_3020; | |
840 | Antenna.field.TxPath = 1; | |
841 | Antenna.field.RxPath = 1; | |
96b3c83d | 842 | } else |
ec278fa2 | 843 | #endif /* RT30xx // */ |
59fe2d89 | 844 | { |
ca97b838 | 845 | |
96b3c83d BZ |
846 | Antenna.word = 0; |
847 | Antenna.field.RfIcType = RFIC_2820; | |
848 | Antenna.field.TxPath = 1; | |
849 | Antenna.field.RxPath = 2; | |
850 | DBGPRINT(RT_DEBUG_WARN, | |
851 | ("E2PROM error, hard code as 0x%04x\n", | |
852 | Antenna.word)); | |
59fe2d89 | 853 | } |
91980990 | 854 | } |
ec278fa2 | 855 | /* Choose the desired Tx&Rx stream. */ |
96b3c83d BZ |
856 | if ((pAd->CommonCfg.TxStream == 0) |
857 | || (pAd->CommonCfg.TxStream > Antenna.field.TxPath)) | |
91980990 GKH |
858 | pAd->CommonCfg.TxStream = Antenna.field.TxPath; |
859 | ||
96b3c83d BZ |
860 | if ((pAd->CommonCfg.RxStream == 0) |
861 | || (pAd->CommonCfg.RxStream > Antenna.field.RxPath)) { | |
91980990 GKH |
862 | pAd->CommonCfg.RxStream = Antenna.field.RxPath; |
863 | ||
864 | if ((pAd->MACVersion < RALINK_2883_VERSION) && | |
96b3c83d | 865 | (pAd->CommonCfg.RxStream > 2)) { |
ec278fa2 | 866 | /* only 2 Rx streams for RT2860 series */ |
91980990 GKH |
867 | pAd->CommonCfg.RxStream = 2; |
868 | } | |
869 | } | |
ec278fa2 BZ |
870 | /* 3*3 */ |
871 | /* read value from EEPROM and set them to CSR174 ~ 177 in chain0 ~ chain2 */ | |
872 | /* yet implement */ | |
96b3c83d | 873 | for (i = 0; i < 3; i++) { |
91980990 GKH |
874 | } |
875 | ||
876 | NicConfig2.word = pAd->EEPROMDefaultValue[1]; | |
877 | ||
91980990 | 878 | { |
96b3c83d | 879 | if ((NicConfig2.word & 0x00ff) == 0xff) { |
91980990 GKH |
880 | NicConfig2.word &= 0xff00; |
881 | } | |
882 | ||
96b3c83d | 883 | if ((NicConfig2.word >> 8) == 0xff) { |
91980990 GKH |
884 | NicConfig2.word &= 0x00ff; |
885 | } | |
886 | } | |
91980990 GKH |
887 | |
888 | if (NicConfig2.field.DynamicTxAgcControl == 1) | |
889 | pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = TRUE; | |
890 | else | |
891 | pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = FALSE; | |
892 | ||
96b3c83d BZ |
893 | DBGPRINT_RAW(RT_DEBUG_TRACE, |
894 | ("NICReadEEPROMParameters: RxPath = %d, TxPath = %d\n", | |
895 | Antenna.field.RxPath, Antenna.field.TxPath)); | |
91980990 | 896 | |
ec278fa2 | 897 | /* Save the antenna for future use */ |
91980990 GKH |
898 | pAd->Antenna.word = Antenna.word; |
899 | ||
ec278fa2 | 900 | /* Set the RfICType here, then we can initialize RFIC related operation callbacks */ |
51126deb BZ |
901 | pAd->Mlme.RealRxPath = (u8)Antenna.field.RxPath; |
902 | pAd->RfIcType = (u8)Antenna.field.RfIcType; | |
ca97b838 BZ |
903 | |
904 | #ifdef RTMP_RF_RW_SUPPORT | |
905 | RtmpChipOpsRFHook(pAd); | |
ec278fa2 | 906 | #endif /* RTMP_RF_RW_SUPPORT // */ |
ca97b838 BZ |
907 | |
908 | #ifdef RTMP_MAC_PCI | |
51126deb | 909 | sprintf((char *)pAd->nickname, "RT2860STA"); |
ec278fa2 | 910 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 | 911 | |
ec278fa2 BZ |
912 | /* */ |
913 | /* Reset PhyMode if we don't support 802.11a */ | |
914 | /* Only RFIC_2850 & RFIC_2750 support 802.11a */ | |
915 | /* */ | |
ca97b838 | 916 | if ((Antenna.field.RfIcType != RFIC_2850) |
96b3c83d BZ |
917 | && (Antenna.field.RfIcType != RFIC_2750) |
918 | && (Antenna.field.RfIcType != RFIC_3052)) { | |
91980990 | 919 | if ((pAd->CommonCfg.PhyMode == PHY_11ABG_MIXED) || |
96b3c83d | 920 | (pAd->CommonCfg.PhyMode == PHY_11A)) |
91980990 | 921 | pAd->CommonCfg.PhyMode = PHY_11BG_MIXED; |
96b3c83d BZ |
922 | else if ((pAd->CommonCfg.PhyMode == PHY_11ABGN_MIXED) || |
923 | (pAd->CommonCfg.PhyMode == PHY_11AN_MIXED) || | |
924 | (pAd->CommonCfg.PhyMode == PHY_11AGN_MIXED) || | |
925 | (pAd->CommonCfg.PhyMode == PHY_11N_5G)) | |
91980990 | 926 | pAd->CommonCfg.PhyMode = PHY_11BGN_MIXED; |
91980990 | 927 | } |
ec278fa2 BZ |
928 | /* Read TSSI reference and TSSI boundary for temperature compensation. This is ugly */ |
929 | /* 0. 11b/g */ | |
91980990 GKH |
930 | { |
931 | /* these are tempature reference value (0x00 ~ 0xFE) | |
932 | ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0 | |
933 | TssiPlusBoundaryG [4] [3] [2] [1] [0] (smaller) + | |
934 | TssiMinusBoundaryG[0] [1] [2] [3] [4] (larger) */ | |
935 | RT28xx_EEPROM_READ16(pAd, 0x6E, Power.word); | |
936 | pAd->TssiMinusBoundaryG[4] = Power.field.Byte0; | |
937 | pAd->TssiMinusBoundaryG[3] = Power.field.Byte1; | |
938 | RT28xx_EEPROM_READ16(pAd, 0x70, Power.word); | |
939 | pAd->TssiMinusBoundaryG[2] = Power.field.Byte0; | |
940 | pAd->TssiMinusBoundaryG[1] = Power.field.Byte1; | |
941 | RT28xx_EEPROM_READ16(pAd, 0x72, Power.word); | |
96b3c83d | 942 | pAd->TssiRefG = Power.field.Byte0; /* reference value [0] */ |
91980990 GKH |
943 | pAd->TssiPlusBoundaryG[1] = Power.field.Byte1; |
944 | RT28xx_EEPROM_READ16(pAd, 0x74, Power.word); | |
945 | pAd->TssiPlusBoundaryG[2] = Power.field.Byte0; | |
946 | pAd->TssiPlusBoundaryG[3] = Power.field.Byte1; | |
947 | RT28xx_EEPROM_READ16(pAd, 0x76, Power.word); | |
948 | pAd->TssiPlusBoundaryG[4] = Power.field.Byte0; | |
949 | pAd->TxAgcStepG = Power.field.Byte1; | |
950 | pAd->TxAgcCompensateG = 0; | |
951 | pAd->TssiMinusBoundaryG[0] = pAd->TssiRefG; | |
96b3c83d | 952 | pAd->TssiPlusBoundaryG[0] = pAd->TssiRefG; |
91980990 | 953 | |
ec278fa2 | 954 | /* Disable TxAgc if the based value is not right */ |
91980990 GKH |
955 | if (pAd->TssiRefG == 0xff) |
956 | pAd->bAutoTxAgcG = FALSE; | |
957 | ||
96b3c83d BZ |
958 | DBGPRINT(RT_DEBUG_TRACE, |
959 | ("E2PROM: G Tssi[-4 .. +4] = %d %d %d %d - %d -%d %d %d %d, step=%d, tuning=%d\n", | |
960 | pAd->TssiMinusBoundaryG[4], | |
961 | pAd->TssiMinusBoundaryG[3], | |
962 | pAd->TssiMinusBoundaryG[2], | |
963 | pAd->TssiMinusBoundaryG[1], pAd->TssiRefG, | |
964 | pAd->TssiPlusBoundaryG[1], pAd->TssiPlusBoundaryG[2], | |
965 | pAd->TssiPlusBoundaryG[3], pAd->TssiPlusBoundaryG[4], | |
966 | pAd->TxAgcStepG, pAd->bAutoTxAgcG)); | |
91980990 | 967 | } |
ec278fa2 | 968 | /* 1. 11a */ |
91980990 GKH |
969 | { |
970 | RT28xx_EEPROM_READ16(pAd, 0xD4, Power.word); | |
971 | pAd->TssiMinusBoundaryA[4] = Power.field.Byte0; | |
972 | pAd->TssiMinusBoundaryA[3] = Power.field.Byte1; | |
973 | RT28xx_EEPROM_READ16(pAd, 0xD6, Power.word); | |
974 | pAd->TssiMinusBoundaryA[2] = Power.field.Byte0; | |
975 | pAd->TssiMinusBoundaryA[1] = Power.field.Byte1; | |
976 | RT28xx_EEPROM_READ16(pAd, 0xD8, Power.word); | |
96b3c83d | 977 | pAd->TssiRefA = Power.field.Byte0; |
91980990 GKH |
978 | pAd->TssiPlusBoundaryA[1] = Power.field.Byte1; |
979 | RT28xx_EEPROM_READ16(pAd, 0xDA, Power.word); | |
980 | pAd->TssiPlusBoundaryA[2] = Power.field.Byte0; | |
981 | pAd->TssiPlusBoundaryA[3] = Power.field.Byte1; | |
982 | RT28xx_EEPROM_READ16(pAd, 0xDC, Power.word); | |
983 | pAd->TssiPlusBoundaryA[4] = Power.field.Byte0; | |
984 | pAd->TxAgcStepA = Power.field.Byte1; | |
985 | pAd->TxAgcCompensateA = 0; | |
986 | pAd->TssiMinusBoundaryA[0] = pAd->TssiRefA; | |
96b3c83d | 987 | pAd->TssiPlusBoundaryA[0] = pAd->TssiRefA; |
91980990 | 988 | |
ec278fa2 | 989 | /* Disable TxAgc if the based value is not right */ |
91980990 GKH |
990 | if (pAd->TssiRefA == 0xff) |
991 | pAd->bAutoTxAgcA = FALSE; | |
992 | ||
96b3c83d BZ |
993 | DBGPRINT(RT_DEBUG_TRACE, |
994 | ("E2PROM: A Tssi[-4 .. +4] = %d %d %d %d - %d -%d %d %d %d, step=%d, tuning=%d\n", | |
995 | pAd->TssiMinusBoundaryA[4], | |
996 | pAd->TssiMinusBoundaryA[3], | |
997 | pAd->TssiMinusBoundaryA[2], | |
998 | pAd->TssiMinusBoundaryA[1], pAd->TssiRefA, | |
999 | pAd->TssiPlusBoundaryA[1], pAd->TssiPlusBoundaryA[2], | |
1000 | pAd->TssiPlusBoundaryA[3], pAd->TssiPlusBoundaryA[4], | |
1001 | pAd->TxAgcStepA, pAd->bAutoTxAgcA)); | |
91980990 GKH |
1002 | } |
1003 | pAd->BbpRssiToDbmDelta = 0x0; | |
1004 | ||
ec278fa2 | 1005 | /* Read frequency offset setting for RF */ |
91980990 GKH |
1006 | RT28xx_EEPROM_READ16(pAd, EEPROM_FREQ_OFFSET, value); |
1007 | if ((value & 0x00FF) != 0x00FF) | |
51126deb | 1008 | pAd->RfFreqOffset = (unsigned long)(value & 0x00FF); |
91980990 GKH |
1009 | else |
1010 | pAd->RfFreqOffset = 0; | |
96b3c83d BZ |
1011 | DBGPRINT(RT_DEBUG_TRACE, |
1012 | ("E2PROM: RF FreqOffset=0x%lx \n", pAd->RfFreqOffset)); | |
91980990 | 1013 | |
ec278fa2 BZ |
1014 | /*CountryRegion byte offset (38h) */ |
1015 | value = pAd->EEPROMDefaultValue[2] >> 8; /* 2.4G band */ | |
1016 | value2 = pAd->EEPROMDefaultValue[2] & 0x00FF; /* 5G band */ | |
91980990 | 1017 | |
96b3c83d BZ |
1018 | if ((value <= REGION_MAXIMUM_BG_BAND) |
1019 | && (value2 <= REGION_MAXIMUM_A_BAND)) { | |
51126deb BZ |
1020 | pAd->CommonCfg.CountryRegion = ((u8)value) | 0x80; |
1021 | pAd->CommonCfg.CountryRegionForABand = ((u8)value2) | 0x80; | |
91980990 GKH |
1022 | TmpPhy = pAd->CommonCfg.PhyMode; |
1023 | pAd->CommonCfg.PhyMode = 0xff; | |
1024 | RTMPSetPhyMode(pAd, TmpPhy); | |
91980990 | 1025 | SetCommonHT(pAd); |
91980990 | 1026 | } |
ec278fa2 BZ |
1027 | /* */ |
1028 | /* Get RSSI Offset on EEPROM 0x9Ah & 0x9Ch. */ | |
1029 | /* The valid value are (-10 ~ 10) */ | |
1030 | /* */ | |
91980990 GKH |
1031 | RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET, value); |
1032 | pAd->BGRssiOffset0 = value & 0x00ff; | |
1033 | pAd->BGRssiOffset1 = (value >> 8); | |
96b3c83d | 1034 | RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET + 2, value); |
91980990 GKH |
1035 | pAd->BGRssiOffset2 = value & 0x00ff; |
1036 | pAd->ALNAGain1 = (value >> 8); | |
1037 | RT28xx_EEPROM_READ16(pAd, EEPROM_LNA_OFFSET, value); | |
1038 | pAd->BLNAGain = value & 0x00ff; | |
1039 | pAd->ALNAGain0 = (value >> 8); | |
1040 | ||
ec278fa2 | 1041 | /* Validate 11b/g RSSI_0 offset. */ |
91980990 GKH |
1042 | if ((pAd->BGRssiOffset0 < -10) || (pAd->BGRssiOffset0 > 10)) |
1043 | pAd->BGRssiOffset0 = 0; | |
1044 | ||
ec278fa2 | 1045 | /* Validate 11b/g RSSI_1 offset. */ |
91980990 GKH |
1046 | if ((pAd->BGRssiOffset1 < -10) || (pAd->BGRssiOffset1 > 10)) |
1047 | pAd->BGRssiOffset1 = 0; | |
1048 | ||
ec278fa2 | 1049 | /* Validate 11b/g RSSI_2 offset. */ |
91980990 GKH |
1050 | if ((pAd->BGRssiOffset2 < -10) || (pAd->BGRssiOffset2 > 10)) |
1051 | pAd->BGRssiOffset2 = 0; | |
1052 | ||
1053 | RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_A_OFFSET, value); | |
1054 | pAd->ARssiOffset0 = value & 0x00ff; | |
1055 | pAd->ARssiOffset1 = (value >> 8); | |
96b3c83d | 1056 | RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_A_OFFSET + 2), value); |
91980990 GKH |
1057 | pAd->ARssiOffset2 = value & 0x00ff; |
1058 | pAd->ALNAGain2 = (value >> 8); | |
1059 | ||
51126deb | 1060 | if (((u8)pAd->ALNAGain1 == 0xFF) || (pAd->ALNAGain1 == 0x00)) |
91980990 | 1061 | pAd->ALNAGain1 = pAd->ALNAGain0; |
51126deb | 1062 | if (((u8)pAd->ALNAGain2 == 0xFF) || (pAd->ALNAGain2 == 0x00)) |
91980990 GKH |
1063 | pAd->ALNAGain2 = pAd->ALNAGain0; |
1064 | ||
ec278fa2 | 1065 | /* Validate 11a RSSI_0 offset. */ |
91980990 GKH |
1066 | if ((pAd->ARssiOffset0 < -10) || (pAd->ARssiOffset0 > 10)) |
1067 | pAd->ARssiOffset0 = 0; | |
1068 | ||
ec278fa2 | 1069 | /* Validate 11a RSSI_1 offset. */ |
91980990 GKH |
1070 | if ((pAd->ARssiOffset1 < -10) || (pAd->ARssiOffset1 > 10)) |
1071 | pAd->ARssiOffset1 = 0; | |
1072 | ||
ec278fa2 | 1073 | /*Validate 11a RSSI_2 offset. */ |
91980990 GKH |
1074 | if ((pAd->ARssiOffset2 < -10) || (pAd->ARssiOffset2 > 10)) |
1075 | pAd->ARssiOffset2 = 0; | |
1076 | ||
ca97b838 | 1077 | #ifdef RT30xx |
ec278fa2 BZ |
1078 | /* */ |
1079 | /* Get TX mixer gain setting */ | |
1080 | /* 0xff are invalid value */ | |
1081 | /* Note: RT30xX default value is 0x00 and will program to RF_R17 only when this value is not zero. */ | |
1082 | /* RT359X default value is 0x02 */ | |
1083 | /* */ | |
96b3c83d | 1084 | if (IS_RT30xx(pAd) || IS_RT3572(pAd)) { |
ca97b838 BZ |
1085 | RT28xx_EEPROM_READ16(pAd, EEPROM_TXMIXER_GAIN_2_4G, value); |
1086 | pAd->TxMixerGain24G = 0; | |
1087 | value &= 0x00ff; | |
96b3c83d | 1088 | if (value != 0xff) { |
ca97b838 | 1089 | value &= 0x07; |
51126deb | 1090 | pAd->TxMixerGain24G = (u8)value; |
ca97b838 BZ |
1091 | } |
1092 | } | |
ec278fa2 | 1093 | #endif /* RT30xx // */ |
ca97b838 | 1094 | |
ec278fa2 BZ |
1095 | /* */ |
1096 | /* Get LED Setting. */ | |
1097 | /* */ | |
91980990 | 1098 | RT28xx_EEPROM_READ16(pAd, 0x3a, value); |
96b3c83d | 1099 | pAd->LedCntl.word = (value >> 8); |
91980990 GKH |
1100 | RT28xx_EEPROM_READ16(pAd, EEPROM_LED1_OFFSET, value); |
1101 | pAd->Led1 = value; | |
1102 | RT28xx_EEPROM_READ16(pAd, EEPROM_LED2_OFFSET, value); | |
1103 | pAd->Led2 = value; | |
1104 | RT28xx_EEPROM_READ16(pAd, EEPROM_LED3_OFFSET, value); | |
1105 | pAd->Led3 = value; | |
1106 | ||
1107 | RTMPReadTxPwrPerRate(pAd); | |
1108 | ||
ca97b838 BZ |
1109 | #ifdef RT30xx |
1110 | #ifdef RTMP_EFUSE_SUPPORT | |
1111 | RtmpEfuseSupportCheck(pAd); | |
ec278fa2 BZ |
1112 | #endif /* RTMP_EFUSE_SUPPORT // */ |
1113 | #endif /* RT30xx // */ | |
ca97b838 | 1114 | |
91980990 GKH |
1115 | DBGPRINT(RT_DEBUG_TRACE, ("<-- NICReadEEPROMParameters\n")); |
1116 | } | |
1117 | ||
1118 | /* | |
1119 | ======================================================================== | |
1120 | ||
1121 | Routine Description: | |
1122 | Set default value from EEPROM | |
1123 | ||
1124 | Arguments: | |
1125 | Adapter Pointer to our adapter | |
1126 | ||
1127 | Return Value: | |
1128 | None | |
1129 | ||
1130 | IRQL = PASSIVE_LEVEL | |
1131 | ||
1132 | Note: | |
1133 | ||
1134 | ======================================================================== | |
1135 | */ | |
62eb734b | 1136 | void NICInitAsicFromEEPROM(struct rt_rtmp_adapter *pAd) |
91980990 | 1137 | { |
51126deb BZ |
1138 | u32 data = 0; |
1139 | u8 BBPR1 = 0; | |
1140 | u16 i; | |
ec278fa2 | 1141 | /* EEPROM_ANTENNA_STRUC Antenna; */ |
96b3c83d | 1142 | EEPROM_NIC_CONFIG2_STRUC NicConfig2; |
51126deb | 1143 | u8 BBPR3 = 0; |
91980990 GKH |
1144 | |
1145 | DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitAsicFromEEPROM\n")); | |
96b3c83d | 1146 | for (i = 3; i < NUM_EEPROM_BBP_PARMS; i++) { |
51126deb | 1147 | u8 BbpRegIdx, BbpValue; |
91980990 | 1148 | |
96b3c83d BZ |
1149 | if ((pAd->EEPROMDefaultValue[i] != 0xFFFF) |
1150 | && (pAd->EEPROMDefaultValue[i] != 0)) { | |
51126deb BZ |
1151 | BbpRegIdx = (u8)(pAd->EEPROMDefaultValue[i] >> 8); |
1152 | BbpValue = (u8)(pAd->EEPROMDefaultValue[i] & 0xff); | |
91980990 GKH |
1153 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BbpRegIdx, BbpValue); |
1154 | } | |
1155 | } | |
1156 | ||
91980990 GKH |
1157 | NicConfig2.word = pAd->EEPROMDefaultValue[1]; |
1158 | ||
59fe2d89 | 1159 | { |
96b3c83d | 1160 | if ((NicConfig2.word & 0x00ff) == 0xff) { |
59fe2d89 BZ |
1161 | NicConfig2.word &= 0xff00; |
1162 | } | |
91980990 | 1163 | |
96b3c83d | 1164 | if ((NicConfig2.word >> 8) == 0xff) { |
59fe2d89 BZ |
1165 | NicConfig2.word &= 0x00ff; |
1166 | } | |
1167 | } | |
ca97b838 | 1168 | |
ec278fa2 | 1169 | /* Save the antenna for future use */ |
91980990 GKH |
1170 | pAd->NicConfig2.word = NicConfig2.word; |
1171 | ||
ca97b838 | 1172 | #ifdef RT30xx |
ec278fa2 | 1173 | /* set default antenna as main */ |
59fe2d89 BZ |
1174 | if (pAd->RfIcType == RFIC_3020) |
1175 | AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); | |
ec278fa2 | 1176 | #endif /* RT30xx // */ |
ca97b838 | 1177 | |
ec278fa2 BZ |
1178 | /* */ |
1179 | /* Send LED Setting to MCU. */ | |
1180 | /* */ | |
96b3c83d | 1181 | if (pAd->LedCntl.word == 0xFF) { |
91980990 GKH |
1182 | pAd->LedCntl.word = 0x01; |
1183 | pAd->Led1 = 0x5555; | |
1184 | pAd->Led2 = 0x2221; | |
59fe2d89 | 1185 | |
ca97b838 BZ |
1186 | #ifdef RTMP_MAC_PCI |
1187 | pAd->Led3 = 0xA9F8; | |
ec278fa2 | 1188 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 | 1189 | #ifdef RTMP_MAC_USB |
59fe2d89 | 1190 | pAd->Led3 = 0x5627; |
ec278fa2 | 1191 | #endif /* RTMP_MAC_USB // */ |
91980990 GKH |
1192 | } |
1193 | ||
51126deb BZ |
1194 | AsicSendCommandToMcu(pAd, 0x52, 0xff, (u8)pAd->Led1, |
1195 | (u8)(pAd->Led1 >> 8)); | |
1196 | AsicSendCommandToMcu(pAd, 0x53, 0xff, (u8)pAd->Led2, | |
1197 | (u8)(pAd->Led2 >> 8)); | |
1198 | AsicSendCommandToMcu(pAd, 0x54, 0xff, (u8)pAd->Led3, | |
1199 | (u8)(pAd->Led3 >> 8)); | |
ca97b838 BZ |
1200 | AsicSendCommandToMcu(pAd, 0x51, 0xff, 0, pAd->LedCntl.field.Polarity); |
1201 | ||
1202 | pAd->LedIndicatorStrength = 0xFF; | |
ec278fa2 | 1203 | RTMPSetSignalLED(pAd, -100); /* Force signal strength Led to be turned off, before link up */ |
91980990 | 1204 | |
91980990 | 1205 | { |
ec278fa2 | 1206 | /* Read Hardware controlled Radio state enable bit */ |
96b3c83d | 1207 | if (NicConfig2.field.HardwareRadioControl == 1) { |
91980990 GKH |
1208 | pAd->StaCfg.bHardwareRadio = TRUE; |
1209 | ||
ec278fa2 | 1210 | /* Read GPIO pin2 as Hardware controlled radio state */ |
91980990 | 1211 | RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &data); |
96b3c83d | 1212 | if ((data & 0x04) == 0) { |
91980990 GKH |
1213 | pAd->StaCfg.bHwRadio = FALSE; |
1214 | pAd->StaCfg.bRadio = FALSE; | |
ec278fa2 | 1215 | /* RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x00001818); */ |
91980990 GKH |
1216 | RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); |
1217 | } | |
96b3c83d | 1218 | } else |
91980990 GKH |
1219 | pAd->StaCfg.bHardwareRadio = FALSE; |
1220 | ||
96b3c83d | 1221 | if (pAd->StaCfg.bRadio == FALSE) { |
91980990 | 1222 | RTMPSetLED(pAd, LED_RADIO_OFF); |
96b3c83d | 1223 | } else { |
91980990 | 1224 | RTMPSetLED(pAd, LED_RADIO_ON); |
ca97b838 | 1225 | #ifdef RTMP_MAC_PCI |
e44fd1cf | 1226 | #ifdef RT3090 |
96b3c83d BZ |
1227 | AsicSendCommandToMcu(pAd, 0x30, PowerRadioOffCID, 0xff, |
1228 | 0x02); | |
e44fd1cf | 1229 | AsicCheckCommanOk(pAd, PowerRadioOffCID); |
ec278fa2 | 1230 | #endif /* RT3090 // */ |
e44fd1cf | 1231 | #ifndef RT3090 |
91980990 | 1232 | AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02); |
ec278fa2 | 1233 | #endif /* RT3090 // */ |
96b3c83d BZ |
1234 | AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, |
1235 | 0x00); | |
ec278fa2 | 1236 | /* 2-1. wait command ok. */ |
91980990 | 1237 | AsicCheckCommanOk(pAd, PowerWakeCID); |
ec278fa2 | 1238 | #endif /* RTMP_MAC_PCI // */ |
91980990 GKH |
1239 | } |
1240 | } | |
91980990 | 1241 | |
e44fd1cf BZ |
1242 | #ifdef RTMP_MAC_PCI |
1243 | #ifdef RT30xx | |
96b3c83d | 1244 | if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) { |
62eb734b | 1245 | struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps; |
96b3c83d BZ |
1246 | if (pChipOps->AsicReverseRfFromSleepMode) |
1247 | pChipOps->AsicReverseRfFromSleepMode(pAd); | |
1248 | } | |
ec278fa2 BZ |
1249 | /* 3090 MCU Wakeup command needs more time to be stable. */ |
1250 | /* Before stable, don't issue other MCU command to prevent from firmware error. */ | |
96b3c83d BZ |
1251 | |
1252 | if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) | |
1253 | && IS_VERSION_AFTER_F(pAd) | |
1254 | && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3) | |
1255 | && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) { | |
1256 | DBGPRINT(RT_DEBUG_TRACE, ("%s, release Mcu Lock\n", __func__)); | |
1257 | RTMP_SEM_LOCK(&pAd->McuCmdLock); | |
1258 | pAd->brt30xxBanMcuCmd = FALSE; | |
1259 | RTMP_SEM_UNLOCK(&pAd->McuCmdLock); | |
1260 | } | |
ec278fa2 BZ |
1261 | #endif /* RT30xx // */ |
1262 | #endif /* RTMP_MAC_PCI // */ | |
e44fd1cf | 1263 | |
ec278fa2 | 1264 | /* Turn off patching for cardbus controller */ |
96b3c83d | 1265 | if (NicConfig2.field.CardbusAcceleration == 1) { |
ec278fa2 | 1266 | /* pAd->bTest1 = TRUE; */ |
91980990 GKH |
1267 | } |
1268 | ||
1269 | if (NicConfig2.field.DynamicTxAgcControl == 1) | |
1270 | pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = TRUE; | |
1271 | else | |
1272 | pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = FALSE; | |
ec278fa2 BZ |
1273 | /* */ |
1274 | /* Since BBP has been progamed, to make sure BBP setting will be */ | |
1275 | /* upate inside of AsicAntennaSelect, so reset to UNKNOWN_BAND!! */ | |
1276 | /* */ | |
91980990 GKH |
1277 | pAd->CommonCfg.BandState = UNKNOWN_BAND; |
1278 | ||
1279 | RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3); | |
1280 | BBPR3 &= (~0x18); | |
96b3c83d | 1281 | if (pAd->Antenna.field.RxPath == 3) { |
91980990 | 1282 | BBPR3 |= (0x10); |
96b3c83d | 1283 | } else if (pAd->Antenna.field.RxPath == 2) { |
91980990 | 1284 | BBPR3 |= (0x8); |
96b3c83d | 1285 | } else if (pAd->Antenna.field.RxPath == 1) { |
91980990 GKH |
1286 | BBPR3 |= (0x0); |
1287 | } | |
1288 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3); | |
1289 | ||
91980990 | 1290 | { |
ec278fa2 | 1291 | /* Handle the difference when 1T */ |
91980990 | 1292 | RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BBPR1); |
96b3c83d BZ |
1293 | if (pAd->Antenna.field.TxPath == 1) { |
1294 | BBPR1 &= (~0x18); | |
91980990 GKH |
1295 | } |
1296 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BBPR1); | |
1297 | ||
96b3c83d BZ |
1298 | DBGPRINT(RT_DEBUG_TRACE, |
1299 | ("Use Hw Radio Control Pin=%d; if used Pin=%d;\n", | |
1300 | pAd->CommonCfg.bHardwareRadio, | |
1301 | pAd->CommonCfg.bHardwareRadio)); | |
91980990 | 1302 | } |
6a28a69a | 1303 | |
ca97b838 BZ |
1304 | #ifdef RTMP_MAC_USB |
1305 | #ifdef RT30xx | |
ec278fa2 | 1306 | /* update registers from EEPROM for RT3071 or later(3572/3592). */ |
ca97b838 | 1307 | |
96b3c83d | 1308 | if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) { |
51126deb BZ |
1309 | u8 RegIdx, RegValue; |
1310 | u16 value; | |
ca97b838 | 1311 | |
ec278fa2 | 1312 | /* after RT3071, write BBP from EEPROM 0xF0 to 0x102 */ |
96b3c83d | 1313 | for (i = 0xF0; i <= 0x102; i = i + 2) { |
ca97b838 BZ |
1314 | value = 0xFFFF; |
1315 | RT28xx_EEPROM_READ16(pAd, i, value); | |
96b3c83d | 1316 | if ((value != 0xFFFF) && (value != 0)) { |
51126deb BZ |
1317 | RegIdx = (u8)(value >> 8); |
1318 | RegValue = (u8)(value & 0xff); | |
96b3c83d BZ |
1319 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, RegIdx, |
1320 | RegValue); | |
1321 | DBGPRINT(RT_DEBUG_TRACE, | |
1322 | ("Update BBP Registers from EEPROM(0x%0x), BBP(0x%x) = 0x%x\n", | |
1323 | i, RegIdx, RegValue)); | |
ca97b838 BZ |
1324 | } |
1325 | } | |
1326 | ||
ec278fa2 | 1327 | /* after RT3071, write RF from EEPROM 0x104 to 0x116 */ |
96b3c83d | 1328 | for (i = 0x104; i <= 0x116; i = i + 2) { |
ca97b838 BZ |
1329 | value = 0xFFFF; |
1330 | RT28xx_EEPROM_READ16(pAd, i, value); | |
96b3c83d | 1331 | if ((value != 0xFFFF) && (value != 0)) { |
51126deb BZ |
1332 | RegIdx = (u8)(value >> 8); |
1333 | RegValue = (u8)(value & 0xff); | |
ca97b838 | 1334 | RT30xxWriteRFRegister(pAd, RegIdx, RegValue); |
96b3c83d BZ |
1335 | DBGPRINT(RT_DEBUG_TRACE, |
1336 | ("Update RF Registers from EEPROM0x%x), BBP(0x%x) = 0x%x\n", | |
1337 | i, RegIdx, RegValue)); | |
ca97b838 BZ |
1338 | } |
1339 | } | |
1340 | } | |
ec278fa2 BZ |
1341 | #endif /* RT30xx // */ |
1342 | #endif /* RTMP_MAC_USB // */ | |
ca97b838 | 1343 | |
96b3c83d BZ |
1344 | DBGPRINT(RT_DEBUG_TRACE, |
1345 | ("TxPath = %d, RxPath = %d, RFIC=%d, Polar+LED mode=%x\n", | |
1346 | pAd->Antenna.field.TxPath, pAd->Antenna.field.RxPath, | |
1347 | pAd->RfIcType, pAd->LedCntl.word)); | |
91980990 GKH |
1348 | DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitAsicFromEEPROM\n")); |
1349 | } | |
1350 | ||
1351 | /* | |
1352 | ======================================================================== | |
1353 | ||
1354 | Routine Description: | |
1355 | Initialize NIC hardware | |
1356 | ||
1357 | Arguments: | |
1358 | Adapter Pointer to our adapter | |
1359 | ||
1360 | Return Value: | |
1361 | None | |
1362 | ||
1363 | IRQL = PASSIVE_LEVEL | |
1364 | ||
1365 | Note: | |
1366 | ||
1367 | ======================================================================== | |
1368 | */ | |
62eb734b | 1369 | int NICInitializeAdapter(struct rt_rtmp_adapter *pAd, IN BOOLEAN bHardReset) |
91980990 | 1370 | { |
51126deb | 1371 | int Status = NDIS_STATUS_SUCCESS; |
96b3c83d | 1372 | WPDMA_GLO_CFG_STRUC GloCfg; |
ca97b838 | 1373 | #ifdef RTMP_MAC_PCI |
51126deb | 1374 | u32 Value; |
96b3c83d | 1375 | DELAY_INT_CFG_STRUC IntCfg; |
ec278fa2 BZ |
1376 | #endif /* RTMP_MAC_PCI // */ |
1377 | /* INT_MASK_CSR_STRUC IntMask; */ | |
51126deb | 1378 | unsigned long i = 0, j = 0; |
96b3c83d | 1379 | AC_TXOP_CSR0_STRUC csr0; |
91980990 GKH |
1380 | |
1381 | DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAdapter\n")); | |
1382 | ||
ec278fa2 | 1383 | /* 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits: */ |
91980990 GKH |
1384 | retry: |
1385 | i = 0; | |
96b3c83d | 1386 | do { |
91980990 | 1387 | RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); |
96b3c83d BZ |
1388 | if ((GloCfg.field.TxDMABusy == 0) |
1389 | && (GloCfg.field.RxDMABusy == 0)) | |
91980990 GKH |
1390 | break; |
1391 | ||
1392 | RTMPusecDelay(1000); | |
1393 | i++; | |
96b3c83d BZ |
1394 | } while (i < 100); |
1395 | DBGPRINT(RT_DEBUG_TRACE, | |
1396 | ("<== DMA offset 0x208 = 0x%x\n", GloCfg.word)); | |
91980990 | 1397 | GloCfg.word &= 0xff0; |
96b3c83d | 1398 | GloCfg.field.EnTXWriteBackDDONE = 1; |
91980990 GKH |
1399 | RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); |
1400 | ||
ec278fa2 | 1401 | /* Record HW Beacon offset */ |
91980990 GKH |
1402 | pAd->BeaconOffset[0] = HW_BEACON_BASE0; |
1403 | pAd->BeaconOffset[1] = HW_BEACON_BASE1; | |
1404 | pAd->BeaconOffset[2] = HW_BEACON_BASE2; | |
1405 | pAd->BeaconOffset[3] = HW_BEACON_BASE3; | |
1406 | pAd->BeaconOffset[4] = HW_BEACON_BASE4; | |
1407 | pAd->BeaconOffset[5] = HW_BEACON_BASE5; | |
1408 | pAd->BeaconOffset[6] = HW_BEACON_BASE6; | |
1409 | pAd->BeaconOffset[7] = HW_BEACON_BASE7; | |
1410 | ||
ec278fa2 BZ |
1411 | /* */ |
1412 | /* write all shared Ring's base address into ASIC */ | |
1413 | /* */ | |
91980990 | 1414 | |
ec278fa2 BZ |
1415 | /* asic simulation sequence put this ahead before loading firmware. */ |
1416 | /* pbf hardware reset */ | |
ca97b838 | 1417 | #ifdef RTMP_MAC_PCI |
ec278fa2 | 1418 | RTMP_IO_WRITE32(pAd, WPDMA_RST_IDX, 0x1003f); /* 0x10000 for reset rx, 0x3f resets all 6 tx rings. */ |
91980990 GKH |
1419 | RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe1f); |
1420 | RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe00); | |
ec278fa2 | 1421 | #endif /* RTMP_MAC_PCI // */ |
91980990 | 1422 | |
ec278fa2 | 1423 | /* Initialze ASIC for TX & Rx operation */ |
96b3c83d BZ |
1424 | if (NICInitializeAsic(pAd, bHardReset) != NDIS_STATUS_SUCCESS) { |
1425 | if (j++ == 0) { | |
91980990 GKH |
1426 | NICLoadFirmware(pAd); |
1427 | goto retry; | |
1428 | } | |
1429 | return NDIS_STATUS_FAILURE; | |
1430 | } | |
1431 | ||
ca97b838 | 1432 | #ifdef RTMP_MAC_PCI |
ec278fa2 | 1433 | /* Write AC_BK base address register */ |
96b3c83d BZ |
1434 | Value = |
1435 | RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BK].Cell[0].AllocPa); | |
91980990 GKH |
1436 | RTMP_IO_WRITE32(pAd, TX_BASE_PTR1, Value); |
1437 | DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR1 : 0x%x\n", Value)); | |
1438 | ||
ec278fa2 | 1439 | /* Write AC_BE base address register */ |
96b3c83d BZ |
1440 | Value = |
1441 | RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BE].Cell[0].AllocPa); | |
91980990 GKH |
1442 | RTMP_IO_WRITE32(pAd, TX_BASE_PTR0, Value); |
1443 | DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR0 : 0x%x\n", Value)); | |
1444 | ||
ec278fa2 | 1445 | /* Write AC_VI base address register */ |
96b3c83d BZ |
1446 | Value = |
1447 | RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_VI].Cell[0].AllocPa); | |
91980990 GKH |
1448 | RTMP_IO_WRITE32(pAd, TX_BASE_PTR2, Value); |
1449 | DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR2 : 0x%x\n", Value)); | |
1450 | ||
ec278fa2 | 1451 | /* Write AC_VO base address register */ |
96b3c83d BZ |
1452 | Value = |
1453 | RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_VO].Cell[0].AllocPa); | |
91980990 GKH |
1454 | RTMP_IO_WRITE32(pAd, TX_BASE_PTR3, Value); |
1455 | DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR3 : 0x%x\n", Value)); | |
1456 | ||
ec278fa2 | 1457 | /* Write MGMT_BASE_CSR register */ |
91980990 GKH |
1458 | Value = RTMP_GetPhysicalAddressLow(pAd->MgmtRing.Cell[0].AllocPa); |
1459 | RTMP_IO_WRITE32(pAd, TX_BASE_PTR5, Value); | |
1460 | DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR5 : 0x%x\n", Value)); | |
1461 | ||
ec278fa2 | 1462 | /* Write RX_BASE_CSR register */ |
91980990 GKH |
1463 | Value = RTMP_GetPhysicalAddressLow(pAd->RxRing.Cell[0].AllocPa); |
1464 | RTMP_IO_WRITE32(pAd, RX_BASE_PTR, Value); | |
1465 | DBGPRINT(RT_DEBUG_TRACE, ("--> RX_BASE_PTR : 0x%x\n", Value)); | |
1466 | ||
ec278fa2 | 1467 | /* Init RX Ring index pointer */ |
91980990 | 1468 | pAd->RxRing.RxSwReadIdx = 0; |
96b3c83d | 1469 | pAd->RxRing.RxCpuIdx = RX_RING_SIZE - 1; |
91980990 GKH |
1470 | RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx); |
1471 | ||
ec278fa2 | 1472 | /* Init TX rings index pointer */ |
91980990 | 1473 | { |
96b3c83d | 1474 | for (i = 0; i < NUM_OF_TX_RING; i++) { |
91980990 GKH |
1475 | pAd->TxRing[i].TxSwFreeIdx = 0; |
1476 | pAd->TxRing[i].TxCpuIdx = 0; | |
96b3c83d BZ |
1477 | RTMP_IO_WRITE32(pAd, (TX_CTX_IDX0 + i * 0x10), |
1478 | pAd->TxRing[i].TxCpuIdx); | |
91980990 GKH |
1479 | } |
1480 | } | |
1481 | ||
ec278fa2 | 1482 | /* init MGMT ring index pointer */ |
91980990 GKH |
1483 | pAd->MgmtRing.TxSwFreeIdx = 0; |
1484 | pAd->MgmtRing.TxCpuIdx = 0; | |
96b3c83d | 1485 | RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx); |
91980990 | 1486 | |
ec278fa2 BZ |
1487 | /* */ |
1488 | /* set each Ring's SIZE into ASIC. Descriptor Size is fixed by design. */ | |
1489 | /* */ | |
91980990 | 1490 | |
ec278fa2 | 1491 | /* Write TX_RING_CSR0 register */ |
91980990 GKH |
1492 | Value = TX_RING_SIZE; |
1493 | RTMP_IO_WRITE32(pAd, TX_MAX_CNT0, Value); | |
1494 | RTMP_IO_WRITE32(pAd, TX_MAX_CNT1, Value); | |
1495 | RTMP_IO_WRITE32(pAd, TX_MAX_CNT2, Value); | |
1496 | RTMP_IO_WRITE32(pAd, TX_MAX_CNT3, Value); | |
1497 | RTMP_IO_WRITE32(pAd, TX_MAX_CNT4, Value); | |
1498 | Value = MGMT_RING_SIZE; | |
1499 | RTMP_IO_WRITE32(pAd, TX_MGMTMAX_CNT, Value); | |
1500 | ||
ec278fa2 | 1501 | /* Write RX_RING_CSR register */ |
91980990 GKH |
1502 | Value = RX_RING_SIZE; |
1503 | RTMP_IO_WRITE32(pAd, RX_MAX_CNT, Value); | |
ec278fa2 | 1504 | #endif /* RTMP_MAC_PCI // */ |
91980990 | 1505 | |
ec278fa2 | 1506 | /* WMM parameter */ |
91980990 GKH |
1507 | csr0.word = 0; |
1508 | RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word); | |
96b3c83d | 1509 | if (pAd->CommonCfg.PhyMode == PHY_11B) { |
ec278fa2 BZ |
1510 | csr0.field.Ac0Txop = 192; /* AC_VI: 192*32us ~= 6ms */ |
1511 | csr0.field.Ac1Txop = 96; /* AC_VO: 96*32us ~= 3ms */ | |
96b3c83d | 1512 | } else { |
ec278fa2 BZ |
1513 | csr0.field.Ac0Txop = 96; /* AC_VI: 96*32us ~= 3ms */ |
1514 | csr0.field.Ac1Txop = 48; /* AC_VO: 48*32us ~= 1.5ms */ | |
91980990 GKH |
1515 | } |
1516 | RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr0.word); | |
1517 | ||
ca97b838 | 1518 | #ifdef RTMP_MAC_PCI |
ec278fa2 | 1519 | /* 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits: */ |
91980990 | 1520 | i = 0; |
96b3c83d | 1521 | do { |
91980990 | 1522 | RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); |
96b3c83d BZ |
1523 | if ((GloCfg.field.TxDMABusy == 0) |
1524 | && (GloCfg.field.RxDMABusy == 0)) | |
91980990 GKH |
1525 | break; |
1526 | ||
1527 | RTMPusecDelay(1000); | |
1528 | i++; | |
96b3c83d | 1529 | } while (i < 100); |
91980990 GKH |
1530 | |
1531 | GloCfg.word &= 0xff0; | |
96b3c83d | 1532 | GloCfg.field.EnTXWriteBackDDONE = 1; |
91980990 GKH |
1533 | RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); |
1534 | ||
1535 | IntCfg.word = 0; | |
1536 | RTMP_IO_WRITE32(pAd, DELAY_INT_CFG, IntCfg.word); | |
ec278fa2 | 1537 | #endif /* RTMP_MAC_PCI // */ |
91980990 | 1538 | |
ec278fa2 BZ |
1539 | /* reset action */ |
1540 | /* Load firmware */ | |
1541 | /* Status = NICLoadFirmware(pAd); */ | |
91980990 GKH |
1542 | |
1543 | DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAdapter\n")); | |
1544 | return Status; | |
1545 | } | |
1546 | ||
1547 | /* | |
1548 | ======================================================================== | |
1549 | ||
1550 | Routine Description: | |
1551 | Initialize ASIC | |
1552 | ||
1553 | Arguments: | |
1554 | Adapter Pointer to our adapter | |
1555 | ||
1556 | Return Value: | |
1557 | None | |
1558 | ||
1559 | IRQL = PASSIVE_LEVEL | |
1560 | ||
1561 | Note: | |
1562 | ||
1563 | ======================================================================== | |
1564 | */ | |
62eb734b | 1565 | int NICInitializeAsic(struct rt_rtmp_adapter *pAd, IN BOOLEAN bHardReset) |
91980990 | 1566 | { |
51126deb BZ |
1567 | unsigned long Index = 0; |
1568 | u8 R0 = 0xff; | |
1569 | u32 MacCsr12 = 0, Counter = 0; | |
ca97b838 | 1570 | #ifdef RTMP_MAC_USB |
51126deb BZ |
1571 | u32 MacCsr0 = 0; |
1572 | int Status; | |
1573 | u8 Value = 0xff; | |
ec278fa2 | 1574 | #endif /* RTMP_MAC_USB // */ |
ca97b838 | 1575 | #ifdef RT30xx |
51126deb BZ |
1576 | u8 bbpreg = 0; |
1577 | u8 RFValue = 0; | |
ec278fa2 | 1578 | #endif /* RT30xx // */ |
51126deb BZ |
1579 | u16 KeyIdx; |
1580 | int i, apidx; | |
91980990 GKH |
1581 | |
1582 | DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAsic\n")); | |
1583 | ||
ca97b838 | 1584 | #ifdef RTMP_MAC_PCI |
ec278fa2 | 1585 | RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x3); /* To fix driver disable/enable hang issue when radio off */ |
96b3c83d | 1586 | if (bHardReset == TRUE) { |
91980990 | 1587 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3); |
96b3c83d | 1588 | } else |
91980990 | 1589 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1); |
ca97b838 BZ |
1590 | |
1591 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0); | |
ec278fa2 | 1592 | /* Initialize MAC register to default value */ |
96b3c83d BZ |
1593 | for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++) { |
1594 | RTMP_IO_WRITE32(pAd, MACRegTable[Index].Register, | |
1595 | MACRegTable[Index].Value); | |
ca97b838 BZ |
1596 | } |
1597 | ||
1598 | { | |
96b3c83d BZ |
1599 | for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++) { |
1600 | RTMP_IO_WRITE32(pAd, STAMACRegTable[Index].Register, | |
1601 | STAMACRegTable[Index].Value); | |
ca97b838 BZ |
1602 | } |
1603 | } | |
ec278fa2 | 1604 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 | 1605 | #ifdef RTMP_MAC_USB |
ec278fa2 BZ |
1606 | /* */ |
1607 | /* Make sure MAC gets ready after NICLoadFirmware(). */ | |
1608 | /* */ | |
59fe2d89 BZ |
1609 | Index = 0; |
1610 | ||
ec278fa2 BZ |
1611 | /*To avoid hang-on issue when interface up in kernel 2.4, */ |
1612 | /*we use a local variable "MacCsr0" instead of using "pAd->MACVersion" directly. */ | |
96b3c83d | 1613 | do { |
59fe2d89 BZ |
1614 | RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); |
1615 | ||
1616 | if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) | |
1617 | break; | |
1618 | ||
1619 | RTMPusecDelay(10); | |
1620 | } while (Index++ < 100); | |
1621 | ||
1622 | pAd->MACVersion = MacCsr0; | |
96b3c83d BZ |
1623 | DBGPRINT(RT_DEBUG_TRACE, |
1624 | ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion)); | |
ec278fa2 | 1625 | /* turn on bit13 (set to zero) after rt2860D. This is to solve high-current issue. */ |
59fe2d89 BZ |
1626 | RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacCsr12); |
1627 | MacCsr12 &= (~0x2000); | |
1628 | RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, MacCsr12); | |
1629 | ||
1630 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3); | |
1631 | RTMP_IO_WRITE32(pAd, USB_DMA_CFG, 0x0); | |
1632 | Status = RTUSBVenderReset(pAd); | |
91980990 GKH |
1633 | |
1634 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0); | |
59fe2d89 | 1635 | |
ec278fa2 | 1636 | /* Initialize MAC register to default value */ |
96b3c83d | 1637 | for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++) { |
ca97b838 | 1638 | #ifdef RT30xx |
96b3c83d BZ |
1639 | if ((MACRegTable[Index].Register == TX_SW_CFG0) |
1640 | && (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd) | |
1641 | || IS_RT3090(pAd) || IS_RT3390(pAd))) { | |
59fe2d89 BZ |
1642 | MACRegTable[Index].Value = 0x00000400; |
1643 | } | |
ec278fa2 | 1644 | #endif /* RT30xx // */ |
51126deb | 1645 | RTMP_IO_WRITE32(pAd, (u16)MACRegTable[Index].Register, |
96b3c83d | 1646 | MACRegTable[Index].Value); |
59fe2d89 | 1647 | } |
91980990 | 1648 | |
91980990 | 1649 | { |
96b3c83d BZ |
1650 | for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++) { |
1651 | RTMP_IO_WRITE32(pAd, | |
51126deb | 1652 | (u16)STAMACRegTable[Index].Register, |
96b3c83d | 1653 | STAMACRegTable[Index].Value); |
91980990 GKH |
1654 | } |
1655 | } | |
ec278fa2 | 1656 | #endif /* RTMP_MAC_USB // */ |
91980990 | 1657 | |
ca97b838 | 1658 | #ifdef RT30xx |
ec278fa2 | 1659 | /* Initialize RT3070 serial MAC registers which is different from RT2870 serial */ |
96b3c83d | 1660 | if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) { |
59fe2d89 BZ |
1661 | RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0); |
1662 | ||
ec278fa2 | 1663 | /* RT3071 version E has fixed this issue */ |
96b3c83d BZ |
1664 | if ((pAd->MACVersion & 0xffff) < 0x0211) { |
1665 | if (pAd->NicConfig2.field.DACTestBit == 1) { | |
ec278fa2 | 1666 | RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x2C); /* To fix throughput drop drastically */ |
96b3c83d | 1667 | } else { |
ec278fa2 | 1668 | RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0F); /* To fix throughput drop drastically */ |
59fe2d89 | 1669 | } |
96b3c83d | 1670 | } else { |
59fe2d89 BZ |
1671 | RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0); |
1672 | } | |
96b3c83d BZ |
1673 | } else if (IS_RT3070(pAd)) { |
1674 | if (((pAd->MACVersion & 0xffff) < 0x0201)) { | |
1675 | RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0); | |
ec278fa2 | 1676 | RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x2C); /* To fix throughput drop drastically */ |
96b3c83d | 1677 | } else { |
ca97b838 BZ |
1678 | RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0); |
1679 | } | |
59fe2d89 | 1680 | } |
ec278fa2 | 1681 | #endif /* RT30xx // */ |
59fe2d89 | 1682 | |
ec278fa2 BZ |
1683 | /* */ |
1684 | /* Before program BBP, we need to wait BBP/RF get wake up. */ | |
1685 | /* */ | |
91980990 | 1686 | Index = 0; |
96b3c83d | 1687 | do { |
91980990 GKH |
1688 | RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &MacCsr12); |
1689 | ||
ec278fa2 | 1690 | if ((MacCsr12 & 0x03) == 0) /* if BB.RF is stable */ |
91980990 GKH |
1691 | break; |
1692 | ||
96b3c83d BZ |
1693 | DBGPRINT(RT_DEBUG_TRACE, |
1694 | ("Check MAC_STATUS_CFG = Busy = %x\n", MacCsr12)); | |
91980990 GKH |
1695 | RTMPusecDelay(1000); |
1696 | } while (Index++ < 100); | |
1697 | ||
ec278fa2 BZ |
1698 | /* The commands to firmware should be after these commands, these commands will init firmware */ |
1699 | /* PCI and USB are not the same because PCI driver needs to wait for PCI bus ready */ | |
1700 | RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, 0); /* initialize BBP R/W access agent */ | |
91980990 | 1701 | RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CSR, 0); |
e44fd1cf | 1702 | #ifdef RT3090 |
ec278fa2 | 1703 | /*2008/11/28:KH add to fix the dead rf frequency offset bug<-- */ |
e44fd1cf | 1704 | AsicSendCommandToMcu(pAd, 0x72, 0, 0, 0); |
ec278fa2 BZ |
1705 | /*2008/11/28:KH add to fix the dead rf frequency offset bug--> */ |
1706 | #endif /* RT3090 // */ | |
91980990 GKH |
1707 | RTMPusecDelay(1000); |
1708 | ||
ec278fa2 | 1709 | /* Read BBP register, make sure BBP is up and running before write new data */ |
91980990 | 1710 | Index = 0; |
96b3c83d | 1711 | do { |
91980990 GKH |
1712 | RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R0, &R0); |
1713 | DBGPRINT(RT_DEBUG_TRACE, ("BBP version = %x\n", R0)); | |
1714 | } while ((++Index < 20) && ((R0 == 0xff) || (R0 == 0x00))); | |
ec278fa2 | 1715 | /*ASSERT(Index < 20); //this will cause BSOD on Check-build driver */ |
91980990 GKH |
1716 | |
1717 | if ((R0 == 0xff) || (R0 == 0x00)) | |
1718 | return NDIS_STATUS_FAILURE; | |
1719 | ||
ec278fa2 | 1720 | /* Initialize BBP register to default value */ |
96b3c83d BZ |
1721 | for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++) { |
1722 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register, | |
1723 | BBPRegTable[Index].Value); | |
91980990 GKH |
1724 | } |
1725 | ||
ca97b838 | 1726 | #ifdef RTMP_MAC_PCI |
ec278fa2 | 1727 | /* TODO: shiang, check MACVersion, currently, rbus-based chip use this. */ |
96b3c83d | 1728 | if (pAd->MACVersion == 0x28720200) { |
51126deb BZ |
1729 | /*u8 value; */ |
1730 | unsigned long value2; | |
ca97b838 | 1731 | |
ec278fa2 BZ |
1732 | /*disable MLD by Bruce 20080704 */ |
1733 | /*BBP_IO_READ8_BY_REG_ID(pAd, BBP_R105, &value); */ | |
1734 | /*BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R105, value | 4); */ | |
ca97b838 | 1735 | |
ec278fa2 | 1736 | /*Maximum PSDU length from 16K to 32K bytes */ |
ca97b838 | 1737 | RTMP_IO_READ32(pAd, MAX_LEN_CFG, &value2); |
96b3c83d BZ |
1738 | value2 &= ~(0x3 << 12); |
1739 | value2 |= (0x2 << 12); | |
ca97b838 BZ |
1740 | RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, value2); |
1741 | } | |
ec278fa2 | 1742 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 | 1743 | |
ec278fa2 BZ |
1744 | /* for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT. */ |
1745 | /* RT3090 should not program BBP R84 to 0x19, otherwise TX will block. */ | |
1746 | /*3070/71/72,3090,3090A( are included in RT30xx),3572,3390 */ | |
96b3c83d BZ |
1747 | if (((pAd->MACVersion & 0xffff) != 0x0101) |
1748 | && !(IS_RT30xx(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) | |
59fe2d89 BZ |
1749 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19); |
1750 | ||
ca97b838 | 1751 | #ifdef RT30xx |
ec278fa2 BZ |
1752 | /* add by johnli, RF power sequence setup */ |
1753 | if (IS_RT30xx(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) { /*update for RT3070/71/72/90/91/92,3572,3390. */ | |
59fe2d89 BZ |
1754 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R79, 0x13); |
1755 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R80, 0x05); | |
1756 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R81, 0x33); | |
1757 | } | |
1758 | ||
ec278fa2 | 1759 | if (IS_RT3090(pAd) || IS_RT3390(pAd)) /* RT309x, RT3071/72 */ |
59fe2d89 | 1760 | { |
ec278fa2 | 1761 | /* enable DC filter */ |
96b3c83d | 1762 | if ((pAd->MACVersion & 0xffff) >= 0x0211) { |
59fe2d89 BZ |
1763 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0); |
1764 | } | |
ec278fa2 | 1765 | /* improve power consumption */ |
59fe2d89 | 1766 | RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg); |
96b3c83d | 1767 | if (pAd->Antenna.field.TxPath == 1) { |
ec278fa2 | 1768 | /* turn off tx DAC_1 */ |
59fe2d89 BZ |
1769 | bbpreg = (bbpreg | 0x20); |
1770 | } | |
1771 | ||
96b3c83d | 1772 | if (pAd->Antenna.field.RxPath == 1) { |
ec278fa2 | 1773 | /* turn off tx ADC_1 */ |
59fe2d89 BZ |
1774 | bbpreg &= (~0x2); |
1775 | } | |
1776 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg); | |
1777 | ||
ec278fa2 | 1778 | /* improve power consumption in RT3071 Ver.E */ |
96b3c83d | 1779 | if ((pAd->MACVersion & 0xffff) >= 0x0211) { |
59fe2d89 BZ |
1780 | RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg); |
1781 | bbpreg &= (~0x3); | |
1782 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg); | |
1783 | } | |
96b3c83d BZ |
1784 | } else if (IS_RT3070(pAd)) { |
1785 | if ((pAd->MACVersion & 0xffff) >= 0x0201) { | |
ec278fa2 | 1786 | /* enable DC filter */ |
ca97b838 BZ |
1787 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0); |
1788 | ||
ec278fa2 | 1789 | /* improve power consumption in RT3070 Ver.F */ |
ca97b838 BZ |
1790 | RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg); |
1791 | bbpreg &= (~0x3); | |
1792 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg); | |
1793 | } | |
ec278fa2 | 1794 | /* TX_LO1_en, RF R17 register Bit 3 to 0 */ |
ca97b838 BZ |
1795 | RT30xxReadRFRegister(pAd, RF_R17, &RFValue); |
1796 | RFValue &= (~0x08); | |
ec278fa2 | 1797 | /* to fix rx long range issue */ |
96b3c83d | 1798 | if (pAd->NicConfig2.field.ExternalLNAForG == 0) { |
ca97b838 BZ |
1799 | RFValue |= 0x20; |
1800 | } | |
ec278fa2 | 1801 | /* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h */ |
96b3c83d | 1802 | if (pAd->TxMixerGain24G >= 1) { |
ec278fa2 | 1803 | RFValue &= (~0x7); /* clean bit [2:0] */ |
ca97b838 BZ |
1804 | RFValue |= pAd->TxMixerGain24G; |
1805 | } | |
1806 | RT30xxWriteRFRegister(pAd, RF_R17, RFValue); | |
1807 | } | |
ec278fa2 BZ |
1808 | /* end johnli */ |
1809 | #endif /* RT30xx // */ | |
ca97b838 | 1810 | |
96b3c83d | 1811 | if (pAd->MACVersion == 0x28600100) { |
91980990 GKH |
1812 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); |
1813 | RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12); | |
96b3c83d | 1814 | } |
91980990 | 1815 | |
ec278fa2 | 1816 | if (pAd->MACVersion >= RALINK_2880E_VERSION && pAd->MACVersion < RALINK_3070_VERSION) /* 3*3 */ |
91980990 | 1817 | { |
ec278fa2 | 1818 | /* enlarge MAX_LEN_CFG */ |
51126deb | 1819 | u32 csr; |
91980990 GKH |
1820 | RTMP_IO_READ32(pAd, MAX_LEN_CFG, &csr); |
1821 | csr &= 0xFFF; | |
1822 | csr |= 0x2000; | |
1823 | RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, csr); | |
1824 | } | |
ca97b838 | 1825 | #ifdef RTMP_MAC_USB |
59fe2d89 | 1826 | { |
51126deb | 1827 | u8 MAC_Value[] = |
96b3c83d BZ |
1828 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0 }; |
1829 | ||
ec278fa2 | 1830 | /*Initialize WCID table */ |
96b3c83d BZ |
1831 | Value = 0xff; |
1832 | for (Index = 0; Index < 254; Index++) { | |
1833 | RTUSBMultiWrite(pAd, | |
51126deb | 1834 | (u16)(MAC_WCID_BASE + Index * 8), |
96b3c83d BZ |
1835 | MAC_Value, 8); |
1836 | } | |
59fe2d89 | 1837 | } |
ec278fa2 | 1838 | #endif /* RTMP_MAC_USB // */ |
91980990 | 1839 | |
ec278fa2 | 1840 | /* Add radio off control */ |
91980990 | 1841 | { |
96b3c83d | 1842 | if (pAd->StaCfg.bRadio == FALSE) { |
ec278fa2 | 1843 | /* RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x00001818); */ |
91980990 GKH |
1844 | RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); |
1845 | DBGPRINT(RT_DEBUG_TRACE, ("Set Radio Off\n")); | |
1846 | } | |
1847 | } | |
91980990 | 1848 | |
ec278fa2 | 1849 | /* Clear raw counters */ |
91980990 GKH |
1850 | RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter); |
1851 | RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter); | |
1852 | RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter); | |
1853 | RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter); | |
1854 | RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter); | |
1855 | RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter); | |
1856 | ||
ec278fa2 BZ |
1857 | /* ASIC will keep garbage value after boot */ |
1858 | /* Clear all shared key table when initial */ | |
1859 | /* This routine can be ignored in radio-ON/OFF operation. */ | |
96b3c83d BZ |
1860 | if (bHardReset) { |
1861 | for (KeyIdx = 0; KeyIdx < 4; KeyIdx++) { | |
1862 | RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4 * KeyIdx, | |
1863 | 0); | |
91980990 GKH |
1864 | } |
1865 | ||
ec278fa2 | 1866 | /* Clear all pairwise key table when initial */ |
96b3c83d BZ |
1867 | for (KeyIdx = 0; KeyIdx < 256; KeyIdx++) { |
1868 | RTMP_IO_WRITE32(pAd, | |
1869 | MAC_WCID_ATTRIBUTE_BASE + | |
1870 | (KeyIdx * HW_WCID_ATTRI_SIZE), 1); | |
91980990 GKH |
1871 | } |
1872 | } | |
ec278fa2 BZ |
1873 | /* assert HOST ready bit */ |
1874 | /* RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x0); // 2004-09-14 asked by Mark */ | |
1875 | /* RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x4); */ | |
91980990 | 1876 | |
ec278fa2 | 1877 | /* It isn't necessary to clear this space when not hard reset. */ |
96b3c83d | 1878 | if (bHardReset == TRUE) { |
ec278fa2 | 1879 | /* clear all on-chip BEACON frame space */ |
96b3c83d BZ |
1880 | for (apidx = 0; apidx < HW_BEACON_MAX_COUNT; apidx++) { |
1881 | for (i = 0; i < HW_BEACON_OFFSET >> 2; i += 4) | |
1882 | RTMP_IO_WRITE32(pAd, | |
1883 | pAd->BeaconOffset[apidx] + i, | |
1884 | 0x00); | |
91980990 GKH |
1885 | } |
1886 | } | |
ca97b838 | 1887 | #ifdef RTMP_MAC_USB |
59fe2d89 | 1888 | AsicDisableSync(pAd); |
ec278fa2 | 1889 | /* Clear raw counters */ |
59fe2d89 BZ |
1890 | RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter); |
1891 | RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter); | |
1892 | RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter); | |
1893 | RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter); | |
1894 | RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter); | |
1895 | RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter); | |
ec278fa2 | 1896 | /* Default PCI clock cycle per ms is different as default setting, which is based on PCI. */ |
59fe2d89 | 1897 | RTMP_IO_READ32(pAd, USB_CYC_CFG, &Counter); |
96b3c83d BZ |
1898 | Counter &= 0xffffff00; |
1899 | Counter |= 0x000001e; | |
59fe2d89 | 1900 | RTMP_IO_WRITE32(pAd, USB_CYC_CFG, Counter); |
ec278fa2 | 1901 | #endif /* RTMP_MAC_USB // */ |
91980990 | 1902 | |
91980990 | 1903 | { |
ec278fa2 | 1904 | /* for rt2860E and after, init TXOP_CTRL_CFG with 0x583f. This is for extension channel overlapping IOT. */ |
96b3c83d | 1905 | if ((pAd->MACVersion & 0xffff) != 0x0101) |
91980990 GKH |
1906 | RTMP_IO_WRITE32(pAd, TXOP_CTRL_CFG, 0x583f); |
1907 | } | |
91980990 GKH |
1908 | |
1909 | DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAsic\n")); | |
1910 | return NDIS_STATUS_SUCCESS; | |
1911 | } | |
1912 | ||
1913 | /* | |
1914 | ======================================================================== | |
1915 | ||
1916 | Routine Description: | |
1917 | Reset NIC Asics | |
1918 | ||
1919 | Arguments: | |
1920 | Adapter Pointer to our adapter | |
1921 | ||
1922 | Return Value: | |
1923 | None | |
1924 | ||
1925 | IRQL = PASSIVE_LEVEL | |
1926 | ||
1927 | Note: | |
1928 | Reset NIC to initial state AS IS system boot up time. | |
1929 | ||
1930 | ======================================================================== | |
1931 | */ | |
62eb734b | 1932 | void NICIssueReset(struct rt_rtmp_adapter *pAd) |
91980990 | 1933 | { |
51126deb | 1934 | u32 Value = 0; |
91980990 GKH |
1935 | DBGPRINT(RT_DEBUG_TRACE, ("--> NICIssueReset\n")); |
1936 | ||
ec278fa2 BZ |
1937 | /* Abort Tx, prevent ASIC from writing to Host memory */ |
1938 | /*RTMP_IO_WRITE32(pAd, TX_CNTL_CSR, 0x001f0000); */ | |
ca97b838 | 1939 | |
ec278fa2 | 1940 | /* Disable Rx, register value supposed will remain after reset */ |
91980990 GKH |
1941 | RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value); |
1942 | Value &= (0xfffffff3); | |
1943 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value); | |
1944 | ||
ec278fa2 BZ |
1945 | /* Issue reset and clear from reset state */ |
1946 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x03); /* 2004-09-17 change from 0x01 */ | |
91980990 GKH |
1947 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x00); |
1948 | ||
1949 | DBGPRINT(RT_DEBUG_TRACE, ("<-- NICIssueReset\n")); | |
1950 | } | |
1951 | ||
1952 | /* | |
1953 | ======================================================================== | |
1954 | ||
1955 | Routine Description: | |
1956 | Check ASIC registers and find any reason the system might hang | |
1957 | ||
1958 | Arguments: | |
1959 | Adapter Pointer to our adapter | |
1960 | ||
1961 | Return Value: | |
1962 | None | |
1963 | ||
1964 | IRQL = DISPATCH_LEVEL | |
1965 | ||
1966 | ======================================================================== | |
1967 | */ | |
62eb734b | 1968 | BOOLEAN NICCheckForHang(struct rt_rtmp_adapter *pAd) |
91980990 GKH |
1969 | { |
1970 | return (FALSE); | |
1971 | } | |
1972 | ||
62eb734b | 1973 | void NICUpdateFifoStaCounters(struct rt_rtmp_adapter *pAd) |
91980990 | 1974 | { |
96b3c83d | 1975 | TX_STA_FIFO_STRUC StaFifo; |
62eb734b | 1976 | struct rt_mac_table_entry *pEntry; |
51126deb BZ |
1977 | u8 i = 0; |
1978 | u8 pid = 0, wcid = 0; | |
1979 | char reTry; | |
1980 | u8 succMCS; | |
91980990 | 1981 | |
96b3c83d BZ |
1982 | do { |
1983 | RTMP_IO_READ32(pAd, TX_STA_FIFO, &StaFifo.word); | |
91980990 | 1984 | |
96b3c83d BZ |
1985 | if (StaFifo.field.bValid == 0) |
1986 | break; | |
91980990 | 1987 | |
51126deb | 1988 | wcid = (u8)StaFifo.field.wcid; |
91980990 GKH |
1989 | |
1990 | /* ignore NoACK and MGMT frame use 0xFF as WCID */ | |
96b3c83d BZ |
1991 | if ((StaFifo.field.TxAckRequired == 0) |
1992 | || (wcid >= MAX_LEN_OF_MAC_TABLE)) { | |
1993 | i++; | |
1994 | continue; | |
1995 | } | |
91980990 | 1996 | |
96b3c83d | 1997 | /* PID store Tx MCS Rate */ |
51126deb | 1998 | pid = (u8)StaFifo.field.PidType; |
91980990 | 1999 | |
96b3c83d | 2000 | pEntry = &pAd->MacTab.Content[wcid]; |
91980990 | 2001 | |
96b3c83d | 2002 | pEntry->DebugFIFOCount++; |
91980990 | 2003 | |
ec278fa2 | 2004 | if (StaFifo.field.TxBF) /* 3*3 */ |
96b3c83d | 2005 | pEntry->TxBFCount++; |
91980990 | 2006 | |
96b3c83d BZ |
2007 | if (!StaFifo.field.TxSuccess) { |
2008 | pEntry->FIFOCount++; | |
2009 | pEntry->OneSecTxFailCount++; | |
91980990 | 2010 | |
96b3c83d BZ |
2011 | if (pEntry->FIFOCount >= 1) { |
2012 | DBGPRINT(RT_DEBUG_TRACE, ("#")); | |
2013 | pEntry->NoBADataCountDown = 64; | |
91980990 | 2014 | |
96b3c83d BZ |
2015 | if (pEntry->PsMode == PWR_ACTIVE) { |
2016 | int tid; | |
2017 | for (tid = 0; tid < NUM_OF_TID; tid++) { | |
2018 | BAOriSessionTearDown(pAd, | |
2019 | pEntry-> | |
2020 | Aid, tid, | |
2021 | FALSE, | |
2022 | FALSE); | |
91980990 | 2023 | } |
96b3c83d | 2024 | |
ec278fa2 | 2025 | /* Update the continuous transmission counter except PS mode */ |
96b3c83d BZ |
2026 | pEntry->ContinueTxFailCnt++; |
2027 | } else { | |
ec278fa2 BZ |
2028 | /* Clear the FIFOCount when sta in Power Save mode. Basically we assume */ |
2029 | /* this tx error happened due to sta just go to sleep. */ | |
96b3c83d BZ |
2030 | pEntry->FIFOCount = 0; |
2031 | pEntry->ContinueTxFailCnt = 0; | |
91980990 | 2032 | } |
ec278fa2 | 2033 | /*pEntry->FIFOCount = 0; */ |
91980990 | 2034 | } |
ec278fa2 | 2035 | /*pEntry->bSendBAR = TRUE; */ |
96b3c83d BZ |
2036 | } else { |
2037 | if ((pEntry->PsMode != PWR_SAVE) | |
2038 | && (pEntry->NoBADataCountDown > 0)) { | |
2039 | pEntry->NoBADataCountDown--; | |
2040 | if (pEntry->NoBADataCountDown == 0) { | |
2041 | DBGPRINT(RT_DEBUG_TRACE, ("@\n")); | |
91980990 | 2042 | } |
91980990 GKH |
2043 | } |
2044 | ||
96b3c83d BZ |
2045 | pEntry->FIFOCount = 0; |
2046 | pEntry->OneSecTxNoRetryOkCount++; | |
ec278fa2 | 2047 | /* update NoDataIdleCount when sucessful send packet to STA. */ |
96b3c83d BZ |
2048 | pEntry->NoDataIdleCount = 0; |
2049 | pEntry->ContinueTxFailCnt = 0; | |
2050 | } | |
91980990 | 2051 | |
96b3c83d | 2052 | succMCS = StaFifo.field.SuccessRate & 0x7F; |
91980990 | 2053 | |
96b3c83d BZ |
2054 | reTry = pid - succMCS; |
2055 | ||
2056 | if (StaFifo.field.TxSuccess) { | |
2057 | pEntry->TXMCSExpected[pid]++; | |
2058 | if (pid == succMCS) { | |
2059 | pEntry->TXMCSSuccessful[pid]++; | |
2060 | } else { | |
2061 | pEntry->TXMCSAutoFallBack[pid][succMCS]++; | |
91980990 | 2062 | } |
96b3c83d BZ |
2063 | } else { |
2064 | pEntry->TXMCSFailed[pid]++; | |
2065 | } | |
91980990 | 2066 | |
96b3c83d BZ |
2067 | if (reTry > 0) { |
2068 | if ((pid >= 12) && succMCS <= 7) { | |
2069 | reTry -= 4; | |
91980990 | 2070 | } |
96b3c83d BZ |
2071 | pEntry->OneSecTxRetryOkCount += reTry; |
2072 | } | |
91980990 | 2073 | |
96b3c83d | 2074 | i++; |
ec278fa2 | 2075 | /* ASIC store 16 stack */ |
96b3c83d | 2076 | } while (i < (2 * TX_RING_SIZE)); |
91980990 GKH |
2077 | |
2078 | } | |
2079 | ||
2080 | /* | |
2081 | ======================================================================== | |
2082 | ||
2083 | Routine Description: | |
2084 | Read statistical counters from hardware registers and record them | |
2085 | in software variables for later on query | |
2086 | ||
2087 | Arguments: | |
2088 | pAd Pointer to our adapter | |
2089 | ||
2090 | Return Value: | |
2091 | None | |
2092 | ||
2093 | IRQL = DISPATCH_LEVEL | |
2094 | ||
2095 | ======================================================================== | |
2096 | */ | |
62eb734b | 2097 | void NICUpdateRawCounters(struct rt_rtmp_adapter *pAd) |
91980990 | 2098 | { |
51126deb BZ |
2099 | u32 OldValue; /*, Value2; */ |
2100 | /*unsigned long PageSum, OneSecTransmitCount; */ | |
2101 | /*unsigned long TxErrorRatio, Retry, Fail; */ | |
96b3c83d BZ |
2102 | RX_STA_CNT0_STRUC RxStaCnt0; |
2103 | RX_STA_CNT1_STRUC RxStaCnt1; | |
2104 | RX_STA_CNT2_STRUC RxStaCnt2; | |
2105 | TX_STA_CNT0_STRUC TxStaCnt0; | |
2106 | TX_STA_CNT1_STRUC StaTx1; | |
2107 | TX_STA_CNT2_STRUC StaTx2; | |
2108 | TX_AGG_CNT_STRUC TxAggCnt; | |
2109 | TX_AGG_CNT0_STRUC TxAggCnt0; | |
2110 | TX_AGG_CNT1_STRUC TxAggCnt1; | |
2111 | TX_AGG_CNT2_STRUC TxAggCnt2; | |
2112 | TX_AGG_CNT3_STRUC TxAggCnt3; | |
2113 | TX_AGG_CNT4_STRUC TxAggCnt4; | |
2114 | TX_AGG_CNT5_STRUC TxAggCnt5; | |
2115 | TX_AGG_CNT6_STRUC TxAggCnt6; | |
2116 | TX_AGG_CNT7_STRUC TxAggCnt7; | |
62eb734b | 2117 | struct rt_counter_ralink *pRalinkCounters; |
ca97b838 BZ |
2118 | |
2119 | pRalinkCounters = &pAd->RalinkCounters; | |
91980990 GKH |
2120 | |
2121 | RTMP_IO_READ32(pAd, RX_STA_CNT0, &RxStaCnt0.word); | |
2122 | RTMP_IO_READ32(pAd, RX_STA_CNT2, &RxStaCnt2.word); | |
2123 | ||
2124 | { | |
2125 | RTMP_IO_READ32(pAd, RX_STA_CNT1, &RxStaCnt1.word); | |
ec278fa2 | 2126 | /* Update RX PLCP error counter */ |
96b3c83d | 2127 | pAd->PrivateInfo.PhyRxErrCnt += RxStaCnt1.field.PlcpErr; |
ec278fa2 | 2128 | /* Update False CCA counter */ |
96b3c83d BZ |
2129 | pAd->RalinkCounters.OneSecFalseCCACnt += |
2130 | RxStaCnt1.field.FalseCca; | |
91980990 GKH |
2131 | } |
2132 | ||
ec278fa2 | 2133 | /* Update FCS counters */ |
96b3c83d | 2134 | OldValue = pAd->WlanCounters.FCSErrorCount.u.LowPart; |
ec278fa2 | 2135 | pAd->WlanCounters.FCSErrorCount.u.LowPart += (RxStaCnt0.field.CrcErr); /* >> 7); */ |
91980990 GKH |
2136 | if (pAd->WlanCounters.FCSErrorCount.u.LowPart < OldValue) |
2137 | pAd->WlanCounters.FCSErrorCount.u.HighPart++; | |
2138 | ||
ec278fa2 | 2139 | /* Add FCS error count to private counters */ |
ca97b838 BZ |
2140 | pRalinkCounters->OneSecRxFcsErrCnt += RxStaCnt0.field.CrcErr; |
2141 | OldValue = pRalinkCounters->RealFcsErrCount.u.LowPart; | |
2142 | pRalinkCounters->RealFcsErrCount.u.LowPart += RxStaCnt0.field.CrcErr; | |
2143 | if (pRalinkCounters->RealFcsErrCount.u.LowPart < OldValue) | |
2144 | pRalinkCounters->RealFcsErrCount.u.HighPart++; | |
91980990 | 2145 | |
ec278fa2 | 2146 | /* Update Duplicate Rcv check */ |
ca97b838 | 2147 | pRalinkCounters->DuplicateRcv += RxStaCnt2.field.RxDupliCount; |
96b3c83d BZ |
2148 | pAd->WlanCounters.FrameDuplicateCount.u.LowPart += |
2149 | RxStaCnt2.field.RxDupliCount; | |
ec278fa2 | 2150 | /* Update RX Overflow counter */ |
91980990 GKH |
2151 | pAd->Counters8023.RxNoBuffer += (RxStaCnt2.field.RxFifoOverflowCount); |
2152 | ||
ec278fa2 | 2153 | /*pAd->RalinkCounters.RxCount = 0; */ |
ca97b838 | 2154 | #ifdef RTMP_MAC_USB |
96b3c83d | 2155 | if (pRalinkCounters->RxCount != pAd->watchDogRxCnt) { |
ca97b838 | 2156 | pAd->watchDogRxCnt = pRalinkCounters->RxCount; |
59fe2d89 | 2157 | pAd->watchDogRxOverFlowCnt = 0; |
96b3c83d | 2158 | } else { |
59fe2d89 BZ |
2159 | if (RxStaCnt2.field.RxFifoOverflowCount) |
2160 | pAd->watchDogRxOverFlowCnt++; | |
2161 | else | |
2162 | pAd->watchDogRxOverFlowCnt = 0; | |
2163 | } | |
ec278fa2 | 2164 | #endif /* RTMP_MAC_USB // */ |
59fe2d89 | 2165 | |
ec278fa2 BZ |
2166 | /*if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED) || */ |
2167 | /* (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED) && (pAd->MacTab.Size != 1))) */ | |
96b3c83d | 2168 | if (!pAd->bUpdateBcnCntDone) { |
ec278fa2 | 2169 | /* Update BEACON sent count */ |
96b3c83d BZ |
2170 | RTMP_IO_READ32(pAd, TX_STA_CNT0, &TxStaCnt0.word); |
2171 | RTMP_IO_READ32(pAd, TX_STA_CNT1, &StaTx1.word); | |
2172 | RTMP_IO_READ32(pAd, TX_STA_CNT2, &StaTx2.word); | |
2173 | pRalinkCounters->OneSecBeaconSentCnt += | |
2174 | TxStaCnt0.field.TxBeaconCount; | |
2175 | pRalinkCounters->OneSecTxRetryOkCount += | |
2176 | StaTx1.field.TxRetransmit; | |
2177 | pRalinkCounters->OneSecTxNoRetryOkCount += | |
2178 | StaTx1.field.TxSuccess; | |
2179 | pRalinkCounters->OneSecTxFailCount += | |
2180 | TxStaCnt0.field.TxFailCount; | |
2181 | pAd->WlanCounters.TransmittedFragmentCount.u.LowPart += | |
2182 | StaTx1.field.TxSuccess; | |
2183 | pAd->WlanCounters.RetryCount.u.LowPart += | |
2184 | StaTx1.field.TxRetransmit; | |
2185 | pAd->WlanCounters.FailedCount.u.LowPart += | |
2186 | TxStaCnt0.field.TxFailCount; | |
91980990 GKH |
2187 | } |
2188 | ||
ec278fa2 | 2189 | /*if (pAd->bStaFifoTest == TRUE) */ |
91980990 GKH |
2190 | { |
2191 | RTMP_IO_READ32(pAd, TX_AGG_CNT, &TxAggCnt.word); | |
2192 | RTMP_IO_READ32(pAd, TX_AGG_CNT0, &TxAggCnt0.word); | |
2193 | RTMP_IO_READ32(pAd, TX_AGG_CNT1, &TxAggCnt1.word); | |
2194 | RTMP_IO_READ32(pAd, TX_AGG_CNT2, &TxAggCnt2.word); | |
2195 | RTMP_IO_READ32(pAd, TX_AGG_CNT3, &TxAggCnt3.word); | |
2196 | RTMP_IO_READ32(pAd, TX_AGG_CNT4, &TxAggCnt4.word); | |
2197 | RTMP_IO_READ32(pAd, TX_AGG_CNT5, &TxAggCnt5.word); | |
2198 | RTMP_IO_READ32(pAd, TX_AGG_CNT6, &TxAggCnt6.word); | |
2199 | RTMP_IO_READ32(pAd, TX_AGG_CNT7, &TxAggCnt7.word); | |
ca97b838 BZ |
2200 | pRalinkCounters->TxAggCount += TxAggCnt.field.AggTxCount; |
2201 | pRalinkCounters->TxNonAggCount += TxAggCnt.field.NonAggTxCount; | |
96b3c83d BZ |
2202 | pRalinkCounters->TxAgg1MPDUCount += |
2203 | TxAggCnt0.field.AggSize1Count; | |
2204 | pRalinkCounters->TxAgg2MPDUCount += | |
2205 | TxAggCnt0.field.AggSize2Count; | |
2206 | ||
2207 | pRalinkCounters->TxAgg3MPDUCount += | |
2208 | TxAggCnt1.field.AggSize3Count; | |
2209 | pRalinkCounters->TxAgg4MPDUCount += | |
2210 | TxAggCnt1.field.AggSize4Count; | |
2211 | pRalinkCounters->TxAgg5MPDUCount += | |
2212 | TxAggCnt2.field.AggSize5Count; | |
2213 | pRalinkCounters->TxAgg6MPDUCount += | |
2214 | TxAggCnt2.field.AggSize6Count; | |
2215 | ||
2216 | pRalinkCounters->TxAgg7MPDUCount += | |
2217 | TxAggCnt3.field.AggSize7Count; | |
2218 | pRalinkCounters->TxAgg8MPDUCount += | |
2219 | TxAggCnt3.field.AggSize8Count; | |
2220 | pRalinkCounters->TxAgg9MPDUCount += | |
2221 | TxAggCnt4.field.AggSize9Count; | |
2222 | pRalinkCounters->TxAgg10MPDUCount += | |
2223 | TxAggCnt4.field.AggSize10Count; | |
2224 | ||
2225 | pRalinkCounters->TxAgg11MPDUCount += | |
2226 | TxAggCnt5.field.AggSize11Count; | |
2227 | pRalinkCounters->TxAgg12MPDUCount += | |
2228 | TxAggCnt5.field.AggSize12Count; | |
2229 | pRalinkCounters->TxAgg13MPDUCount += | |
2230 | TxAggCnt6.field.AggSize13Count; | |
2231 | pRalinkCounters->TxAgg14MPDUCount += | |
2232 | TxAggCnt6.field.AggSize14Count; | |
2233 | ||
2234 | pRalinkCounters->TxAgg15MPDUCount += | |
2235 | TxAggCnt7.field.AggSize15Count; | |
2236 | pRalinkCounters->TxAgg16MPDUCount += | |
2237 | TxAggCnt7.field.AggSize16Count; | |
91980990 | 2238 | |
ec278fa2 | 2239 | /* Calculate the transmitted A-MPDU count */ |
96b3c83d BZ |
2240 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += |
2241 | TxAggCnt0.field.AggSize1Count; | |
2242 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2243 | (TxAggCnt0.field.AggSize2Count / 2); | |
2244 | ||
2245 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2246 | (TxAggCnt1.field.AggSize3Count / 3); | |
2247 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2248 | (TxAggCnt1.field.AggSize4Count / 4); | |
2249 | ||
2250 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2251 | (TxAggCnt2.field.AggSize5Count / 5); | |
2252 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2253 | (TxAggCnt2.field.AggSize6Count / 6); | |
2254 | ||
2255 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2256 | (TxAggCnt3.field.AggSize7Count / 7); | |
2257 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2258 | (TxAggCnt3.field.AggSize8Count / 8); | |
2259 | ||
2260 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2261 | (TxAggCnt4.field.AggSize9Count / 9); | |
2262 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2263 | (TxAggCnt4.field.AggSize10Count / 10); | |
2264 | ||
2265 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2266 | (TxAggCnt5.field.AggSize11Count / 11); | |
2267 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2268 | (TxAggCnt5.field.AggSize12Count / 12); | |
2269 | ||
2270 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2271 | (TxAggCnt6.field.AggSize13Count / 13); | |
2272 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2273 | (TxAggCnt6.field.AggSize14Count / 14); | |
2274 | ||
2275 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2276 | (TxAggCnt7.field.AggSize15Count / 15); | |
2277 | pRalinkCounters->TransmittedAMPDUCount.u.LowPart += | |
2278 | (TxAggCnt7.field.AggSize16Count / 16); | |
91980990 GKH |
2279 | } |
2280 | ||
91980990 GKH |
2281 | } |
2282 | ||
91980990 GKH |
2283 | /* |
2284 | ======================================================================== | |
2285 | ||
2286 | Routine Description: | |
2287 | Reset NIC from error | |
2288 | ||
2289 | Arguments: | |
2290 | Adapter Pointer to our adapter | |
2291 | ||
2292 | Return Value: | |
2293 | None | |
2294 | ||
2295 | IRQL = PASSIVE_LEVEL | |
2296 | ||
2297 | Note: | |
2298 | Reset NIC from error state | |
2299 | ||
2300 | ======================================================================== | |
2301 | */ | |
62eb734b | 2302 | void NICResetFromError(struct rt_rtmp_adapter *pAd) |
91980990 | 2303 | { |
ec278fa2 BZ |
2304 | /* Reset BBP (according to alex, reset ASIC will force reset BBP */ |
2305 | /* Therefore, skip the reset BBP */ | |
2306 | /* RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x2); */ | |
91980990 GKH |
2307 | |
2308 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1); | |
ec278fa2 | 2309 | /* Remove ASIC from reset state */ |
91980990 GKH |
2310 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0); |
2311 | ||
2312 | NICInitializeAdapter(pAd, FALSE); | |
2313 | NICInitAsicFromEEPROM(pAd); | |
2314 | ||
ec278fa2 | 2315 | /* Switch to current channel, since during reset process, the connection should remains on. */ |
91980990 GKH |
2316 | AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE); |
2317 | AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel); | |
2318 | } | |
2319 | ||
62eb734b | 2320 | int NICLoadFirmware(struct rt_rtmp_adapter *pAd) |
91980990 | 2321 | { |
51126deb | 2322 | int status = NDIS_STATUS_SUCCESS; |
ca97b838 BZ |
2323 | if (pAd->chipOps.loadFirmware) |
2324 | status = pAd->chipOps.loadFirmware(pAd); | |
91980990 | 2325 | |
ca97b838 BZ |
2326 | return status; |
2327 | } | |
91980990 | 2328 | |
91980990 GKH |
2329 | /* |
2330 | ======================================================================== | |
2331 | ||
2332 | Routine Description: | |
ca97b838 | 2333 | erase 8051 firmware image in MAC ASIC |
91980990 GKH |
2334 | |
2335 | Arguments: | |
2336 | Adapter Pointer to our adapter | |
2337 | ||
91980990 GKH |
2338 | IRQL = PASSIVE_LEVEL |
2339 | ||
2340 | ======================================================================== | |
2341 | */ | |
62eb734b | 2342 | void NICEraseFirmware(struct rt_rtmp_adapter *pAd) |
91980990 | 2343 | { |
ca97b838 BZ |
2344 | if (pAd->chipOps.eraseFirmware) |
2345 | pAd->chipOps.eraseFirmware(pAd); | |
59fe2d89 | 2346 | |
96b3c83d | 2347 | } /* End of NICEraseFirmware */ |
91980990 GKH |
2348 | |
2349 | /* | |
2350 | ======================================================================== | |
2351 | ||
2352 | Routine Description: | |
2353 | Load Tx rate switching parameters | |
2354 | ||
2355 | Arguments: | |
2356 | Adapter Pointer to our adapter | |
2357 | ||
2358 | Return Value: | |
2359 | NDIS_STATUS_SUCCESS firmware image load ok | |
2360 | NDIS_STATUS_FAILURE image not found | |
2361 | ||
2362 | IRQL = PASSIVE_LEVEL | |
2363 | ||
2364 | Rate Table Format: | |
2365 | 1. (B0: Valid Item number) (B1:Initial item from zero) | |
2366 | 2. Item Number(Dec) Mode(Hex) Current MCS(Dec) TrainUp(Dec) TrainDown(Dec) | |
2367 | ||
2368 | ======================================================================== | |
2369 | */ | |
62eb734b | 2370 | int NICLoadRateSwitchingParams(struct rt_rtmp_adapter *pAd) |
91980990 GKH |
2371 | { |
2372 | return NDIS_STATUS_SUCCESS; | |
2373 | } | |
2374 | ||
91980990 GKH |
2375 | /* |
2376 | ======================================================================== | |
2377 | ||
2378 | Routine Description: | |
2379 | Compare two memory block | |
2380 | ||
2381 | Arguments: | |
2382 | pSrc1 Pointer to first memory address | |
2383 | pSrc2 Pointer to second memory address | |
2384 | ||
2385 | Return Value: | |
2386 | 0: memory is equal | |
2387 | 1: pSrc1 memory is larger | |
2388 | 2: pSrc2 memory is larger | |
2389 | ||
2390 | IRQL = DISPATCH_LEVEL | |
2391 | ||
2392 | Note: | |
2393 | ||
2394 | ======================================================================== | |
2395 | */ | |
51126deb | 2396 | unsigned long RTMPCompareMemory(void *pSrc1, void *pSrc2, unsigned long Length) |
91980990 | 2397 | { |
51126deb BZ |
2398 | u8 *pMem1; |
2399 | u8 *pMem2; | |
2400 | unsigned long Index = 0; | |
91980990 | 2401 | |
51126deb BZ |
2402 | pMem1 = (u8 *)pSrc1; |
2403 | pMem2 = (u8 *)pSrc2; | |
91980990 | 2404 | |
96b3c83d | 2405 | for (Index = 0; Index < Length; Index++) { |
91980990 GKH |
2406 | if (pMem1[Index] > pMem2[Index]) |
2407 | return (1); | |
2408 | else if (pMem1[Index] < pMem2[Index]) | |
2409 | return (2); | |
2410 | } | |
2411 | ||
ec278fa2 | 2412 | /* Equal */ |
91980990 GKH |
2413 | return (0); |
2414 | } | |
2415 | ||
2416 | /* | |
2417 | ======================================================================== | |
2418 | ||
2419 | Routine Description: | |
2420 | Zero out memory block | |
2421 | ||
2422 | Arguments: | |
2423 | pSrc1 Pointer to memory address | |
2424 | Length Size | |
2425 | ||
2426 | Return Value: | |
2427 | None | |
2428 | ||
2429 | IRQL = PASSIVE_LEVEL | |
2430 | IRQL = DISPATCH_LEVEL | |
2431 | ||
2432 | Note: | |
2433 | ||
2434 | ======================================================================== | |
2435 | */ | |
51126deb | 2436 | void RTMPZeroMemory(void *pSrc, unsigned long Length) |
91980990 | 2437 | { |
51126deb BZ |
2438 | u8 *pMem; |
2439 | unsigned long Index = 0; | |
91980990 | 2440 | |
51126deb | 2441 | pMem = (u8 *)pSrc; |
91980990 | 2442 | |
96b3c83d | 2443 | for (Index = 0; Index < Length; Index++) { |
91980990 GKH |
2444 | pMem[Index] = 0x00; |
2445 | } | |
2446 | } | |
2447 | ||
91980990 GKH |
2448 | /* |
2449 | ======================================================================== | |
2450 | ||
2451 | Routine Description: | |
2452 | Copy data from memory block 1 to memory block 2 | |
2453 | ||
2454 | Arguments: | |
2455 | pDest Pointer to destination memory address | |
2456 | pSrc Pointer to source memory address | |
2457 | Length Copy size | |
2458 | ||
2459 | Return Value: | |
2460 | None | |
2461 | ||
2462 | IRQL = PASSIVE_LEVEL | |
2463 | IRQL = DISPATCH_LEVEL | |
2464 | ||
2465 | Note: | |
2466 | ||
2467 | ======================================================================== | |
2468 | */ | |
51126deb | 2469 | void RTMPMoveMemory(void *pDest, void *pSrc, unsigned long Length) |
91980990 | 2470 | { |
51126deb BZ |
2471 | u8 *pMem1; |
2472 | u8 *pMem2; | |
2473 | u32 Index; | |
91980990 | 2474 | |
96b3c83d | 2475 | ASSERT((Length == 0) || (pDest && pSrc)); |
91980990 | 2476 | |
51126deb BZ |
2477 | pMem1 = (u8 *)pDest; |
2478 | pMem2 = (u8 *)pSrc; | |
91980990 | 2479 | |
96b3c83d | 2480 | for (Index = 0; Index < Length; Index++) { |
91980990 GKH |
2481 | pMem1[Index] = pMem2[Index]; |
2482 | } | |
2483 | } | |
2484 | ||
2485 | /* | |
2486 | ======================================================================== | |
2487 | ||
2488 | Routine Description: | |
2489 | Initialize port configuration structure | |
2490 | ||
2491 | Arguments: | |
2492 | Adapter Pointer to our adapter | |
2493 | ||
2494 | Return Value: | |
2495 | None | |
2496 | ||
2497 | IRQL = PASSIVE_LEVEL | |
2498 | ||
2499 | Note: | |
2500 | ||
2501 | ======================================================================== | |
2502 | */ | |
62eb734b | 2503 | void UserCfgInit(struct rt_rtmp_adapter *pAd) |
91980990 | 2504 | { |
51126deb | 2505 | u32 key_index, bss_index; |
91980990 GKH |
2506 | |
2507 | DBGPRINT(RT_DEBUG_TRACE, ("--> UserCfgInit\n")); | |
2508 | ||
ec278fa2 BZ |
2509 | /* */ |
2510 | /* part I. intialize common configuration */ | |
2511 | /* */ | |
ca97b838 | 2512 | #ifdef RTMP_MAC_USB |
59fe2d89 BZ |
2513 | pAd->BulkOutReq = 0; |
2514 | ||
2515 | pAd->BulkOutComplete = 0; | |
2516 | pAd->BulkOutCompleteOther = 0; | |
2517 | pAd->BulkOutCompleteCancel = 0; | |
2518 | pAd->BulkInReq = 0; | |
2519 | pAd->BulkInComplete = 0; | |
2520 | pAd->BulkInCompleteFail = 0; | |
2521 | ||
ec278fa2 BZ |
2522 | /*pAd->QuickTimerP = 100; */ |
2523 | /*pAd->TurnAggrBulkInCount = 0; */ | |
59fe2d89 BZ |
2524 | pAd->bUsbTxBulkAggre = 0; |
2525 | ||
ec278fa2 | 2526 | /* init as unsed value to ensure driver will set to MCU once. */ |
ca97b838 | 2527 | pAd->LedIndicatorStrength = 0xFF; |
59fe2d89 BZ |
2528 | |
2529 | pAd->CommonCfg.MaxPktOneTxBulk = 2; | |
2530 | pAd->CommonCfg.TxBulkFactor = 1; | |
96b3c83d | 2531 | pAd->CommonCfg.RxBulkFactor = 1; |
59fe2d89 | 2532 | |
ec278fa2 | 2533 | pAd->CommonCfg.TxPower = 100; /*mW */ |
59fe2d89 | 2534 | |
96b3c83d BZ |
2535 | NdisZeroMemory(&pAd->CommonCfg.IOTestParm, |
2536 | sizeof(pAd->CommonCfg.IOTestParm)); | |
ec278fa2 | 2537 | #endif /* RTMP_MAC_USB // */ |
91980990 | 2538 | |
96b3c83d BZ |
2539 | for (key_index = 0; key_index < SHARE_KEY_NUM; key_index++) { |
2540 | for (bss_index = 0; bss_index < MAX_MBSSID_NUM; bss_index++) { | |
91980990 | 2541 | pAd->SharedKey[bss_index][key_index].KeyLen = 0; |
96b3c83d BZ |
2542 | pAd->SharedKey[bss_index][key_index].CipherAlg = |
2543 | CIPHER_NONE; | |
91980990 GKH |
2544 | } |
2545 | } | |
2546 | ||
59fe2d89 | 2547 | pAd->EepromAccess = FALSE; |
ca97b838 | 2548 | |
91980990 GKH |
2549 | pAd->Antenna.word = 0; |
2550 | pAd->CommonCfg.BBPCurrentBW = BW_20; | |
2551 | ||
2552 | pAd->LedCntl.word = 0; | |
ca97b838 BZ |
2553 | #ifdef RTMP_MAC_PCI |
2554 | pAd->LedIndicatorStrength = 0; | |
91980990 GKH |
2555 | pAd->RLnkCtrlOffset = 0; |
2556 | pAd->HostLnkCtrlOffset = 0; | |
96b3c83d | 2557 | pAd->StaCfg.PSControl.field.EnableNewPS = TRUE; |
e44fd1cf | 2558 | pAd->CheckDmaBusyCount = 0; |
ec278fa2 | 2559 | #endif /* RTMP_MAC_PCI // */ |
91980990 | 2560 | |
ec278fa2 BZ |
2561 | pAd->bAutoTxAgcA = FALSE; /* Default is OFF */ |
2562 | pAd->bAutoTxAgcG = FALSE; /* Default is OFF */ | |
91980990 GKH |
2563 | pAd->RfIcType = RFIC_2820; |
2564 | ||
ec278fa2 | 2565 | /* Init timer for reset complete event */ |
91980990 GKH |
2566 | pAd->CommonCfg.CentralChannel = 1; |
2567 | pAd->bForcePrintTX = FALSE; | |
2568 | pAd->bForcePrintRX = FALSE; | |
2569 | pAd->bStaFifoTest = FALSE; | |
2570 | pAd->bProtectionTest = FALSE; | |
ec278fa2 BZ |
2571 | pAd->CommonCfg.Dsifs = 10; /* in units of usec */ |
2572 | pAd->CommonCfg.TxPower = 100; /*mW */ | |
2573 | pAd->CommonCfg.TxPowerPercentage = 0xffffffff; /* AUTO */ | |
2574 | pAd->CommonCfg.TxPowerDefault = 0xffffffff; /* AUTO */ | |
2575 | pAd->CommonCfg.TxPreamble = Rt802_11PreambleAuto; /* use Long preamble on TX by defaut */ | |
91980990 GKH |
2576 | pAd->CommonCfg.bUseZeroToDisableFragment = FALSE; |
2577 | pAd->CommonCfg.RtsThreshold = 2347; | |
2578 | pAd->CommonCfg.FragmentThreshold = 2346; | |
ec278fa2 BZ |
2579 | pAd->CommonCfg.UseBGProtection = 0; /* 0: AUTO */ |
2580 | pAd->CommonCfg.bEnableTxBurst = TRUE; /*0; */ | |
2581 | pAd->CommonCfg.PhyMode = 0xff; /* unknown */ | |
91980990 GKH |
2582 | pAd->CommonCfg.BandState = UNKNOWN_BAND; |
2583 | pAd->CommonCfg.RadarDetect.CSPeriod = 10; | |
2584 | pAd->CommonCfg.RadarDetect.CSCount = 0; | |
2585 | pAd->CommonCfg.RadarDetect.RDMode = RD_NORMAL_MODE; | |
ca97b838 | 2586 | |
91980990 GKH |
2587 | pAd->CommonCfg.RadarDetect.ChMovingTime = 65; |
2588 | pAd->CommonCfg.RadarDetect.LongPulseRadarTh = 3; | |
2589 | pAd->CommonCfg.bAPSDCapable = FALSE; | |
2590 | pAd->CommonCfg.bNeedSendTriggerFrame = FALSE; | |
2591 | pAd->CommonCfg.TriggerTimerCount = 0; | |
2592 | pAd->CommonCfg.bAPSDForcePowerSave = FALSE; | |
2593 | pAd->CommonCfg.bCountryFlag = FALSE; | |
2594 | pAd->CommonCfg.TxStream = 0; | |
2595 | pAd->CommonCfg.RxStream = 0; | |
2596 | ||
2597 | NdisZeroMemory(&pAd->BeaconTxWI, sizeof(pAd->BeaconTxWI)); | |
2598 | ||
96b3c83d BZ |
2599 | NdisZeroMemory(&pAd->CommonCfg.HtCapability, |
2600 | sizeof(pAd->CommonCfg.HtCapability)); | |
91980990 GKH |
2601 | pAd->HTCEnable = FALSE; |
2602 | pAd->bBroadComHT = FALSE; | |
2603 | pAd->CommonCfg.bRdg = FALSE; | |
2604 | ||
96b3c83d BZ |
2605 | NdisZeroMemory(&pAd->CommonCfg.AddHTInfo, |
2606 | sizeof(pAd->CommonCfg.AddHTInfo)); | |
91980990 GKH |
2607 | pAd->CommonCfg.BACapability.field.MMPSmode = MMPS_ENABLE; |
2608 | pAd->CommonCfg.BACapability.field.MpduDensity = 0; | |
2609 | pAd->CommonCfg.BACapability.field.Policy = IMMED_BA; | |
ec278fa2 BZ |
2610 | pAd->CommonCfg.BACapability.field.RxBAWinLimit = 64; /*32; */ |
2611 | pAd->CommonCfg.BACapability.field.TxBAWinLimit = 64; /*32; */ | |
96b3c83d BZ |
2612 | DBGPRINT(RT_DEBUG_TRACE, |
2613 | ("--> UserCfgInit. BACapability = 0x%x\n", | |
2614 | pAd->CommonCfg.BACapability.word)); | |
91980990 GKH |
2615 | |
2616 | pAd->CommonCfg.BACapability.field.AutoBA = FALSE; | |
2617 | BATableInit(pAd, &pAd->BATable); | |
2618 | ||
2619 | pAd->CommonCfg.bExtChannelSwitchAnnouncement = 1; | |
2620 | pAd->CommonCfg.bHTProtect = 1; | |
2621 | pAd->CommonCfg.bMIMOPSEnable = TRUE; | |
ec278fa2 | 2622 | /*2008/11/05:KH add to support Antenna power-saving of AP<-- */ |
96b3c83d | 2623 | pAd->CommonCfg.bGreenAPEnable = FALSE; |
ec278fa2 | 2624 | /*2008/11/05:KH add to support Antenna power-saving of AP--> */ |
91980990 GKH |
2625 | pAd->CommonCfg.bBADecline = FALSE; |
2626 | pAd->CommonCfg.bDisableReordering = FALSE; | |
2627 | ||
96b3c83d | 2628 | if (pAd->MACVersion == 0x28720200) { |
ec278fa2 | 2629 | pAd->CommonCfg.TxBASize = 13; /*by Jerry recommend */ |
96b3c83d BZ |
2630 | } else { |
2631 | pAd->CommonCfg.TxBASize = 7; | |
ca97b838 | 2632 | } |
91980990 GKH |
2633 | |
2634 | pAd->CommonCfg.REGBACapability.word = pAd->CommonCfg.BACapability.word; | |
91980990 | 2635 | |
ec278fa2 BZ |
2636 | /*pAd->CommonCfg.HTPhyMode.field.BW = BW_20; */ |
2637 | /*pAd->CommonCfg.HTPhyMode.field.MCS = MCS_AUTO; */ | |
2638 | /*pAd->CommonCfg.HTPhyMode.field.ShortGI = GI_800; */ | |
2639 | /*pAd->CommonCfg.HTPhyMode.field.STBC = STBC_NONE; */ | |
91980990 GKH |
2640 | pAd->CommonCfg.TxRate = RATE_6; |
2641 | ||
2642 | pAd->CommonCfg.MlmeTransmit.field.MCS = MCS_RATE_6; | |
2643 | pAd->CommonCfg.MlmeTransmit.field.BW = BW_20; | |
2644 | pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_OFDM; | |
2645 | ||
ec278fa2 | 2646 | pAd->CommonCfg.BeaconPeriod = 100; /* in mSec */ |
91980990 | 2647 | |
ec278fa2 BZ |
2648 | /* */ |
2649 | /* part II. intialize STA specific configuration */ | |
2650 | /* */ | |
91980990 GKH |
2651 | { |
2652 | RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_DIRECT); | |
2653 | RX_FILTER_CLEAR_FLAG(pAd, fRX_FILTER_ACCEPT_MULTICAST); | |
2654 | RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_BROADCAST); | |
2655 | RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_ALL_MULTICAST); | |
2656 | ||
2657 | pAd->StaCfg.Psm = PWR_ACTIVE; | |
2658 | ||
2659 | pAd->StaCfg.OrigWepStatus = Ndis802_11EncryptionDisabled; | |
2660 | pAd->StaCfg.PairCipher = Ndis802_11EncryptionDisabled; | |
2661 | pAd->StaCfg.GroupCipher = Ndis802_11EncryptionDisabled; | |
2662 | pAd->StaCfg.bMixCipher = FALSE; | |
2663 | pAd->StaCfg.DefaultKeyId = 0; | |
2664 | ||
ec278fa2 | 2665 | /* 802.1x port control */ |
91980990 GKH |
2666 | pAd->StaCfg.PrivacyFilter = Ndis802_11PrivFilter8021xWEP; |
2667 | pAd->StaCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED; | |
2668 | pAd->StaCfg.LastMicErrorTime = 0; | |
96b3c83d BZ |
2669 | pAd->StaCfg.MicErrCnt = 0; |
2670 | pAd->StaCfg.bBlockAssoc = FALSE; | |
2671 | pAd->StaCfg.WpaState = SS_NOTUSE; | |
91980990 | 2672 | |
ec278fa2 | 2673 | pAd->CommonCfg.NdisRadioStateOff = FALSE; /* New to support microsoft disable radio with OID command */ |
91980990 GKH |
2674 | |
2675 | pAd->StaCfg.RssiTrigger = 0; | |
62eb734b | 2676 | NdisZeroMemory(&pAd->StaCfg.RssiSample, sizeof(struct rt_rssi_sample)); |
96b3c83d BZ |
2677 | pAd->StaCfg.RssiTriggerMode = |
2678 | RSSI_TRIGGERED_UPON_BELOW_THRESHOLD; | |
91980990 | 2679 | pAd->StaCfg.AtimWin = 0; |
ec278fa2 BZ |
2680 | pAd->StaCfg.DefaultListenCount = 3; /*default listen count; */ |
2681 | pAd->StaCfg.BssType = BSS_INFRA; /* BSS_INFRA or BSS_ADHOC or BSS_MONITOR */ | |
91980990 GKH |
2682 | pAd->StaCfg.bScanReqIsFromWebUI = FALSE; |
2683 | OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE); | |
2684 | OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_WAKEUP_NOW); | |
2685 | ||
2686 | pAd->StaCfg.bAutoTxRateSwitch = TRUE; | |
2687 | pAd->StaCfg.DesiredTransmitSetting.field.MCS = MCS_AUTO; | |
2688 | } | |
91980990 | 2689 | |
e44fd1cf | 2690 | #ifdef PCIE_PS_SUPPORT |
96b3c83d BZ |
2691 | pAd->brt30xxBanMcuCmd = FALSE; |
2692 | pAd->b3090ESpecialChip = FALSE; | |
ec278fa2 | 2693 | /*KH Debug:the following must be removed */ |
96b3c83d BZ |
2694 | pAd->StaCfg.PSControl.field.rt30xxPowerMode = 3; |
2695 | pAd->StaCfg.PSControl.field.rt30xxForceASPMTest = 0; | |
2696 | pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM = 1; | |
ec278fa2 | 2697 | #endif /* PCIE_PS_SUPPORT // */ |
e44fd1cf | 2698 | |
ec278fa2 | 2699 | /* global variables mXXXX used in MAC protocol state machines */ |
91980990 GKH |
2700 | OPSTATUS_SET_FLAG(pAd, fOP_STATUS_RECEIVE_DTIM); |
2701 | OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADHOC_ON); | |
2702 | OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_INFRA_ON); | |
2703 | ||
ec278fa2 BZ |
2704 | /* PHY specification */ |
2705 | pAd->CommonCfg.PhyMode = PHY_11BG_MIXED; /* default PHY mode */ | |
51126deb | 2706 | OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED); /* CCK use long preamble */ |
91980990 | 2707 | |
91980990 | 2708 | { |
ec278fa2 | 2709 | /* user desired power mode */ |
91980990 GKH |
2710 | pAd->StaCfg.WindowsPowerMode = Ndis802_11PowerModeCAM; |
2711 | pAd->StaCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeCAM; | |
2712 | pAd->StaCfg.bWindowsACCAMEnable = FALSE; | |
2713 | ||
96b3c83d BZ |
2714 | RTMPInitTimer(pAd, &pAd->StaCfg.StaQuickResponeForRateUpTimer, |
2715 | GET_TIMER_FUNCTION(StaQuickResponeForRateUpExec), | |
2716 | pAd, FALSE); | |
91980990 GKH |
2717 | pAd->StaCfg.StaQuickResponeForRateUpTimerRunning = FALSE; |
2718 | ||
ec278fa2 | 2719 | /* Patch for Ndtest */ |
91980990 GKH |
2720 | pAd->StaCfg.ScanCnt = 0; |
2721 | ||
ec278fa2 BZ |
2722 | pAd->StaCfg.bHwRadio = TRUE; /* Default Hardware Radio status is On */ |
2723 | pAd->StaCfg.bSwRadio = TRUE; /* Default Software Radio status is On */ | |
2724 | pAd->StaCfg.bRadio = TRUE; /* bHwRadio && bSwRadio */ | |
2725 | pAd->StaCfg.bHardwareRadio = FALSE; /* Default is OFF */ | |
2726 | pAd->StaCfg.bShowHiddenSSID = FALSE; /* Default no show */ | |
91980990 | 2727 | |
ec278fa2 | 2728 | /* Nitro mode control */ |
91980990 GKH |
2729 | pAd->StaCfg.bAutoReconnect = TRUE; |
2730 | ||
ec278fa2 BZ |
2731 | /* Save the init time as last scan time, the system should do scan after 2 seconds. */ |
2732 | /* This patch is for driver wake up from standby mode, system will do scan right away. */ | |
ca97b838 BZ |
2733 | NdisGetSystemUpTime(&pAd->StaCfg.LastScanTime); |
2734 | if (pAd->StaCfg.LastScanTime > 10 * OS_HZ) | |
2735 | pAd->StaCfg.LastScanTime -= (10 * OS_HZ); | |
2736 | ||
96b3c83d | 2737 | NdisZeroMemory(pAd->nickname, IW_ESSID_MAX_SIZE + 1); |
e44fd1cf | 2738 | #ifdef RTMP_MAC_PCI |
51126deb | 2739 | sprintf((char *)pAd->nickname, "RT2860STA"); |
ec278fa2 | 2740 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 | 2741 | #ifdef RTMP_MAC_USB |
51126deb | 2742 | sprintf((char *)pAd->nickname, "RT2870STA"); |
ec278fa2 | 2743 | #endif /* RTMP_MAC_USB // */ |
96b3c83d BZ |
2744 | RTMPInitTimer(pAd, &pAd->StaCfg.WpaDisassocAndBlockAssocTimer, |
2745 | GET_TIMER_FUNCTION(WpaDisassocApAndBlockAssoc), | |
2746 | pAd, FALSE); | |
91980990 GKH |
2747 | pAd->StaCfg.IEEE8021X = FALSE; |
2748 | pAd->StaCfg.IEEE8021x_required_keys = FALSE; | |
2749 | pAd->StaCfg.WpaSupplicantUP = WPA_SUPPLICANT_DISABLE; | |
ca97b838 | 2750 | pAd->StaCfg.bRSN_IE_FromWpaSupplicant = FALSE; |
91980990 | 2751 | pAd->StaCfg.WpaSupplicantUP = WPA_SUPPLICANT_ENABLE; |
ca97b838 BZ |
2752 | |
2753 | NdisZeroMemory(pAd->StaCfg.ReplayCounter, 8); | |
2754 | ||
ca97b838 BZ |
2755 | pAd->StaCfg.bAutoConnectByBssid = FALSE; |
2756 | pAd->StaCfg.BeaconLostTime = BEACON_LOST_TIME; | |
2757 | NdisZeroMemory(pAd->StaCfg.WpaPassPhrase, 64); | |
2758 | pAd->StaCfg.WpaPassPhraseLen = 0; | |
2759 | pAd->StaCfg.bAutoRoaming = FALSE; | |
2760 | pAd->StaCfg.bForceTxBurst = FALSE; | |
91980990 | 2761 | } |
91980990 | 2762 | |
ec278fa2 | 2763 | /* Default for extra information is not valid */ |
91980990 GKH |
2764 | pAd->ExtraInfo = EXTRA_INFO_CLEAR; |
2765 | ||
ec278fa2 | 2766 | /* Default Config change flag */ |
91980990 GKH |
2767 | pAd->bConfigChanged = FALSE; |
2768 | ||
ec278fa2 BZ |
2769 | /* */ |
2770 | /* part III. AP configurations */ | |
2771 | /* */ | |
91980990 | 2772 | |
ec278fa2 BZ |
2773 | /* */ |
2774 | /* part IV. others */ | |
2775 | /* */ | |
2776 | /* dynamic BBP R66:sensibity tuning to overcome background noise */ | |
96b3c83d | 2777 | pAd->BbpTuning.bEnable = TRUE; |
91980990 GKH |
2778 | pAd->BbpTuning.FalseCcaLowerThreshold = 100; |
2779 | pAd->BbpTuning.FalseCcaUpperThreshold = 512; | |
96b3c83d | 2780 | pAd->BbpTuning.R66Delta = 4; |
91980990 GKH |
2781 | pAd->Mlme.bEnableAutoAntennaCheck = TRUE; |
2782 | ||
ec278fa2 BZ |
2783 | /* */ |
2784 | /* Also initial R66CurrentValue, RTUSBResumeMsduTransmission might use this value. */ | |
2785 | /* if not initial this value, the default value will be 0. */ | |
2786 | /* */ | |
91980990 GKH |
2787 | pAd->BbpTuning.R66CurrentValue = 0x38; |
2788 | ||
2789 | pAd->Bbp94 = BBPR94_DEFAULT; | |
2790 | pAd->BbpForCCK = FALSE; | |
2791 | ||
ec278fa2 BZ |
2792 | /* Default is FALSE for test bit 1 */ |
2793 | /*pAd->bTest1 = FALSE; */ | |
ca97b838 | 2794 | |
ec278fa2 | 2795 | /* initialize MAC table and allocate spin lock */ |
62eb734b | 2796 | NdisZeroMemory(&pAd->MacTab, sizeof(struct rt_mac_table)); |
91980990 GKH |
2797 | InitializeQueueHeader(&pAd->MacTab.McastPsQueue); |
2798 | NdisAllocateSpinLock(&pAd->MacTabLock); | |
2799 | ||
ec278fa2 BZ |
2800 | /*RTMPInitTimer(pAd, &pAd->RECBATimer, RECBATimerTimeout, pAd, TRUE); */ |
2801 | /*RTMPSetTimer(&pAd->RECBATimer, REORDER_EXEC_INTV); */ | |
ca97b838 | 2802 | |
91980990 | 2803 | pAd->CommonCfg.bWiFiTest = FALSE; |
ca97b838 | 2804 | #ifdef RTMP_MAC_PCI |
bdc0a173 | 2805 | pAd->bPCIclkOff = FALSE; |
ec278fa2 | 2806 | #endif /* RTMP_MAC_PCI // */ |
91980990 | 2807 | |
96b3c83d | 2808 | RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); |
91980990 GKH |
2809 | DBGPRINT(RT_DEBUG_TRACE, ("<-- UserCfgInit\n")); |
2810 | } | |
2811 | ||
ec278fa2 | 2812 | /* IRQL = PASSIVE_LEVEL */ |
51126deb | 2813 | u8 BtoH(char ch) |
91980990 | 2814 | { |
96b3c83d | 2815 | if (ch >= '0' && ch <= '9') |
ec278fa2 | 2816 | return (ch - '0'); /* Handle numerals */ |
96b3c83d | 2817 | if (ch >= 'A' && ch <= 'F') |
ec278fa2 | 2818 | return (ch - 'A' + 0xA); /* Handle capitol hex digits */ |
96b3c83d | 2819 | if (ch >= 'a' && ch <= 'f') |
ec278fa2 | 2820 | return (ch - 'a' + 0xA); /* Handle small hex digits */ |
96b3c83d | 2821 | return (255); |
91980990 GKH |
2822 | } |
2823 | ||
ec278fa2 | 2824 | /* */ |
51126deb | 2825 | /* FUNCTION: AtoH(char *, u8 *, int) */ |
ec278fa2 BZ |
2826 | /* */ |
2827 | /* PURPOSE: Converts ascii string to network order hex */ | |
2828 | /* */ | |
2829 | /* PARAMETERS: */ | |
2830 | /* src - pointer to input ascii string */ | |
2831 | /* dest - pointer to output hex */ | |
2832 | /* destlen - size of dest */ | |
2833 | /* */ | |
2834 | /* COMMENTS: */ | |
2835 | /* */ | |
2836 | /* 2 ascii bytes make a hex byte so must put 1st ascii byte of pair */ | |
2837 | /* into upper nibble and 2nd ascii byte of pair into lower nibble. */ | |
2838 | /* */ | |
2839 | /* IRQL = PASSIVE_LEVEL */ | |
91980990 | 2840 | |
51126deb | 2841 | void AtoH(char *src, u8 *dest, int destlen) |
91980990 | 2842 | { |
51126deb BZ |
2843 | char *srcptr; |
2844 | u8 *destTemp; | |
91980990 GKH |
2845 | |
2846 | srcptr = src; | |
51126deb | 2847 | destTemp = (u8 *)dest; |
91980990 | 2848 | |
96b3c83d | 2849 | while (destlen--) { |
ec278fa2 BZ |
2850 | *destTemp = BtoH(*srcptr++) << 4; /* Put 1st ascii byte in upper nibble. */ |
2851 | *destTemp += BtoH(*srcptr++); /* Add 2nd ascii byte to above. */ | |
91980990 GKH |
2852 | destTemp++; |
2853 | } | |
2854 | } | |
2855 | ||
ec278fa2 BZ |
2856 | /*+++Mark by shiang, not use now, need to remove after confirm */ |
2857 | /*---Mark by shiang, not use now, need to remove after confirm */ | |
91980990 | 2858 | |
91980990 GKH |
2859 | /* |
2860 | ======================================================================== | |
2861 | ||
2862 | Routine Description: | |
2863 | Init timer objects | |
2864 | ||
2865 | Arguments: | |
2866 | pAd Pointer to our adapter | |
2867 | pTimer Timer structure | |
2868 | pTimerFunc Function to execute when timer expired | |
2869 | Repeat Ture for period timer | |
2870 | ||
2871 | Return Value: | |
2872 | None | |
2873 | ||
2874 | Note: | |
2875 | ||
2876 | ======================================================================== | |
2877 | */ | |
62eb734b BZ |
2878 | void RTMPInitTimer(struct rt_rtmp_adapter *pAd, |
2879 | struct rt_ralink_timer *pTimer, | |
51126deb | 2880 | void *pTimerFunc, void *pData, IN BOOLEAN Repeat) |
91980990 | 2881 | { |
ec278fa2 BZ |
2882 | /* */ |
2883 | /* Set Valid to TRUE for later used. */ | |
2884 | /* It will crash if we cancel a timer or set a timer */ | |
2885 | /* that we haven't initialize before. */ | |
2886 | /* */ | |
96b3c83d | 2887 | pTimer->Valid = TRUE; |
91980990 GKH |
2888 | |
2889 | pTimer->PeriodicType = Repeat; | |
96b3c83d | 2890 | pTimer->State = FALSE; |
51126deb | 2891 | pTimer->cookie = (unsigned long)pData; |
91980990 | 2892 | |
ca97b838 | 2893 | #ifdef RTMP_TIMER_TASK_SUPPORT |
59fe2d89 | 2894 | pTimer->pAd = pAd; |
ec278fa2 | 2895 | #endif /* RTMP_TIMER_TASK_SUPPORT // */ |
91980990 | 2896 | |
51126deb | 2897 | RTMP_OS_Init_Timer(pAd, &pTimer->TimerObj, pTimerFunc, (void *)pTimer); |
91980990 GKH |
2898 | } |
2899 | ||
2900 | /* | |
2901 | ======================================================================== | |
2902 | ||
2903 | Routine Description: | |
2904 | Init timer objects | |
2905 | ||
2906 | Arguments: | |
2907 | pTimer Timer structure | |
2908 | Value Timer value in milliseconds | |
2909 | ||
2910 | Return Value: | |
2911 | None | |
2912 | ||
2913 | Note: | |
2914 | To use this routine, must call RTMPInitTimer before. | |
2915 | ||
2916 | ======================================================================== | |
2917 | */ | |
62eb734b | 2918 | void RTMPSetTimer(struct rt_ralink_timer *pTimer, unsigned long Value) |
91980990 | 2919 | { |
96b3c83d | 2920 | if (pTimer->Valid) { |
91980990 | 2921 | pTimer->TimerValue = Value; |
96b3c83d BZ |
2922 | pTimer->State = FALSE; |
2923 | if (pTimer->PeriodicType == TRUE) { | |
91980990 GKH |
2924 | pTimer->Repeat = TRUE; |
2925 | RTMP_SetPeriodicTimer(&pTimer->TimerObj, Value); | |
96b3c83d | 2926 | } else { |
91980990 GKH |
2927 | pTimer->Repeat = FALSE; |
2928 | RTMP_OS_Add_Timer(&pTimer->TimerObj, Value); | |
2929 | } | |
96b3c83d | 2930 | } else { |
91980990 GKH |
2931 | DBGPRINT_ERR(("RTMPSetTimer failed, Timer hasn't been initialize!\n")); |
2932 | } | |
2933 | } | |
2934 | ||
91980990 GKH |
2935 | /* |
2936 | ======================================================================== | |
2937 | ||
2938 | Routine Description: | |
2939 | Init timer objects | |
2940 | ||
2941 | Arguments: | |
2942 | pTimer Timer structure | |
2943 | Value Timer value in milliseconds | |
2944 | ||
2945 | Return Value: | |
2946 | None | |
2947 | ||
2948 | Note: | |
2949 | To use this routine, must call RTMPInitTimer before. | |
2950 | ||
2951 | ======================================================================== | |
2952 | */ | |
62eb734b | 2953 | void RTMPModTimer(struct rt_ralink_timer *pTimer, unsigned long Value) |
91980990 | 2954 | { |
96b3c83d | 2955 | BOOLEAN Cancel; |
91980990 | 2956 | |
96b3c83d | 2957 | if (pTimer->Valid) { |
91980990 | 2958 | pTimer->TimerValue = Value; |
96b3c83d BZ |
2959 | pTimer->State = FALSE; |
2960 | if (pTimer->PeriodicType == TRUE) { | |
91980990 GKH |
2961 | RTMPCancelTimer(pTimer, &Cancel); |
2962 | RTMPSetTimer(pTimer, Value); | |
96b3c83d | 2963 | } else { |
91980990 GKH |
2964 | RTMP_OS_Mod_Timer(&pTimer->TimerObj, Value); |
2965 | } | |
96b3c83d | 2966 | } else { |
91980990 GKH |
2967 | DBGPRINT_ERR(("RTMPModTimer failed, Timer hasn't been initialize!\n")); |
2968 | } | |
2969 | } | |
2970 | ||
2971 | /* | |
2972 | ======================================================================== | |
2973 | ||
2974 | Routine Description: | |
2975 | Cancel timer objects | |
2976 | ||
2977 | Arguments: | |
2978 | Adapter Pointer to our adapter | |
2979 | ||
2980 | Return Value: | |
2981 | None | |
2982 | ||
2983 | IRQL = PASSIVE_LEVEL | |
2984 | IRQL = DISPATCH_LEVEL | |
2985 | ||
2986 | Note: | |
2987 | 1.) To use this routine, must call RTMPInitTimer before. | |
2988 | 2.) Reset NIC to initial state AS IS system boot up time. | |
2989 | ||
2990 | ======================================================================== | |
2991 | */ | |
62eb734b | 2992 | void RTMPCancelTimer(struct rt_ralink_timer *pTimer, OUT BOOLEAN * pCancelled) |
91980990 | 2993 | { |
96b3c83d | 2994 | if (pTimer->Valid) { |
91980990 GKH |
2995 | if (pTimer->State == FALSE) |
2996 | pTimer->Repeat = FALSE; | |
ca97b838 | 2997 | |
96b3c83d | 2998 | RTMP_OS_Del_Timer(&pTimer->TimerObj, pCancelled); |
91980990 GKH |
2999 | |
3000 | if (*pCancelled == TRUE) | |
3001 | pTimer->State = TRUE; | |
3002 | ||
ca97b838 | 3003 | #ifdef RTMP_TIMER_TASK_SUPPORT |
ec278fa2 BZ |
3004 | /* We need to go-through the TimerQ to findout this timer handler and remove it if */ |
3005 | /* it's still waiting for execution. */ | |
ca97b838 | 3006 | RtmpTimerQRemove(pTimer->pAd, pTimer); |
ec278fa2 | 3007 | #endif /* RTMP_TIMER_TASK_SUPPORT // */ |
96b3c83d | 3008 | } else { |
91980990 GKH |
3009 | DBGPRINT_ERR(("RTMPCancelTimer failed, Timer hasn't been initialize!\n")); |
3010 | } | |
3011 | } | |
3012 | ||
3013 | /* | |
3014 | ======================================================================== | |
3015 | ||
3016 | Routine Description: | |
3017 | Set LED Status | |
3018 | ||
3019 | Arguments: | |
3020 | pAd Pointer to our adapter | |
3021 | Status LED Status | |
3022 | ||
3023 | Return Value: | |
3024 | None | |
3025 | ||
3026 | IRQL = PASSIVE_LEVEL | |
3027 | IRQL = DISPATCH_LEVEL | |
3028 | ||
3029 | Note: | |
3030 | ||
3031 | ======================================================================== | |
3032 | */ | |
62eb734b | 3033 | void RTMPSetLED(struct rt_rtmp_adapter *pAd, u8 Status) |
91980990 | 3034 | { |
51126deb BZ |
3035 | /*unsigned long data; */ |
3036 | u8 HighByte = 0; | |
3037 | u8 LowByte; | |
96b3c83d BZ |
3038 | |
3039 | LowByte = pAd->LedCntl.field.LedMode & 0x7f; | |
3040 | switch (Status) { | |
3041 | case LED_LINK_DOWN: | |
3042 | HighByte = 0x20; | |
3043 | AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte); | |
3044 | pAd->LedIndicatorStrength = 0; | |
3045 | break; | |
3046 | case LED_LINK_UP: | |
3047 | if (pAd->CommonCfg.Channel > 14) | |
3048 | HighByte = 0xa0; | |
3049 | else | |
3050 | HighByte = 0x60; | |
3051 | AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte); | |
3052 | break; | |
3053 | case LED_RADIO_ON: | |
3054 | HighByte = 0x20; | |
3055 | AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte); | |
3056 | break; | |
3057 | case LED_HALT: | |
ec278fa2 | 3058 | LowByte = 0; /* Driver sets MAC register and MAC controls LED */ |
96b3c83d BZ |
3059 | case LED_RADIO_OFF: |
3060 | HighByte = 0; | |
3061 | AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte); | |
3062 | break; | |
3063 | case LED_WPS: | |
3064 | HighByte = 0x10; | |
3065 | AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte); | |
3066 | break; | |
3067 | case LED_ON_SITE_SURVEY: | |
3068 | HighByte = 0x08; | |
3069 | AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte); | |
3070 | break; | |
3071 | case LED_POWER_UP: | |
3072 | HighByte = 0x04; | |
3073 | AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte); | |
3074 | break; | |
3075 | default: | |
3076 | DBGPRINT(RT_DEBUG_WARN, | |
3077 | ("RTMPSetLED::Unknown Status %d\n", Status)); | |
3078 | break; | |
91980990 GKH |
3079 | } |
3080 | ||
ec278fa2 BZ |
3081 | /* */ |
3082 | /* Keep LED status for LED SiteSurvey mode. */ | |
3083 | /* After SiteSurvey, we will set the LED mode to previous status. */ | |
3084 | /* */ | |
91980990 GKH |
3085 | if ((Status != LED_ON_SITE_SURVEY) && (Status != LED_POWER_UP)) |
3086 | pAd->LedStatus = Status; | |
3087 | ||
96b3c83d BZ |
3088 | DBGPRINT(RT_DEBUG_TRACE, |
3089 | ("RTMPSetLED::Mode=%d,HighByte=0x%02x,LowByte=0x%02x\n", | |
3090 | pAd->LedCntl.field.LedMode, HighByte, LowByte)); | |
91980990 GKH |
3091 | } |
3092 | ||
3093 | /* | |
3094 | ======================================================================== | |
3095 | ||
3096 | Routine Description: | |
3097 | Set LED Signal Stregth | |
3098 | ||
3099 | Arguments: | |
3100 | pAd Pointer to our adapter | |
3101 | Dbm Signal Stregth | |
3102 | ||
3103 | Return Value: | |
3104 | None | |
3105 | ||
3106 | IRQL = PASSIVE_LEVEL | |
3107 | ||
3108 | Note: | |
3109 | Can be run on any IRQL level. | |
3110 | ||
3111 | According to Microsoft Zero Config Wireless Signal Stregth definition as belows. | |
3112 | <= -90 No Signal | |
3113 | <= -81 Very Low | |
3114 | <= -71 Low | |
3115 | <= -67 Good | |
3116 | <= -57 Very Good | |
3117 | > -57 Excellent | |
3118 | ======================================================================== | |
3119 | */ | |
62eb734b | 3120 | void RTMPSetSignalLED(struct rt_rtmp_adapter *pAd, IN NDIS_802_11_RSSI Dbm) |
91980990 | 3121 | { |
51126deb | 3122 | u8 nLed = 0; |
96b3c83d BZ |
3123 | |
3124 | if (pAd->LedCntl.field.LedMode == LED_MODE_SIGNAL_STREGTH) { | |
3125 | if (Dbm <= -90) | |
3126 | nLed = 0; | |
3127 | else if (Dbm <= -81) | |
3128 | nLed = 1; | |
3129 | else if (Dbm <= -71) | |
3130 | nLed = 3; | |
3131 | else if (Dbm <= -67) | |
3132 | nLed = 7; | |
3133 | else if (Dbm <= -57) | |
3134 | nLed = 15; | |
3135 | else | |
3136 | nLed = 31; | |
91980990 | 3137 | |
ec278fa2 BZ |
3138 | /* */ |
3139 | /* Update Signal Stregth to firmware if changed. */ | |
3140 | /* */ | |
96b3c83d BZ |
3141 | if (pAd->LedIndicatorStrength != nLed) { |
3142 | AsicSendCommandToMcu(pAd, 0x51, 0xff, nLed, | |
3143 | pAd->LedCntl.field.Polarity); | |
3144 | pAd->LedIndicatorStrength = nLed; | |
3145 | } | |
91980990 GKH |
3146 | } |
3147 | } | |
3148 | ||
3149 | /* | |
3150 | ======================================================================== | |
3151 | ||
3152 | Routine Description: | |
3153 | Enable RX | |
3154 | ||
3155 | Arguments: | |
3156 | pAd Pointer to our adapter | |
3157 | ||
3158 | Return Value: | |
3159 | None | |
3160 | ||
3161 | IRQL <= DISPATCH_LEVEL | |
3162 | ||
3163 | Note: | |
3164 | Before Enable RX, make sure you have enabled Interrupt. | |
3165 | ======================================================================== | |
3166 | */ | |
62eb734b | 3167 | void RTMPEnableRxTx(struct rt_rtmp_adapter *pAd) |
91980990 | 3168 | { |
ec278fa2 | 3169 | /* WPDMA_GLO_CFG_STRUC GloCfg; */ |
51126deb BZ |
3170 | /* unsigned long i = 0; */ |
3171 | u32 rx_filter_flag; | |
ca97b838 | 3172 | |
91980990 GKH |
3173 | DBGPRINT(RT_DEBUG_TRACE, ("==> RTMPEnableRxTx\n")); |
3174 | ||
ec278fa2 | 3175 | /* Enable Rx DMA. */ |
91980990 GKH |
3176 | RT28XXDMAEnable(pAd); |
3177 | ||
ec278fa2 | 3178 | /* enable RX of MAC block */ |
96b3c83d | 3179 | if (pAd->OpMode == OPMODE_AP) { |
ca97b838 | 3180 | rx_filter_flag = APNORMAL; |
91980990 | 3181 | |
ec278fa2 | 3182 | RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, rx_filter_flag); /* enable RX of DMA block */ |
96b3c83d | 3183 | } else { |
ca97b838 BZ |
3184 | if (pAd->CommonCfg.PSPXlink) |
3185 | rx_filter_flag = PSPXLINK; | |
3186 | else | |
ec278fa2 | 3187 | rx_filter_flag = STANORMAL; /* Staion not drop control frame will fail WiFi Certification. */ |
ca97b838 | 3188 | RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, rx_filter_flag); |
91980990 GKH |
3189 | } |
3190 | ||
3191 | RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0xc); | |
3192 | DBGPRINT(RT_DEBUG_TRACE, ("<== RTMPEnableRxTx\n")); | |
3193 | } | |
3194 | ||
ec278fa2 | 3195 | /*+++Add by shiang, move from os/linux/rt_main_dev.c */ |
62eb734b | 3196 | void CfgInitHook(struct rt_rtmp_adapter *pAd) |
ca97b838 BZ |
3197 | { |
3198 | pAd->bBroadComHT = TRUE; | |
3199 | } | |
3200 | ||
62eb734b | 3201 | int rt28xx_init(struct rt_rtmp_adapter *pAd, |
51126deb | 3202 | char *pDefaultMac, char *pHostName) |
ca97b838 | 3203 | { |
51126deb BZ |
3204 | u32 index; |
3205 | u8 TmpPhy; | |
3206 | int Status; | |
3207 | u32 MacCsr0 = 0; | |
ca97b838 BZ |
3208 | |
3209 | #ifdef RTMP_MAC_PCI | |
3210 | { | |
ec278fa2 BZ |
3211 | /* If dirver doesn't wake up firmware here, */ |
3212 | /* NICLoadFirmware will hang forever when interface is up again. */ | |
3213 | /* RT2860 PCI */ | |
96b3c83d BZ |
3214 | if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) && |
3215 | OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) { | |
3216 | AUTO_WAKEUP_STRUC AutoWakeupCfg; | |
ca97b838 | 3217 | AsicForceWakeup(pAd, TRUE); |
96b3c83d BZ |
3218 | AutoWakeupCfg.word = 0; |
3219 | RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, | |
3220 | AutoWakeupCfg.word); | |
3221 | OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE); | |
3222 | } | |
ca97b838 | 3223 | } |
ec278fa2 | 3224 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 | 3225 | |
ec278fa2 | 3226 | /* reset Adapter flags */ |
ca97b838 BZ |
3227 | RTMP_CLEAR_FLAGS(pAd); |
3228 | ||
ec278fa2 | 3229 | /* Init BssTab & ChannelInfo tabbles for auto channel select. */ |
ca97b838 | 3230 | |
ec278fa2 | 3231 | /* Allocate BA Reordering memory */ |
ca97b838 BZ |
3232 | ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM); |
3233 | ||
ec278fa2 | 3234 | /* Make sure MAC gets ready. */ |
ca97b838 | 3235 | index = 0; |
96b3c83d | 3236 | do { |
ca97b838 BZ |
3237 | RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); |
3238 | pAd->MACVersion = MacCsr0; | |
3239 | ||
96b3c83d BZ |
3240 | if ((pAd->MACVersion != 0x00) |
3241 | && (pAd->MACVersion != 0xFFFFFFFF)) | |
ca97b838 BZ |
3242 | break; |
3243 | ||
3244 | RTMPusecDelay(10); | |
3245 | } while (index++ < 100); | |
96b3c83d BZ |
3246 | DBGPRINT(RT_DEBUG_TRACE, |
3247 | ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion)); | |
ca97b838 BZ |
3248 | |
3249 | #ifdef RTMP_MAC_PCI | |
e44fd1cf BZ |
3250 | #ifdef PCIE_PS_SUPPORT |
3251 | /*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */ | |
96b3c83d BZ |
3252 | if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) |
3253 | && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) { | |
e44fd1cf BZ |
3254 | RTMP_IO_READ32(pAd, AUX_CTRL, &MacCsr0); |
3255 | MacCsr0 |= 0x402; | |
3256 | RTMP_IO_WRITE32(pAd, AUX_CTRL, MacCsr0); | |
3257 | DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacCsr0)); | |
3258 | } | |
ec278fa2 | 3259 | #endif /* PCIE_PS_SUPPORT // */ |
ca97b838 | 3260 | |
ec278fa2 | 3261 | /* To fix driver disable/enable hang issue when radio off */ |
ca97b838 | 3262 | RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2); |
ec278fa2 | 3263 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 | 3264 | |
ec278fa2 | 3265 | /* Disable DMA */ |
ca97b838 BZ |
3266 | RT28XXDMADisable(pAd); |
3267 | ||
ec278fa2 | 3268 | /* Load 8051 firmware */ |
ca97b838 | 3269 | Status = NICLoadFirmware(pAd); |
96b3c83d BZ |
3270 | if (Status != NDIS_STATUS_SUCCESS) { |
3271 | DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", | |
3272 | Status)); | |
ca97b838 BZ |
3273 | goto err1; |
3274 | } | |
3275 | ||
3276 | NICLoadRateSwitchingParams(pAd); | |
3277 | ||
ec278fa2 BZ |
3278 | /* Disable interrupts here which is as soon as possible */ |
3279 | /* This statement should never be true. We might consider to remove it later */ | |
ca97b838 | 3280 | #ifdef RTMP_MAC_PCI |
96b3c83d | 3281 | if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) { |
ca97b838 BZ |
3282 | RTMP_ASIC_INTERRUPT_DISABLE(pAd); |
3283 | } | |
ec278fa2 | 3284 | #endif /* RTMP_MAC_PCI // */ |
ca97b838 BZ |
3285 | |
3286 | Status = RTMPAllocTxRxRingMemory(pAd); | |
96b3c83d BZ |
3287 | if (Status != NDIS_STATUS_SUCCESS) { |
3288 | DBGPRINT_ERR(("RTMPAllocDMAMemory failed, Status[=0x%08x]\n", | |
3289 | Status)); | |
ca97b838 BZ |
3290 | goto err1; |
3291 | } | |
3292 | ||
3293 | RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); | |
3294 | ||
ec278fa2 BZ |
3295 | /* initialize MLME */ |
3296 | /* */ | |
ca97b838 BZ |
3297 | |
3298 | Status = RtmpMgmtTaskInit(pAd); | |
3299 | if (Status != NDIS_STATUS_SUCCESS) | |
3300 | goto err2; | |
3301 | ||
3302 | Status = MlmeInit(pAd); | |
96b3c83d | 3303 | if (Status != NDIS_STATUS_SUCCESS) { |
ca97b838 BZ |
3304 | DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status)); |
3305 | goto err2; | |
3306 | } | |
ec278fa2 BZ |
3307 | /* Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default */ |
3308 | /* */ | |
ca97b838 BZ |
3309 | UserCfgInit(pAd); |
3310 | Status = RtmpNetTaskInit(pAd); | |
3311 | if (Status != NDIS_STATUS_SUCCESS) | |
3312 | goto err3; | |
3313 | ||
ec278fa2 BZ |
3314 | /* COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr); */ |
3315 | /* pAd->bForcePrintTX = TRUE; */ | |
ca97b838 BZ |
3316 | |
3317 | CfgInitHook(pAd); | |
3318 | ||
96b3c83d | 3319 | NdisAllocateSpinLock(&pAd->MacTabLock); |
ca97b838 BZ |
3320 | |
3321 | MeasureReqTabInit(pAd); | |
3322 | TpcReqTabInit(pAd); | |
3323 | ||
ec278fa2 BZ |
3324 | /* */ |
3325 | /* Init the hardware, we need to init asic before read registry, otherwise mac register will be reset */ | |
3326 | /* */ | |
ca97b838 | 3327 | Status = NICInitializeAdapter(pAd, TRUE); |
96b3c83d BZ |
3328 | if (Status != NDIS_STATUS_SUCCESS) { |
3329 | DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", | |
3330 | Status)); | |
ca97b838 | 3331 | if (Status != NDIS_STATUS_SUCCESS) |
96b3c83d | 3332 | goto err3; |
ca97b838 BZ |
3333 | } |
3334 | ||
ca97b838 | 3335 | DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); |
ca97b838 BZ |
3336 | |
3337 | #ifdef RTMP_MAC_USB | |
3338 | pAd->CommonCfg.bMultipleIRP = FALSE; | |
3339 | ||
3340 | if (pAd->CommonCfg.bMultipleIRP) | |
3341 | pAd->CommonCfg.NumOfBulkInIRP = RX_RING_SIZE; | |
3342 | else | |
3343 | pAd->CommonCfg.NumOfBulkInIRP = 1; | |
ec278fa2 | 3344 | #endif /* RTMP_MAC_USB // */ |
ca97b838 | 3345 | |
ec278fa2 BZ |
3346 | /*Init Ba Capability parameters. */ |
3347 | /* RT28XX_BA_INIT(pAd); */ | |
96b3c83d | 3348 | pAd->CommonCfg.DesiredHtPhy.MpduDensity = |
51126deb | 3349 | (u8)pAd->CommonCfg.BACapability.field.MpduDensity; |
96b3c83d | 3350 | pAd->CommonCfg.DesiredHtPhy.AmsduEnable = |
51126deb | 3351 | (u16)pAd->CommonCfg.BACapability.field.AmsduEnable; |
96b3c83d | 3352 | pAd->CommonCfg.DesiredHtPhy.AmsduSize = |
51126deb | 3353 | (u16)pAd->CommonCfg.BACapability.field.AmsduSize; |
96b3c83d | 3354 | pAd->CommonCfg.DesiredHtPhy.MimoPs = |
51126deb | 3355 | (u16)pAd->CommonCfg.BACapability.field.MMPSmode; |
ec278fa2 | 3356 | /* UPdata to HT IE */ |
96b3c83d | 3357 | pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = |
51126deb | 3358 | (u16)pAd->CommonCfg.BACapability.field.MMPSmode; |
96b3c83d | 3359 | pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = |
51126deb | 3360 | (u16)pAd->CommonCfg.BACapability.field.AmsduSize; |
96b3c83d | 3361 | pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = |
51126deb | 3362 | (u8)pAd->CommonCfg.BACapability.field.MpduDensity; |
ca97b838 | 3363 | |
ec278fa2 | 3364 | /* after reading Registry, we now know if in AP mode or STA mode */ |
ca97b838 | 3365 | |
ec278fa2 BZ |
3366 | /* Load 8051 firmware; crash when FW image not existent */ |
3367 | /* Status = NICLoadFirmware(pAd); */ | |
3368 | /* if (Status != NDIS_STATUS_SUCCESS) */ | |
3369 | /* break; */ | |
ca97b838 BZ |
3370 | |
3371 | DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); | |
3372 | ||
ec278fa2 | 3373 | /* We should read EEPROM for all cases. rt2860b */ |
51126deb | 3374 | NICReadEEPROMParameters(pAd, (u8 *)pDefaultMac); |
ca97b838 BZ |
3375 | |
3376 | DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); | |
3377 | ||
ec278fa2 | 3378 | NICInitAsicFromEEPROM(pAd); /*rt2860b */ |
ca97b838 | 3379 | |
ec278fa2 | 3380 | /* Set PHY to appropriate mode */ |
ca97b838 BZ |
3381 | TmpPhy = pAd->CommonCfg.PhyMode; |
3382 | pAd->CommonCfg.PhyMode = 0xff; | |
3383 | RTMPSetPhyMode(pAd, TmpPhy); | |
3384 | SetCommonHT(pAd); | |
3385 | ||
ec278fa2 | 3386 | /* No valid channels. */ |
96b3c83d BZ |
3387 | if (pAd->ChannelListNum == 0) { |
3388 | DBGPRINT(RT_DEBUG_ERROR, | |
3389 | ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n")); | |
ca97b838 BZ |
3390 | goto err4; |
3391 | } | |
3392 | ||
96b3c83d BZ |
3393 | DBGPRINT(RT_DEBUG_OFF, |
3394 | ("MCS Set = %02x %02x %02x %02x %02x\n", | |
3395 | pAd->CommonCfg.HtCapability.MCSSet[0], | |
3396 | pAd->CommonCfg.HtCapability.MCSSet[1], | |
3397 | pAd->CommonCfg.HtCapability.MCSSet[2], | |
3398 | pAd->CommonCfg.HtCapability.MCSSet[3], | |
3399 | pAd->CommonCfg.HtCapability.MCSSet[4])); | |
ca97b838 BZ |
3400 | |
3401 | #ifdef RTMP_RF_RW_SUPPORT | |
ec278fa2 | 3402 | /*Init RT30xx RFRegisters after read RFIC type from EEPROM */ |
ca97b838 | 3403 | NICInitRFRegisters(pAd); |
ec278fa2 | 3404 | #endif /* RTMP_RF_RW_SUPPORT // */ |
ca97b838 | 3405 | |
ec278fa2 | 3406 | /* APInitialize(pAd); */ |
ca97b838 | 3407 | |
ec278fa2 BZ |
3408 | /* */ |
3409 | /* Initialize RF register to default value */ | |
3410 | /* */ | |
ca97b838 BZ |
3411 | AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); |
3412 | AsicLockChannel(pAd, pAd->CommonCfg.Channel); | |
3413 | ||
ec278fa2 BZ |
3414 | /* 8051 firmware require the signal during booting time. */ |
3415 | /*2008/11/28:KH marked the following codes to patch Frequency offset bug */ | |
3416 | /*AsicSendCommandToMcu(pAd, 0x72, 0xFF, 0x00, 0x00); */ | |
ca97b838 | 3417 | |
96b3c83d | 3418 | if (pAd && (Status != NDIS_STATUS_SUCCESS)) { |
ec278fa2 BZ |
3419 | /* */ |
3420 | /* Undo everything if it failed */ | |
3421 | /* */ | |
96b3c83d | 3422 | if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) { |
ec278fa2 | 3423 | /* NdisMDeregisterInterrupt(&pAd->Interrupt); */ |
ca97b838 BZ |
3424 | RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); |
3425 | } | |
ec278fa2 | 3426 | /* RTMPFreeAdapter(pAd); // we will free it in disconnect() */ |
96b3c83d | 3427 | } else if (pAd) { |
ec278fa2 | 3428 | /* Microsoft HCT require driver send a disconnect event after driver initialization. */ |
ca97b838 | 3429 | OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED); |
ec278fa2 | 3430 | /* pAd->IndicateMediaState = NdisMediaStateDisconnected; */ |
ca97b838 BZ |
3431 | RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE); |
3432 | ||
96b3c83d BZ |
3433 | DBGPRINT(RT_DEBUG_TRACE, |
3434 | ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n")); | |
ca97b838 BZ |
3435 | |
3436 | #ifdef RTMP_MAC_USB | |
3437 | RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS); | |
3438 | RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_REMOVE_IN_PROGRESS); | |
3439 | ||
ec278fa2 BZ |
3440 | /* */ |
3441 | /* Support multiple BulkIn IRP, */ | |
3442 | /* the value on pAd->CommonCfg.NumOfBulkInIRP may be large than 1. */ | |
3443 | /* */ | |
96b3c83d | 3444 | for (index = 0; index < pAd->CommonCfg.NumOfBulkInIRP; index++) { |
ca97b838 | 3445 | RTUSBBulkReceive(pAd); |
96b3c83d | 3446 | DBGPRINT(RT_DEBUG_TRACE, ("RTUSBBulkReceive!\n")); |
ca97b838 | 3447 | } |
ec278fa2 BZ |
3448 | #endif /* RTMP_MAC_USB // */ |
3449 | } /* end of else */ | |
ca97b838 | 3450 | |
ec278fa2 | 3451 | /* Set up the Mac address */ |
ca97b838 BZ |
3452 | RtmpOSNetDevAddrSet(pAd->net_dev, &pAd->CurrentAddress[0]); |
3453 | ||
3454 | DBGPRINT_S(Status, ("<==== rt28xx_init, Status=%x\n", Status)); | |
3455 | ||
3456 | return TRUE; | |
3457 | ||
ca97b838 BZ |
3458 | err4: |
3459 | err3: | |
3460 | MlmeHalt(pAd); | |
3461 | err2: | |
3462 | RTMPFreeTxRxRingMemory(pAd); | |
3463 | err1: | |
3464 | ||
ec278fa2 | 3465 | os_free_mem(pAd, pAd->mpdu_blk_pool.mem); /* free BA pool */ |
ca97b838 | 3466 | |
ec278fa2 BZ |
3467 | /* shall not set priv to NULL here because the priv didn't been free yet. */ |
3468 | /*net_dev->ml_priv = 0; */ | |
ca97b838 BZ |
3469 | #ifdef ST |
3470 | err0: | |
ec278fa2 | 3471 | #endif /* ST // */ |
ca97b838 BZ |
3472 | |
3473 | DBGPRINT(RT_DEBUG_ERROR, ("!!! rt28xx Initialized fail !!!\n")); | |
3474 | return FALSE; | |
3475 | } | |
ca97b838 | 3476 | |
ec278fa2 | 3477 | /*---Add by shiang, move from os/linux/rt_main_dev.c */ |
ca97b838 | 3478 | |
62eb734b | 3479 | static int RtmpChipOpsRegister(struct rt_rtmp_adapter *pAd, int infType) |
ca97b838 | 3480 | { |
62eb734b | 3481 | struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps; |
ca97b838 BZ |
3482 | int status; |
3483 | ||
62eb734b | 3484 | memset(pChipOps, 0, sizeof(struct rt_rtmp_chip_op)); |
ca97b838 BZ |
3485 | |
3486 | /* set eeprom related hook functions */ | |
3487 | status = RtmpChipOpsEepromHook(pAd, infType); | |
3488 | ||
3489 | /* set mcu related hook functions */ | |
96b3c83d | 3490 | switch (infType) { |
ca97b838 | 3491 | #ifdef RTMP_PCI_SUPPORT |
96b3c83d BZ |
3492 | case RTMP_DEV_INF_PCI: |
3493 | pChipOps->loadFirmware = RtmpAsicLoadFirmware; | |
3494 | pChipOps->eraseFirmware = RtmpAsicEraseFirmware; | |
3495 | pChipOps->sendCommandToMcu = RtmpAsicSendCommandToMcu; | |
3496 | break; | |
ec278fa2 | 3497 | #endif /* RTMP_PCI_SUPPORT // */ |
ca97b838 | 3498 | #ifdef RTMP_USB_SUPPORT |
96b3c83d BZ |
3499 | case RTMP_DEV_INF_USB: |
3500 | pChipOps->loadFirmware = RtmpAsicLoadFirmware; | |
3501 | pChipOps->sendCommandToMcu = RtmpAsicSendCommandToMcu; | |
3502 | break; | |
ec278fa2 | 3503 | #endif /* RTMP_USB_SUPPORT // */ |
96b3c83d BZ |
3504 | default: |
3505 | break; | |
ca97b838 BZ |
3506 | } |
3507 | ||
3508 | return status; | |
3509 | } | |
3510 | ||
62eb734b | 3511 | int RtmpRaDevCtrlInit(struct rt_rtmp_adapter *pAd, IN RTMP_INF_TYPE infType) |
ca97b838 | 3512 | { |
51126deb | 3513 | /*void *handle; */ |
ca97b838 | 3514 | |
ec278fa2 | 3515 | /* Assign the interface type. We need use it when do register/EEPROM access. */ |
ca97b838 BZ |
3516 | pAd->infType = infType; |
3517 | ||
ca97b838 | 3518 | pAd->OpMode = OPMODE_STA; |
96b3c83d BZ |
3519 | DBGPRINT(RT_DEBUG_TRACE, |
3520 | ("STA Driver version-%s\n", STA_DRIVER_VERSION)); | |
ca97b838 BZ |
3521 | |
3522 | #ifdef RTMP_MAC_USB | |
3523 | init_MUTEX(&(pAd->UsbVendorReq_semaphore)); | |
51126deb | 3524 | os_alloc_mem(pAd, (u8 **) & pAd->UsbVendorReqBuf, |
ca58fb30 | 3525 | MAX_PARAM_BUFFER_SIZE - 1); |
96b3c83d BZ |
3526 | if (pAd->UsbVendorReqBuf == NULL) { |
3527 | DBGPRINT(RT_DEBUG_ERROR, | |
3528 | ("Allocate vendor request temp buffer failed!\n")); | |
ca97b838 BZ |
3529 | return FALSE; |
3530 | } | |
ec278fa2 | 3531 | #endif /* RTMP_MAC_USB // */ |
ca97b838 BZ |
3532 | |
3533 | RtmpChipOpsRegister(pAd, infType); | |
3534 | ||
ca97b838 BZ |
3535 | return 0; |
3536 | } | |
3537 | ||
62eb734b | 3538 | BOOLEAN RtmpRaDevCtrlExit(struct rt_rtmp_adapter *pAd) |
ca97b838 BZ |
3539 | { |
3540 | ||
ca97b838 BZ |
3541 | RTMPFreeAdapter(pAd); |
3542 | ||
3543 | return TRUE; | |
3544 | } | |
3545 | ||
ec278fa2 | 3546 | /* not yet support MBSS */ |
62eb734b | 3547 | struct net_device *get_netdev_from_bssid(struct rt_rtmp_adapter *pAd, u8 FromWhichBSSID) |
ca97b838 | 3548 | { |
8a10a546 | 3549 | struct net_device *dev_p = NULL; |
ca97b838 BZ |
3550 | |
3551 | { | |
3552 | dev_p = pAd->net_dev; | |
3553 | } | |
3554 | ||
3555 | ASSERT(dev_p); | |
96b3c83d | 3556 | return dev_p; /* return one of MBSS */ |
ca97b838 | 3557 | } |