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Staging: rt28x0: remove typedefs (part three)
[net-next-2.6.git] / drivers / staging / rt2860 / chip / rtmp_phy.h
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1/*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26
27 Module Name:
28 rtmp_phy.h
29
30 Abstract:
31 Ralink Wireless Chip PHY(BBP/RF) related definition & structures
32
33 Revision History:
34 Who When What
35 -------- ---------- ----------------------------------------------
36*/
37
38#ifndef __RTMP_PHY_H__
39#define __RTMP_PHY_H__
40
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41/*
42 RF sections
43*/
44#define RF_R00 0
45#define RF_R01 1
46#define RF_R02 2
47#define RF_R03 3
48#define RF_R04 4
49#define RF_R05 5
50#define RF_R06 6
51#define RF_R07 7
52#define RF_R08 8
53#define RF_R09 9
54#define RF_R10 10
55#define RF_R11 11
56#define RF_R12 12
57#define RF_R13 13
58#define RF_R14 14
59#define RF_R15 15
60#define RF_R16 16
61#define RF_R17 17
62#define RF_R18 18
63#define RF_R19 19
64#define RF_R20 20
65#define RF_R21 21
66#define RF_R22 22
67#define RF_R23 23
68#define RF_R24 24
69#define RF_R25 25
70#define RF_R26 26
71#define RF_R27 27
72#define RF_R28 28
73#define RF_R29 29
74#define RF_R30 30
75#define RF_R31 31
76
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77/* value domain of pAd->RfIcType */
78#define RFIC_2820 1 /* 2.4G 2T3R */
79#define RFIC_2850 2 /* 2.4G/5G 2T3R */
80#define RFIC_2720 3 /* 2.4G 1T2R */
81#define RFIC_2750 4 /* 2.4G/5G 1T2R */
82#define RFIC_3020 5 /* 2.4G 1T1R */
83#define RFIC_2020 6 /* 2.4G B/G */
84#define RFIC_3021 7 /* 2.4G 1T2R */
85#define RFIC_3022 8 /* 2.4G 2T2R */
86#define RFIC_3052 9 /* 2.4G/5G 2T2R */
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87
88/*
89 BBP sections
90*/
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91#define BBP_R0 0 /* version */
92#define BBP_R1 1 /* TSSI */
93#define BBP_R2 2 /* TX configure */
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94#define BBP_R3 3
95#define BBP_R4 4
96#define BBP_R5 5
97#define BBP_R6 6
cc277069 98#define BBP_R14 14 /* RX configure */
ca97b838 99#define BBP_R16 16
cc277069 100#define BBP_R17 17 /* RX sensibility */
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101#define BBP_R18 18
102#define BBP_R21 21
103#define BBP_R22 22
104#define BBP_R24 24
105#define BBP_R25 25
106#define BBP_R26 26
107#define BBP_R27 27
108#define BBP_R31 31
cc277069 109#define BBP_R49 49 /*TSSI */
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110#define BBP_R50 50
111#define BBP_R51 51
112#define BBP_R52 52
113#define BBP_R55 55
cc277069 114#define BBP_R62 62 /* Rx SQ0 Threshold HIGH */
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115#define BBP_R63 63
116#define BBP_R64 64
117#define BBP_R65 65
118#define BBP_R66 66
119#define BBP_R67 67
120#define BBP_R68 68
121#define BBP_R69 69
cc277069 122#define BBP_R70 70 /* Rx AGC SQ CCK Xcorr threshold */
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123#define BBP_R73 73
124#define BBP_R75 75
125#define BBP_R77 77
126#define BBP_R78 78
127#define BBP_R79 79
128#define BBP_R80 80
129#define BBP_R81 81
130#define BBP_R82 82
131#define BBP_R83 83
132#define BBP_R84 84
133#define BBP_R86 86
134#define BBP_R91 91
135#define BBP_R92 92
cc277069 136#define BBP_R94 94 /* Tx Gain Control */
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137#define BBP_R103 103
138#define BBP_R105 105
139#define BBP_R106 106
140#define BBP_R113 113
141#define BBP_R114 114
142#define BBP_R115 115
143#define BBP_R116 116
144#define BBP_R117 117
145#define BBP_R118 118
146#define BBP_R119 119
147#define BBP_R120 120
148#define BBP_R121 121
149#define BBP_R122 122
150#define BBP_R123 123
151#ifdef RT30xx
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152#define BBP_R138 138 /* add by johnli, RF power sequence setup, ADC dynamic on/off control */
153#endif /* RT30xx // */
ca97b838 154
cc277069 155#define BBPR94_DEFAULT 0x06 /* Add 1 value will gain 1db */
ca97b838 156
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157/* */
158/* BBP & RF are using indirect access. Before write any value into it. */
159/* We have to make sure there is no outstanding command pending via checking busy bit. */
160/* */
161#define MAX_BUSY_COUNT 100 /* Number of retry before failing access BBP & RF indirect register */
ca97b838 162
cc277069 163/*#define PHY_TR_SWITCH_TIME 5 // usec */
ca97b838 164
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165/*#define BBP_R17_LOW_SENSIBILITY 0x50 */
166/*#define BBP_R17_MID_SENSIBILITY 0x41 */
167/*#define BBP_R17_DYNAMIC_UP_BOUND 0x40 */
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168
169#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
170#define RSSI_FOR_LOW_SENSIBILITY -58
171#define RSSI_FOR_MID_LOW_SENSIBILITY -80
172#define RSSI_FOR_MID_SENSIBILITY -90
173
174/*****************************************************************************
175 RF register Read/Write marco definition
176 *****************************************************************************/
177#ifdef RTMP_MAC_PCI
178#define RTMP_RF_IO_WRITE32(_A, _V) \
179{ \
180 if ((_A)->bPCIclkOff == FALSE) \
181 { \
182 PHY_CSR4_STRUC _value; \
51126deb 183 unsigned long _busyCnt = 0; \
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184 \
185 do { \
186 RTMP_IO_READ32((_A), RF_CSR_CFG0, &_value.word); \
187 if (_value.field.Busy == IDLE) \
188 break; \
189 _busyCnt++; \
190 }while (_busyCnt < MAX_BUSY_COUNT); \
191 if(_busyCnt < MAX_BUSY_COUNT) \
192 { \
193 RTMP_IO_WRITE32((_A), RF_CSR_CFG0, (_V)); \
194 } \
195 } \
196}
cc277069 197#endif /* RTMP_MAC_PCI // */
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198#ifdef RTMP_MAC_USB
199#define RTMP_RF_IO_WRITE32(_A, _V) RTUSBWriteRFRegister(_A, _V)
cc277069 200#endif /* RTMP_MAC_USB // */
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201
202#ifdef RT30xx
203#define RTMP_RF_IO_READ8_BY_REG_ID(_A, _I, _pV) RT30xxReadRFRegister(_A, _I, _pV)
204#define RTMP_RF_IO_WRITE8_BY_REG_ID(_A, _I, _V) RT30xxWriteRFRegister(_A, _I, _V)
cc277069 205#endif /* RT30xx // */
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206
207/*****************************************************************************
208 BBP register Read/Write marco definitions.
209 we read/write the bbp value by register's ID.
210 Generate PER to test BA
211 *****************************************************************************/
212#ifdef RTMP_MAC_PCI
213/*
214 basic marco for BBP read operation.
62eb734b 215 _pAd: the data structure pointer of struct rt_rtmp_adapter
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216 _bbpID : the bbp register ID
217 _pV: data pointer used to save the value of queried bbp register.
218 _bViaMCU: if we need access the bbp via the MCU.
219*/
220#define RTMP_BBP_IO_READ8(_pAd, _bbpID, _pV, _bViaMCU) \
221 do{ \
222 BBP_CSR_CFG_STRUC BbpCsr; \
223 int _busyCnt, _secCnt, _regID; \
224 \
225 _regID = ((_bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG); \
226 for (_busyCnt=0; _busyCnt<MAX_BUSY_COUNT; _busyCnt++) \
227 { \
228 RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
229 if (BbpCsr.field.Busy == BUSY) \
230 continue; \
231 BbpCsr.word = 0; \
232 BbpCsr.field.fRead = 1; \
233 BbpCsr.field.BBP_RW_MODE = 1; \
234 BbpCsr.field.Busy = 1; \
235 BbpCsr.field.RegNum = _bbpID; \
236 RTMP_IO_WRITE32(_pAd, _regID, BbpCsr.word); \
237 if ((_bViaMCU) == TRUE) \
238 { \
239 AsicSendCommandToMcu(_pAd, 0x80, 0xff, 0x0, 0x0); \
240 RTMPusecDelay(1000); \
241 } \
242 for (_secCnt=0; _secCnt<MAX_BUSY_COUNT; _secCnt++) \
243 { \
244 RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
245 if (BbpCsr.field.Busy == IDLE) \
246 break; \
247 } \
248 if ((BbpCsr.field.Busy == IDLE) && \
249 (BbpCsr.field.RegNum == _bbpID)) \
250 { \
51126deb 251 *(_pV) = (u8)BbpCsr.field.Value; \
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252 break; \
253 } \
254 } \
255 if (BbpCsr.field.Busy == BUSY) \
256 { \
257 DBGPRINT_ERR(("BBP(viaMCU=%d) read R%d fail\n", (_bViaMCU), _bbpID)); \
258 *(_pV) = (_pAd)->BbpWriteLatch[_bbpID]; \
259 if ((_bViaMCU) == TRUE) \
260 { \
261 RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
262 BbpCsr.field.Busy = 0; \
263 RTMP_IO_WRITE32(_pAd, _regID, BbpCsr.word); \
264 } \
265 } \
266 }while(0)
267
268/*
269 This marco used for the BBP read operation which didn't need via MCU.
270*/
271#define BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
272 RTMP_BBP_IO_READ8((_A), (_I), (_pV), FALSE)
273
274/*
275 This marco used for the BBP read operation which need via MCU.
276 But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
277 will use this function too and didn't access the bbp register via the MCU.
278*/
cc277069 279/* Read BBP register by register's ID. Generate PER to test BA */
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280#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
281{ \
282 BBP_CSR_CFG_STRUC BbpCsr; \
283 int i, k; \
284 BOOLEAN brc; \
285 BbpCsr.field.Busy = IDLE; \
286 if ((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
287 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE) \
288 && ((_A)->bPCIclkOff == FALSE) \
289 && ((_A)->brt30xxBanMcuCmd == FALSE)) \
290 { \
291 for (i=0; i<MAX_BUSY_COUNT; i++) \
292 { \
293 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
294 if (BbpCsr.field.Busy == BUSY) \
295 { \
296 continue; \
297 } \
298 BbpCsr.word = 0; \
299 BbpCsr.field.fRead = 1; \
300 BbpCsr.field.BBP_RW_MODE = 1; \
301 BbpCsr.field.Busy = 1; \
302 BbpCsr.field.RegNum = _I; \
303 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
304 brc = AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
305 if (brc == TRUE) \
306 { \
307 for (k=0; k<MAX_BUSY_COUNT; k++) \
308 { \
309 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
310 if (BbpCsr.field.Busy == IDLE) \
311 break; \
312 } \
313 if ((BbpCsr.field.Busy == IDLE) && \
314 (BbpCsr.field.RegNum == _I)) \
315 { \
51126deb 316 *(_pV) = (u8)BbpCsr.field.Value; \
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317 break; \
318 } \
319 } \
320 else \
321 { \
322 BbpCsr.field.Busy = 0; \
323 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
324 } \
325 } \
326 } \
327 else if (!((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
328 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE)) \
329 && ((_A)->bPCIclkOff == FALSE)) \
330 { \
331 for (i=0; i<MAX_BUSY_COUNT; i++) \
332 { \
333 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
334 if (BbpCsr.field.Busy == BUSY) \
335 { \
336 continue; \
337 } \
338 BbpCsr.word = 0; \
339 BbpCsr.field.fRead = 1; \
340 BbpCsr.field.BBP_RW_MODE = 1; \
341 BbpCsr.field.Busy = 1; \
342 BbpCsr.field.RegNum = _I; \
343 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
344 AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
345 for (k=0; k<MAX_BUSY_COUNT; k++) \
346 { \
347 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
348 if (BbpCsr.field.Busy == IDLE) \
349 break; \
350 } \
351 if ((BbpCsr.field.Busy == IDLE) && \
352 (BbpCsr.field.RegNum == _I)) \
353 { \
51126deb 354 *(_pV) = (u8)BbpCsr.field.Value; \
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355 break; \
356 } \
357 } \
358 } \
359 else \
360 { \
361 DBGPRINT_ERR((" , brt30xxBanMcuCmd = %d, Read BBP %d \n", (_A)->brt30xxBanMcuCmd, (_I))); \
362 *(_pV) = (_A)->BbpWriteLatch[_I]; \
363 } \
364 if ((BbpCsr.field.Busy == BUSY) || ((_A)->bPCIclkOff == TRUE)) \
365 { \
366 DBGPRINT_ERR(("BBP read R%d=0x%x fail\n", _I, BbpCsr.word)); \
367 *(_pV) = (_A)->BbpWriteLatch[_I]; \
368 } \
369}
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370
371/*
372 basic marco for BBP write operation.
62eb734b 373 _pAd: the data structure pointer of struct rt_rtmp_adapter
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374 _bbpID : the bbp register ID
375 _pV: data used to save the value of queried bbp register.
376 _bViaMCU: if we need access the bbp via the MCU.
377*/
378#define RTMP_BBP_IO_WRITE8(_pAd, _bbpID, _pV, _bViaMCU) \
379 do{ \
380 BBP_CSR_CFG_STRUC BbpCsr; \
381 int _busyCnt, _regID; \
382 \
383 _regID = ((_bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG); \
384 for (_busyCnt=0; _busyCnt<MAX_BUSY_COUNT; _busyCnt++) \
385 { \
386 RTMP_IO_READ32((_pAd), BBP_CSR_CFG, &BbpCsr.word); \
387 if (BbpCsr.field.Busy == BUSY) \
388 continue; \
389 BbpCsr.word = 0; \
390 BbpCsr.field.fRead = 0; \
391 BbpCsr.field.BBP_RW_MODE = 1; \
392 BbpCsr.field.Busy = 1; \
393 BbpCsr.field.Value = _pV; \
394 BbpCsr.field.RegNum = _bbpID; \
395 RTMP_IO_WRITE32((_pAd), BBP_CSR_CFG, BbpCsr.word); \
396 if ((_bViaMCU) == TRUE) \
397 { \
398 AsicSendCommandToMcu(_pAd, 0x80, 0xff, 0x0, 0x0); \
399 if ((_pAd)->OpMode == OPMODE_AP) \
400 RTMPusecDelay(1000); \
401 } \
402 (_pAd)->BbpWriteLatch[_bbpID] = _pV; \
403 break; \
404 } \
405 if (_busyCnt == MAX_BUSY_COUNT) \
406 { \
407 DBGPRINT_ERR(("BBP write R%d fail\n", _bbpID)); \
408 if((_bViaMCU) == TRUE) \
409 { \
410 RTMP_IO_READ32(_pAd, H2M_BBP_AGENT, &BbpCsr.word); \
411 BbpCsr.field.Busy = 0; \
412 RTMP_IO_WRITE32(_pAd, H2M_BBP_AGENT, BbpCsr.word); \
413 } \
414 } \
415 }while(0)
416
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417/*
418 This marco used for the BBP write operation which didn't need via MCU.
419*/
420#define BBP_IO_WRITE8_BY_REG_ID(_A, _I, _pV) \
421 RTMP_BBP_IO_WRITE8((_A), (_I), (_pV), FALSE)
422
423/*
424 This marco used for the BBP write operation which need via MCU.
425 But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
426 will use this function too and didn't access the bbp register via the MCU.
427*/
cc277069 428/* Write BBP register by register's ID & value */
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429#define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) \
430{ \
431 BBP_CSR_CFG_STRUC BbpCsr; \
51126deb 432 int BusyCnt = 0; \
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433 BOOLEAN brc; \
434 if (_I < MAX_NUM_OF_BBP_LATCH) \
435 { \
436 if ((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
437 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE) \
438 && ((_A)->bPCIclkOff == FALSE) \
439 && ((_A)->brt30xxBanMcuCmd == FALSE)) \
440 { \
441 if (_A->AccessBBPFailCount > 20) \
442 { \
443 AsicResetBBPAgent(_A); \
444 _A->AccessBBPFailCount = 0; \
445 } \
446 for (BusyCnt=0; BusyCnt<MAX_BUSY_COUNT; BusyCnt++) \
447 { \
448 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
449 if (BbpCsr.field.Busy == BUSY) \
450 continue; \
451 BbpCsr.word = 0; \
452 BbpCsr.field.fRead = 0; \
453 BbpCsr.field.BBP_RW_MODE = 1; \
454 BbpCsr.field.Busy = 1; \
455 BbpCsr.field.Value = _V; \
456 BbpCsr.field.RegNum = _I; \
457 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
458 brc = AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
459 if (brc == TRUE) \
460 { \
461 (_A)->BbpWriteLatch[_I] = _V; \
462 } \
463 else \
464 { \
465 BbpCsr.field.Busy = 0; \
466 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
467 } \
468 break; \
469 } \
470 } \
471 else if (!((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
472 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE)) \
473 && ((_A)->bPCIclkOff == FALSE)) \
474 { \
475 if (_A->AccessBBPFailCount > 20) \
476 { \
477 AsicResetBBPAgent(_A); \
478 _A->AccessBBPFailCount = 0; \
479 } \
480 for (BusyCnt=0; BusyCnt<MAX_BUSY_COUNT; BusyCnt++) \
481 { \
482 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
483 if (BbpCsr.field.Busy == BUSY) \
484 continue; \
485 BbpCsr.word = 0; \
486 BbpCsr.field.fRead = 0; \
487 BbpCsr.field.BBP_RW_MODE = 1; \
488 BbpCsr.field.Busy = 1; \
489 BbpCsr.field.Value = _V; \
490 BbpCsr.field.RegNum = _I; \
491 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
492 AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
493 (_A)->BbpWriteLatch[_I] = _V; \
494 break; \
495 } \
496 } \
497 else \
498 { \
499 DBGPRINT_ERR((" brt30xxBanMcuCmd = %d. Write BBP %d \n", (_A)->brt30xxBanMcuCmd, (_I))); \
500 } \
501 if ((BusyCnt == MAX_BUSY_COUNT) || ((_A)->bPCIclkOff == TRUE)) \
502 { \
503 if (BusyCnt == MAX_BUSY_COUNT) \
504 (_A)->AccessBBPFailCount++; \
505 DBGPRINT_ERR(("BBP write R%d=0x%x fail. BusyCnt= %d.bPCIclkOff = %d. \n", _I, BbpCsr.word, BusyCnt, (_A)->bPCIclkOff )); \
506 } \
507 } \
508 else \
509 { \
510 DBGPRINT_ERR(("****** BBP_Write_Latch Buffer exceeds max boundry ****** \n")); \
511 } \
512}
cc277069 513#endif /* RTMP_MAC_PCI // */
46ff6239 514
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515#ifdef RTMP_MAC_USB
516#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
517#define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTUSBWriteBBPRegister(_A, _I, _V)
518
519#define BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTUSBWriteBBPRegister(_A, _I, _V)
520#define BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
cc277069 521#endif /* RTMP_MAC_USB // */
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522
523#ifdef RT30xx
524#define RTMP_ASIC_MMPS_DISABLE(_pAd) \
525 do{ \
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526 u32 _macData; \
527 u8 _bbpData = 0; \
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528 /* disable MMPS BBP control register */ \
529 RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
530 _bbpData &= ~(0x04); /*bit 2*/ \
531 RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
532 \
533 /* disable MMPS MAC control register */ \
534 RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
535 _macData &= ~(0x09); /*bit 0, 3*/ \
536 RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
537 }while(0)
538
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539#define RTMP_ASIC_MMPS_ENABLE(_pAd) \
540 do{ \
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541 u32 _macData; \
542 u8 _bbpData = 0; \
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543 /* enable MMPS BBP control register */ \
544 RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
545 _bbpData |= (0x04); /*bit 2*/ \
546 RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
547 \
548 /* enable MMPS MAC control register */ \
549 RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
550 _macData |= (0x09); /*bit 0, 3*/ \
551 RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
552 }while(0)
553
cc277069 554#endif /* RT30xx // */
ca97b838 555
cc277069 556#endif /* __RTMP_PHY_H__ // */