git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| eb7b797b BS |
1 | /* |
| 2 | * Copyright (C) 2009 QUALCOMM Incorporated. | |
| 3 | */ | |
| 4 | ||
| 5 | #include "mt9t013.h" | |
| 6 | #include <linux/kernel.h> | |
| 7 | ||
| 8 | struct reg_struct const mt9t013_reg_pat[2] = { | |
| 9 | { /* Preview 2x2 binning 20fps, pclk MHz, MCLK 24MHz */ | |
| 10 | /* vt_pix_clk_div:REG=0x0300 update get_snapshot_fps | |
| 11 | * if this change */ | |
| 12 | 8, | |
| 13 | ||
| 14 | /* vt_sys_clk_div: REG=0x0302 update get_snapshot_fps | |
| 15 | * if this change */ | |
| 16 | 1, | |
| 17 | ||
| 18 | /* pre_pll_clk_div REG=0x0304 update get_snapshot_fps | |
| 19 | * if this change */ | |
| 20 | 2, | |
| 21 | ||
| 22 | /* pll_multiplier REG=0x0306 60 for 30fps preview, 40 | |
| 23 | * for 20fps preview | |
| 24 | * 46 for 30fps preview, try 47/48 to increase further */ | |
| 25 | 46, | |
| 26 | ||
| 27 | /* op_pix_clk_div REG=0x0308 */ | |
| 28 | 8, | |
| 29 | ||
| 30 | /* op_sys_clk_div REG=0x030A */ | |
| 31 | 1, | |
| 32 | ||
| 33 | /* scale_m REG=0x0404 */ | |
| 34 | 16, | |
| 35 | ||
| 36 | /* row_speed REG=0x3016 */ | |
| 37 | 0x0111, | |
| 38 | ||
| 39 | /* x_addr_start REG=0x3004 */ | |
| 40 | 8, | |
| 41 | ||
| 42 | /* x_addr_end REG=0x3008 */ | |
| 43 | 2053, | |
| 44 | ||
| 45 | /* y_addr_start REG=0x3002 */ | |
| 46 | 8, | |
| 47 | ||
| 48 | /* y_addr_end REG=0x3006 */ | |
| 49 | 1541, | |
| 50 | ||
| 51 | /* read_mode REG=0x3040 */ | |
| 52 | 0x046C, | |
| 53 | ||
| 54 | /* x_output_size REG=0x034C */ | |
| 55 | 1024, | |
| 56 | ||
| 57 | /* y_output_size REG=0x034E */ | |
| 58 | 768, | |
| 59 | ||
| 60 | /* line_length_pck REG=0x300C */ | |
| 61 | 2616, | |
| 62 | ||
| 63 | /* frame_length_lines REG=0x300A */ | |
| 64 | 916, | |
| 65 | ||
| 66 | /* coarse_int_time REG=0x3012 */ | |
| 67 | 16, | |
| 68 | ||
| 69 | /* fine_int_time REG=0x3014 */ | |
| 70 | 1461 | |
| 71 | }, | |
| 72 | { /*Snapshot */ | |
| 73 | /* vt_pix_clk_div REG=0x0300 update get_snapshot_fps | |
| 74 | * if this change */ | |
| 75 | 8, | |
| 76 | ||
| 77 | /* vt_sys_clk_div REG=0x0302 update get_snapshot_fps | |
| 78 | * if this change */ | |
| 79 | 1, | |
| 80 | ||
| 81 | /* pre_pll_clk_div REG=0x0304 update get_snapshot_fps | |
| 82 | * if this change */ | |
| 83 | 2, | |
| 84 | ||
| 85 | /* pll_multiplier REG=0x0306 50 for 15fps snapshot, | |
| 86 | * 40 for 10fps snapshot | |
| 87 | * 46 for 30fps snapshot, try 47/48 to increase further */ | |
| 88 | 46, | |
| 89 | ||
| 90 | /* op_pix_clk_div REG=0x0308 */ | |
| 91 | 8, | |
| 92 | ||
| 93 | /* op_sys_clk_div REG=0x030A */ | |
| 94 | 1, | |
| 95 | ||
| 96 | /* scale_m REG=0x0404 */ | |
| 97 | 16, | |
| 98 | ||
| 99 | /* row_speed REG=0x3016 */ | |
| 100 | 0x0111, | |
| 101 | ||
| 102 | /* x_addr_start REG=0x3004 */ | |
| 103 | 8, | |
| 104 | ||
| 105 | /* x_addr_end REG=0x3008 */ | |
| 106 | 2071, | |
| 107 | ||
| 108 | /* y_addr_start REG=0x3002 */ | |
| 109 | 8, | |
| 110 | ||
| 111 | /* y_addr_end REG=0x3006 */ | |
| 112 | 1551, | |
| 113 | ||
| 114 | /* read_mode REG=0x3040 */ | |
| 115 | 0x0024, | |
| 116 | ||
| 117 | /* x_output_size REG=0x034C */ | |
| 118 | 2064, | |
| 119 | ||
| 120 | /* y_output_size REG=0x034E */ | |
| 121 | 1544, | |
| 122 | ||
| 123 | /* line_length_pck REG=0x300C */ | |
| 124 | 2952, | |
| 125 | ||
| 126 | /* frame_length_lines REG=0x300A */ | |
| 127 | 1629, | |
| 128 | ||
| 129 | /* coarse_int_time REG=0x3012 */ | |
| 130 | 16, | |
| 131 | ||
| 132 | /* fine_int_time REG=0x3014 */ | |
| 133 | 733 | |
| 134 | } | |
| 135 | }; | |
| 136 | ||
| 137 | struct mt9t013_i2c_reg_conf mt9t013_test_tbl[] = { | |
| 138 | { 0x3044, 0x0544 & 0xFBFF }, | |
| 139 | { 0x30CA, 0x0004 | 0x0001 }, | |
| 140 | { 0x30D4, 0x9020 & 0x7FFF }, | |
| 141 | { 0x31E0, 0x0003 & 0xFFFE }, | |
| 142 | { 0x3180, 0x91FF & 0x7FFF }, | |
| 143 | { 0x301A, (0x10CC | 0x8000) & 0xFFF7 }, | |
| 144 | { 0x301E, 0x0000 }, | |
| 145 | { 0x3780, 0x0000 }, | |
| 146 | }; | |
| 147 | ||
| 148 | /* [Lens shading 85 Percent TL84] */ | |
| 149 | struct mt9t013_i2c_reg_conf mt9t013_lc_tbl[] = { | |
| 150 | { 0x360A, 0x0290 }, /* P_RD_P0Q0 */ | |
| 151 | { 0x360C, 0xC92D }, /* P_RD_P0Q1 */ | |
| 152 | { 0x360E, 0x0771 }, /* P_RD_P0Q2 */ | |
| 153 | { 0x3610, 0xE38C }, /* P_RD_P0Q3 */ | |
| 154 | { 0x3612, 0xD74F }, /* P_RD_P0Q4 */ | |
| 155 | { 0x364A, 0x168C }, /* P_RD_P1Q0 */ | |
| 156 | { 0x364C, 0xCACB }, /* P_RD_P1Q1 */ | |
| 157 | { 0x364E, 0x8C4C }, /* P_RD_P1Q2 */ | |
| 158 | { 0x3650, 0x0BEA }, /* P_RD_P1Q3 */ | |
| 159 | { 0x3652, 0xDC0F }, /* P_RD_P1Q4 */ | |
| 160 | { 0x368A, 0x70B0 }, /* P_RD_P2Q0 */ | |
| 161 | { 0x368C, 0x200B }, /* P_RD_P2Q1 */ | |
| 162 | { 0x368E, 0x30B2 }, /* P_RD_P2Q2 */ | |
| 163 | { 0x3690, 0xD04F }, /* P_RD_P2Q3 */ | |
| 164 | { 0x3692, 0xACF5 }, /* P_RD_P2Q4 */ | |
| 165 | { 0x36CA, 0xF7C9 }, /* P_RD_P3Q0 */ | |
| 166 | { 0x36CC, 0x2AED }, /* P_RD_P3Q1 */ | |
| 167 | { 0x36CE, 0xA652 }, /* P_RD_P3Q2 */ | |
| 168 | { 0x36D0, 0x8192 }, /* P_RD_P3Q3 */ | |
| 169 | { 0x36D2, 0x3A15 }, /* P_RD_P3Q4 */ | |
| 170 | { 0x370A, 0xDA30 }, /* P_RD_P4Q0 */ | |
| 171 | { 0x370C, 0x2E2F }, /* P_RD_P4Q1 */ | |
| 172 | { 0x370E, 0xBB56 }, /* P_RD_P4Q2 */ | |
| 173 | { 0x3710, 0x8195 }, /* P_RD_P4Q3 */ | |
| 174 | { 0x3712, 0x02F9 }, /* P_RD_P4Q4 */ | |
| 175 | { 0x3600, 0x0230 }, /* P_GR_P0Q0 */ | |
| 176 | { 0x3602, 0x58AD }, /* P_GR_P0Q1 */ | |
| 177 | { 0x3604, 0x18D1 }, /* P_GR_P0Q2 */ | |
| 178 | { 0x3606, 0x260D }, /* P_GR_P0Q3 */ | |
| 179 | { 0x3608, 0xF530 }, /* P_GR_P0Q4 */ | |
| 180 | { 0x3640, 0x17EB }, /* P_GR_P1Q0 */ | |
| 181 | { 0x3642, 0x3CAB }, /* P_GR_P1Q1 */ | |
| 182 | { 0x3644, 0x87CE }, /* P_GR_P1Q2 */ | |
| 183 | { 0x3646, 0xC02E }, /* P_GR_P1Q3 */ | |
| 184 | { 0x3648, 0xF48F }, /* P_GR_P1Q4 */ | |
| 185 | { 0x3680, 0x5350 }, /* P_GR_P2Q0 */ | |
| 186 | { 0x3682, 0x7EAF }, /* P_GR_P2Q1 */ | |
| 187 | { 0x3684, 0x4312 }, /* P_GR_P2Q2 */ | |
| 188 | { 0x3686, 0xC652 }, /* P_GR_P2Q3 */ | |
| 189 | { 0x3688, 0xBC15 }, /* P_GR_P2Q4 */ | |
| 190 | { 0x36C0, 0xB8AD }, /* P_GR_P3Q0 */ | |
| 191 | { 0x36C2, 0xBDCD }, /* P_GR_P3Q1 */ | |
| 192 | { 0x36C4, 0xE4B2 }, /* P_GR_P3Q2 */ | |
| 193 | { 0x36C6, 0xB50F }, /* P_GR_P3Q3 */ | |
| 194 | { 0x36C8, 0x5B95 }, /* P_GR_P3Q4 */ | |
| 195 | { 0x3700, 0xFC90 }, /* P_GR_P4Q0 */ | |
| 196 | { 0x3702, 0x8C51 }, /* P_GR_P4Q1 */ | |
| 197 | { 0x3704, 0xCED6 }, /* P_GR_P4Q2 */ | |
| 198 | { 0x3706, 0xB594 }, /* P_GR_P4Q3 */ | |
| 199 | { 0x3708, 0x0A39 }, /* P_GR_P4Q4 */ | |
| 200 | { 0x3614, 0x0230 }, /* P_BL_P0Q0 */ | |
| 201 | { 0x3616, 0x160D }, /* P_BL_P0Q1 */ | |
| 202 | { 0x3618, 0x08D1 }, /* P_BL_P0Q2 */ | |
| 203 | { 0x361A, 0x98AB }, /* P_BL_P0Q3 */ | |
| 204 | { 0x361C, 0xEA50 }, /* P_BL_P0Q4 */ | |
| 205 | { 0x3654, 0xB4EA }, /* P_BL_P1Q0 */ | |
| 206 | { 0x3656, 0xEA6C }, /* P_BL_P1Q1 */ | |
| 207 | { 0x3658, 0xFE08 }, /* P_BL_P1Q2 */ | |
| 208 | { 0x365A, 0x2C6E }, /* P_BL_P1Q3 */ | |
| 209 | { 0x365C, 0xEB0E }, /* P_BL_P1Q4 */ | |
| 210 | { 0x3694, 0x6DF0 }, /* P_BL_P2Q0 */ | |
| 211 | { 0x3696, 0x3ACF }, /* P_BL_P2Q1 */ | |
| 212 | { 0x3698, 0x3E0F }, /* P_BL_P2Q2 */ | |
| 213 | { 0x369A, 0xB2B1 }, /* P_BL_P2Q3 */ | |
| 214 | { 0x369C, 0xC374 }, /* P_BL_P2Q4 */ | |
| 215 | { 0x36D4, 0xF2AA }, /* P_BL_P3Q0 */ | |
| 216 | { 0x36D6, 0x8CCC }, /* P_BL_P3Q1 */ | |
| 217 | { 0x36D8, 0xDEF2 }, /* P_BL_P3Q2 */ | |
| 218 | { 0x36DA, 0xFA11 }, /* P_BL_P3Q3 */ | |
| 219 | { 0x36DC, 0x42F5 }, /* P_BL_P3Q4 */ | |
| 220 | { 0x3714, 0xF4F1 }, /* P_BL_P4Q0 */ | |
| 221 | { 0x3716, 0xF6F0 }, /* P_BL_P4Q1 */ | |
| 222 | { 0x3718, 0x8FD6 }, /* P_BL_P4Q2 */ | |
| 223 | { 0x371A, 0xEA14 }, /* P_BL_P4Q3 */ | |
| 224 | { 0x371C, 0x6338 }, /* P_BL_P4Q4 */ | |
| 225 | { 0x361E, 0x0350 }, /* P_GB_P0Q0 */ | |
| 226 | { 0x3620, 0x91AE }, /* P_GB_P0Q1 */ | |
| 227 | { 0x3622, 0x0571 }, /* P_GB_P0Q2 */ | |
| 228 | { 0x3624, 0x100D }, /* P_GB_P0Q3 */ | |
| 229 | { 0x3626, 0xCA70 }, /* P_GB_P0Q4 */ | |
| 230 | { 0x365E, 0xE6CB }, /* P_GB_P1Q0 */ | |
| 231 | { 0x3660, 0x50ED }, /* P_GB_P1Q1 */ | |
| 232 | { 0x3662, 0x3DAE }, /* P_GB_P1Q2 */ | |
| 233 | { 0x3664, 0xAA4F }, /* P_GB_P1Q3 */ | |
| 234 | { 0x3666, 0xDC50 }, /* P_GB_P1Q4 */ | |
| 235 | { 0x369E, 0x5470 }, /* P_GB_P2Q0 */ | |
| 236 | { 0x36A0, 0x1F6E }, /* P_GB_P2Q1 */ | |
| 237 | { 0x36A2, 0x6671 }, /* P_GB_P2Q2 */ | |
| 238 | { 0x36A4, 0xC010 }, /* P_GB_P2Q3 */ | |
| 239 | { 0x36A6, 0x8DF5 }, /* P_GB_P2Q4 */ | |
| 240 | { 0x36DE, 0x0B0C }, /* P_GB_P3Q0 */ | |
| 241 | { 0x36E0, 0x84CE }, /* P_GB_P3Q1 */ | |
| 242 | { 0x36E2, 0x8493 }, /* P_GB_P3Q2 */ | |
| 243 | { 0x36E4, 0xA610 }, /* P_GB_P3Q3 */ | |
| 244 | { 0x36E6, 0x50B5 }, /* P_GB_P3Q4 */ | |
| 245 | { 0x371E, 0x9651 }, /* P_GB_P4Q0 */ | |
| 246 | { 0x3720, 0x1EAB }, /* P_GB_P4Q1 */ | |
| 247 | { 0x3722, 0xAF76 }, /* P_GB_P4Q2 */ | |
| 248 | { 0x3724, 0xE4F4 }, /* P_GB_P4Q3 */ | |
| 249 | { 0x3726, 0x79F8 }, /* P_GB_P4Q4 */ | |
| 250 | { 0x3782, 0x0410 }, /* POLY_ORIGIN_C */ | |
| 251 | { 0x3784, 0x0320 }, /* POLY_ORIGIN_R */ | |
| 252 | { 0x3780, 0x8000 } /* POLY_SC_ENABLE */ | |
| 253 | }; | |
| 254 | ||
| 255 | struct mt9t013_reg mt9t013_regs = { | |
| 256 | .reg_pat = &mt9t013_reg_pat[0], | |
| 257 | .reg_pat_size = ARRAY_SIZE(mt9t013_reg_pat), | |
| 258 | .ttbl = &mt9t013_test_tbl[0], | |
| 259 | .ttbl_size = ARRAY_SIZE(mt9t013_test_tbl), | |
| 260 | .lctbl = &mt9t013_lc_tbl[0], | |
| 261 | .lctbl_size = ARRAY_SIZE(mt9t013_lc_tbl), | |
| 262 | .rftbl = &mt9t013_lc_tbl[0], /* &mt9t013_rolloff_tbl[0], */ | |
| 263 | .rftbl_size = ARRAY_SIZE(mt9t013_lc_tbl) | |
| 264 | }; | |
| 265 | ||
| 266 |