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1 | /* |
2 | * Copyright (C) 2008-2009 QUALCOMM Incorporated. | |
3 | */ | |
4 | ||
5 | #ifndef __MSM_VFE8X_REG_H__ | |
6 | #define __MSM_VFE8X_REG_H__ | |
7 | ||
8 | #include <mach/msm_iomap.h> | |
9 | #include <mach/camera.h> | |
10 | #include "msm_vfe8x.h" | |
11 | ||
12 | /* at start of camif, bit 1:0 = 0x01:enable | |
13 | * image data capture at frame boundary. */ | |
14 | #define CAMIF_COMMAND_START 0x00000005 | |
15 | ||
16 | /* bit 2= 0x1:clear the CAMIF_STATUS register | |
17 | * value. */ | |
18 | #define CAMIF_COMMAND_CLEAR 0x00000004 | |
19 | ||
20 | /* at stop of vfe pipeline, for now it is assumed | |
21 | * that camif will stop at any time. Bit 1:0 = 0x10: | |
22 | * disable image data capture immediately. */ | |
23 | #define CAMIF_COMMAND_STOP_IMMEDIATELY 0x00000002 | |
24 | ||
25 | /* at stop of vfe pipeline, for now it is assumed | |
26 | * that camif will stop at any time. Bit 1:0 = 0x00: | |
27 | * disable image data capture at frame boundary */ | |
28 | #define CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY 0x00000000 | |
29 | ||
30 | /* to halt axi bridge */ | |
31 | #define AXI_HALT 0x00000001 | |
32 | ||
33 | /* clear the halt bit. */ | |
34 | #define AXI_HALT_CLEAR 0x00000000 | |
35 | ||
36 | /* reset the pipeline when stop command is issued. | |
37 | * (without reset the register.) bit 26-31 = 0, | |
38 | * domain reset, bit 0-9 = 1 for module reset, except | |
39 | * register module. */ | |
40 | #define VFE_RESET_UPON_STOP_CMD 0x000003ef | |
41 | ||
42 | /* reset the pipeline when reset command. | |
43 | * bit 26-31 = 0, domain reset, bit 0-9 = 1 for module reset. */ | |
44 | #define VFE_RESET_UPON_RESET_CMD 0x000003ff | |
45 | ||
46 | /* bit 5 is for axi status idle or busy. | |
47 | * 1 = halted, 0 = busy */ | |
48 | #define AXI_STATUS_BUSY_MASK 0x00000020 | |
49 | ||
50 | /* bit 0 & bit 1 = 1, both y and cbcr irqs need to be present | |
51 | * for frame done interrupt */ | |
52 | #define VFE_COMP_IRQ_BOTH_Y_CBCR 3 | |
53 | ||
54 | /* bit 1 = 1, only cbcr irq triggers frame done interrupt */ | |
55 | #define VFE_COMP_IRQ_CBCR_ONLY 2 | |
56 | ||
57 | /* bit 0 = 1, only y irq triggers frame done interrupt */ | |
58 | #define VFE_COMP_IRQ_Y_ONLY 1 | |
59 | ||
60 | /* bit 0 = 1, PM go; bit1 = 1, PM stop */ | |
61 | #define VFE_PERFORMANCE_MONITOR_GO 0x00000001 | |
62 | #define VFE_PERFORMANCE_MONITOR_STOP 0x00000002 | |
63 | ||
64 | /* bit 0 = 1, test gen go; bit1 = 1, test gen stop */ | |
65 | #define VFE_TEST_GEN_GO 0x00000001 | |
66 | #define VFE_TEST_GEN_STOP 0x00000002 | |
67 | ||
68 | /* the chroma is assumed to be interpolated between | |
69 | * the luma samples. JPEG 4:2:2 */ | |
70 | #define VFE_CHROMA_UPSAMPLE_INTERPOLATED 0 | |
71 | ||
72 | /* constants for irq registers */ | |
73 | #define VFE_DISABLE_ALL_IRQS 0 | |
74 | /* bit =1 is to clear the corresponding bit in VFE_IRQ_STATUS. */ | |
75 | #define VFE_CLEAR_ALL_IRQS 0xffffffff | |
76 | /* imask for while waiting for stop ack, driver has already | |
77 | * requested stop, waiting for reset irq, | |
78 | * bit 29,28,27,26 for async timer, bit 9 for reset */ | |
79 | #define VFE_IMASK_WHILE_STOPPING 0x3c000200 | |
80 | ||
81 | /* when normal case, don't want to block error status. | |
82 | * bit 0,6,20,21,22,30,31 */ | |
83 | #define VFE_IMASK_ERROR_ONLY 0xC0700041 | |
84 | #define VFE_REG_UPDATE_TRIGGER 1 | |
85 | #define VFE_PM_BUF_MAX_CNT_MASK 0xFF | |
86 | #define VFE_DMI_CFG_DEFAULT 0x00000100 | |
87 | #define LENS_ROLL_OFF_DELTA_TABLE_OFFSET 32 | |
88 | #define VFE_AF_PINGPONG_STATUS_BIT 0x100 | |
89 | #define VFE_AWB_PINGPONG_STATUS_BIT 0x200 | |
90 | ||
91 | /* VFE I/O registers */ | |
92 | enum { | |
93 | VFE_HW_VERSION = 0x00000000, | |
94 | VFE_GLOBAL_RESET_CMD = 0x00000004, | |
95 | VFE_MODULE_RESET = 0x00000008, | |
96 | VFE_CGC_OVERRIDE = 0x0000000C, | |
97 | VFE_MODULE_CFG = 0x00000010, | |
98 | VFE_CFG = 0x00000014, | |
99 | VFE_IRQ_MASK = 0x00000018, | |
100 | VFE_IRQ_CLEAR = 0x0000001C, | |
101 | VFE_IRQ_STATUS = 0x00000020, | |
102 | VFE_IRQ_COMPOSITE_MASK = 0x00000024, | |
103 | VFE_BUS_CMD = 0x00000028, | |
104 | VFE_BUS_CFG = 0x0000002C, | |
105 | VFE_BUS_ENC_Y_WR_PING_ADDR = 0x00000030, | |
106 | VFE_BUS_ENC_Y_WR_PONG_ADDR = 0x00000034, | |
107 | VFE_BUS_ENC_Y_WR_IMAGE_SIZE = 0x00000038, | |
108 | VFE_BUS_ENC_Y_WR_BUFFER_CFG = 0x0000003C, | |
109 | VFE_BUS_ENC_CBCR_WR_PING_ADDR = 0x00000040, | |
110 | VFE_BUS_ENC_CBCR_WR_PONG_ADDR = 0x00000044, | |
111 | VFE_BUS_ENC_CBCR_WR_IMAGE_SIZE = 0x00000048, | |
112 | VFE_BUS_ENC_CBCR_WR_BUFFER_CFG = 0x0000004C, | |
113 | VFE_BUS_VIEW_Y_WR_PING_ADDR = 0x00000050, | |
114 | VFE_BUS_VIEW_Y_WR_PONG_ADDR = 0x00000054, | |
115 | VFE_BUS_VIEW_Y_WR_IMAGE_SIZE = 0x00000058, | |
116 | VFE_BUS_VIEW_Y_WR_BUFFER_CFG = 0x0000005C, | |
117 | VFE_BUS_VIEW_CBCR_WR_PING_ADDR = 0x00000060, | |
118 | VFE_BUS_VIEW_CBCR_WR_PONG_ADDR = 0x00000064, | |
119 | VFE_BUS_VIEW_CBCR_WR_IMAGE_SIZE = 0x00000068, | |
120 | VFE_BUS_VIEW_CBCR_WR_BUFFER_CFG = 0x0000006C, | |
121 | VFE_BUS_STATS_AF_WR_PING_ADDR = 0x00000070, | |
122 | VFE_BUS_STATS_AF_WR_PONG_ADDR = 0x00000074, | |
123 | VFE_BUS_STATS_AWB_WR_PING_ADDR = 0x00000078, | |
124 | VFE_BUS_STATS_AWB_WR_PONG_ADDR = 0x0000007C, | |
125 | VFE_BUS_STATS_HIST_WR_PING_ADDR = 0x00000080, | |
126 | VFE_BUS_STATS_HIST_WR_PONG_ADDR = 0x00000084, | |
127 | VFE_BUS_STATS_WR_PRIORITY = 0x00000088, | |
128 | VFE_BUS_STRIPE_RD_ADDR_0 = 0x0000008C, | |
129 | VFE_BUS_STRIPE_RD_ADDR_1 = 0x00000090, | |
130 | VFE_BUS_STRIPE_RD_ADDR_2 = 0x00000094, | |
131 | VFE_BUS_STRIPE_RD_ADDR_3 = 0x00000098, | |
132 | VFE_BUS_STRIPE_RD_VSIZE = 0x0000009C, | |
133 | VFE_BUS_STRIPE_RD_HSIZE = 0x000000A0, | |
134 | VFE_BUS_STRIPE_RD_BUFFER_CFG = 0x000000A4, | |
135 | VFE_BUS_STRIPE_RD_UNPACK_CFG = 0x000000A8, | |
136 | VFE_BUS_STRIPE_RD_UNPACK = 0x000000AC, | |
137 | VFE_BUS_STRIPE_RD_PAD_SIZE = 0x000000B0, | |
138 | VFE_BUS_STRIPE_RD_PAD_L_UNPACK = 0x000000B4, | |
139 | VFE_BUS_STRIPE_RD_PAD_R_UNPACK = 0x000000B8, | |
140 | VFE_BUS_STRIPE_RD_PAD_TB_UNPACK = 0x000000BC, | |
141 | VFE_BUS_PINGPONG_IRQ_EN = 0x000000C0, | |
142 | VFE_BUS_PINGPONG_STATUS = 0x000000C4, | |
143 | VFE_BUS_PM_CMD = 0x000000C8, | |
144 | VFE_BUS_PM_CFG = 0x000000CC, | |
145 | VFE_BUS_ENC_Y_WR_PM_STATS_0 = 0x000000D0, | |
146 | VFE_BUS_ENC_Y_WR_PM_STATS_1 = 0x000000D4, | |
147 | VFE_BUS_ENC_CBCR_WR_PM_STATS_0 = 0x000000D8, | |
148 | VFE_BUS_ENC_CBCR_WR_PM_STATS_1 = 0x000000DC, | |
149 | VFE_BUS_VIEW_Y_WR_PM_STATS_0 = 0x000000E0, | |
150 | VFE_BUS_VIEW_Y_WR_PM_STATS_1 = 0x000000E4, | |
151 | VFE_BUS_VIEW_CBCR_WR_PM_STATS_0 = 0x000000E8, | |
152 | VFE_BUS_VIEW_CBCR_WR_PM_STATS_1 = 0x000000EC, | |
153 | VFE_BUS_MISR_CFG = 0x000000F4, | |
154 | VFE_BUS_MISR_MAST_CFG_0 = 0x000000F8, | |
155 | VFE_BUS_MISR_MAST_CFG_1 = 0x000000FC, | |
156 | VFE_BUS_MISR_RD_VAL = 0x00000100, | |
157 | VFE_AXI_CMD = 0x00000104, | |
158 | VFE_AXI_CFG = 0x00000108, | |
159 | VFE_AXI_STATUS = 0x0000010C, | |
160 | CAMIF_COMMAND = 0x00000110, | |
161 | CAMIF_CONFIG = 0x00000114, | |
162 | CAMIF_EFS_CONFIG = 0x00000118, | |
163 | CAMIF_FRAME_CONFIG = 0x0000011C, | |
164 | CAMIF_WINDOW_WIDTH_CONFIG = 0x00000120, | |
165 | CAMIF_WINDOW_HEIGHT_CONFIG = 0x00000124, | |
166 | CAMIF_SUBSAMPLE1_CONFIG = 0x00000128, | |
167 | CAMIF_SUBSAMPLE2_CONFIG = 0x0000012C, | |
168 | CAMIF_EPOCH_IRQ = 0x00000130, | |
169 | CAMIF_STATUS = 0x00000134, | |
170 | CAMIF_MISR = 0x00000138, | |
171 | VFE_SYNC_TIMER_CMD = 0x0000013C, | |
172 | VFE_SYNC_TIMER0_LINE_START = 0x00000140, | |
173 | VFE_SYNC_TIMER0_PIXEL_START = 0x00000144, | |
174 | VFE_SYNC_TIMER0_PIXEL_DURATION = 0x00000148, | |
175 | VFE_SYNC_TIMER1_LINE_START = 0x0000014C, | |
176 | VFE_SYNC_TIMER1_PIXEL_START = 0x00000150, | |
177 | VFE_SYNC_TIMER1_PIXEL_DURATION = 0x00000154, | |
178 | VFE_SYNC_TIMER2_LINE_START = 0x00000158, | |
179 | VFE_SYNC_TIMER2_PIXEL_START = 0x0000015C, | |
180 | VFE_SYNC_TIMER2_PIXEL_DURATION = 0x00000160, | |
181 | VFE_SYNC_TIMER_POLARITY = 0x00000164, | |
182 | VFE_ASYNC_TIMER_CMD = 0x00000168, | |
183 | VFE_ASYNC_TIMER0_CFG_0 = 0x0000016C, | |
184 | VFE_ASYNC_TIMER0_CFG_1 = 0x00000170, | |
185 | VFE_ASYNC_TIMER1_CFG_0 = 0x00000174, | |
186 | VFE_ASYNC_TIMER1_CFG_1 = 0x00000178, | |
187 | VFE_ASYNC_TIMER2_CFG_0 = 0x0000017C, | |
188 | VFE_ASYNC_TIMER2_CFG_1 = 0x00000180, | |
189 | VFE_ASYNC_TIMER3_CFG_0 = 0x00000184, | |
190 | VFE_ASYNC_TIMER3_CFG_1 = 0x00000188, | |
191 | VFE_TIMER_SEL = 0x0000018C, | |
192 | VFE_REG_UPDATE_CMD = 0x00000190, | |
193 | VFE_BLACK_EVEN_EVEN_VALUE = 0x00000194, | |
194 | VFE_BLACK_EVEN_ODD_VALUE = 0x00000198, | |
195 | VFE_BLACK_ODD_EVEN_VALUE = 0x0000019C, | |
196 | VFE_BLACK_ODD_ODD_VALUE = 0x000001A0, | |
197 | VFE_ROLLOFF_CFG_0 = 0x000001A4, | |
198 | VFE_ROLLOFF_CFG_1 = 0x000001A8, | |
199 | VFE_ROLLOFF_CFG_2 = 0x000001AC, | |
200 | VFE_DEMUX_CFG = 0x000001B0, | |
201 | VFE_DEMUX_GAIN_0 = 0x000001B4, | |
202 | VFE_DEMUX_GAIN_1 = 0x000001B8, | |
203 | VFE_DEMUX_EVEN_CFG = 0x000001BC, | |
204 | VFE_DEMUX_ODD_CFG = 0x000001C0, | |
205 | VFE_DEMOSAIC_CFG = 0x000001C4, | |
206 | VFE_DEMOSAIC_ABF_CFG_0 = 0x000001C8, | |
207 | VFE_DEMOSAIC_ABF_CFG_1 = 0x000001CC, | |
208 | VFE_DEMOSAIC_BPC_CFG_0 = 0x000001D0, | |
209 | VFE_DEMOSAIC_BPC_CFG_1 = 0x000001D4, | |
210 | VFE_DEMOSAIC_STATUS = 0x000001D8, | |
211 | VFE_CHROMA_UPSAMPLE_CFG = 0x000001DC, | |
212 | VFE_CROP_WIDTH_CFG = 0x000001E0, | |
213 | VFE_CROP_HEIGHT_CFG = 0x000001E4, | |
214 | VFE_COLOR_CORRECT_COEFF_0 = 0x000001E8, | |
215 | VFE_COLOR_CORRECT_COEFF_1 = 0x000001EC, | |
216 | VFE_COLOR_CORRECT_COEFF_2 = 0x000001F0, | |
217 | VFE_COLOR_CORRECT_COEFF_3 = 0x000001F4, | |
218 | VFE_COLOR_CORRECT_COEFF_4 = 0x000001F8, | |
219 | VFE_COLOR_CORRECT_COEFF_5 = 0x000001FC, | |
220 | VFE_COLOR_CORRECT_COEFF_6 = 0x00000200, | |
221 | VFE_COLOR_CORRECT_COEFF_7 = 0x00000204, | |
222 | VFE_COLOR_CORRECT_COEFF_8 = 0x00000208, | |
223 | VFE_COLOR_CORRECT_OFFSET_0 = 0x0000020C, | |
224 | VFE_COLOR_CORRECT_OFFSET_1 = 0x00000210, | |
225 | VFE_COLOR_CORRECT_OFFSET_2 = 0x00000214, | |
226 | VFE_COLOR_CORRECT_COEFF_Q = 0x00000218, | |
227 | VFE_LA_CFG = 0x0000021C, | |
228 | VFE_LUT_BANK_SEL = 0x00000220, | |
229 | VFE_CHROMA_ENHAN_A = 0x00000224, | |
230 | VFE_CHROMA_ENHAN_B = 0x00000228, | |
231 | VFE_CHROMA_ENHAN_C = 0x0000022C, | |
232 | VFE_CHROMA_ENHAN_D = 0x00000230, | |
233 | VFE_CHROMA_ENHAN_K = 0x00000234, | |
234 | VFE_COLOR_CONVERT_COEFF_0 = 0x00000238, | |
235 | VFE_COLOR_CONVERT_COEFF_1 = 0x0000023C, | |
236 | VFE_COLOR_CONVERT_COEFF_2 = 0x00000240, | |
237 | VFE_COLOR_CONVERT_OFFSET = 0x00000244, | |
238 | VFE_ASF_CFG = 0x00000248, | |
239 | VFE_ASF_SHARP_CFG_0 = 0x0000024C, | |
240 | VFE_ASF_SHARP_CFG_1 = 0x00000250, | |
241 | VFE_ASF_SHARP_COEFF_0 = 0x00000254, | |
242 | VFE_ASF_SHARP_COEFF_1 = 0x00000258, | |
243 | VFE_ASF_SHARP_COEFF_2 = 0x0000025C, | |
244 | VFE_ASF_SHARP_COEFF_3 = 0x00000260, | |
245 | VFE_ASF_MAX_EDGE = 0x00000264, | |
246 | VFE_ASF_CROP_WIDTH_CFG = 0x00000268, | |
247 | VFE_ASF_CROP_HEIGHT_CFG = 0x0000026C, | |
248 | VFE_SCALE_CFG = 0x00000270, | |
249 | VFE_SCALE_H_IMAGE_SIZE_CFG = 0x00000274, | |
250 | VFE_SCALE_H_PHASE_CFG = 0x00000278, | |
251 | VFE_SCALE_H_STRIPE_CFG = 0x0000027C, | |
252 | VFE_SCALE_V_IMAGE_SIZE_CFG = 0x00000280, | |
253 | VFE_SCALE_V_PHASE_CFG = 0x00000284, | |
254 | VFE_SCALE_V_STRIPE_CFG = 0x00000288, | |
255 | VFE_SCALE_Y_CFG = 0x0000028C, | |
256 | VFE_SCALE_Y_H_IMAGE_SIZE_CFG = 0x00000290, | |
257 | VFE_SCALE_Y_H_PHASE_CFG = 0x00000294, | |
258 | VFE_SCALE_Y_V_IMAGE_SIZE_CFG = 0x00000298, | |
259 | VFE_SCALE_Y_V_PHASE_CFG = 0x0000029C, | |
260 | VFE_SCALE_CBCR_CFG = 0x000002A0, | |
261 | VFE_SCALE_CBCR_H_IMAGE_SIZE_CFG = 0x000002A4, | |
262 | VFE_SCALE_CBCR_H_PHASE_CFG = 0x000002A8, | |
263 | VFE_SCALE_CBCR_V_IMAGE_SIZE_CFG = 0x000002AC, | |
264 | VFE_SCALE_CBCR_V_PHASE_CFG = 0x000002B0, | |
265 | VFE_WB_CFG = 0x000002B4, | |
266 | VFE_CHROMA_SUPPRESS_CFG_0 = 0x000002B8, | |
267 | VFE_CHROMA_SUPPRESS_CFG_1 = 0x000002BC, | |
268 | VFE_CHROMA_SUBSAMPLE_CFG = 0x000002C0, | |
269 | VFE_CHROMA_SUB_CROP_WIDTH_CFG = 0x000002C4, | |
270 | VFE_CHROMA_SUB_CROP_HEIGHT_CFG = 0x000002C8, | |
271 | VFE_FRAMEDROP_ENC_Y_CFG = 0x000002CC, | |
272 | VFE_FRAMEDROP_ENC_CBCR_CFG = 0x000002D0, | |
273 | VFE_FRAMEDROP_ENC_Y_PATTERN = 0x000002D4, | |
274 | VFE_FRAMEDROP_ENC_CBCR_PATTERN = 0x000002D8, | |
275 | VFE_FRAMEDROP_VIEW_Y_CFG = 0x000002DC, | |
276 | VFE_FRAMEDROP_VIEW_CBCR_CFG = 0x000002E0, | |
277 | VFE_FRAMEDROP_VIEW_Y_PATTERN = 0x000002E4, | |
278 | VFE_FRAMEDROP_VIEW_CBCR_PATTERN = 0x000002E8, | |
279 | VFE_CLAMP_MAX_CFG = 0x000002EC, | |
280 | VFE_CLAMP_MIN_CFG = 0x000002F0, | |
281 | VFE_STATS_CMD = 0x000002F4, | |
282 | VFE_STATS_AF_CFG = 0x000002F8, | |
283 | VFE_STATS_AF_DIM = 0x000002FC, | |
284 | VFE_STATS_AF_GRID_0 = 0x00000300, | |
285 | VFE_STATS_AF_GRID_1 = 0x00000304, | |
286 | VFE_STATS_AF_GRID_2 = 0x00000308, | |
287 | VFE_STATS_AF_GRID_3 = 0x0000030C, | |
288 | VFE_STATS_AF_HEADER = 0x00000310, | |
289 | VFE_STATS_AF_COEF0 = 0x00000314, | |
290 | VFE_STATS_AF_COEF1 = 0x00000318, | |
291 | VFE_STATS_AWBAE_CFG = 0x0000031C, | |
292 | VFE_STATS_AXW_HEADER = 0x00000320, | |
293 | VFE_STATS_AWB_MCFG = 0x00000324, | |
294 | VFE_STATS_AWB_CCFG1 = 0x00000328, | |
295 | VFE_STATS_AWB_CCFG2 = 0x0000032C, | |
296 | VFE_STATS_HIST_HEADER = 0x00000330, | |
297 | VFE_STATS_HIST_INNER_OFFSET = 0x00000334, | |
298 | VFE_STATS_HIST_INNER_DIM = 0x00000338, | |
299 | VFE_STATS_FRAME_SIZE = 0x0000033C, | |
300 | VFE_DMI_CFG = 0x00000340, | |
301 | VFE_DMI_ADDR = 0x00000344, | |
302 | VFE_DMI_DATA_HI = 0x00000348, | |
303 | VFE_DMI_DATA_LO = 0x0000034C, | |
304 | VFE_DMI_RAM_AUTO_LOAD_CMD = 0x00000350, | |
305 | VFE_DMI_RAM_AUTO_LOAD_STATUS = 0x00000354, | |
306 | VFE_DMI_RAM_AUTO_LOAD_CFG = 0x00000358, | |
307 | VFE_DMI_RAM_AUTO_LOAD_SEED = 0x0000035C, | |
308 | VFE_TESTBUS_SEL = 0x00000360, | |
309 | VFE_TESTGEN_CFG = 0x00000364, | |
310 | VFE_SW_TESTGEN_CMD = 0x00000368, | |
311 | VFE_HW_TESTGEN_CMD = 0x0000036C, | |
312 | VFE_HW_TESTGEN_CFG = 0x00000370, | |
313 | VFE_HW_TESTGEN_IMAGE_CFG = 0x00000374, | |
314 | VFE_HW_TESTGEN_SOF_OFFSET_CFG = 0x00000378, | |
315 | VFE_HW_TESTGEN_EOF_NOFFSET_CFG = 0x0000037C, | |
316 | VFE_HW_TESTGEN_SOL_OFFSET_CFG = 0x00000380, | |
317 | VFE_HW_TESTGEN_EOL_NOFFSET_CFG = 0x00000384, | |
318 | VFE_HW_TESTGEN_HBI_CFG = 0x00000388, | |
319 | VFE_HW_TESTGEN_VBL_CFG = 0x0000038C, | |
320 | VFE_HW_TESTGEN_SOF_DUMMY_LINE_CFG2 = 0x00000390, | |
321 | VFE_HW_TESTGEN_EOF_DUMMY_LINE_CFG2 = 0x00000394, | |
322 | VFE_HW_TESTGEN_COLOR_BARS_CFG = 0x00000398, | |
323 | VFE_HW_TESTGEN_RANDOM_CFG = 0x0000039C, | |
324 | VFE_SPARE = 0x000003A0, | |
325 | }; | |
326 | ||
327 | #define ping 0x0 | |
328 | #define pong 0x1 | |
329 | ||
330 | struct vfe_bus_cfg_data { | |
331 | boolean stripeRdPathEn; | |
332 | boolean encYWrPathEn; | |
333 | boolean encCbcrWrPathEn; | |
334 | boolean viewYWrPathEn; | |
335 | boolean viewCbcrWrPathEn; | |
336 | enum VFE_RAW_PIXEL_DATA_SIZE rawPixelDataSize; | |
337 | enum VFE_RAW_WR_PATH_SEL rawWritePathSelect; | |
338 | }; | |
339 | ||
340 | struct vfe_camif_cfg_data { | |
341 | boolean camif2OutputEnable; | |
342 | boolean camif2BusEnable; | |
343 | struct vfe_cmds_camif_cfg camifCfgFromCmd; | |
344 | }; | |
345 | ||
346 | struct vfe_irq_composite_mask_config { | |
347 | uint8_t encIrqComMask; | |
348 | uint8_t viewIrqComMask; | |
349 | uint8_t ceDoneSel; | |
350 | }; | |
351 | ||
352 | /* define a structure for each output path.*/ | |
353 | struct vfe_output_path { | |
354 | uint32_t addressBuffer[8]; | |
355 | uint16_t fragIndex; | |
356 | boolean hwCurrentFlag; | |
357 | uint8_t *hwRegPingAddress; | |
358 | uint8_t *hwRegPongAddress; | |
359 | }; | |
360 | ||
361 | struct vfe_output_path_combo { | |
362 | boolean whichOutputPath; | |
363 | boolean pathEnabled; | |
364 | boolean multiFrag; | |
365 | uint8_t fragCount; | |
366 | boolean ackPending; | |
367 | uint8_t currentFrame; | |
368 | uint32_t nextFrameAddrBuf[8]; | |
369 | struct vfe_output_path yPath; | |
370 | struct vfe_output_path cbcrPath; | |
371 | uint8_t snapshotPendingCount; | |
372 | boolean pmEnabled; | |
373 | uint8_t cbcrStatusBit; | |
374 | }; | |
375 | ||
376 | struct vfe_stats_control { | |
377 | boolean ackPending; | |
378 | uint32_t addressBuffer[2]; | |
379 | uint32_t nextFrameAddrBuf; | |
380 | boolean pingPongStatus; | |
381 | uint8_t *hwRegPingAddress; | |
382 | uint8_t *hwRegPongAddress; | |
383 | uint32_t droppedStatsFrameCount; | |
384 | uint32_t bufToRender; | |
385 | }; | |
386 | ||
387 | struct vfe_gamma_lut_sel { | |
388 | boolean ch0BankSelect; | |
389 | boolean ch1BankSelect; | |
390 | boolean ch2BankSelect; | |
391 | }; | |
392 | ||
393 | struct vfe_interrupt_mask { | |
394 | boolean camifErrorIrq; | |
395 | boolean camifSofIrq; | |
396 | boolean camifEolIrq; | |
397 | boolean camifEofIrq; | |
398 | boolean camifEpoch1Irq; | |
399 | boolean camifEpoch2Irq; | |
400 | boolean camifOverflowIrq; | |
401 | boolean ceIrq; | |
402 | boolean regUpdateIrq; | |
403 | boolean resetAckIrq; | |
404 | boolean encYPingpongIrq; | |
405 | boolean encCbcrPingpongIrq; | |
406 | boolean viewYPingpongIrq; | |
407 | boolean viewCbcrPingpongIrq; | |
408 | boolean rdPingpongIrq; | |
409 | boolean afPingpongIrq; | |
410 | boolean awbPingpongIrq; | |
411 | boolean histPingpongIrq; | |
412 | boolean encIrq; | |
413 | boolean viewIrq; | |
414 | boolean busOverflowIrq; | |
415 | boolean afOverflowIrq; | |
416 | boolean awbOverflowIrq; | |
417 | boolean syncTimer0Irq; | |
418 | boolean syncTimer1Irq; | |
419 | boolean syncTimer2Irq; | |
420 | boolean asyncTimer0Irq; | |
421 | boolean asyncTimer1Irq; | |
422 | boolean asyncTimer2Irq; | |
423 | boolean asyncTimer3Irq; | |
424 | boolean axiErrorIrq; | |
425 | boolean violationIrq; | |
426 | }; | |
427 | ||
428 | enum vfe_interrupt_name { | |
429 | CAMIF_ERROR_IRQ, | |
430 | CAMIF_SOF_IRQ, | |
431 | CAMIF_EOL_IRQ, | |
432 | CAMIF_EOF_IRQ, | |
433 | CAMIF_EPOCH1_IRQ, | |
434 | CAMIF_EPOCH2_IRQ, | |
435 | CAMIF_OVERFLOW_IRQ, | |
436 | CE_IRQ, | |
437 | REG_UPDATE_IRQ, | |
438 | RESET_ACK_IRQ, | |
439 | ENC_Y_PINGPONG_IRQ, | |
440 | ENC_CBCR_PINGPONG_IRQ, | |
441 | VIEW_Y_PINGPONG_IRQ, | |
442 | VIEW_CBCR_PINGPONG_IRQ, | |
443 | RD_PINGPONG_IRQ, | |
444 | AF_PINGPONG_IRQ, | |
445 | AWB_PINGPONG_IRQ, | |
446 | HIST_PINGPONG_IRQ, | |
447 | ENC_IRQ, | |
448 | VIEW_IRQ, | |
449 | BUS_OVERFLOW_IRQ, | |
450 | AF_OVERFLOW_IRQ, | |
451 | AWB_OVERFLOW_IRQ, | |
452 | SYNC_TIMER0_IRQ, | |
453 | SYNC_TIMER1_IRQ, | |
454 | SYNC_TIMER2_IRQ, | |
455 | ASYNC_TIMER0_IRQ, | |
456 | ASYNC_TIMER1_IRQ, | |
457 | ASYNC_TIMER2_IRQ, | |
458 | ASYNC_TIMER3_IRQ, | |
459 | AXI_ERROR_IRQ, | |
460 | VIOLATION_IRQ | |
461 | }; | |
462 | ||
463 | enum VFE_DMI_RAM_SEL { | |
464 | NO_MEM_SELECTED = 0, | |
465 | ROLLOFF_RAM = 0x1, | |
466 | RGBLUT_RAM_CH0_BANK0 = 0x2, | |
467 | RGBLUT_RAM_CH0_BANK1 = 0x3, | |
468 | RGBLUT_RAM_CH1_BANK0 = 0x4, | |
469 | RGBLUT_RAM_CH1_BANK1 = 0x5, | |
470 | RGBLUT_RAM_CH2_BANK0 = 0x6, | |
471 | RGBLUT_RAM_CH2_BANK1 = 0x7, | |
472 | STATS_HIST_CB_EVEN_RAM = 0x8, | |
473 | STATS_HIST_CB_ODD_RAM = 0x9, | |
474 | STATS_HIST_CR_EVEN_RAM = 0xa, | |
475 | STATS_HIST_CR_ODD_RAM = 0xb, | |
476 | RGBLUT_CHX_BANK0 = 0xc, | |
477 | RGBLUT_CHX_BANK1 = 0xd, | |
478 | LUMA_ADAPT_LUT_RAM_BANK0 = 0xe, | |
479 | LUMA_ADAPT_LUT_RAM_BANK1 = 0xf | |
480 | }; | |
481 | ||
482 | struct vfe_module_enable { | |
483 | boolean blackLevelCorrectionEnable; | |
484 | boolean lensRollOffEnable; | |
485 | boolean demuxEnable; | |
486 | boolean chromaUpsampleEnable; | |
487 | boolean demosaicEnable; | |
488 | boolean statsEnable; | |
489 | boolean cropEnable; | |
490 | boolean mainScalerEnable; | |
491 | boolean whiteBalanceEnable; | |
492 | boolean colorCorrectionEnable; | |
493 | boolean yHistEnable; | |
494 | boolean skinToneEnable; | |
495 | boolean lumaAdaptationEnable; | |
496 | boolean rgbLUTEnable; | |
497 | boolean chromaEnhanEnable; | |
498 | boolean asfEnable; | |
499 | boolean chromaSuppressionEnable; | |
500 | boolean chromaSubsampleEnable; | |
501 | boolean scaler2YEnable; | |
502 | boolean scaler2CbcrEnable; | |
503 | }; | |
504 | ||
505 | struct vfe_bus_cmd_data { | |
506 | boolean stripeReload; | |
507 | boolean busPingpongReload; | |
508 | boolean statsPingpongReload; | |
509 | }; | |
510 | ||
511 | struct vfe_stats_cmd_data { | |
512 | boolean autoFocusEnable; | |
513 | boolean axwEnable; | |
514 | boolean histEnable; | |
515 | boolean clearHistEnable; | |
516 | boolean histAutoClearEnable; | |
517 | boolean colorConversionEnable; | |
518 | }; | |
519 | ||
520 | struct vfe_hw_ver { | |
521 | uint32_t minorVersion:8; | |
522 | uint32_t majorVersion:8; | |
523 | uint32_t coreVersion:4; | |
524 | uint32_t /* reserved */ : 12; | |
525 | } __attribute__((packed, aligned(4))); | |
526 | ||
527 | struct vfe_cfg { | |
528 | uint32_t pixelPattern:3; | |
529 | uint32_t /* reserved */ : 13; | |
530 | uint32_t inputSource:2; | |
531 | uint32_t /* reserved */ : 14; | |
532 | } __attribute__((packed, aligned(4))); | |
533 | ||
534 | struct vfe_buscmd { | |
535 | uint32_t stripeReload:1; | |
536 | uint32_t /* reserved */ : 3; | |
537 | uint32_t busPingpongReload:1; | |
538 | uint32_t statsPingpongReload:1; | |
539 | uint32_t /* reserved */ : 26; | |
540 | } __attribute__((packed, aligned(4))); | |
541 | ||
542 | struct VFE_Irq_Composite_MaskType { | |
543 | uint32_t encIrqComMaskBits:2; | |
544 | uint32_t viewIrqComMaskBits:2; | |
545 | uint32_t ceDoneSelBits:5; | |
546 | uint32_t /* reserved */ : 23; | |
547 | } __attribute__((packed, aligned(4))); | |
548 | ||
549 | struct vfe_mod_enable { | |
550 | uint32_t blackLevelCorrectionEnable:1; | |
551 | uint32_t lensRollOffEnable:1; | |
552 | uint32_t demuxEnable:1; | |
553 | uint32_t chromaUpsampleEnable:1; | |
554 | uint32_t demosaicEnable:1; | |
555 | uint32_t statsEnable:1; | |
556 | uint32_t cropEnable:1; | |
557 | uint32_t mainScalerEnable:1; | |
558 | uint32_t whiteBalanceEnable:1; | |
559 | uint32_t colorCorrectionEnable:1; | |
560 | uint32_t yHistEnable:1; | |
561 | uint32_t skinToneEnable:1; | |
562 | uint32_t lumaAdaptationEnable:1; | |
563 | uint32_t rgbLUTEnable:1; | |
564 | uint32_t chromaEnhanEnable:1; | |
565 | uint32_t asfEnable:1; | |
566 | uint32_t chromaSuppressionEnable:1; | |
567 | uint32_t chromaSubsampleEnable:1; | |
568 | uint32_t scaler2YEnable:1; | |
569 | uint32_t scaler2CbcrEnable:1; | |
570 | uint32_t /* reserved */ : 14; | |
571 | } __attribute__((packed, aligned(4))); | |
572 | ||
573 | struct vfe_irqenable { | |
574 | uint32_t camifErrorIrq:1; | |
575 | uint32_t camifSofIrq:1; | |
576 | uint32_t camifEolIrq:1; | |
577 | uint32_t camifEofIrq:1; | |
578 | uint32_t camifEpoch1Irq:1; | |
579 | uint32_t camifEpoch2Irq:1; | |
580 | uint32_t camifOverflowIrq:1; | |
581 | uint32_t ceIrq:1; | |
582 | uint32_t regUpdateIrq:1; | |
583 | uint32_t resetAckIrq:1; | |
584 | uint32_t encYPingpongIrq:1; | |
585 | uint32_t encCbcrPingpongIrq:1; | |
586 | uint32_t viewYPingpongIrq:1; | |
587 | uint32_t viewCbcrPingpongIrq:1; | |
588 | uint32_t rdPingpongIrq:1; | |
589 | uint32_t afPingpongIrq:1; | |
590 | uint32_t awbPingpongIrq:1; | |
591 | uint32_t histPingpongIrq:1; | |
592 | uint32_t encIrq:1; | |
593 | uint32_t viewIrq:1; | |
594 | uint32_t busOverflowIrq:1; | |
595 | uint32_t afOverflowIrq:1; | |
596 | uint32_t awbOverflowIrq:1; | |
597 | uint32_t syncTimer0Irq:1; | |
598 | uint32_t syncTimer1Irq:1; | |
599 | uint32_t syncTimer2Irq:1; | |
600 | uint32_t asyncTimer0Irq:1; | |
601 | uint32_t asyncTimer1Irq:1; | |
602 | uint32_t asyncTimer2Irq:1; | |
603 | uint32_t asyncTimer3Irq:1; | |
604 | uint32_t axiErrorIrq:1; | |
605 | uint32_t violationIrq:1; | |
606 | } __attribute__((packed, aligned(4))); | |
607 | ||
608 | struct vfe_upsample_cfg { | |
609 | uint32_t chromaCositingForYCbCrInputs:1; | |
610 | uint32_t /* reserved */ : 31; | |
611 | } __attribute__((packed, aligned(4))); | |
612 | ||
613 | struct VFE_CAMIFConfigType { | |
614 | /* CAMIF Config */ | |
615 | uint32_t /* reserved */ : 1; | |
616 | uint32_t VSyncEdge:1; | |
617 | uint32_t HSyncEdge:1; | |
618 | uint32_t syncMode:2; | |
619 | uint32_t vfeSubsampleEnable:1; | |
620 | uint32_t /* reserved */ : 1; | |
621 | uint32_t busSubsampleEnable:1; | |
622 | uint32_t camif2vfeEnable:1; | |
623 | uint32_t /* reserved */ : 1; | |
624 | uint32_t camif2busEnable:1; | |
625 | uint32_t irqSubsampleEnable:1; | |
626 | uint32_t binningEnable:1; | |
627 | uint32_t /* reserved */ : 18; | |
628 | uint32_t misrEnable:1; | |
629 | } __attribute__((packed, aligned(4))); | |
630 | ||
631 | struct vfe_camifcfg { | |
632 | /* EFS_Config */ | |
633 | uint32_t efsEndOfLine:8; | |
634 | uint32_t efsStartOfLine:8; | |
635 | uint32_t efsEndOfFrame:8; | |
636 | uint32_t efsStartOfFrame:8; | |
637 | /* Frame Config */ | |
638 | uint32_t frameConfigPixelsPerLine:14; | |
639 | uint32_t /* reserved */ : 2; | |
640 | uint32_t frameConfigLinesPerFrame:14; | |
641 | uint32_t /* reserved */ : 2; | |
642 | /* Window Width Config */ | |
643 | uint32_t windowWidthCfgLastPixel:14; | |
644 | uint32_t /* reserved */ : 2; | |
645 | uint32_t windowWidthCfgFirstPixel:14; | |
646 | uint32_t /* reserved */ : 2; | |
647 | /* Window Height Config */ | |
648 | uint32_t windowHeightCfglastLine:14; | |
649 | uint32_t /* reserved */ : 2; | |
650 | uint32_t windowHeightCfgfirstLine:14; | |
651 | uint32_t /* reserved */ : 2; | |
652 | /* Subsample 1 Config */ | |
653 | uint32_t subsample1CfgPixelSkip:16; | |
654 | uint32_t subsample1CfgLineSkip:16; | |
655 | /* Subsample 2 Config */ | |
656 | uint32_t subsample2CfgFrameSkip:4; | |
657 | uint32_t subsample2CfgFrameSkipMode:1; | |
658 | uint32_t subsample2CfgPixelSkipWrap:1; | |
659 | uint32_t /* reserved */ : 26; | |
660 | /* Epoch Interrupt */ | |
661 | uint32_t epoch1Line:14; | |
662 | uint32_t /* reserved */ : 2; | |
663 | uint32_t epoch2Line:14; | |
664 | uint32_t /* reserved */ : 2; | |
665 | } __attribute__((packed, aligned(4))); | |
666 | ||
667 | struct vfe_camifframe_update { | |
668 | uint32_t pixelsPerLine:14; | |
669 | uint32_t /* reserved */ : 2; | |
670 | uint32_t linesPerFrame:14; | |
671 | uint32_t /* reserved */ : 2; | |
672 | } __attribute__((packed, aligned(4))); | |
673 | ||
674 | struct vfe_axi_bus_cfg { | |
675 | uint32_t stripeRdPathEn:1; | |
676 | uint32_t /* reserved */ : 3; | |
677 | uint32_t encYWrPathEn:1; | |
678 | uint32_t encCbcrWrPathEn:1; | |
679 | uint32_t viewYWrPathEn:1; | |
680 | uint32_t viewCbcrWrPathEn:1; | |
681 | uint32_t rawPixelDataSize:2; | |
682 | uint32_t rawWritePathSelect:2; | |
683 | uint32_t /* reserved */ : 20; | |
684 | } __attribute__((packed, aligned(4))); | |
685 | ||
686 | struct vfe_axi_out_cfg { | |
687 | uint32_t out2YPingAddr:32; | |
688 | uint32_t out2YPongAddr:32; | |
689 | uint32_t out2YImageHeight:12; | |
690 | uint32_t /* reserved */ : 4; | |
691 | uint32_t out2YImageWidthin64bit:10; | |
692 | uint32_t /* reserved */ : 6; | |
693 | uint32_t out2YBurstLength:2; | |
694 | uint32_t /* reserved */ : 2; | |
695 | uint32_t out2YNumRows:12; | |
696 | uint32_t out2YRowIncrementIn64bit:12; | |
697 | uint32_t /* reserved */ : 4; | |
698 | uint32_t out2CbcrPingAddr:32; | |
699 | uint32_t out2CbcrPongAddr:32; | |
700 | uint32_t out2CbcrImageHeight:12; | |
701 | uint32_t /* reserved */ : 4; | |
702 | uint32_t out2CbcrImageWidthIn64bit:10; | |
703 | uint32_t /* reserved */ : 6; | |
704 | uint32_t out2CbcrBurstLength:2; | |
705 | uint32_t /* reserved */ : 2; | |
706 | uint32_t out2CbcrNumRows:12; | |
707 | uint32_t out2CbcrRowIncrementIn64bit:12; | |
708 | uint32_t /* reserved */ : 4; | |
709 | uint32_t out1YPingAddr:32; | |
710 | uint32_t out1YPongAddr:32; | |
711 | uint32_t out1YImageHeight:12; | |
712 | uint32_t /* reserved */ : 4; | |
713 | uint32_t out1YImageWidthin64bit:10; | |
714 | uint32_t /* reserved */ : 6; | |
715 | uint32_t out1YBurstLength:2; | |
716 | uint32_t /* reserved */ : 2; | |
717 | uint32_t out1YNumRows:12; | |
718 | uint32_t out1YRowIncrementIn64bit:12; | |
719 | uint32_t /* reserved */ : 4; | |
720 | uint32_t out1CbcrPingAddr:32; | |
721 | uint32_t out1CbcrPongAddr:32; | |
722 | uint32_t out1CbcrImageHeight:12; | |
723 | uint32_t /* reserved */ : 4; | |
724 | uint32_t out1CbcrImageWidthIn64bit:10; | |
725 | uint32_t /* reserved */ : 6; | |
726 | uint32_t out1CbcrBurstLength:2; | |
727 | uint32_t /* reserved */ : 2; | |
728 | uint32_t out1CbcrNumRows:12; | |
729 | uint32_t out1CbcrRowIncrementIn64bit:12; | |
730 | uint32_t /* reserved */ : 4; | |
731 | } __attribute__((packed, aligned(4))); | |
732 | ||
733 | struct vfe_output_clamp_cfg { | |
734 | /* Output Clamp Maximums */ | |
735 | uint32_t yChanMax:8; | |
736 | uint32_t cbChanMax:8; | |
737 | uint32_t crChanMax:8; | |
738 | uint32_t /* reserved */ : 8; | |
739 | /* Output Clamp Minimums */ | |
740 | uint32_t yChanMin:8; | |
741 | uint32_t cbChanMin:8; | |
742 | uint32_t crChanMin:8; | |
743 | uint32_t /* reserved */ : 8; | |
744 | } __attribute__((packed, aligned(4))); | |
745 | ||
746 | struct vfe_fov_crop_cfg { | |
747 | uint32_t lastPixel:12; | |
748 | uint32_t /* reserved */ : 4; | |
749 | uint32_t firstPixel:12; | |
750 | uint32_t /* reserved */ : 4; | |
751 | ||
752 | /* FOV Corp, Part 2 */ | |
753 | uint32_t lastLine:12; | |
754 | uint32_t /* reserved */ : 4; | |
755 | uint32_t firstLine:12; | |
756 | uint32_t /* reserved */ : 4; | |
757 | } __attribute__((packed, aligned(4))); | |
758 | ||
759 | struct VFE_FRAME_SKIP_UpdateCmdType { | |
760 | uint32_t yPattern:32; | |
761 | uint32_t cbcrPattern:32; | |
762 | } __attribute__((packed, aligned(4))); | |
763 | ||
764 | struct vfe_frame_skip_cfg { | |
765 | /* Frame Drop Enc (output2) */ | |
766 | uint32_t output2YPeriod:5; | |
767 | uint32_t /* reserved */ : 27; | |
768 | uint32_t output2CbCrPeriod:5; | |
769 | uint32_t /* reserved */ : 27; | |
770 | uint32_t output2YPattern:32; | |
771 | uint32_t output2CbCrPattern:32; | |
772 | /* Frame Drop View (output1) */ | |
773 | uint32_t output1YPeriod:5; | |
774 | uint32_t /* reserved */ : 27; | |
775 | uint32_t output1CbCrPeriod:5; | |
776 | uint32_t /* reserved */ : 27; | |
777 | uint32_t output1YPattern:32; | |
778 | uint32_t output1CbCrPattern:32; | |
779 | } __attribute__((packed, aligned(4))); | |
780 | ||
781 | struct vfe_main_scaler_cfg { | |
782 | /* Scaler Enable Config */ | |
783 | uint32_t hEnable:1; | |
784 | uint32_t vEnable:1; | |
785 | uint32_t /* reserved */ : 30; | |
786 | /* Scale H Image Size Config */ | |
787 | uint32_t inWidth:12; | |
788 | uint32_t /* reserved */ : 4; | |
789 | uint32_t outWidth:12; | |
790 | uint32_t /* reserved */ : 4; | |
791 | /* Scale H Phase Config */ | |
792 | uint32_t horizPhaseMult:18; | |
793 | uint32_t /* reserved */ : 2; | |
794 | uint32_t horizInterResolution:2; | |
795 | uint32_t /* reserved */ : 10; | |
796 | /* Scale H Stripe Config */ | |
797 | uint32_t horizMNInit:12; | |
798 | uint32_t /* reserved */ : 4; | |
799 | uint32_t horizPhaseInit:15; | |
800 | uint32_t /* reserved */ : 1; | |
801 | /* Scale V Image Size Config */ | |
802 | uint32_t inHeight:12; | |
803 | uint32_t /* reserved */ : 4; | |
804 | uint32_t outHeight:12; | |
805 | uint32_t /* reserved */ : 4; | |
806 | /* Scale V Phase Config */ | |
807 | uint32_t vertPhaseMult:18; | |
808 | uint32_t /* reserved */ : 2; | |
809 | uint32_t vertInterResolution:2; | |
810 | uint32_t /* reserved */ : 10; | |
811 | /* Scale V Stripe Config */ | |
812 | uint32_t vertMNInit:12; | |
813 | uint32_t /* reserved */ : 4; | |
814 | uint32_t vertPhaseInit:15; | |
815 | uint32_t /* reserved */ : 1; | |
816 | } __attribute__((packed, aligned(4))); | |
817 | ||
818 | struct vfe_scaler2_cfg { | |
819 | /* Scaler Enable Config */ | |
820 | uint32_t hEnable:1; | |
821 | uint32_t vEnable:1; | |
822 | uint32_t /* reserved */ : 30; | |
823 | /* Scaler H Image Size Config */ | |
824 | uint32_t inWidth:12; | |
825 | uint32_t /* reserved */ : 4; | |
826 | uint32_t outWidth:12; | |
827 | uint32_t /* reserved */ : 4; | |
828 | /* Scaler H Phase Config */ | |
829 | uint32_t horizPhaseMult:18; | |
830 | uint32_t /* reserved */ : 2; | |
831 | uint32_t horizInterResolution:2; | |
832 | uint32_t /* reserved */ : 10; | |
833 | /* Scaler V Image Size Config */ | |
834 | uint32_t inHeight:12; | |
835 | uint32_t /* reserved */ : 4; | |
836 | uint32_t outHeight:12; | |
837 | uint32_t /* reserved */ : 4; | |
838 | /* Scaler V Phase Config */ | |
839 | uint32_t vertPhaseMult:18; | |
840 | uint32_t /* reserved */ : 2; | |
841 | uint32_t vertInterResolution:2; | |
842 | uint32_t /* reserved */ : 10; | |
843 | } __attribute__((packed, aligned(4))); | |
844 | ||
845 | struct vfe_rolloff_cfg { | |
846 | /* Rolloff 0 Config */ | |
847 | uint32_t gridWidth:9; | |
848 | uint32_t gridHeight:9; | |
849 | uint32_t yDelta:9; | |
850 | uint32_t /* reserved */ : 5; | |
851 | /* Rolloff 1 Config*/ | |
852 | uint32_t gridX:4; | |
853 | uint32_t gridY:4; | |
854 | uint32_t pixelX:9; | |
855 | uint32_t /* reserved */ : 3; | |
856 | uint32_t pixelY:9; | |
857 | uint32_t /* reserved */ : 3; | |
858 | /* Rolloff 2 Config */ | |
859 | uint32_t yDeltaAccum:12; | |
860 | uint32_t /* reserved */ : 20; | |
861 | } __attribute__((packed, aligned(4))); | |
862 | ||
863 | struct vfe_asf_update { | |
864 | /* ASF Config Command */ | |
865 | uint32_t smoothEnable:1; | |
866 | uint32_t sharpMode:2; | |
867 | uint32_t /* reserved */ : 1; | |
868 | uint32_t smoothCoeff1:4; | |
869 | uint32_t smoothCoeff0:8; | |
870 | uint32_t pipeFlushCount:12; | |
871 | uint32_t pipeFlushOvd:1; | |
872 | uint32_t flushHaltOvd:1; | |
873 | uint32_t cropEnable:1; | |
874 | uint32_t /* reserved */ : 1; | |
875 | /* Sharpening Config 0 */ | |
876 | uint32_t sharpThresholdE1:7; | |
877 | uint32_t /* reserved */ : 1; | |
878 | uint32_t sharpDegreeK1:5; | |
879 | uint32_t /* reserved */ : 3; | |
880 | uint32_t sharpDegreeK2:5; | |
881 | uint32_t /* reserved */ : 3; | |
882 | uint32_t normalizeFactor:7; | |
883 | uint32_t /* reserved */ : 1; | |
884 | /* Sharpening Config 1 */ | |
885 | uint32_t sharpThresholdE2:8; | |
886 | uint32_t sharpThresholdE3:8; | |
887 | uint32_t sharpThresholdE4:8; | |
888 | uint32_t sharpThresholdE5:8; | |
889 | /* Sharpening Coefficients 0 */ | |
890 | uint32_t F1Coeff0:6; | |
891 | uint32_t F1Coeff1:6; | |
892 | uint32_t F1Coeff2:6; | |
893 | uint32_t F1Coeff3:6; | |
894 | uint32_t F1Coeff4:6; | |
895 | uint32_t /* reserved */ : 2; | |
896 | /* Sharpening Coefficients 1 */ | |
897 | uint32_t F1Coeff5:6; | |
898 | uint32_t F1Coeff6:6; | |
899 | uint32_t F1Coeff7:6; | |
900 | uint32_t F1Coeff8:7; | |
901 | uint32_t /* reserved */ : 7; | |
902 | /* Sharpening Coefficients 2 */ | |
903 | uint32_t F2Coeff0:6; | |
904 | uint32_t F2Coeff1:6; | |
905 | uint32_t F2Coeff2:6; | |
906 | uint32_t F2Coeff3:6; | |
907 | uint32_t F2Coeff4:6; | |
908 | uint32_t /* reserved */ : 2; | |
909 | /* Sharpening Coefficients 3 */ | |
910 | uint32_t F2Coeff5:6; | |
911 | uint32_t F2Coeff6:6; | |
912 | uint32_t F2Coeff7:6; | |
913 | uint32_t F2Coeff8:7; | |
914 | uint32_t /* reserved */ : 7; | |
915 | } __attribute__((packed, aligned(4))); | |
916 | ||
917 | struct vfe_asfcrop_cfg { | |
918 | /* ASF Crop Width Config */ | |
919 | uint32_t lastPixel:12; | |
920 | uint32_t /* reserved */ : 4; | |
921 | uint32_t firstPixel:12; | |
922 | uint32_t /* reserved */ : 4; | |
923 | /* ASP Crop Height Config */ | |
924 | uint32_t lastLine:12; | |
925 | uint32_t /* reserved */ : 4; | |
926 | uint32_t firstLine:12; | |
927 | uint32_t /* reserved */ : 4; | |
928 | } __attribute__((packed, aligned(4))); | |
929 | ||
930 | struct vfe_chroma_suppress_cfg { | |
931 | /* Chroma Suppress 0 Config */ | |
932 | uint32_t m1:8; | |
933 | uint32_t m3:8; | |
934 | uint32_t n1:3; | |
935 | uint32_t /* reserved */ : 1; | |
936 | uint32_t n3:3; | |
937 | uint32_t /* reserved */ : 9; | |
938 | /* Chroma Suppress 1 Config */ | |
939 | uint32_t mm1:8; | |
940 | uint32_t nn1:3; | |
941 | uint32_t /* reserved */ : 21; | |
942 | } __attribute__((packed, aligned(4))); | |
943 | ||
944 | struct vfe_chromasubsample_cfg { | |
945 | /* Chroma Subsample Selection */ | |
946 | uint32_t hCositedPhase:1; | |
947 | uint32_t vCositedPhase:1; | |
948 | uint32_t hCosited:1; | |
949 | uint32_t vCosited:1; | |
950 | uint32_t hsubSampleEnable:1; | |
951 | uint32_t vsubSampleEnable:1; | |
952 | uint32_t cropEnable:1; | |
953 | uint32_t /* reserved */ : 25; | |
954 | uint32_t cropWidthLastPixel:12; | |
955 | uint32_t /* reserved */ : 4; | |
956 | uint32_t cropWidthFirstPixel:12; | |
957 | uint32_t /* reserved */ : 4; | |
958 | uint32_t cropHeightLastLine:12; | |
959 | uint32_t /* reserved */ : 4; | |
960 | uint32_t cropHeightFirstLine:12; | |
961 | uint32_t /* reserved */ : 4; | |
962 | } __attribute__((packed, aligned(4))); | |
963 | ||
964 | struct vfe_blacklevel_cfg { | |
965 | /* Black Even-Even Value Config */ | |
966 | uint32_t evenEvenAdjustment:9; | |
967 | uint32_t /* reserved */ : 23; | |
968 | /* Black Even-Odd Value Config */ | |
969 | uint32_t evenOddAdjustment:9; | |
970 | uint32_t /* reserved */ : 23; | |
971 | /* Black Odd-Even Value Config */ | |
972 | uint32_t oddEvenAdjustment:9; | |
973 | uint32_t /* reserved */ : 23; | |
974 | /* Black Odd-Odd Value Config */ | |
975 | uint32_t oddOddAdjustment:9; | |
976 | uint32_t /* reserved */ : 23; | |
977 | } __attribute__((packed, aligned(4))); | |
978 | ||
979 | struct vfe_demux_cfg { | |
980 | /* Demux Gain 0 Config */ | |
981 | uint32_t ch0EvenGain:10; | |
982 | uint32_t /* reserved */ : 6; | |
983 | uint32_t ch0OddGain:10; | |
984 | uint32_t /* reserved */ : 6; | |
985 | /* Demux Gain 1 Config */ | |
986 | uint32_t ch1Gain:10; | |
987 | uint32_t /* reserved */ : 6; | |
988 | uint32_t ch2Gain:10; | |
989 | uint32_t /* reserved */ : 6; | |
990 | } __attribute__((packed, aligned(4))); | |
991 | ||
992 | struct vfe_bps_info { | |
993 | uint32_t greenBadPixelCount:8; | |
994 | uint32_t /* reserved */ : 8; | |
995 | uint32_t RedBlueBadPixelCount:8; | |
996 | uint32_t /* reserved */ : 8; | |
997 | } __attribute__((packed, aligned(4))); | |
998 | ||
999 | struct vfe_demosaic_cfg { | |
1000 | /* Demosaic Config */ | |
1001 | uint32_t abfEnable:1; | |
1002 | uint32_t badPixelCorrEnable:1; | |
1003 | uint32_t forceAbfOn:1; | |
1004 | uint32_t /* reserved */ : 1; | |
1005 | uint32_t abfShift:4; | |
1006 | uint32_t fminThreshold:7; | |
1007 | uint32_t /* reserved */ : 1; | |
1008 | uint32_t fmaxThreshold:7; | |
1009 | uint32_t /* reserved */ : 5; | |
1010 | uint32_t slopeShift:3; | |
1011 | uint32_t /* reserved */ : 1; | |
1012 | } __attribute__((packed, aligned(4))); | |
1013 | ||
1014 | struct vfe_demosaic_bpc_cfg { | |
1015 | /* Demosaic BPC Config 0 */ | |
1016 | uint32_t blueDiffThreshold:12; | |
1017 | uint32_t redDiffThreshold:12; | |
1018 | uint32_t /* reserved */ : 8; | |
1019 | /* Demosaic BPC Config 1 */ | |
1020 | uint32_t greenDiffThreshold:12; | |
1021 | uint32_t /* reserved */ : 20; | |
1022 | } __attribute__((packed, aligned(4))); | |
1023 | ||
1024 | struct vfe_demosaic_abf_cfg { | |
1025 | /* Demosaic ABF Config 0 */ | |
1026 | uint32_t lpThreshold:10; | |
1027 | uint32_t /* reserved */ : 22; | |
1028 | /* Demosaic ABF Config 1 */ | |
1029 | uint32_t ratio:4; | |
1030 | uint32_t minValue:10; | |
1031 | uint32_t /* reserved */ : 2; | |
1032 | uint32_t maxValue:10; | |
1033 | uint32_t /* reserved */ : 6; | |
1034 | } __attribute__((packed, aligned(4))); | |
1035 | ||
1036 | struct vfe_color_correction_cfg { | |
1037 | /* Color Corr. Coefficient 0 Config */ | |
1038 | uint32_t c0:12; | |
1039 | uint32_t /* reserved */ : 20; | |
1040 | /* Color Corr. Coefficient 1 Config */ | |
1041 | uint32_t c1:12; | |
1042 | uint32_t /* reserved */ : 20; | |
1043 | /* Color Corr. Coefficient 2 Config */ | |
1044 | uint32_t c2:12; | |
1045 | uint32_t /* reserved */ : 20; | |
1046 | /* Color Corr. Coefficient 3 Config */ | |
1047 | uint32_t c3:12; | |
1048 | uint32_t /* reserved */ : 20; | |
1049 | /* Color Corr. Coefficient 4 Config */ | |
1050 | uint32_t c4:12; | |
1051 | uint32_t /* reserved */ : 20; | |
1052 | /* Color Corr. Coefficient 5 Config */ | |
1053 | uint32_t c5:12; | |
1054 | uint32_t /* reserved */ : 20; | |
1055 | /* Color Corr. Coefficient 6 Config */ | |
1056 | uint32_t c6:12; | |
1057 | uint32_t /* reserved */ : 20; | |
1058 | /* Color Corr. Coefficient 7 Config */ | |
1059 | uint32_t c7:12; | |
1060 | uint32_t /* reserved */ : 20; | |
1061 | /* Color Corr. Coefficient 8 Config */ | |
1062 | uint32_t c8:12; | |
1063 | uint32_t /* reserved */ : 20; | |
1064 | /* Color Corr. Offset 0 Config */ | |
1065 | uint32_t k0:11; | |
1066 | uint32_t /* reserved */ : 21; | |
1067 | /* Color Corr. Offset 1 Config */ | |
1068 | uint32_t k1:11; | |
1069 | uint32_t /* reserved */ : 21; | |
1070 | /* Color Corr. Offset 2 Config */ | |
1071 | uint32_t k2:11; | |
1072 | uint32_t /* reserved */ : 21; | |
1073 | /* Color Corr. Coefficient Q Config */ | |
1074 | uint32_t coefQFactor:2; | |
1075 | uint32_t /* reserved */ : 30; | |
1076 | } __attribute__((packed, aligned(4))); | |
1077 | ||
1078 | struct VFE_LumaAdaptation_ConfigCmdType { | |
1079 | /* LA Config */ | |
1080 | uint32_t lutBankSelect:1; | |
1081 | uint32_t /* reserved */ : 31; | |
1082 | } __attribute__((packed, aligned(4))); | |
1083 | ||
1084 | struct vfe_wb_cfg { | |
1085 | /* WB Config */ | |
1086 | uint32_t ch0Gain:9; | |
1087 | uint32_t ch1Gain:9; | |
1088 | uint32_t ch2Gain:9; | |
1089 | uint32_t /* reserved */ : 5; | |
1090 | } __attribute__((packed, aligned(4))); | |
1091 | ||
1092 | struct VFE_GammaLutSelect_ConfigCmdType { | |
1093 | /* LUT Bank Select Config */ | |
1094 | uint32_t ch0BankSelect:1; | |
1095 | uint32_t ch1BankSelect:1; | |
1096 | uint32_t ch2BankSelect:1; | |
1097 | uint32_t /* reserved */ : 29; | |
1098 | } __attribute__((packed, aligned(4))); | |
1099 | ||
1100 | struct vfe_chroma_enhance_cfg { | |
1101 | /* Chroma Enhance A Config */ | |
1102 | uint32_t ap:11; | |
1103 | uint32_t /* reserved */ : 5; | |
1104 | uint32_t am:11; | |
1105 | uint32_t /* reserved */ : 5; | |
1106 | /* Chroma Enhance B Config */ | |
1107 | uint32_t bp:11; | |
1108 | uint32_t /* reserved */ : 5; | |
1109 | uint32_t bm:11; | |
1110 | uint32_t /* reserved */ : 5; | |
1111 | /* Chroma Enhance C Config */ | |
1112 | uint32_t cp:11; | |
1113 | uint32_t /* reserved */ : 5; | |
1114 | uint32_t cm:11; | |
1115 | uint32_t /* reserved */ : 5; | |
1116 | /* Chroma Enhance D Config */ | |
1117 | uint32_t dp:11; | |
1118 | uint32_t /* reserved */ : 5; | |
1119 | uint32_t dm:11; | |
1120 | uint32_t /* reserved */ : 5; | |
1121 | /* Chroma Enhance K Config */ | |
1122 | uint32_t kcb:11; | |
1123 | uint32_t /* reserved */ : 5; | |
1124 | uint32_t kcr:11; | |
1125 | uint32_t /* reserved */ : 5; | |
1126 | } __attribute__((packed, aligned(4))); | |
1127 | ||
1128 | struct vfe_color_convert_cfg { | |
1129 | /* Conversion Coefficient 0 */ | |
1130 | uint32_t v0:12; | |
1131 | uint32_t /* reserved */ : 20; | |
1132 | /* Conversion Coefficient 1 */ | |
1133 | uint32_t v1:12; | |
1134 | uint32_t /* reserved */ : 20; | |
1135 | /* Conversion Coefficient 2 */ | |
1136 | uint32_t v2:12; | |
1137 | uint32_t /* reserved */ : 20; | |
1138 | /* Conversion Offset */ | |
1139 | uint32_t ConvertOffset:8; | |
1140 | uint32_t /* reserved */ : 24; | |
1141 | } __attribute__((packed, aligned(4))); | |
1142 | ||
1143 | struct VFE_SyncTimer_ConfigCmdType { | |
1144 | /* Timer Line Start Config */ | |
1145 | uint32_t timerLineStart:12; | |
1146 | uint32_t /* reserved */ : 20; | |
1147 | /* Timer Pixel Start Config */ | |
1148 | uint32_t timerPixelStart:18; | |
1149 | uint32_t /* reserved */ : 14; | |
1150 | /* Timer Pixel Duration Config */ | |
1151 | uint32_t timerPixelDuration:28; | |
1152 | uint32_t /* reserved */ : 4; | |
1153 | /* Sync Timer Polarity Config */ | |
1154 | uint32_t timer0Polarity:1; | |
1155 | uint32_t timer1Polarity:1; | |
1156 | uint32_t timer2Polarity:1; | |
1157 | uint32_t /* reserved */ : 29; | |
1158 | } __attribute__((packed, aligned(4))); | |
1159 | ||
1160 | struct VFE_AsyncTimer_ConfigCmdType { | |
1161 | /* Async Timer Config 0 */ | |
1162 | uint32_t inactiveLength:20; | |
1163 | uint32_t numRepetition:10; | |
1164 | uint32_t /* reserved */ : 1; | |
1165 | uint32_t polarity:1; | |
1166 | /* Async Timer Config 1 */ | |
1167 | uint32_t activeLength:20; | |
1168 | uint32_t /* reserved */ : 12; | |
1169 | } __attribute__((packed, aligned(4))); | |
1170 | ||
1171 | struct VFE_AWBAEStatistics_ConfigCmdType { | |
1172 | /* AWB autoexposure Config */ | |
1173 | uint32_t aeRegionConfig:1; | |
1174 | uint32_t aeSubregionConfig:1; | |
1175 | uint32_t /* reserved */ : 14; | |
1176 | uint32_t awbYMin:8; | |
1177 | uint32_t awbYMax:8; | |
1178 | /* AXW Header */ | |
1179 | uint32_t axwHeader:8; | |
1180 | uint32_t /* reserved */ : 24; | |
1181 | /* AWB Mconfig */ | |
1182 | uint32_t m4:8; | |
1183 | uint32_t m3:8; | |
1184 | uint32_t m2:8; | |
1185 | uint32_t m1:8; | |
1186 | /* AWB Cconfig */ | |
1187 | uint32_t c2:12; | |
1188 | uint32_t /* reserved */ : 4; | |
1189 | uint32_t c1:12; | |
1190 | uint32_t /* reserved */ : 4; | |
1191 | /* AWB Cconfig 2 */ | |
1192 | uint32_t c4:12; | |
1193 | uint32_t /* reserved */ : 4; | |
1194 | uint32_t c3:12; | |
1195 | uint32_t /* reserved */ : 4; | |
1196 | } __attribute__((packed, aligned(4))); | |
1197 | ||
1198 | struct VFE_TestGen_ConfigCmdType { | |
1199 | /* HW Test Gen Config */ | |
1200 | uint32_t numFrame:10; | |
1201 | uint32_t /* reserved */ : 2; | |
1202 | uint32_t pixelDataSelect:1; | |
1203 | uint32_t systematicDataSelect:1; | |
1204 | uint32_t /* reserved */ : 2; | |
1205 | uint32_t pixelDataSize:2; | |
1206 | uint32_t hsyncEdge:1; | |
1207 | uint32_t vsyncEdge:1; | |
1208 | uint32_t /* reserved */ : 12; | |
1209 | /* HW Test Gen Image Config */ | |
1210 | uint32_t imageWidth:14; | |
1211 | uint32_t /* reserved */ : 2; | |
1212 | uint32_t imageHeight:14; | |
1213 | uint32_t /* reserved */ : 2; | |
1214 | /* SOF Offset Config */ | |
1215 | uint32_t sofOffset:24; | |
1216 | uint32_t /* reserved */ : 8; | |
1217 | /* EOF NOffset Config */ | |
1218 | uint32_t eofNOffset:24; | |
1219 | uint32_t /* reserved */ : 8; | |
1220 | /* SOL Offset Config */ | |
1221 | uint32_t solOffset:9; | |
1222 | uint32_t /* reserved */ : 23; | |
1223 | /* EOL NOffset Config */ | |
1224 | uint32_t eolNOffset:9; | |
1225 | uint32_t /* reserved */ : 23; | |
1226 | /* HBI Config */ | |
1227 | uint32_t hBlankInterval:14; | |
1228 | uint32_t /* reserved */ : 18; | |
1229 | /* VBL Config */ | |
1230 | uint32_t vBlankInterval:14; | |
1231 | uint32_t /* reserved */ : 2; | |
1232 | uint32_t vBlankIntervalEnable:1; | |
1233 | uint32_t /* reserved */ : 15; | |
1234 | /* SOF Dummy Line Config */ | |
1235 | uint32_t sofDummy:8; | |
1236 | uint32_t /* reserved */ : 24; | |
1237 | /* EOF Dummy Line Config */ | |
1238 | uint32_t eofDummy:8; | |
1239 | uint32_t /* reserved */ : 24; | |
1240 | /* Color Bars Config */ | |
1241 | uint32_t unicolorBarSelect:3; | |
1242 | uint32_t /* reserved */ : 1; | |
1243 | uint32_t unicolorBarEnable:1; | |
1244 | uint32_t splitEnable:1; | |
1245 | uint32_t pixelPattern:2; | |
1246 | uint32_t rotatePeriod:6; | |
1247 | uint32_t /* reserved */ : 18; | |
1248 | /* Random Config */ | |
1249 | uint32_t randomSeed:16; | |
1250 | uint32_t /* reserved */ : 16; | |
1251 | } __attribute__((packed, aligned(4))); | |
1252 | ||
1253 | struct VFE_Bus_Pm_ConfigCmdType { | |
1254 | /* VFE Bus Performance Monitor Config */ | |
1255 | uint32_t output2YWrPmEnable:1; | |
1256 | uint32_t output2CbcrWrPmEnable:1; | |
1257 | uint32_t output1YWrPmEnable:1; | |
1258 | uint32_t output1CbcrWrPmEnable:1; | |
1259 | uint32_t /* reserved */ : 28; | |
1260 | } __attribute__((packed, aligned(4))); | |
1261 | ||
1262 | struct vfe_asf_info { | |
1263 | /* asf max edge */ | |
1264 | uint32_t maxEdge:13; | |
1265 | uint32_t /* reserved */ : 3; | |
1266 | /* HBi count */ | |
1267 | uint32_t HBICount:12; | |
1268 | uint32_t /* reserved */ : 4; | |
1269 | } __attribute__((packed, aligned(4))); | |
1270 | ||
1271 | struct vfe_camif_stats { | |
1272 | uint32_t pixelCount:14; | |
1273 | uint32_t /* reserved */ : 2; | |
1274 | uint32_t lineCount:14; | |
1275 | uint32_t /* reserved */ : 1; | |
1276 | uint32_t camifHalt:1; | |
1277 | } __attribute__((packed, aligned(4))); | |
1278 | ||
1279 | struct VFE_StatsCmdType { | |
1280 | uint32_t autoFocusEnable:1; | |
1281 | uint32_t axwEnable:1; | |
1282 | uint32_t histEnable:1; | |
1283 | uint32_t clearHistEnable:1; | |
1284 | uint32_t histAutoClearEnable:1; | |
1285 | uint32_t colorConversionEnable:1; | |
1286 | uint32_t /* reserved */ : 26; | |
1287 | } __attribute__((packed, aligned(4))); | |
1288 | ||
1289 | ||
1290 | struct vfe_statsframe { | |
1291 | uint32_t lastPixel:12; | |
1292 | uint32_t /* reserved */ : 4; | |
1293 | uint32_t lastLine:12; | |
1294 | uint32_t /* reserved */ : 4; | |
1295 | } __attribute__((packed, aligned(4))); | |
1296 | ||
1297 | struct vfe_busstats_wrprio { | |
1298 | uint32_t afBusPriority:4; | |
1299 | uint32_t awbBusPriority:4; | |
1300 | uint32_t histBusPriority:4; | |
1301 | uint32_t afBusPriorityEn:1; | |
1302 | uint32_t awbBusPriorityEn:1; | |
1303 | uint32_t histBusPriorityEn:1; | |
1304 | uint32_t /* reserved */ : 17; | |
1305 | } __attribute__((packed, aligned(4))); | |
1306 | ||
1307 | struct vfe_statsaf_update { | |
1308 | /* VFE_STATS_AF_CFG */ | |
1309 | uint32_t windowVOffset:12; | |
1310 | uint32_t /* reserved */ : 4; | |
1311 | uint32_t windowHOffset:12; | |
1312 | uint32_t /* reserved */ : 3; | |
1313 | uint32_t windowMode:1; | |
1314 | ||
1315 | /* VFE_STATS_AF_DIM */ | |
1316 | uint32_t windowHeight:12; | |
1317 | uint32_t /* reserved */ : 4; | |
1318 | uint32_t windowWidth:12; | |
1319 | uint32_t /* reserved */ : 4; | |
1320 | } __attribute__((packed, aligned(4))); | |
1321 | ||
1322 | struct vfe_statsaf_cfg { | |
1323 | /* VFE_STATS_AF_GRID_0 */ | |
1324 | uint32_t entry00:8; | |
1325 | uint32_t entry01:8; | |
1326 | uint32_t entry02:8; | |
1327 | uint32_t entry03:8; | |
1328 | ||
1329 | /* VFE_STATS_AF_GRID_1 */ | |
1330 | uint32_t entry10:8; | |
1331 | uint32_t entry11:8; | |
1332 | uint32_t entry12:8; | |
1333 | uint32_t entry13:8; | |
1334 | ||
1335 | /* VFE_STATS_AF_GRID_2 */ | |
1336 | uint32_t entry20:8; | |
1337 | uint32_t entry21:8; | |
1338 | uint32_t entry22:8; | |
1339 | uint32_t entry23:8; | |
1340 | ||
1341 | /* VFE_STATS_AF_GRID_3 */ | |
1342 | uint32_t entry30:8; | |
1343 | uint32_t entry31:8; | |
1344 | uint32_t entry32:8; | |
1345 | uint32_t entry33:8; | |
1346 | ||
1347 | /* VFE_STATS_AF_HEADER */ | |
1348 | uint32_t afHeader:8; | |
1349 | uint32_t /* reserved */ : 24; | |
1350 | /* VFE_STATS_AF_COEF0 */ | |
1351 | uint32_t a00:5; | |
1352 | uint32_t a04:5; | |
1353 | uint32_t fvMax:11; | |
1354 | uint32_t fvMetric:1; | |
1355 | uint32_t /* reserved */ : 10; | |
1356 | ||
1357 | /* VFE_STATS_AF_COEF1 */ | |
1358 | uint32_t a20:5; | |
1359 | uint32_t a21:5; | |
1360 | uint32_t a22:5; | |
1361 | uint32_t a23:5; | |
1362 | uint32_t a24:5; | |
1363 | uint32_t /* reserved */ : 7; | |
1364 | } __attribute__((packed, aligned(4))); | |
1365 | ||
1366 | struct vfe_statsawbae_update { | |
1367 | uint32_t aeRegionCfg:1; | |
1368 | uint32_t aeSubregionCfg:1; | |
1369 | uint32_t /* reserved */ : 14; | |
1370 | uint32_t awbYMin:8; | |
1371 | uint32_t awbYMax:8; | |
1372 | } __attribute__((packed, aligned(4))); | |
1373 | ||
1374 | struct vfe_statsaxw_hdr_cfg { | |
1375 | /* Stats AXW Header Config */ | |
1376 | uint32_t axwHeader:8; | |
1377 | uint32_t /* reserved */ : 24; | |
1378 | } __attribute__((packed, aligned(4))); | |
1379 | ||
1380 | struct vfe_statsawb_update { | |
1381 | /* AWB MConfig */ | |
1382 | uint32_t m4:8; | |
1383 | uint32_t m3:8; | |
1384 | uint32_t m2:8; | |
1385 | uint32_t m1:8; | |
1386 | ||
1387 | /* AWB CConfig1 */ | |
1388 | uint32_t c2:12; | |
1389 | uint32_t /* reserved */ : 4; | |
1390 | uint32_t c1:12; | |
1391 | uint32_t /* reserved */ : 4; | |
1392 | ||
1393 | /* AWB CConfig2 */ | |
1394 | uint32_t c4:12; | |
1395 | uint32_t /* reserved */ : 4; | |
1396 | uint32_t c3:12; | |
1397 | uint32_t /* reserved */ : 4; | |
1398 | } __attribute__((packed, aligned(4))); | |
1399 | ||
1400 | struct VFE_SyncTimerCmdType { | |
1401 | uint32_t hsyncCount:12; | |
1402 | uint32_t /* reserved */ : 20; | |
1403 | uint32_t pclkCount:18; | |
1404 | uint32_t /* reserved */ : 14; | |
1405 | uint32_t outputDuration:28; | |
1406 | uint32_t /* reserved */ : 4; | |
1407 | } __attribute__((packed, aligned(4))); | |
1408 | ||
1409 | struct VFE_AsyncTimerCmdType { | |
1410 | /* config 0 */ | |
1411 | uint32_t inactiveCount:20; | |
1412 | uint32_t repeatCount:10; | |
1413 | uint32_t /* reserved */ : 1; | |
1414 | uint32_t polarity:1; | |
1415 | /* config 1 */ | |
1416 | uint32_t activeCount:20; | |
1417 | uint32_t /* reserved */ : 12; | |
1418 | } __attribute__((packed, aligned(4))); | |
1419 | ||
1420 | struct VFE_AxiInputCmdType { | |
1421 | uint32_t stripeStartAddr0:32; | |
1422 | uint32_t stripeStartAddr1:32; | |
1423 | uint32_t stripeStartAddr2:32; | |
1424 | uint32_t stripeStartAddr3:32; | |
1425 | ||
1426 | uint32_t ySize:12; | |
1427 | uint32_t yOffsetDelta:12; | |
1428 | uint32_t /* reserved */ : 8; | |
1429 | ||
1430 | /* bus_stripe_rd_hSize */ | |
1431 | uint32_t /* reserved */ : 16; | |
1432 | uint32_t xSizeWord:10; | |
1433 | uint32_t /* reserved */ : 6; | |
1434 | ||
1435 | /* bus_stripe_rd_buffer_cfg */ | |
1436 | uint32_t burstLength:2; | |
1437 | uint32_t /* reserved */ : 2; | |
1438 | uint32_t NumOfRows:12; | |
1439 | uint32_t RowIncrement:12; | |
1440 | uint32_t /* reserved */ : 4; | |
1441 | ||
1442 | /* bus_stripe_rd_unpack_cfg */ | |
1443 | uint32_t mainUnpackHeight:12; | |
1444 | uint32_t mainUnpackWidth:13; | |
1445 | uint32_t mainUnpackHbiSel:3; | |
1446 | uint32_t mainUnpackPhase:3; | |
1447 | uint32_t /* reserved */ : 1; | |
1448 | ||
1449 | /* bus_stripe_rd_unpack */ | |
1450 | uint32_t unpackPattern:32; | |
1451 | ||
1452 | /* bus_stripe_rd_pad_size */ | |
1453 | uint32_t padLeft:7; | |
1454 | uint32_t /* reserved */ : 1; | |
1455 | uint32_t padRight:7; | |
1456 | uint32_t /* reserved */ : 1; | |
1457 | uint32_t padTop:7; | |
1458 | uint32_t /* reserved */ : 1; | |
1459 | uint32_t padBottom:7; | |
1460 | uint32_t /* reserved */ : 1; | |
1461 | ||
1462 | /* bus_stripe_rd_pad_L_unpack */ | |
1463 | uint32_t leftUnpackPattern0:4; | |
1464 | uint32_t leftUnpackPattern1:4; | |
1465 | uint32_t leftUnpackPattern2:4; | |
1466 | uint32_t leftUnpackPattern3:4; | |
1467 | uint32_t leftUnpackStop0:1; | |
1468 | uint32_t leftUnpackStop1:1; | |
1469 | uint32_t leftUnpackStop2:1; | |
1470 | uint32_t leftUnpackStop3:1; | |
1471 | uint32_t /* reserved */ : 12; | |
1472 | ||
1473 | /* bus_stripe_rd_pad_R_unpack */ | |
1474 | uint32_t rightUnpackPattern0:4; | |
1475 | uint32_t rightUnpackPattern1:4; | |
1476 | uint32_t rightUnpackPattern2:4; | |
1477 | uint32_t rightUnpackPattern3:4; | |
1478 | uint32_t rightUnpackStop0:1; | |
1479 | uint32_t rightUnpackStop1:1; | |
1480 | uint32_t rightUnpackStop2:1; | |
1481 | uint32_t rightUnpackStop3:1; | |
1482 | uint32_t /* reserved */ : 12; | |
1483 | ||
1484 | /* bus_stripe_rd_pad_tb_unpack */ | |
1485 | uint32_t topUnapckPattern:4; | |
1486 | uint32_t /* reserved */ : 12; | |
1487 | uint32_t bottomUnapckPattern:4; | |
1488 | uint32_t /* reserved */ : 12; | |
1489 | } __attribute__((packed, aligned(4))); | |
1490 | ||
1491 | struct VFE_AxiRdFragIrqEnable { | |
1492 | uint32_t stripeRdFragirq0Enable:1; | |
1493 | uint32_t stripeRdFragirq1Enable:1; | |
1494 | uint32_t stripeRdFragirq2Enable:1; | |
1495 | uint32_t stripeRdFragirq3Enable:1; | |
1496 | uint32_t /* reserved */ : 28; | |
1497 | } __attribute__((packed, aligned(4))); | |
1498 | ||
1499 | int vfe_cmd_init(struct msm_vfe_callback *, struct platform_device *, void *); | |
1500 | void vfe_stats_af_stop(void); | |
1501 | void vfe_stop(void); | |
1502 | void vfe_update(void); | |
1503 | int vfe_rgb_gamma_update(struct vfe_cmd_rgb_gamma_config *); | |
1504 | int vfe_rgb_gamma_config(struct vfe_cmd_rgb_gamma_config *); | |
1505 | void vfe_stats_wb_exp_ack(struct vfe_cmd_stats_wb_exp_ack *); | |
1506 | void vfe_stats_af_ack(struct vfe_cmd_stats_af_ack *); | |
1507 | void vfe_start(struct vfe_cmd_start *); | |
1508 | void vfe_la_update(struct vfe_cmd_la_config *); | |
1509 | void vfe_la_config(struct vfe_cmd_la_config *); | |
1510 | void vfe_test_gen_start(struct vfe_cmd_test_gen_start *); | |
1511 | void vfe_frame_skip_update(struct vfe_cmd_frame_skip_update *); | |
1512 | void vfe_frame_skip_config(struct vfe_cmd_frame_skip_config *); | |
1513 | void vfe_output_clamp_config(struct vfe_cmd_output_clamp_config *); | |
1514 | void vfe_camif_frame_update(struct vfe_cmds_camif_frame *); | |
1515 | void vfe_color_correction_config(struct vfe_cmd_color_correction_config *); | |
1516 | void vfe_demosaic_abf_update(struct vfe_cmd_demosaic_abf_update *); | |
1517 | void vfe_demosaic_bpc_update(struct vfe_cmd_demosaic_bpc_update *); | |
1518 | void vfe_demosaic_config(struct vfe_cmd_demosaic_config *); | |
1519 | void vfe_demux_channel_gain_update(struct vfe_cmd_demux_channel_gain_config *); | |
1520 | void vfe_demux_channel_gain_config(struct vfe_cmd_demux_channel_gain_config *); | |
1521 | void vfe_black_level_update(struct vfe_cmd_black_level_config *); | |
1522 | void vfe_black_level_config(struct vfe_cmd_black_level_config *); | |
1523 | void vfe_asf_update(struct vfe_cmd_asf_update *); | |
1524 | void vfe_asf_config(struct vfe_cmd_asf_config *); | |
1525 | void vfe_white_balance_config(struct vfe_cmd_white_balance_config *); | |
1526 | void vfe_chroma_sup_config(struct vfe_cmd_chroma_suppression_config *); | |
1527 | void vfe_roll_off_config(struct vfe_cmd_roll_off_config *); | |
1528 | void vfe_chroma_subsample_config(struct vfe_cmd_chroma_subsample_config *); | |
1529 | void vfe_chroma_enhan_config(struct vfe_cmd_chroma_enhan_config *); | |
1530 | void vfe_scaler2cbcr_config(struct vfe_cmd_scaler2_config *); | |
1531 | void vfe_scaler2y_config(struct vfe_cmd_scaler2_config *); | |
1532 | void vfe_main_scaler_config(struct vfe_cmd_main_scaler_config *); | |
1533 | void vfe_stats_wb_exp_stop(void); | |
1534 | void vfe_stats_update_wb_exp(struct vfe_cmd_stats_wb_exp_update *); | |
1535 | void vfe_stats_update_af(struct vfe_cmd_stats_af_update *); | |
1536 | void vfe_stats_start_wb_exp(struct vfe_cmd_stats_wb_exp_start *); | |
1537 | void vfe_stats_start_af(struct vfe_cmd_stats_af_start *); | |
1538 | void vfe_stats_setting(struct vfe_cmd_stats_setting *); | |
1539 | void vfe_axi_input_config(struct vfe_cmd_axi_input_config *); | |
1540 | void vfe_stats_config(struct vfe_cmd_stats_setting *); | |
1541 | void vfe_axi_output_config(struct vfe_cmd_axi_output_config *); | |
1542 | void vfe_camif_config(struct vfe_cmd_camif_config *); | |
1543 | void vfe_fov_crop_config(struct vfe_cmd_fov_crop_config *); | |
1544 | void vfe_get_hw_version(struct vfe_cmd_hw_version *); | |
1545 | void vfe_reset(void); | |
1546 | void vfe_cmd_release(struct platform_device *); | |
1547 | void vfe_output1_ack(struct vfe_cmd_output_ack *); | |
1548 | void vfe_output2_ack(struct vfe_cmd_output_ack *); | |
1549 | #endif /* __MSM_VFE8X_REG_H__ */ |