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[net-next-2.6.git] / drivers / staging / brcm80211 / phy / wlc_phy_int.h
CommitLineData
a9533e7e
HP		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _wlc_phy_int_h_
18#define _wlc_phy_int_h_
19
20#include <typedefs.h>
21#include <bcmutils.h>
22
23#include <bcmsrom_fmt.h>
24#include <wlc_phy_hal.h>
25
26#define PHYHAL_ERROR 0x0001
27#define PHYHAL_TRACE 0x0002
28#define PHYHAL_INFORM 0x0004
29
30extern uint32 phyhal_msg_level;
31
32#define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM)
33#define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL)
34#define PHY_CAL_ON() (phyhal_msg_level & PHYHAL_CAL)
35
36#ifdef BOARD_TYPE
37#define BOARDTYPE(_type) BOARD_TYPE
38#else
39#define BOARDTYPE(_type) _type
40#endif
41
42#define LCNXN_BASEREV 16
43
44struct wlc_hw_info;
45typedef struct phy_info phy_info_t;
46typedef void (*initfn_t) (phy_info_t *);
47typedef void (*chansetfn_t) (phy_info_t *, chanspec_t);
48typedef int (*longtrnfn_t) (phy_info_t *, int);
7d4df48e
GKH		 49typedef void (*txiqccgetfn_t) (phy_info_t *, u16 *, u16 *);
50typedef void (*txiqccsetfn_t) (phy_info_t *, u16, u16);
51typedef u16(*txloccgetfn_t) (phy_info_t *);
e868ab03
GKH		 52typedef void (*radioloftgetfn_t) (phy_info_t *, u8 *, u8 *, u8 *,
53 u8 *);
a9533e7e
HP		 54typedef int32(*rxsigpwrfn_t) (phy_info_t *, int32);
55typedef void (*detachfn_t) (phy_info_t *);
56
57#undef ISNPHY
58#undef ISLCNPHY
59#define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
60#define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
61
62#define ISPHY_11N_CAP(pi) (ISNPHY(pi) || ISLCNPHY(pi))
63
64#define IS20MHZ(pi) ((pi)->bw == WL_CHANSPEC_BW_20)
65#define IS40MHZ(pi) ((pi)->bw == WL_CHANSPEC_BW_40)
66
67#define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f)
68#define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4)
69#define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
70#define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
71 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
72#define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
73#define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0)))
74
75#define CH_5G_GROUP 3
76#define A_LOW_CHANS 0
77#define A_MID_CHANS 1
78#define A_HIGH_CHANS 2
79#define CH_2G_GROUP 1
80#define G_ALL_CHANS 0
81
82#define FIRST_REF5_CHANNUM 149
83#define LAST_REF5_CHANNUM 165
84#define FIRST_5G_CHAN 14
85#define LAST_5G_CHAN 50
86#define FIRST_MID_5G_CHAN 14
87#define LAST_MID_5G_CHAN 35
88#define FIRST_HIGH_5G_CHAN 36
89#define LAST_HIGH_5G_CHAN 41
90#define FIRST_LOW_5G_CHAN 42
91#define LAST_LOW_5G_CHAN 50
92
93#define BASE_LOW_5G_CHAN 4900
94#define BASE_MID_5G_CHAN 5100
95#define BASE_HIGH_5G_CHAN 5500
96
97#define CHAN5G_FREQ(chan) (5000 + chan*5)
98#define CHAN2G_FREQ(chan) (2407 + chan*5)
99
100#define TXP_FIRST_CCK 0
101#define TXP_LAST_CCK 3
102#define TXP_FIRST_OFDM 4
103#define TXP_LAST_OFDM 11
104#define TXP_FIRST_OFDM_20_CDD 12
105#define TXP_LAST_OFDM_20_CDD 19
106#define TXP_FIRST_MCS_20_SISO 20
107#define TXP_LAST_MCS_20_SISO 27
108#define TXP_FIRST_MCS_20_CDD 28
109#define TXP_LAST_MCS_20_CDD 35
110#define TXP_FIRST_MCS_20_STBC 36
111#define TXP_LAST_MCS_20_STBC 43
112#define TXP_FIRST_MCS_20_SDM 44
113#define TXP_LAST_MCS_20_SDM 51
114#define TXP_FIRST_OFDM_40_SISO 52
115#define TXP_LAST_OFDM_40_SISO 59
116#define TXP_FIRST_OFDM_40_CDD 60
117#define TXP_LAST_OFDM_40_CDD 67
118#define TXP_FIRST_MCS_40_SISO 68
119#define TXP_LAST_MCS_40_SISO 75
120#define TXP_FIRST_MCS_40_CDD 76
121#define TXP_LAST_MCS_40_CDD 83
122#define TXP_FIRST_MCS_40_STBC 84
123#define TXP_LAST_MCS_40_STBC 91
124#define TXP_FIRST_MCS_40_SDM 92
125#define TXP_LAST_MCS_40_SDM 99
126#define TXP_MCS_32 100
127#define TXP_NUM_RATES 101
128#define ADJ_PWR_TBL_LEN 84
129
130#define TXP_FIRST_SISO_MCS_20 20
131#define TXP_LAST_SISO_MCS_20 27
132
133#define PHY_CORE_NUM_1 1
134#define PHY_CORE_NUM_2 2
135#define PHY_CORE_NUM_3 3
136#define PHY_CORE_NUM_4 4
137#define PHY_CORE_MAX PHY_CORE_NUM_4
138#define PHY_CORE_0 0
139#define PHY_CORE_1 1
140#define PHY_CORE_2 2
141#define PHY_CORE_3 3
142
143#define MA_WINDOW_SZ 8
144
145#define PHY_NOISE_SAMPLE_MON 1
146#define PHY_NOISE_SAMPLE_EXTERNAL 2
147#define PHY_NOISE_WINDOW_SZ 16
148#define PHY_NOISE_GLITCH_INIT_MA 10
149#define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
150#define PHY_NOISE_STATE_MON 0x1
151#define PHY_NOISE_STATE_EXTERNAL 0x2
152#define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10
153#define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9
154
155#define PHY_NOISE_OFFSETFACT_4322 (-103)
156#define PHY_NOISE_MA_WINDOW_SZ 2
157
158#define PHY_RSSI_TABLE_SIZE 64
159#define RSSI_ANT_MERGE_MAX 0
160#define RSSI_ANT_MERGE_MIN 1
161#define RSSI_ANT_MERGE_AVG 2
162
163#define PHY_TSSI_TABLE_SIZE 64
164#define APHY_TSSI_TABLE_SIZE 256
165#define TX_GAIN_TABLE_LENGTH 64
166#define DEFAULT_11A_TXP_IDX 24
167#define NUM_TSSI_FRAMES 4
168#define NULL_TSSI 0x7f
169#define NULL_TSSI_W 0x7f7f
170
171#define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
172
173#define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
174
175#define PHY_TXPWR_MIN 10
176#define PHY_TXPWR_MIN_NPHY 8
177#define RADIOPWR_OVERRIDE_DEF (-1)
178
179#define PWRTBL_NUM_COEFF 3
180
181#define SPURAVOID_DISABLE 0
182#define SPURAVOID_AUTO 1
183#define SPURAVOID_FORCEON 2
184#define SPURAVOID_FORCEON2 3
185
186#define PHY_SW_TIMER_FAST 15
187#define PHY_SW_TIMER_SLOW 60
188#define PHY_SW_TIMER_GLACIAL 120
189
190#define PHY_PERICAL_AUTO 0
191#define PHY_PERICAL_FULL 1
192#define PHY_PERICAL_PARTIAL 2
193
194#define PHY_PERICAL_NODELAY 0
195#define PHY_PERICAL_INIT_DELAY 5
196#define PHY_PERICAL_ASSOC_DELAY 5
197#define PHY_PERICAL_WDOG_DELAY 5
198
199#define MPHASE_TXCAL_NUMCMDS 2
200#define PHY_PERICAL_MPHASE_PENDING(pi) (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
201
202enum {
203 MPHASE_CAL_STATE_IDLE = 0,
204 MPHASE_CAL_STATE_INIT = 1,
205 MPHASE_CAL_STATE_TXPHASE0,
206 MPHASE_CAL_STATE_TXPHASE1,
207 MPHASE_CAL_STATE_TXPHASE2,
208 MPHASE_CAL_STATE_TXPHASE3,
209 MPHASE_CAL_STATE_TXPHASE4,
210 MPHASE_CAL_STATE_TXPHASE5,
211 MPHASE_CAL_STATE_PAPDCAL,
212 MPHASE_CAL_STATE_RXCAL,
213 MPHASE_CAL_STATE_RSSICAL,
214 MPHASE_CAL_STATE_IDLETSSI
215};
216
217typedef enum {
218 CAL_FULL,
219 CAL_RECAL,
220 CAL_CURRECAL,
221 CAL_DIGCAL,
222 CAL_GCTRL,
223 CAL_SOFT,
224 CAL_DIGLO
225} phy_cal_mode_t;
226
227#define RDR_NTIERS 1
228#define RDR_TIER_SIZE 64
0d706ef4 229#define RDR_LIST_SIZE (512/3)
a9533e7e
HP		 230#define RDR_EPOCH_SIZE 40
231#define RDR_NANTENNAS 2
232#define RDR_NTIER_SIZE RDR_LIST_SIZE
233#define RDR_LP_BUFFER_SIZE 64
234#define LP_LEN_HIS_SIZE 10
235
236#define STATIC_NUM_RF 32
237#define STATIC_NUM_BB 9
238
239#define BB_MULT_MASK 0x0000ffff
240#define BB_MULT_VALID_MASK 0x80000000
241
242#define CORDIC_AG 39797
243#define CORDIC_NI 18
244#define FIXED(X) ((int32)((X) << 16))
245#define FLOAT(X) (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
246
247#define PHY_CHAIN_TX_DISABLE_TEMP 115
248#define PHY_HYSTERESIS_DELTATEMP 5
249
e868ab03 250#define PHY_BITSCNT(x) bcm_bitcount((u8 *)&(x), sizeof(u8))
a9533e7e
HP		 251
252#define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
253 mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
254 (value) << phy_type##_##reg_name##_##field##_##SHIFT);
255#define READ_PHY_REG(pi, phy_type, reg_name, field) \
256 ((read_phy_reg(pi, phy_type##_##reg_name) & phy_type##_##reg_name##_##field##_##MASK)\
257 >> phy_type##_##reg_name##_##field##_##SHIFT)
258
259#define VALID_PHYTYPE(phytype) (((uint)phytype == PHY_TYPE_N) || \
260 ((uint)phytype == PHY_TYPE_LCN))
261
262#define VALID_N_RADIO(radioid) ((radioid == BCM2055_ID) || (radioid == BCM2056_ID) || \
263 (radioid == BCM2057_ID))
264#define VALID_LCN_RADIO(radioid) (radioid == BCM2064_ID)
265
266#define VALID_RADIO(pi, radioid) (\
267 (ISNPHY(pi) ? VALID_N_RADIO(radioid) : FALSE) || \
268 (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : FALSE))
269
270#define SCAN_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
271#define RM_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_RM))
272#define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
273#define ASSOC_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
274#define SCAN_RM_IN_PROGRESS(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
275#define PHY_MUTED(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
276#define PUB_NOT_ASSOC(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
277
278#if defined(EXT_CBALL)
279#define NORADIO_ENAB(pub) ((pub).radioid == NORADIO_ID)
280#else
281#define NORADIO_ENAB(pub) 0
282#endif
283
284#define PHY_LTRN_LIST_LEN 64
7d4df48e 285extern u16 ltrn_list[PHY_LTRN_LIST_LEN];
a9533e7e
HP		 286
287typedef struct _phy_table_info {
288 uint table;
289 int q;
290 uint max;
291} phy_table_info_t;
292
293typedef struct phytbl_info {
294 const void *tbl_ptr;
295 uint32 tbl_len;
296 uint32 tbl_id;
297 uint32 tbl_offset;
298 uint32 tbl_width;
299} phytbl_info_t;
300
301typedef struct {
e868ab03 302 u8 curr_home_channel;
7d4df48e
GKH		 303 u16 crsminpwrthld_40_stored;
304 u16 crsminpwrthld_20L_stored;
305 u16 crsminpwrthld_20U_stored;
306 u16 init_gain_code_core1_stored;
307 u16 init_gain_code_core2_stored;
308 u16 init_gain_codeb_core1_stored;
309 u16 init_gain_codeb_core2_stored;
310 u16 init_gain_table_stored[4];
311
312 u16 clip1_hi_gain_code_core1_stored;
313 u16 clip1_hi_gain_code_core2_stored;
314 u16 clip1_hi_gain_codeb_core1_stored;
315 u16 clip1_hi_gain_codeb_core2_stored;
316 u16 nb_clip_thresh_core1_stored;
317 u16 nb_clip_thresh_core2_stored;
318 u16 init_ofdmlna2gainchange_stored[4];
319 u16 init_ccklna2gainchange_stored[4];
320 u16 clip1_lo_gain_code_core1_stored;
321 u16 clip1_lo_gain_code_core2_stored;
322 u16 clip1_lo_gain_codeb_core1_stored;
323 u16 clip1_lo_gain_codeb_core2_stored;
324 u16 w1_clip_thresh_core1_stored;
325 u16 w1_clip_thresh_core2_stored;
326 u16 radio_2056_core1_rssi_gain_stored;
327 u16 radio_2056_core2_rssi_gain_stored;
328 u16 energy_drop_timeout_len_stored;
329
330 u16 ed_crs40_assertthld0_stored;
331 u16 ed_crs40_assertthld1_stored;
332 u16 ed_crs40_deassertthld0_stored;
333 u16 ed_crs40_deassertthld1_stored;
334 u16 ed_crs20L_assertthld0_stored;
335 u16 ed_crs20L_assertthld1_stored;
336 u16 ed_crs20L_deassertthld0_stored;
337 u16 ed_crs20L_deassertthld1_stored;
338 u16 ed_crs20U_assertthld0_stored;
339 u16 ed_crs20U_assertthld1_stored;
340 u16 ed_crs20U_deassertthld0_stored;
341 u16 ed_crs20U_deassertthld1_stored;
342
343 u16 badplcp_ma;
344 u16 badplcp_ma_previous;
345 u16 badplcp_ma_total;
346 u16 badplcp_ma_list[MA_WINDOW_SZ];
a9533e7e
HP		 347 int badplcp_ma_index;
348 int16 pre_badplcp_cnt;
349 int16 bphy_pre_badplcp_cnt;
350
7d4df48e
GKH		 351 u16 init_gain_core1;
352 u16 init_gain_core2;
353 u16 init_gainb_core1;
354 u16 init_gainb_core2;
355 u16 init_gain_rfseq[4];
a9533e7e 356
7d4df48e
GKH		 357 u16 crsminpwr0;
358 u16 crsminpwrl0;
359 u16 crsminpwru0;
a9533e7e
HP		 360
361 int16 crsminpwr_index;
362
7d4df48e
GKH		 363 u16 radio_2057_core1_rssi_wb1a_gc_stored;
364 u16 radio_2057_core2_rssi_wb1a_gc_stored;
365 u16 radio_2057_core1_rssi_wb1g_gc_stored;
366 u16 radio_2057_core2_rssi_wb1g_gc_stored;
367 u16 radio_2057_core1_rssi_wb2_gc_stored;
368 u16 radio_2057_core2_rssi_wb2_gc_stored;
369 u16 radio_2057_core1_rssi_nb_gc_stored;
370 u16 radio_2057_core2_rssi_nb_gc_stored;
a9533e7e
HP		 371
372} interference_info_t;
373
374typedef struct {
7d4df48e
GKH		 375 u16 rc_cal_ovr;
376 u16 phycrsth1;
377 u16 phycrsth2;
378 u16 init_n1p1_gain;
379 u16 p1_p2_gain;
380 u16 n1_n2_gain;
381 u16 n1_p1_gain;
382 u16 div_search_gain;
383 u16 div_p1_p2_gain;
384 u16 div_search_gn_change;
385 u16 table_7_2;
386 u16 table_7_3;
387 u16 cckshbits_gnref;
388 u16 clip_thresh;
389 u16 clip2_thresh;
390 u16 clip3_thresh;
391 u16 clip_p2_thresh;
392 u16 clip_pwdn_thresh;
393 u16 clip_n1p1_thresh;
394 u16 clip_n1_pwdn_thresh;
395 u16 bbconfig;
396 u16 cthr_sthr_shdin;
397 u16 energy;
398 u16 clip_p1_p2_thresh;
399 u16 threshold;
400 u16 reg15;
401 u16 reg16;
402 u16 reg17;
403 u16 div_srch_idx;
404 u16 div_srch_p1_p2;
405 u16 div_srch_gn_back;
406 u16 ant_dwell;
407 u16 ant_wr_settle;
a9533e7e
HP		 408} aci_save_gphy_t;
409
410typedef struct _lo_complex_t {
562c8850
GKH		 411 s8 i;
412 s8 q;
a9533e7e
HP		 413} lo_complex_abgphy_info_t;
414
415typedef struct _nphy_iq_comp {
416 int16 a0;
417 int16 b0;
418 int16 a1;
419 int16 b1;
420} nphy_iq_comp_t;
421
422typedef struct _nphy_txpwrindex {
562c8850
GKH		 423 s8 index;
424 s8 index_internal;
425 s8 index_internal_save;
7d4df48e
GKH		 426 u16 AfectrlOverride;
427 u16 AfeCtrlDacGain;
428 u16 rad_gain;
e868ab03 429 u8 bbmult;
7d4df48e
GKH		 430 u16 iqcomp_a;
431 u16 iqcomp_b;
432 u16 locomp;
a9533e7e
HP		 433} phy_txpwrindex_t;
434
435typedef struct {
436
7d4df48e
GKH		 437 u16 txcal_coeffs_2G[8];
438 u16 txcal_radio_regs_2G[8];
a9533e7e
HP		 439 nphy_iq_comp_t rxcal_coeffs_2G;
440
7d4df48e
GKH		 441 u16 txcal_coeffs_5G[8];
442 u16 txcal_radio_regs_5G[8];
a9533e7e
HP		 443 nphy_iq_comp_t rxcal_coeffs_5G;
444} txiqcal_cache_t;
445
446typedef struct _nphy_pwrctrl {
562c8850
GKH		 447 s8 max_pwr_2g;
448 s8 idle_targ_2g;
a9533e7e
HP		 449 int16 pwrdet_2g_a1;
450 int16 pwrdet_2g_b0;
451 int16 pwrdet_2g_b1;
562c8850
GKH		 452 s8 max_pwr_5gm;
453 s8 idle_targ_5gm;
454 s8 max_pwr_5gh;
455 s8 max_pwr_5gl;
a9533e7e
HP		 456 int16 pwrdet_5gm_a1;
457 int16 pwrdet_5gm_b0;
458 int16 pwrdet_5gm_b1;
459 int16 pwrdet_5gl_a1;
460 int16 pwrdet_5gl_b0;
461 int16 pwrdet_5gl_b1;
462 int16 pwrdet_5gh_a1;
463 int16 pwrdet_5gh_b0;
464 int16 pwrdet_5gh_b1;
562c8850
GKH		 465 s8 idle_targ_5gl;
466 s8 idle_targ_5gh;
467 s8 idle_tssi_2g;
468 s8 idle_tssi_5g;
469 s8 idle_tssi;
a9533e7e
HP		 470 int16 a1;
471 int16 b0;
472 int16 b1;
473} phy_pwrctrl_t;
474
475typedef struct _nphy_txgains {
7d4df48e
GKH		 476 u16 txlpf[2];
477 u16 txgm[2];
478 u16 pga[2];
479 u16 pad[2];
480 u16 ipa[2];
a9533e7e
HP		 481} nphy_txgains_t;
482
483#define PHY_NOISEVAR_BUFSIZE 10
484
485typedef struct _nphy_noisevar_buf {
486 int bufcount;
487 int tone_id[PHY_NOISEVAR_BUFSIZE];
488 uint32 noise_vars[PHY_NOISEVAR_BUFSIZE];
489 uint32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
490} phy_noisevar_buf_t;
491
492typedef struct {
7d4df48e
GKH		 493 u16 rssical_radio_regs_2G[2];
494 u16 rssical_phyregs_2G[12];
a9533e7e 495
7d4df48e
GKH		 496 u16 rssical_radio_regs_5G[2];
497 u16 rssical_phyregs_5G[12];
a9533e7e
HP		 498} rssical_cache_t;
499
500typedef struct {
501
7d4df48e
GKH		 502 u16 txiqlocal_a;
503 u16 txiqlocal_b;
504 u16 txiqlocal_didq;
e868ab03
GKH		 505 u8 txiqlocal_ei0;
506 u8 txiqlocal_eq0;
507 u8 txiqlocal_fi0;
508 u8 txiqlocal_fq0;
a9533e7e 509
7d4df48e
GKH		 510 u16 txiqlocal_bestcoeffs[11];
511 u16 txiqlocal_bestcoeffs_valid;
a9533e7e
HP		 512
513 uint32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
7d4df48e
GKH		 514 u16 analog_gain_ref;
515 u16 lut_begin;
516 u16 lut_end;
517 u16 lut_step;
518 u16 rxcompdbm;
519 u16 papdctrl;
520 u16 sslpnCalibClkEnCtrl;
521
522 u16 rxiqcal_coeff_a0;
523 u16 rxiqcal_coeff_b0;
a9533e7e
HP		 524} lcnphy_cal_results_t;
525
526struct shared_phy {
527 struct phy_info *phy_head;
528 uint unit;
529 osl_t *osh;
530 si_t *sih;
531 void *physhim;
532 uint corerev;
533 uint32 machwcap;
534 bool up;
535 bool clk;
536 uint now;
7d4df48e
GKH		 537 u16 vid;
538 u16 did;
a9533e7e
HP		 539 uint chip;
540 uint chiprev;
541 uint chippkg;
542 uint sromrev;
543 uint boardtype;
544 uint boardrev;
545 uint boardvendor;
546 uint32 boardflags;
547 uint32 boardflags2;
548 uint bustype;
549 uint buscorerev;
550 uint fast_timer;
551 uint slow_timer;
552 uint glacial_timer;
e868ab03 553 u8 rx_antdiv;
562c8850 554 s8 phy_noise_window[MA_WINDOW_SZ];
a9533e7e 555 uint phy_noise_index;
e868ab03
GKH		 556 u8 hw_phytxchain;
557 u8 hw_phyrxchain;
558 u8 phytxchain;
559 u8 phyrxchain;
560 u8 rssi_mode;
a9533e7e
HP		 561 bool _rifs_phy;
562};
563
564struct phy_pub {
565 uint phy_type;
566 uint phy_rev;
e868ab03 567 u8 phy_corenum;
7d4df48e 568 u16 radioid;
e868ab03
GKH		 569 u8 radiorev;
570 u8 radiover;
a9533e7e
HP		 571
572 uint coreflags;
573 uint ana_rev;
574 bool abgphy_encore;
575};
576
577struct phy_info_nphy;
578typedef struct phy_info_nphy phy_info_nphy_t;
579
580struct phy_info_lcnphy;
581typedef struct phy_info_lcnphy phy_info_lcnphy_t;
582
583struct phy_func_ptr {
584 initfn_t init;
585 initfn_t calinit;
586 chansetfn_t chanset;
587 initfn_t txpwrrecalc;
588 longtrnfn_t longtrn;
589 txiqccgetfn_t txiqccget;
590 txiqccsetfn_t txiqccset;
591 txloccgetfn_t txloccget;
592 radioloftgetfn_t radioloftget;
593 initfn_t carrsuppr;
594 rxsigpwrfn_t rxsigpwr;
595 detachfn_t detach;
596};
597typedef struct phy_func_ptr phy_func_ptr_t;
598
599struct phy_info {
600 wlc_phy_t pubpi_ro;
601 shared_phy_t *sh;
602 phy_func_ptr_t pi_fptr;
603 void *pi_ptr;
604
605 union {
606 phy_info_lcnphy_t *pi_lcnphy;
607 } u;
608 bool user_txpwr_at_rfport;
609
610 d11regs_t *regs;
611 struct phy_info *next;
612 char *vars;
613 wlc_phy_t pubpi;
614
615 bool do_initcal;
616 bool phytest_on;
617 bool ofdm_rateset_war;
618 bool bf_preempt_4306;
619 chanspec_t radio_chanspec;
e868ab03 620 u8 antsel_type;
7d4df48e 621 u16 bw;
e868ab03 622 u8 txpwr_percent;
a9533e7e
HP		 623 bool phy_init_por;
624
625 bool init_in_progress;
626 bool initialized;
627 bool sbtml_gm;
628 uint refcnt;
629 bool watchdog_override;
e868ab03 630 u8 phynoise_state;
a9533e7e
HP		 631 uint phynoise_now;
632 int phynoise_chan_watchdog;
633 bool phynoise_polling;
634 bool disable_percal;
635 mbool measure_hold;
636
637 int16 txpa_2g[PWRTBL_NUM_COEFF];
638 int16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
639 int16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
640 int16 txpa_5g_low[PWRTBL_NUM_COEFF];
641 int16 txpa_5g_mid[PWRTBL_NUM_COEFF];
642 int16 txpa_5g_hi[PWRTBL_NUM_COEFF];
643
e868ab03
GKH		 644 u8 tx_srom_max_2g;
645 u8 tx_srom_max_5g_low;
646 u8 tx_srom_max_5g_mid;
647 u8 tx_srom_max_5g_hi;
648 u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
649 u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
650 u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
651 u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
652 u8 tx_user_target[TXP_NUM_RATES];
562c8850 653 s8 tx_power_offset[TXP_NUM_RATES];
e868ab03 654 u8 tx_power_target[TXP_NUM_RATES];
a9533e7e
HP		 655
656 srom_fem_t srom_fem2g;
657 srom_fem_t srom_fem5g;
658
e868ab03
GKH		 659 u8 tx_power_max;
660 u8 tx_power_max_rate_ind;
a9533e7e 661 bool hwpwrctrl;
e868ab03 662 u8 nphy_txpwrctrl;
562c8850 663 s8 nphy_txrx_chain;
a9533e7e
HP		 664 bool phy_5g_pwrgain;
665
7d4df48e
GKH		 666 u16 phy_wreg;
667 u16 phy_wreg_limit;
a9533e7e 668
562c8850 669 s8 n_preamble_override;
e868ab03
GKH		 670 u8 antswitch;
671 u8 aa2g, aa5g;
a9533e7e 672
562c8850
GKH		 673 s8 idle_tssi[CH_5G_GROUP];
674 s8 target_idle_tssi;
675 s8 txpwr_est_Pout;
e868ab03
GKH		 676 u8 tx_power_min;
677 u8 txpwr_limit[TXP_NUM_RATES];
678 u8 txpwr_env_limit[TXP_NUM_RATES];
679 u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
a9533e7e
HP		 680
681 bool channel_14_wide_filter;
682
683 bool txpwroverride;
684 bool txpwridx_override_aphy;
685 int16 radiopwr_override;
7d4df48e 686 u16 hwpwr_txcur;
e868ab03 687 u8 saved_txpwr_idx;
a9533e7e
HP		 688
689 bool edcrs_threshold_lock;
690
691 uint32 tr_R_gain_val;
692 uint32 tr_T_gain_val;
693
694 int16 ofdm_analog_filt_bw_override;
695 int16 cck_analog_filt_bw_override;
696 int16 ofdm_rccal_override;
697 int16 cck_rccal_override;
7d4df48e 698 u16 extlna_type;
a9533e7e
HP		 699
700 uint interference_mode_crs_time;
7d4df48e 701 u16 crsglitch_prev;
a9533e7e
HP		 702 bool interference_mode_crs;
703
704 uint32 phy_tx_tone_freq;
705 uint phy_lastcal;
706 bool phy_forcecal;
707 bool phy_fixed_noise;
708 uint32 xtalfreq;
e868ab03 709 u8 pdiv;
562c8850 710 s8 carrier_suppr_disable;
a9533e7e
HP		 711
712 bool phy_bphy_evm;
713 bool phy_bphy_rfcs;
562c8850 714 s8 phy_scraminit;
e868ab03 715 u8 phy_gpiosel;
a9533e7e
HP		 716
717 int16 phy_txcore_disable_temp;
718 int16 phy_txcore_enable_temp;
562c8850 719 s8 phy_tempsense_offset;
a9533e7e
HP		 720 bool phy_txcore_heatedup;
721
7d4df48e
GKH		 722 u16 radiopwr;
723 u16 bb_atten;
724 u16 txctl1;
a9533e7e 725
7d4df48e
GKH		 726 u16 mintxbias;
727 u16 mintxmag;
a9533e7e 728 lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB];
562c8850 729 s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
7d4df48e 730 u16 gain_table[TX_GAIN_TABLE_LENGTH];
a9533e7e
HP		 731 bool loopback_gain;
732 int16 max_lpback_gain_hdB;
733 int16 trsw_rx_gain_hdB;
e868ab03 734 u8 power_vec[8];
a9533e7e 735
7d4df48e 736 u16 rc_cal;
a9533e7e
HP		 737 int nrssi_table_delta;
738 int nrssi_slope_scale;
739 int nrssi_slope_offset;
740 int min_rssi;
741 int max_rssi;
742
562c8850 743 s8 txpwridx;
e868ab03 744 u8 min_txpower;
a9533e7e 745
e868ab03 746 u8 a_band_high_disable;
a9533e7e 747
7d4df48e
GKH		 748 u16 tx_vos;
749 u16 global_tx_bb_dc_bias_loft;
a9533e7e
HP		 750
751 int rf_max;
752 int bb_max;
753 int rf_list_size;
754 int bb_list_size;
7d4df48e
GKH		 755 u16 *rf_attn_list;
756 u16 *bb_attn_list;
757 u16 padmix_mask;
758 u16 padmix_reg;
759 u16 *txmag_list;
a9533e7e
HP		 760 uint txmag_len;
761 bool txmag_enable;
762
562c8850
GKH		 763 s8 *a_tssi_to_dbm;
764 s8 *m_tssi_to_dbm;
765 s8 *l_tssi_to_dbm;
766 s8 *h_tssi_to_dbm;
e868ab03 767 u8 *hwtxpwr;
a9533e7e 768
7d4df48e 769 u16 freqtrack_saved_regs[2];
a9533e7e
HP		 770 int cur_interference_mode;
771 bool hwpwrctrl_capable;
772 bool temppwrctrl_capable;
773
774 uint phycal_nslope;
775 uint phycal_noffset;
776 uint phycal_mlo;
777 uint phycal_txpower;
778
779 bool pkteng_in_progress;
e868ab03 780 u8 phy_aa2g;
a9533e7e
HP		 781
782 bool nphy_tableloaded;
562c8850 783 s8 nphy_rssisel;
a9533e7e 784 uint32 nphy_bb_mult_save;
7d4df48e 785 u16 nphy_txiqlocal_bestc[11];
a9533e7e
HP		 786 bool nphy_txiqlocal_coeffsvalid;
787 phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
788 phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
7d4df48e 789 u16 cck2gpo;
a9533e7e
HP		 790 uint32 ofdm2gpo;
791 uint32 ofdm5gpo;
792 uint32 ofdm5glpo;
793 uint32 ofdm5ghpo;
e868ab03
GKH		 794 u8 bw402gpo;
795 u8 bw405gpo;
796 u8 bw405glpo;
797 u8 bw405ghpo;
798 u8 cdd2gpo;
799 u8 cdd5gpo;
800 u8 cdd5glpo;
801 u8 cdd5ghpo;
802 u8 stbc2gpo;
803 u8 stbc5gpo;
804 u8 stbc5glpo;
805 u8 stbc5ghpo;
806 u8 bwdup2gpo;
807 u8 bwdup5gpo;
808 u8 bwdup5glpo;
809 u8 bwdup5ghpo;
7d4df48e
GKH		 810 u16 mcs2gpo[8];
811 u16 mcs5gpo[8];
812 u16 mcs5glpo[8];
813 u16 mcs5ghpo[8];
a9533e7e
HP		 814 uint32 nphy_rxcalparams;
815
e868ab03 816 u8 phy_spuravoid;
a9533e7e
HP		 817 bool phy_isspuravoid;
818
e868ab03
GKH		 819 u8 phy_pabias;
820 u8 nphy_papd_skip;
821 u8 nphy_tssi_slope;
a9533e7e
HP		 822
823 int16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
e868ab03 824 u8 nphy_noise_index;
a9533e7e 825
e868ab03
GKH		 826 u8 nphy_txpid2g[PHY_CORE_NUM_2];
827 u8 nphy_txpid5g[PHY_CORE_NUM_2];
828 u8 nphy_txpid5gl[PHY_CORE_NUM_2];
829 u8 nphy_txpid5gh[PHY_CORE_NUM_2];
a9533e7e
HP		 830
831 bool nphy_gain_boost;
832 bool nphy_elna_gain_config;
7d4df48e
GKH		 833 u16 old_bphy_test;
834 u16 old_bphy_testcontrol;
a9533e7e
HP		 835
836 bool phyhang_avoid;
837
838 bool rssical_nphy;
e868ab03 839 u8 nphy_perical;
a9533e7e 840 uint nphy_perical_last;
e868ab03
GKH		 841 u8 cal_type_override;
842 u8 mphase_cal_phase_id;
843 u8 mphase_txcal_cmdidx;
844 u8 mphase_txcal_numcmds;
7d4df48e 845 u16 mphase_txcal_bestcoeffs[11];
a9533e7e
HP		 846 chanspec_t nphy_txiqlocal_chanspec;
847 chanspec_t nphy_iqcal_chanspec_2G;
848 chanspec_t nphy_iqcal_chanspec_5G;
849 chanspec_t nphy_rssical_chanspec_2G;
850 chanspec_t nphy_rssical_chanspec_5G;
851 struct wlapi_timer *phycal_timer;
852 bool use_int_tx_iqlo_cal_nphy;
853 bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
854 int16 nphy_lastcal_temp;
855
856 txiqcal_cache_t calibration_cache;
857 rssical_cache_t rssical_cache;
858
e868ab03
GKH		 859 u8 nphy_txpwr_idx[2];
860 u8 nphy_papd_cal_type;
a9533e7e 861 uint nphy_papd_last_cal;
7d4df48e 862 u16 nphy_papd_tx_gain_at_last_cal[2];
e868ab03 863 u8 nphy_papd_cal_gain_index[2];
a9533e7e
HP		 864 int16 nphy_papd_epsilon_offset[2];
865 bool nphy_papd_recal_enable;
866 uint32 nphy_papd_recal_counter;
867 bool nphy_force_papd_cal;
868 bool nphy_papdcomp;
869 bool ipa2g_on;
870 bool ipa5g_on;
871
7d4df48e
GKH		 872 u16 classifier_state;
873 u16 clip_state[2];
a9533e7e 874 uint nphy_deaf_count;
e868ab03
GKH		 875 u8 rxiq_samps;
876 u8 rxiq_antsel;
a9533e7e 877
7d4df48e
GKH		 878 u16 rfctrlIntc1_save;
879 u16 rfctrlIntc2_save;
a9533e7e 880 bool first_cal_after_assoc;
7d4df48e
GKH		 881 u16 tx_rx_cal_radio_saveregs[22];
882 u16 tx_rx_cal_phy_saveregs[15];
a9533e7e 883
e868ab03
GKH		 884 u8 nphy_cal_orig_pwr_idx[2];
885 u8 nphy_txcal_pwr_idx[2];
886 u8 nphy_rxcal_pwr_idx[2];
7d4df48e 887 u16 nphy_cal_orig_tx_gain[2];
a9533e7e 888 nphy_txgains_t nphy_cal_target_gain;
7d4df48e
GKH		 889 u16 nphy_txcal_bbmult;
890 u16 nphy_gmval;
a9533e7e 891
7d4df48e 892 u16 nphy_saved_bbconf;
a9533e7e
HP		 893
894 bool nphy_gband_spurwar_en;
895 bool nphy_gband_spurwar2_en;
896 bool nphy_aband_spurwar_en;
7d4df48e
GKH		 897 u16 nphy_rccal_value;
898 u16 nphy_crsminpwr[3];
a9533e7e
HP		 899 phy_noisevar_buf_t nphy_saved_noisevars;
900 bool nphy_anarxlpf_adjusted;
901 bool nphy_crsminpwr_adjusted;
902 bool nphy_noisevars_adjusted;
903
904 bool nphy_rxcal_active;
7d4df48e 905 u16 radar_percal_mask;
a9533e7e
HP		 906 bool dfs_lp_buffer_nphy;
907
7d4df48e 908 u16 nphy_fineclockgatecontrol;
a9533e7e 909
562c8850 910 s8 rx2tx_biasentry;
a9533e7e 911
7d4df48e
GKH		 912 u16 crsminpwr0;
913 u16 crsminpwrl0;
914 u16 crsminpwru0;
a9533e7e 915 int16 noise_crsminpwr_index;
7d4df48e
GKH		 916 u16 init_gain_core1;
917 u16 init_gain_core2;
918 u16 init_gainb_core1;
919 u16 init_gainb_core2;
e868ab03 920 u8 aci_noise_curr_channel;
7d4df48e 921 u16 init_gain_rfseq[4];
a9533e7e
HP		 922
923 bool radio_is_on;
924
925 bool nphy_sample_play_lpf_bw_ctl_ovr;
926
7d4df48e
GKH		 927 u16 tbl_data_hi;
928 u16 tbl_data_lo;
929 u16 tbl_addr;
a9533e7e
HP		 930
931 uint tbl_save_id;
932 uint tbl_save_offset;
933
e868ab03 934 u8 txpwrctrl;
562c8850 935 s8 txpwrindex[PHY_CORE_MAX];
a9533e7e 936
e868ab03 937 u8 phycal_tempdelta;
a9533e7e
HP		 938 uint32 mcs20_po;
939 uint32 mcs40_po;
940};
941
942typedef int32 fixed;
943
944typedef struct _cint32 {
945 fixed q;
946 fixed i;
947} cint32;
948
949typedef struct radio_regs {
7d4df48e 950 u16 address;
a9533e7e
HP		 951 uint32 init_a;
952 uint32 init_g;
e868ab03
GKH		 953 u8 do_init_a;
954 u8 do_init_g;
a9533e7e
HP		 955} radio_regs_t;
956
957typedef struct radio_20xx_regs {
7d4df48e 958 u16 address;
e868ab03
GKH		 959 u8 init;
960 u8 do_init;
a9533e7e
HP		 961} radio_20xx_regs_t;
962
963typedef struct lcnphy_radio_regs {
7d4df48e 964 u16 address;
e868ab03
GKH		 965 u8 init_a;
966 u8 init_g;
967 u8 do_init_a;
968 u8 do_init_g;
a9533e7e
HP		 969} lcnphy_radio_regs_t;
970
971extern lcnphy_radio_regs_t lcnphy_radio_regs_2064[];
972extern lcnphy_radio_regs_t lcnphy_radio_regs_2066[];
973extern radio_regs_t regs_2055[], regs_SYN_2056[], regs_TX_2056[],
974 regs_RX_2056[];
975extern radio_regs_t regs_SYN_2056_A1[], regs_TX_2056_A1[], regs_RX_2056_A1[];
976extern radio_regs_t regs_SYN_2056_rev5[], regs_TX_2056_rev5[],
977 regs_RX_2056_rev5[];
978extern radio_regs_t regs_SYN_2056_rev6[], regs_TX_2056_rev6[],
979 regs_RX_2056_rev6[];
980extern radio_regs_t regs_SYN_2056_rev7[], regs_TX_2056_rev7[],
981 regs_RX_2056_rev7[];
982extern radio_regs_t regs_SYN_2056_rev8[], regs_TX_2056_rev8[],
983 regs_RX_2056_rev8[];
984extern radio_20xx_regs_t regs_2057_rev4[], regs_2057_rev5[], regs_2057_rev5v1[];
985extern radio_20xx_regs_t regs_2057_rev7[], regs_2057_rev8[];
986
7cc4a4c0
JC		 987extern char *phy_getvar(phy_info_t *pi, const char *name);
988extern int phy_getintvar(phy_info_t *pi, const char *name);
a9533e7e
HP		 989#define PHY_GETVAR(pi, name) phy_getvar(pi, name)
990#define PHY_GETINTVAR(pi, name) phy_getintvar(pi, name)
991
7d4df48e
GKH		 992extern u16 read_phy_reg(phy_info_t *pi, u16 addr);
993extern void write_phy_reg(phy_info_t *pi, u16 addr, u16 val);
994extern void and_phy_reg(phy_info_t *pi, u16 addr, u16 val);
995extern void or_phy_reg(phy_info_t *pi, u16 addr, u16 val);
996extern void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val);
a9533e7e 997
7d4df48e
GKH		 998extern u16 read_radio_reg(phy_info_t *pi, u16 addr);
999extern void or_radio_reg(phy_info_t *pi, u16 addr, u16 val);
1000extern void and_radio_reg(phy_info_t *pi, u16 addr, u16 val);
1001extern void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask,
1002 u16 val);
1003extern void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask);
a9533e7e 1004
7d4df48e 1005extern void write_radio_reg(phy_info_t *pi, u16 addr, u16 val);
a9533e7e 1006
7cc4a4c0
JC		 1007extern void wlc_phyreg_enter(wlc_phy_t *pih);
1008extern void wlc_phyreg_exit(wlc_phy_t *pih);
1009extern void wlc_radioreg_enter(wlc_phy_t *pih);
1010extern void wlc_radioreg_exit(wlc_phy_t *pih);
a9533e7e 1011
7cc4a4c0 1012extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
7d4df48e
GKH		 1013 u16 tblAddr, u16 tblDataHi,
1014 u16 tblDatalo);
7cc4a4c0 1015extern void wlc_phy_write_table(phy_info_t *pi,
7d4df48e
GKH		 1016 const phytbl_info_t *ptbl_info, u16 tblAddr,
1017 u16 tblDataHi, u16 tblDatalo);
7cc4a4c0 1018extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
7d4df48e
GKH		 1019 u16 tblAddr, u16 tblDataHi,
1020 u16 tblDataLo);
7cc4a4c0 1021extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val);
a9533e7e 1022
7cc4a4c0
JC		 1023extern void write_phy_channel_reg(phy_info_t *pi, uint val);
1024extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
a9533e7e 1025
7cc4a4c0 1026extern void wlc_phy_cordic(fixed theta, cint32 *val);
e868ab03 1027extern u8 wlc_phy_nbits(int32 value);
a9533e7e 1028extern uint32 wlc_phy_sqrt_int(uint32 value);
562c8850 1029extern void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_dB, u8 core);
a9533e7e 1030
7cc4a4c0
JC		 1031extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
1032 radio_20xx_regs_t *radioregs);
1033extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
7d4df48e 1034 u16 core_offset);
a9533e7e 1035
7cc4a4c0 1036extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
a9533e7e 1037
7cc4a4c0
JC		 1038extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
1039extern void wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real,
1040 int32 *eps_imag);
a9533e7e 1041
7cc4a4c0
JC		 1042extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
1043extern void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi);
a9533e7e 1044
7cc4a4c0
JC		 1045extern bool wlc_phy_attach_nphy(phy_info_t *pi);
1046extern bool wlc_phy_attach_lcnphy(phy_info_t *pi);
a9533e7e 1047
7cc4a4c0 1048extern void wlc_phy_detach_lcnphy(phy_info_t *pi);
a9533e7e 1049
7cc4a4c0
JC		 1050extern void wlc_phy_init_nphy(phy_info_t *pi);
1051extern void wlc_phy_init_lcnphy(phy_info_t *pi);
a9533e7e 1052
7cc4a4c0
JC		 1053extern void wlc_phy_cal_init_nphy(phy_info_t *pi);
1054extern void wlc_phy_cal_init_lcnphy(phy_info_t *pi);
a9533e7e 1055
7cc4a4c0
JC		 1056extern void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec);
1057extern void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec);
1058extern void wlc_phy_chanspec_set_fixup_lcnphy(phy_info_t *pi,
a9533e7e
HP		 1059 chanspec_t chanspec);
1060extern int wlc_phy_channel2freq(uint channel);
1061extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
1062extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t);
1063
7d4df48e 1064extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode);
562c8850 1065extern s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi);
a9533e7e 1066
7cc4a4c0
JC		 1067extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi);
1068extern void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi);
1069extern void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi);
a9533e7e 1070
7cc4a4c0
JC		 1071extern void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index);
1072extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable);
1073extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi);
1074extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz,
7d4df48e 1075 u16 max_val, bool iqcalmode);
a9533e7e 1076
7cc4a4c0 1077extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan,
e868ab03
GKH		 1078 u8 *max_pwr, u8 rate_id);
1079extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
1080 u8 rate_mcs_end,
1081 u8 rate_ofdm_start);
1082extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
1083 u8 rate_ofdm_start,
1084 u8 rate_ofdm_end,
1085 u8 rate_mcs_start);
a9533e7e 1086
7d4df48e 1087extern u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode);
7cc4a4c0 1088extern int16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode);
562c8850
GKH		 1089extern s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode);
1090extern s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode);
7cc4a4c0
JC		 1091extern void wlc_phy_carrier_suppress_lcnphy(phy_info_t *pi);
1092extern void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel);
1093extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
1094extern void wlc_2064_vco_cal(phy_info_t *pi);
a9533e7e 1095
7cc4a4c0 1096extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
a9533e7e 1097extern uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor,
e868ab03 1098 u8 precision);
a9533e7e
HP		 1099
1100#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
1101#define LCNPHY_TX_POWER_TABLE_SIZE 128
1102#define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
1103#define LCNPHY_TBL_ID_TXPWRCTL 0x07
1104#define LCNPHY_TX_PWR_CTRL_OFF 0
1105#define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
1106#define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
1107 (0x1 << 14) | \
1108 (0x1 << 13))
1109
1110#define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
1111
7cc4a4c0
JC		 1112extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti);
1113extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti);
7d4df48e
GKH		 1114extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b);
1115extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq);
1116extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b);
1117extern u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi);
e868ab03
GKH		 1118extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, u8 *ei0,
1119 u8 *eq0, u8 *fi0, u8 *fq0);
7cc4a4c0
JC		 1120extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode);
1121extern void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode);
1122extern bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi);
1123extern void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi);
a9533e7e 1124extern int32 wlc_lcnphy_tssi2dbm(int32 tssi, int32 a1, int32 b0, int32 b1);
562c8850
GKH		 1125extern void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr,
1126 s8 *cck_pwr);
7cc4a4c0 1127extern void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi);
a9533e7e 1128
7cc4a4c0 1129extern int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index);
a9533e7e
HP		 1130
1131#define NPHY_MAX_HPVGA1_INDEX 10
1132#define NPHY_DEF_HPVGA1_INDEXLIMIT 7
1133
1134typedef struct _phy_iq_est {
1135 int32 iq_prod;
1136 uint32 i_pwr;
1137 uint32 q_pwr;
1138} phy_iq_est_t;
1139
7cc4a4c0
JC		 1140extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
1141extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
a9533e7e
HP		 1142
1143#define wlc_phy_write_table_nphy(pi, pti) wlc_phy_write_table(pi, pti, 0x72, \
1144 0x74, 0x73)
1145#define wlc_phy_read_table_nphy(pi, pti) wlc_phy_read_table(pi, pti, 0x72, \
1146 0x74, 0x73)
1147#define wlc_nphy_table_addr(pi, id, off) wlc_phy_table_addr((pi), (id), (off), \
1148 0x72, 0x74, 0x73)
1149#define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v))
1150
7cc4a4c0 1151extern void wlc_phy_table_read_nphy(phy_info_t *pi, uint32, uint32 l, uint32 o,
a9533e7e 1152 uint32 w, void *d);
7cc4a4c0 1153extern void wlc_phy_table_write_nphy(phy_info_t *pi, uint32, uint32, uint32,
a9533e7e
HP		 1154 uint32, const void *);
1155
1156#define PHY_IPA(pi) \
1157 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1158 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1159
1160#define WLC_PHY_WAR_PR51571(pi) \
1161 if ((BUSTYPE((pi)->sh->bustype) == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
1162 (void)R_REG((pi)->sh->osh, &(pi)->regs->maccontrol)
1163
e868ab03 1164extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);
7cc4a4c0
JC		 1165extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);
1166extern void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en);
a9533e7e 1167
e868ab03 1168extern u8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint chan);
7cc4a4c0 1169extern void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on);
a9533e7e 1170
7cc4a4c0 1171extern void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi);
a9533e7e 1172
e868ab03 1173extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd);
7cc4a4c0 1174extern int16 wlc_phy_tempsense_nphy(phy_info_t *pi);
a9533e7e 1175
7d4df48e 1176extern u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val);
a9533e7e 1177
7cc4a4c0 1178extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est,
7d4df48e 1179 u16 num_samps, u8 wait_time,
e868ab03 1180 u8 wait_for_crs);
a9533e7e 1181
e868ab03 1182extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write,
7cc4a4c0
JC		 1183 nphy_iq_comp_t *comp);
1184extern void wlc_phy_aci_and_noise_reduction_nphy(phy_info_t *pi);
a9533e7e 1185
e868ab03
GKH		 1186extern void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask);
1187extern u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih);
a9533e7e 1188
e868ab03 1189extern void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type);
7cc4a4c0
JC		 1190extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi);
1191extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi);
1192extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi);
7d4df48e 1193extern u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi);
a9533e7e 1194
7cc4a4c0
JC		 1195extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi);
1196extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
a9533e7e 1197 bool full, bool m);
7cc4a4c0 1198extern int wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
e868ab03
GKH		 1199 u8 type, bool d);
1200extern void wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask,
562c8850 1201 s8 txpwrindex, bool res);
e868ab03
GKH		 1202extern void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core, u8 rssi_type);
1203extern int wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type,
1204 int32 *rssi_buf, u8 nsamps);
7cc4a4c0
JC		 1205extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
1206extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
1207extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower,
a9533e7e 1208 bool debug);
7d4df48e 1209extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val,
e868ab03 1210 u8 mode, u8, bool);
7cc4a4c0
JC		 1211extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
1212extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf,
e868ab03 1213 u8 num_samps);
7cc4a4c0 1214extern void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi);
a9533e7e 1215
7cc4a4c0 1216extern int wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh);
a9533e7e
HP		 1217
1218#define NPHY_TESTPATTERN_BPHY_EVM 0
1219#define NPHY_TESTPATTERN_BPHY_RFCS 1
1220
e868ab03 1221extern void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs);
a9533e7e 1222
562c8850
GKH		 1223void wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset,
1224 s8 *ofdmoffset);
1225extern s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi,
a9533e7e
HP		 1226 chanspec_t chanspec);
1227
7cc4a4c0 1228extern bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pih);
a9533e7e 1229#endif /* _wlc_phy_int_h_ */
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